CN102194517A - Memory provided with input voltage conversion unit - Google Patents
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- CN102194517A CN102194517A CN201010125885XA CN201010125885A CN102194517A CN 102194517 A CN102194517 A CN 102194517A CN 201010125885X A CN201010125885X A CN 201010125885XA CN 201010125885 A CN201010125885 A CN 201010125885A CN 102194517 A CN102194517 A CN 102194517A
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Abstract
The invention provides a memory provided with an input voltage conversion unit. The memory comprises storage units, word lines, bit lines, a word line input end, a bit line input end, a word line clamping circuit and a bit line clamping circuit, wherein the storage units are arranged in an array manner; the same-row storage units are connected to one of the work lines; the same-line storage units are connected to one of the bit lines; the word line input end inputs a first voltage; the bit line input end inputs a second voltage; the word line clamping circuit is used for clamping the first voltage to a third voltage and outputting the third voltage to the word lines; the second voltage is smaller than the first voltage; the bit line clamping circuit is used for clamping the second voltage to a fourth voltage and outputting the fourth voltage to bit lines; and the fourth voltage is smaller than the second voltage. Therefore, the crosstalk problem caused by excessive reading current is avoided, and the power consumption is saved.
Description
Technical field
The present invention relates to the memory technology field, particularly a kind of storer with input voltage converting unit.
Background technology
Along with development of integrated circuits, the application of memory device in product more and more widely.Storer is divided into ROM (read-only memory) (ROM) and random access memory (RAM) usually, and wherein ROM (read-only memory) is divided into again: masked edit program (ROM), (PROM) able to programme, erasable programmable ROM (EPROM) and electrically erasable ROM (EEPROM).Random access memory is divided into again: static RAM (SRAM) and dynamic RAM (DRAM).Along with the development of intelligent artifact, all be provided with storer in a large amount of intelligent artifacts, for example MP3, MP4, mobile phone or the like, this also makes the quality of memory performance play crucial effects in intelligent artifact.
Existing memory generally includes the storage unit of arrayed, a line storage unit be connected to a public word line (Word-Line, WL) on, an array storage unit be connected to a public bit line (Bit-Line, BL) on.Word line can be controlled opening of a coupled line storage unit, and bit line can be controlled the read-write of a coupled array storage unit.In read-write operation,, control a certain line storage unit and open at first to the word line input signal; To the bit line input signal, the storage unit of a certain row of this row is read and write again.
For example Fig. 1 shows the structural representation of a kind of existing EPROM, as shown in Figure 1, EPROM comprises the capable m row of the n of arrayed nmos pass transistor, and wherein the grid of the nmos pass transistor of each row is connected on the word line, and the nmos pass transistor that n is capable is connected respectively on the n root word line.The drain electrode of the nmos pass transistor of each row is connected on the bit line, and the nmos pass transistor of m row is connected respectively on the m root bit line.In read operation, as shown in Figure 2, the source electrode of all nmos pass transistors be coupled to 0 voltage (), curve Q1 and Q2 are the curve map that read operation electric current I r changes with word line voltage and bit-line voltage, wherein the word line voltage of curve Q1 is higher than the word line voltage of Q2, from curve Q1 and Q2 as can be seen, the voltage of the voltage of word line WL and bit line BL is high more, and then the read operation electric current is big more.Yet if excessive can the causing of the electric current of read operation reads to crosstalk (read disturb), power consumption is also very big simultaneously.Therefore a kind of voltage translator circuit and the flash memory with this circuit are provided in the patent documentation of application number " 200810000708 ".Voltage conversion circuit comprises: the reference voltage generation unit, be used to generate reference voltage, and this reference voltage has uniform level, and irrelevant with the level of the input voltage that changes with mode of operation; And actuator unit, be used for according to control signal, utilize reference voltage to generate and export working voltage (ACTIVE VOLTAGE) or V Standby (STANDBYVOLTAGE) by the output of reference voltage generation unit.
Along with reducing of dimensions of semiconductor devices, how to reduce excessive cross-interference issue that causes of electric current and power consumption during the memory device read-write operation, more and more be subjected to people and pay close attention to.
Summary of the invention
The technical matters that the present invention solves provides a kind of storer with input voltage converting unit, thereby reduces because read-write excessive cross-interference issue that causes of electric current and power consumption.
The invention provides a kind of storer with input voltage converting unit, comprise: storage unit, word line, bit line, word line input end and bit line input end, wherein said storage unit is arrayed, same line storage unit is connected to a word line, same array storage unit is connected to a bit line, the word line input end is imported first voltage, and the bit line input end is imported second voltage; Also comprise word line clamping circuit and bit line clamping circuit; The word line clamping circuit to tertiary voltage, is exported to word line with described tertiary voltage with described first voltage clamp, and described second voltage is less than first voltage; The bit line clamping circuit is exported to bit line with described second voltage clamp to the, four voltages with described the 4th voltage, and described the 4th voltage is less than second voltage.s
Preferably, described word line clamping circuit is: the grid and the source electrode of first nmos pass transistor are coupled to word line, first nmos pass transistor drain electrode and substrate be coupled to the 5th voltage.
Preferably, described bit line clamping circuit comprises: first voltage divider, second voltage divider, the 3rd nmos pass transistor and difference discharge circuit;
Wherein, the input end of first voltage divider is coupled to the 6th voltage;
The grid of the 3rd nmos pass transistor and drain electrode are coupled to the output terminal of described first voltage divider, and the substrate of the 3rd nmos pass transistor and source electrode are coupled to the input end of second voltage divider;
The output terminal of second voltage divider is coupled to the positive input of described difference discharge circuit;
The reverse input end of described difference discharge circuit is coupled to described bit line, and the output terminal of described difference discharge circuit couples the transistorized grid of the 3rd PMOS;
Transistorized source electrode of the 3rd PMOS and substrate are coupled to the bit line input end, and the 3rd PMOS transistor drain is coupled to bit line.
Preferably, described bit line clamping circuit comprises: first voltage divider, the 3rd nmos pass transistor and difference discharge circuit;
Wherein, the input end of first voltage divider is coupled to the 6th voltage;
The grid of the 3rd nmos pass transistor and drain electrode are coupled to the output terminal of described first voltage divider, and the substrate of the 3rd nmos pass transistor and source electrode are coupled to the positive input of described difference discharge circuit;
The reverse input end of described difference discharge circuit is coupled to described bit line, and the output terminal of described difference discharge circuit couples the transistorized grid of the 3rd PMOS;
Transistorized source electrode of the 3rd PMOS and substrate are coupled to the bit line input end, and the 3rd PMOS transistor drain is coupled to bit line.
Preferably, described first voltage divider and second voltage divider are adjustable resistance.
Preferably, described bit line clamping circuit comprises: a PMOS transistor, the 2nd PMOS transistor and second nmos pass transistor;
Wherein, a PMOS transistor, source electrode is coupled to the 6th voltage, and drain electrode couples the drain electrode of second nmos pass transistor, and grid couples the grid of second nmos pass transistor;
The grid of second nmos pass transistor is coupled to bit line, and the source electrode of second nmos pass transistor is coupled to low-voltage;
The transistorized source electrode of the 2nd PMOS is coupled to the bit line input end, and the transistorized grid of the 2nd PMOS couples a PMOS transistor drain, and the 2nd PMOS transistor drain is coupled to bit line.
Preferably, described the 5th voltage equals the 6th voltage.
Preferably, described low-voltage is 0V.
Preferably, described storage unit is a nmos pass transistor, and its grid is coupled to word line, and drain electrode is coupled to bit line, and source electrode is coupled to 0V voltage.
Preferably, whole described bit lines are coupled to the memory bit line input end by same bit line clamping circuit; Whole described word lines are coupled to storer word line input end by same word line clamping circuit.
Compared with prior art, the present invention has the following advantages:
The present invention is by being provided with the input voltage converting unit that links to each other with storage unit in storer, thereby word line input voltage and bit line input voltage have been carried out clamper, it is reduced on the fixed voltage that is lower than input voltage, this fixed voltage can be configured such that the voltage of storage unit operate as normal, therefore prevented because word line input end and bit line input end instability, crosstalk in case import very high voltage then exist, and the bigger problem of power consumption.In an embodiment preferred of the present invention, also clamping circuit is improved in addition, bit-line voltage can be adjusted, thereby make the input voltage converting unit can not be subjected to the influence of manufacturing process, bit-line voltage is clamped down in a fixed value.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by physical size equal proportion convergent-divergent.
Fig. 1 is the structural representation of a kind of existing EPROM;
Fig. 2 is existing EPROM read operation current diagram;
Fig. 3 is the memory construction synoptic diagram with input voltage converting unit of the present invention;
Fig. 4 is the physical circuit figure of the input voltage converting unit and the storage unit of one embodiment of the invention;
Fig. 5 is the physical circuit figure of the input voltage converting unit and the storage unit of another embodiment of the present invention;
Fig. 6 is the physical circuit figure of the input voltage converting unit and the storage unit of yet another embodiment of the invention.
Embodiment
By background technology as can be known, existing memory generally comprises the capable m row of the n nmos pass transistor of arrayed as shown in Figure 1, and wherein the grid of the nmos pass transistor of each row is connected on the word line, and the nmos pass transistor that n is capable is connected respectively on the n root word line.The drain electrode of the nmos pass transistor of each row is connected on the bit line, and the nmos pass transistor of m row is connected respectively on the m root bit line.As shown in Figure 2, in read operation, the source electrode of all nmos pass transistors be coupled to 0 voltage (), the high more then read operation of the voltage of word line and bit line electric current is big more.Yet in case word line and bit-line voltage are too high, the electric current of read operation is excessive, thereby can cause damage to storage unit.
For this reason, the present inventor proposes a kind of storer with input voltage converting unit, and it comprises: the storage unit of arrayed, same line storage unit are connected to a word line, and same array storage unit is connected to a bit line; Be serially connected with the bit line clamping circuit between described bit line and the memory bit line input end, the bit line clamping circuit with the voltage clamp of bit line at the 4th voltage; Be serially connected with the word line clamping circuit between described word line and the storer word line input end, the word line clamping circuit with the voltage clamp of word line at tertiary voltage; Described the 4th voltage is less than second voltage, and described tertiary voltage is less than first voltage.For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, specific implementation of the present invention is described in detail below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes synoptic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the sectional view of expression device architecture can be disobeyed general ratio and be done local the amplification, and described synoptic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 3 is the memory construction synoptic diagram with input voltage converting unit of the present invention.As shown in Figure 3, storer with input voltage converting unit of the present invention, comprise storage unit 100, word line WL, bit line BL, word line input end 120 and bit line input end 110, wherein: storage unit 100 is arrayed, for example only show the storage unit of 3 row, 3 row in Fig. 3, in fact the ranks number of storage unit can be selected arbitrarily according to actual needs.Same line storage unit 100 is connected to a word line WL, and same array storage unit 100 is connected to a bit line BL.Word line input end 120 inputs first voltage, bit line input end 110 inputs second voltage.
Word line clamping circuit 120 to tertiary voltage, is exported to word line WL with described tertiary voltage with described first voltage clamp, and described second voltage is less than first voltage; Bit line clamping circuit 110 is exported to bit line BL with described second voltage clamp to the, four voltages with described the 4th voltage, and described the 4th voltage is less than second voltage.
As shown in Figure 3, be serially connected with bit line clamping circuit 111 between described bit line BL and the memory bit line input end 110, bit line clamping circuit 111 with second voltage clamp of bit line input end 110 input at the 4th voltage; Be serially connected with word line clamping circuit 121 between described word line WL and the storer word line input end 120, word line clamping circuit 121 is imported first voltage clamp at tertiary voltage with word line input end 120; Described the 4th voltage is less than second voltage, and described tertiary voltage is less than first voltage.
No matter be the bit line clamping circuit, or word line clamping circuit, in fact only need realize just passable in the source of input end, therefore the bit line clamping circuit can be arranged on the sense amplifier place that pairs of bit line voltage amplifies specifically, the word line clamping circuit can be arranged on word line voltage generation place (promptly reading the voltage generation circuit place), and word line of choosing then or bit line will connect.Therefore in a specific implementation, whole described bit lines are coupled to the memory bit line input end by same bit line clamping circuit; Whole described word lines are coupled to storer word line input end by same word line clamping circuit.For example whole described bit lines can be coupled to the bit line clamping circuit by a MUX; Whole described word lines can be coupled to the word line clamping circuit by a MUX again.In addition, also can connect a bit line clamping circuit by each root bit line, all bit line clamping circuits are coupled to the bit line input end by a MUX; Each root word line connects a word line clamping circuit, and all word line clamping circuits are coupled to the word line input end by a MUX.
If the voltage condition with higher of word line input end and bit line input end like this, word line clamping circuit and bit line clamping circuit can be with the voltage clamp of the voltage of word line and bit line in lower fixed values (the 4th voltage and tertiary voltage), thereby avoided because the voltage height of word line input end and bit line input end, the problem that the read current that causes is excessive, thus also just reduced because read-write excessive cross-interference issue that causes of electric current and power consumption.The principle of write operation is similar, repeats no more.
Fig. 4 is the physical circuit figure of the input voltage converting unit and the storage unit of one embodiment of the invention, below in conjunction with Fig. 4 the circuit structure and the principle of work of input voltage converting unit of the present invention and storage unit is elaborated.
In a specific implementation, described word line clamping circuit 121 is: the grid of the first nmos pass transistor N1 and source electrode are coupled to word line WL and word line input end 120, and drain electrode and substrate are coupled to the 5th voltage V3.
Described bit line clamping circuit 111 comprises: the first voltage divider Div1, the second voltage divider Div2, the 3rd nmos pass transistor N3 and difference discharge circuit (OP) 113.Wherein, the input end of the first voltage divider Div1 is coupled to the 6th voltage V4.The grid of the 3rd nmos pass transistor N3 and drain electrode are coupled to the output terminal of the described first voltage divider Div1, and substrate and source electrode are coupled to the input end of the second voltage divider Div2.The output terminal of the second voltage divider Div2 is coupled to the positive input of described difference discharge circuit 113.The reverse input end of described difference discharge circuit 113 is coupled to described bit line BL, and output terminal couples the grid of the 3rd PMOS transistor P3.Source electrode and the substrate of the 3rd PMOS transistor P3 are coupled to bit line input end 110, and drain electrode is coupled to bit line BL.
Principle of work below in conjunction with above-mentioned input voltage converting unit and storage unit further specifies.For convenience of illustration,let us suppose that, and all transistorized cut-in voltages (being the voltage difference between substrate and the grid) are all Vt.
For example when carrying out read operation, an end ground connection (0V) of storage unit, for example storage unit is nmos pass transistor N0, and its grid is coupled to word line WL, and drain electrode is coupled to bit line BL, and source electrode is coupled to 0V voltage.The voltage of word line input end 120 is high voltage (for example being 5V).The drain electrode of the first nmos pass transistor N1 meets the 5th voltage V3 (for example can be 3.3V), and the grid voltage of such first nmos pass transistor N1 and source voltage just are clamped at fixed value (V3+Vt).No matter how the voltage of word line input end changes, the voltage of bit line BL is clamped at and the identical value of difference discharge circuit (OP) 113 positive input voltages like this, and the voltage of word line remains fixed value (V3-Vt) always.Therefore storer of the present invention just can not cause that read current (promptly flowing through the electric current of nmos pass transistor N0) is excessive because of the overtension of word line input end.
One end ground connection (0V) of storage unit, for example storage unit is nmos pass transistor N0, and its grid is coupled to word line WL, and drain electrode is coupled to bit line BL, and source electrode is coupled to 0V voltage.The voltage of bit line input end 110 is high voltage (for example being 5V).Input termination the 6th voltage V4 (for example can be 3.3V) of the first voltage divider Div1 (for example can be 3.3V, promptly described the 5th voltage equals the 6th voltage, and the 5th voltage, the 6th voltage equate).After the dividing potential drop of the 6th voltage V4 through the first voltage divider Div1, output end voltage reduces (if the dividing potential drop coefficient of first voltage divider is a, then the voltage of output terminal is a*V4); Then reduced the cut-in voltage (Vt) (promptly the source electrode of the 3rd nmos pass transistor N3 is output as a*V4-Vt) of the 3rd nmos pass transistor N3 through voltage behind the 3rd nmos pass transistor N3; After following again dividing potential drop through the second voltage divider Div2, output end voltage reduces (if the dividing potential drop coefficient of second voltage divider is b again, then the voltage of output terminal is b* (a*V4-Vt)=a*b*V3-b*Vt), and just bit-line voltage is fixed value (a*b*V3-b*Vt).No matter how the voltage of bit line input end changes, the voltage of bit line remains a*b*V3-b*Vt always like this.Therefore storer of the present invention just can not cause that read current (promptly flowing through the electric current of nmos pass transistor N0) is excessive because of the overtension of bit line input end.
Because in the manufacture process of semiconductor devices, cut-in voltage (Vt) drift of MOS transistor may take place, if the cut-in voltage drift is too many, may make word line voltage and bit-line voltage have greatly changed simultaneously, thereby read current is caused bigger variation, therefore also might cause read current excessive.And in the present invention, can be by (a b) adjusts, thereby makes bit-line voltage not be subjected to the influence of cut-in voltage drift to the dividing potential drop coefficient of the first voltage divider Div1 and the second voltage divider Div2.
Described first voltage divider and second voltage divider can be voltage divider arrangement well known to those skilled in the art, for example in a preferred implementation, described first voltage divider and second voltage divider are adjustable resistance, change thereby can compensate the bit-line voltage that the drift of cut-in voltage causes by the adjusting to adjustable resistance.
Fig. 5 is the physical circuit figure of the input voltage converting unit and the storage unit of another embodiment of the present invention.As shown in Figure 5, described bit line clamping circuit comprises: the first voltage divider Div1, the 3rd nmos pass transistor N3 and difference discharge circuit (OP) 113.Wherein, the input end of the first voltage divider Div1 is coupled to the 6th voltage V4.The grid of the 3rd nmos pass transistor N3 and drain electrode are coupled to the output terminal of the described first voltage divider Div1, and substrate and source electrode are coupled to the positive input of described difference discharge circuit 113.The reverse input end of described difference discharge circuit 113 is coupled to described bit line BL, and output terminal couples the grid of the 3rd PMOS transistor P3.Source electrode and the substrate of the 3rd PMOS transistor P3 are coupled to bit line input end 110, and drain electrode is coupled to bit line BL, thereby the voltage of bit line BL is clamped at the value (be a*V4-Vt) identical with difference discharge circuit (OP) 113 positive input voltages.
The principle of work of this bit line clamping circuit is close with aforesaid embodiment, therefore repeats no more, and difference is that if cut-in voltage Vt changes greatly in the present embodiment, then the adjustability of bit-line voltage is relatively poor.
Fig. 6 is the physical circuit figure of the input voltage converting unit and the storage unit of yet another embodiment of the invention.As shown in Figure 6, preferred, described bit line clamping circuit comprises: a PMOS transistor P1, the 2nd PMOS transistor P2 and the second nmos pass transistor N2.
Wherein, a PMOS transistor P1, source electrode is coupled to the 6th voltage V4, and drain electrode couples the drain electrode of the second nmos pass transistor N2, and grid couples the grid of the second nmos pass transistor N2; The grid of the second nmos pass transistor N2 is coupled to bit line WL, and source electrode is coupled to 0V voltage; The source electrode of the 2nd PMOS transistor P2 is coupled to bit line input end 111, and grid couples the drain electrode of a PMOS transistor P1, and drain electrode is coupled to bit line BL, thereby bit-line voltage is clamped at cut-in voltage Vt.
For example when carrying out read operation, an end ground connection (0V) of storage unit, for example storage unit is nmos pass transistor N0, and its grid is coupled to word line WL, and drain electrode is coupled to bit line BL, and source electrode is coupled to 0V voltage.The voltage of bit line input end 110 is high voltage (for example being 5V).The voltage of bit line be clamped at Vt (principle of work of this bit line clamping circuit for those skilled in the art in conjunction with technical scheme of the present invention, can analyze and obtain, therefore repeat no more).In the present embodiment, because bit-line voltage is clamped at Vt, if therefore cut-in voltage Vt changes, then bit-line voltage is non-adjustable.
In the above-described embodiments, the parameter of each original paper, the breadth length ratio of MOS transistor for example, the circuit of voltage divider and difference discharge circuit, available for those skilled in the art in conjunction with the solution of the present invention and purpose, therefore repeat no more.
The present invention is by being provided with the input voltage converting unit that links to each other with storage unit in storer, thereby word line input voltage and bit line input voltage have been carried out clamper, it is reduced on the fixed voltage that is lower than input voltage, this fixed voltage can be configured such that the voltage of storage unit operate as normal, therefore prevented that owing to word line input end and bit line input end instability, what cause in case import very high voltage crosstalks and the bigger problem of power consumption.In an embodiment preferred of the present invention, also clamping circuit is improved in addition, bit-line voltage can be adjusted, thereby make the input voltage converting unit can not be subjected to the influence of manufacturing process, bit-line voltage can be clamped down in a fixed value.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, be equal to.
Claims (10)
1. storer with input voltage converting unit comprises:
Storage unit, word line, bit line, word line input end and bit line input end, wherein said storage unit is arrayed, and same line storage unit is connected to a word line, and same array storage unit is connected to a bit line, the word line input end is imported first voltage, and the bit line input end is imported second voltage;
It is characterized in that, also comprise word line clamping circuit and bit line clamping circuit;
The word line clamping circuit to tertiary voltage, is exported to word line with described tertiary voltage with described first voltage clamp, and described second voltage is less than first voltage;
The bit line clamping circuit is exported to bit line with described second voltage clamp to the, four voltages with described the 4th voltage, and described the 4th voltage is less than second voltage.
2. the storer with input voltage converting unit according to claim 1, it is characterized in that, described word line clamping circuit is: the grid and the source electrode of first nmos pass transistor are coupled to word line, first nmos pass transistor drain electrode and substrate be coupled to the 5th voltage.
3. the storer with input voltage converting unit according to claim 1 is characterized in that, described bit line clamping circuit comprises: first voltage divider, second voltage divider, the 3rd nmos pass transistor and difference discharge circuit;
Wherein, the input end of first voltage divider is coupled to the 6th voltage;
The grid of the 3rd nmos pass transistor and drain electrode are coupled to the output terminal of described first voltage divider, and the substrate of the 3rd nmos pass transistor and source electrode are coupled to the input end of second voltage divider;
The output terminal of second voltage divider is coupled to the positive input of described difference discharge circuit;
The reverse input end of described difference discharge circuit is coupled to described bit line, and the output terminal of described difference discharge circuit couples the transistorized grid of the 3rd PMOS;
Transistorized source electrode of the 3rd PMOS and substrate are coupled to the bit line input end, and the 3rd PMOS transistor drain is coupled to bit line.
4. the storer with input voltage converting unit according to claim 3 is characterized in that, described first voltage divider and second voltage divider are adjustable resistance.
5. the storer with input voltage converting unit according to claim 1 is characterized in that, described bit line clamping circuit comprises: first voltage divider, the 3rd nmos pass transistor and difference discharge circuit;
Wherein, the input end of first voltage divider is coupled to the 6th voltage;
The grid of the 3rd nmos pass transistor and drain electrode are coupled to the output terminal of described first voltage divider, and the substrate of the 3rd nmos pass transistor and source electrode are coupled to the positive input of described difference discharge circuit;
The reverse input end of described difference discharge circuit is coupled to described bit line, and the output terminal of described difference discharge circuit couples the transistorized grid of the 3rd PMOS;
Transistorized source electrode of the 3rd PMOS and substrate are coupled to the bit line input end, and the 3rd PMOS transistor drain is coupled to bit line.
6. the storer with input voltage converting unit according to claim 1 is characterized in that, described bit line clamping circuit comprises: a PMOS transistor, the 2nd PMOS transistor and second nmos pass transistor;
Wherein, a PMOS transistor, source electrode is coupled to the 6th voltage, and drain electrode couples the drain electrode of second nmos pass transistor, and grid couples the grid of second nmos pass transistor;
The grid of second nmos pass transistor is coupled to bit line, and the source electrode of second nmos pass transistor is coupled to low-voltage;
The transistorized source electrode of the 2nd PMOS is coupled to the bit line input end, and the transistorized grid of the 2nd PMOS couples a PMOS transistor drain, and the 2nd PMOS transistor drain is coupled to bit line.
7. according to claim 3,5 or 6 described storeies, it is characterized in that described the 5th voltage equals the 6th voltage with input voltage converting unit.
8. the storer with input voltage converting unit according to claim 6 is characterized in that, described low-voltage is 0V.
9. the storer with input voltage converting unit according to claim 1 is characterized in that, described storage unit is a nmos pass transistor, and its grid is coupled to word line, and drain electrode is coupled to bit line, and source electrode is coupled to 0V voltage.
10. the storer with input voltage converting unit according to claim 1 is characterized in that, whole described bit lines are coupled to the memory bit line input end by same bit line clamping circuit; Whole described word lines are coupled to storer word line input end by same word line clamping circuit.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114676834A (en) * | 2022-05-26 | 2022-06-28 | 中科南京智能技术研究院 | Bit line voltage clamping circuit for memory computing array |
| CN114676834B (en) * | 2022-05-26 | 2022-08-02 | 中科南京智能技术研究院 | Bit line voltage clamping circuit for memory computing array |
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| CN102194517B (en) | 2015-05-20 |
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