CN102158377A - Embedded detection system of train images - Google Patents
Embedded detection system of train images Download PDFInfo
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- CN102158377A CN102158377A CN2011100559360A CN201110055936A CN102158377A CN 102158377 A CN102158377 A CN 102158377A CN 2011100559360 A CN2011100559360 A CN 2011100559360A CN 201110055936 A CN201110055936 A CN 201110055936A CN 102158377 A CN102158377 A CN 102158377A
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Abstract
The invention discloses an embedded detection system of train images, comprising a gigabit Ethernet camera, a gigabit Ethernet interface circuit, a fast Ethernet interface circuit, a data acquisition and control circuit, an image compression circuit, a serial advanced technology attachment (SATA), an SATA interface circuit, a train coming/going detector, a recommend standard (RS) 232 interface circuit, a trigger control panel and a server, wherein the data acquisition and control circuit is respectively connected with the gigabit Ethernet camera, the server, the SATA and the train coming/going detector by the gigabit Ethernet interface circuit, the fast Ethernet interface circuit, the SATA interface circuit and the RS 232 interface circuit; the trigger control panel is connected with the data acquisition and control circuit and the train coming/going detector simultaneously; and the image compression circuit is connected with the data acquisition and control circuit and the SATA interface circuit simultaneously. Compared with a traditional detection system of the train images, the embedded detection system reduces the complexity, the cost, the volume and the power consumption, improves the stability, and is provided with good robustness.
Description
Technical field
The invention belongs to the electronic monitoring technical field, relate in particular to a kind of embedded train image detecting system.
Background technology
Along with the direction of railway construction in China to high speed develops, traditional dependence train detection person can not adapt to the requirement of railway transportation to daily train skill inspection with the method that traditional-handwork instruments such as cautious hammer, hand lamp and spanner carry out each position of hand inspection train.The train image detecting system of a new generation is to adopt the high-speed camera technology that each position of operating train is captured fast, the image compression of capturing is stored in the computer, and train detection person just can check that by computer picture that camera is captured detects the safe condition of train in the train detection chamber preferably at environment.
The camera major part that adopts in the present employed train image detecting system is the camera A312f of the IEEE 1394a interface of Basler company, and uses the industrial computer and the Windows operating system that have IEEE 1394a interface to come image is carried out acquisition process.Because the maximum transmission rate of IEEE 1394a interface is 400Mbps, transmission cable length is 4.5 meters, therefore there is following subject matter in present train image detecting system: (1) is because the transmission rate of IEEE 1394a interface is limited, cause the resolution and the frame per second of camera limited, can't satisfy bullet train and obtain the more needs of clear pictures; (2) adopt 1394 interfaces to transmit data, in transmission course, be subjected to various factors interference such as electromagnetism easily, in addition, because transmission cable limited length, must be in the train image detection is used according to actual transmissions apart from increasing relaying, cause camera to go offline so that to obtain image incomplete easilier like this; (3) because present image acquisition and processing is to adopt the scheme of industrial computer and Windows operating system, so have system complex, volume is big, susceptible viral infects, shortcoming such as easily go wrong works long hours under adverse circumstances.
Summary of the invention
At the deficiencies in the prior art, the invention provides a kind of transmission rate higher, reduced system complexity, improved the embedded train image detecting system of the stability of a system and robustness excellence.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of embedded train image detecting system, comprise: kilomega network camera (1), kilomega network interface circuit (2), 100,000,000 network interface circuit (3), data acquisition and control circuit (4), image compression circuit (5), serial ports hard disk (6), serial ports hard-disk interface circuit (7), train advances/sets off detector (8), RS232 interface circuit (9), trigger control board (10) and server (11), wherein, data acquisition and control circuit (4) are by kilomega network interface circuit (2), 100,000,000 network interface circuit (3), serial ports hard-disk interface circuit (7), RS232 interface circuit (9) respectively with kilomega network camera (1), server (11), serial ports hard disk (6), train advances/sets off detector (8) and links to each other, trigger control board (10) while and data acquisition and control circuit (4), train advances/sets off detector (8) and links to each other, image compression circuit (5) while and data acquisition and control circuit (4), serial ports hard-disk interface circuit (7) links to each other;
Wherein,
Kilomega network interface circuit (2) comprises Gigabit Ethernet transceiver (21), network transformer (22), network interface (23), status lamp display circuit (24) and voltage protection circuit (25), wherein, Gigabit Ethernet transceiver (21), network transformer (22), network interface (23) links to each other successively, the output connection status lamp display circuit (24) of Gigabit Ethernet transceiver (21), input connects voltage protection circuit (25), Gigabit Ethernet transceiver (21) also links to each other with kilomega network interface circuit interface (41), and network interface (23) links to each other with kilomega network camera (1);
Data acquisition and control circuit (4) are made of interconnective FPGA and DSP, wherein, FPGA includes kilomega network interface circuit interface (41), serial ports hard-disk interface circuit interface (42), triggering signal interface (43), DSP includes VPORT interface (44), EMIF interface (45), UART interface (46) and 100,000,000 network interfaces (47), kilomega network interface circuit interface (41) is connected with Gigabit Ethernet transceiver (21), serial ports hard-disk interface circuit interface (42) is connected with serial ports hard drive protocol chip (71), the input of triggering signal interface (43) is connected with triggering signal output interface (103), the output of kilomega network interface circuit interface (41) and triggering signal interface (43) also all is connected with the input of image compression circuit (5), the input of VPORT interface (44) and EMIF interface (45) all is connected with the output of image compression circuit (5), the input of UART interface (46) links to each other with UART transceiver (93), and 100,000,000 network interfaces (47) are connected with 100,000,000 network interface circuit (3);
Image compression circuit (5) is by the Data Input Interface (51) that links to each other successively, data pre-process circuit (52), metadata cache and 2 dimension dct transform circuit (53), Zigzag coding circuit (54), sample circuit (55), huffman coding circuit (56) and code stream parallel-to-serial converter (57) constitute, wherein, the input of Data Input Interface (51) and kilomega network interface circuit interface (41), the output of triggering signal interface (43) connects, the output of code stream parallel-to-serial converter (57) and VPORT interface (44), EMIF interface (45) is connected with the input of serial ports hard drive protocol chip (71);
Serial ports hard-disk interface circuit (7) comprises the connector (72) and the voltage protection circuit (73) of serial ports hard drive protocol chip (71), serial ports hard disk line, wherein, serial ports hard drive protocol chip (71) is connected with voltage protection circuit (73), code stream parallel-to-serial converter (57), serial ports hard-disk interface circuit interface (42), its output is connected with the connector (72) of serial ports hard disk line, and serial ports hard disk line connector (72) is connected with serial ports hard disk (6);
RS232 interface circuit (9) is made of the RS232-A interface (91) that links to each other successively, multichannel RS232 Linear Driving/receiver (92) and UART transceiver (93), RS232-A interface (91) connects the input that train advances/set off detector (8) and multichannel RS232 Linear Driving/receiver (92), the output of multichannel RS232 Linear Driving/receiver (92) is connected with the receiving terminal of UART transceiver (93), and the transmitting terminal of UART transceiver (93) is connected with UART interface (46);
Trigger control board (10) and comprise triggering signal input interface (101), FPGA (102) and triggering signal output interface (103), FPGA (102) links to each other with the output of triggering signal input interface (101) and the input of triggering signal output interface (103) respectively.
Above-mentioned voltage protection circuit (25) is formed by polar capacitor, nonpolar electric capacity and inductor combination.
Described polar capacitor, nonpolar electric capacity, inductance are respectively 10uF/10V specification, 0.1uF specification, 10uH specification.
Above-mentioned voltage protection circuit (73) only is made up of nonpolar electric capacity.
Described nonpolar electric capacity is the 0.1uF specification.
System of the present invention is installed in the row inspection station on rail next door, when train will reach row inspection station, after train advances/sets off detector (8) and detects train and arrive, kilomega network camera (1) is captured fast to each position of operating train, the image of capturing is passed through kilomega network interface circuit (2), data acquisition and control circuit (4) are transferred to image compression circuit (5), view data after the compression stores in the serial ports hard disk (6) by serial ports hard-disk interface circuit (7), upload to the server (11) that is arranged in row inspection center in the FTP mode by 100,000,000 network interface circuit (3) simultaneously, the staff just can go up the image that preview kilomega network camera (1) photographs at the server (11) at row inspection center, detects the safe condition of train.
Compared with prior art, the present invention has the following advantages and beneficial effect:
1, embedded train image detecting system of the present invention adopts embedded system to substitute existing industrial computer and Windows operating system, overcome the defective that often crashes and poison easily based on the train image detecting system of industrial computer and Windows operating system, thereby made row inspection person can be under environment preferably clap the safe condition that image detects train by checking;
2, compare with existing train image detecting system based on industrial computer and Windows operating system, the inventive method has reduced the complexity of image collection processing system, has also reduced cost, volume and power consumption simultaneously, has improved the stability of system;
3, embedded train image detecting system of the present invention can be controlled the kilomega network camera and carries out IMAQ, and the image that collects is carried out hardware JPEG compression, and has the network outage functions of retransmission, and robustness is good;
4, adopt system of the present invention to test at railway scene, Wuhan, result of the test shows: system of the present invention has good stable, the employing image resolution ratio that system of the present invention obtained is up to 1400*1024, the image frame per second is 60, Figure 24 ~ 25th, the train image that adopts system of the present invention to obtain, it is good to obtain image definition as seen from the figure.
Description of drawings
Fig. 1 is a structured flowchart of the present invention;
Fig. 2 is the structured flowchart of kilomega network interface circuit;
Fig. 3 is the circuit diagram of the Gigabit Ethernet transceiver in the kilomega network interface circuit;
Fig. 4 is the circuit diagram of network transformer, network interface, status lamp display circuit and voltage protection circuit in the kilomega network interface circuit;
Fig. 5 is the structured flowchart of data acquisition and control circuit;
Fig. 6 is the circuit diagram of the interface of kilomega network interface circuit in data acquisition and the control circuit and FPGA;
Fig. 7 is the circuit diagram of the interface of serial ports hard-disk interface circuit in data acquisition and the control circuit and FPGA;
Fig. 8 is the circuit diagram of the VPORT interface of the DSP in data acquisition and the control circuit;
Fig. 9 is the circuit diagram of the EMIF interface of the DSP in data acquisition and the control circuit;
Figure 10 is the structured flowchart of image compression circuit;
Figure 11 is the Data Input Interface in the image compression circuit and the circuit diagram of data pre-process circuit;
Figure 12 is the metadata cache in the image compression circuit and the circuit diagram of two-dimensional dct transform circuit;
Figure 13 is the metadata cache in the image compression circuit and the circuit diagram (continuing) of two-dimensional dct transform circuit;
Figure 14 is the circuit diagram of the Zigzag coding circuit in the image compression circuit;
Figure 15 is the circuit diagram of the sample circuit in the image compression circuit;
Figure 16 is the circuit diagram of the huffman coding circuit in the image compression circuit;
Figure 17 is the circuit diagram of the code stream parallel-to-serial converter in the image compression circuit;
Figure 18 is the structured flowchart of serial ports hard-disk interface circuit;
Figure 19 is the circuit diagram of serial ports hard-disk interface circuit;
Figure 20 is the structured flowchart that train advances/set off detector;
Figure 21 is the structured flowchart of RS232 interface circuit;
Figure 22 is the circuit diagram of RS232 interface circuit;
Figure 23 is the structured flowchart that triggers control board;
Figure 24 adopts system of the present invention to detect the 1st group of image of train;
Figure 25 adopts system of the present invention to detect the 66th group of image of train;
Among the figure: kilomega network camera (1); kilomega network interface circuit (2); Gigabit Ethernet transceiver (21); network transformer (22); network interface (23); status lamp display circuit (24); voltage protection circuit (25); 100,000,000 network interface circuit (3); data acquisition and control circuit (4); kilomega network interface circuit interface (41); serial ports hard-disk interface circuit interface (42); triggering signal interface (43); VPORT interface (44); EMIF interface (45); UART interface (46); 100,000,000 network interfaces (47); image compression circuit (5); Data Input Interface (51); data pre-process circuit (52); metadata cache and 2 dimension dct transform circuit (53); Zigzag coding circuit (54); sample circuit (55); huffman coding circuit (56); code stream parallel-to-serial converter (57); serial ports hard disk (6); serial ports hard-disk interface circuit (7); serial ports hard drive protocol chip (71); the connector (72) of serial ports hard disk line; voltage protection circuit (73); train advances/sets off detector (8); RS232 interface circuit (9); RS232-A interface (91); multichannel RS232 Linear Driving/receiver (92); UART transceiver (93); trigger control board (10); triggering signal input interface (101); FPGA (102); triggering signal output interface (103); server (11).
Embodiment
Below in conjunction with drawings and Examples embedded train image detecting system of the present invention is described in further detail.
Be illustrated in figure 1 as embedded train image detecting system of the present invention, comprise: kilomega network camera (1), kilomega network interface circuit (2), 100,000,000 network interface circuit (3), data acquisition and control circuit (4), image compression circuit (5), serial ports hard disk (6), serial ports hard-disk interface circuit (7), train advances/sets off detector (8), RS232 interface circuit (9), trigger control board (10) and server (11), wherein, data acquisition and control circuit (4) are by kilomega network interface circuit (2), 100,000,000 network interface circuit (3), serial ports hard-disk interface circuit (7), RS232 interface circuit (9) respectively with kilomega network camera (1), server (11), serial ports hard disk (6), train advances/sets off detector (8) and links to each other, trigger control board (10) while and data acquisition and control circuit (4), train advances/sets off detector (8) and links to each other, image compression circuit (5) while and data acquisition and control circuit (4), serial ports hard-disk interface circuit (7) links to each other;
Wherein,
Kilomega network interface circuit (2) comprises Gigabit Ethernet transceiver (21), network transformer (22), network interface (23), status lamp display circuit (24) and voltage protection circuit (25), wherein, Gigabit Ethernet transceiver (21), network transformer (22), network interface (23) links to each other successively, the output connection status lamp display circuit (24) of Gigabit Ethernet transceiver (21), input connects voltage protection circuit (25), Gigabit Ethernet transceiver (21) also links to each other with kilomega network interface circuit interface (41), and network interface (23) links to each other with kilomega network camera (1);
Data acquisition and control circuit (4) are made of interconnective FPGA and DSP, wherein, FPGA includes kilomega network interface circuit interface (41), serial ports hard-disk interface circuit interface (42), triggering signal interface (43), DSP includes VPORT interface (44), EMIF interface (45), UART interface (46) and 100,000,000 network interfaces (47), kilomega network interface circuit interface (41) is connected with Gigabit Ethernet transceiver (21), serial ports hard-disk interface circuit interface (42) is connected with serial ports hard drive protocol chip (71), the input of triggering signal interface (43) is connected with triggering signal output interface (103), the output of kilomega network interface circuit interface (41) and triggering signal interface (43) also all is connected with the input of image compression circuit (5), the input of VPORT interface (44) and EMIF interface (45) all is connected with the output of image compression circuit (5), the input of UART interface (46) links to each other with UART transceiver (93), and 100,000,000 network interfaces (47) are connected with 100,000,000 network interface circuit (3);
Image compression circuit (5) is by the Data Input Interface (51) that links to each other successively, data pre-process circuit (52), metadata cache and 2 dimension dct transform circuit (53), Zigzag coding circuit (54), sample circuit (55), huffman coding circuit (56) and code stream parallel-to-serial converter (57) constitute, wherein, the input of Data Input Interface (51) and kilomega network interface circuit interface (41), the output of triggering signal interface (43) connects, the output of code stream parallel-to-serial converter (57) and VPORT interface (44), EMIF interface (45) is connected with the input of serial ports hard drive protocol chip (71);
Serial ports hard-disk interface circuit (7) comprises the connector (72) and the voltage protection circuit (73) of serial ports hard drive protocol chip (71), serial ports hard disk line, wherein, serial ports hard drive protocol chip (71) is connected with voltage protection circuit (73), code stream parallel-to-serial converter (57), serial ports hard-disk interface circuit interface (42), its output is connected with the connector (72) of serial ports hard disk line, and serial ports hard disk line connector (72) is connected with serial ports hard disk (6);
RS232 interface circuit (9) is made of the RS232-A interface (91) that links to each other successively, multichannel RS232 Linear Driving/receiver (92) and UART transceiver (93), RS232-A interface (91) connects the input that train advances/set off detector (8) and multichannel RS232 Linear Driving/receiver (92), the output of multichannel RS232 Linear Driving/receiver (92) is connected with the receiving terminal of UART transceiver (93), and the transmitting terminal of UART transceiver (93) is connected with UART interface (46);
Trigger control board (10) and comprise triggering signal input interface (101), FPGA (102) and triggering signal output interface (103), FPGA (102) links to each other with the output of triggering signal input interface (101) and the input of triggering signal output interface (103) respectively.
1, kilomega network interface circuit (2)
Parameters such as the mode of operation, frame per second, time for exposure, gain of kilomega network camera (1) can be controlled and adjust to kilomega network interface circuit (2), and can receive kilomega network camera (1) shot image data and send the camera order, the structured flowchart of kilomega network interface circuit (2) as shown in Figure 2, the physical circuit figure of each part of kilomega network interface circuit (2) is shown in Fig. 3 ~ 4.
In the present embodiment, the Gigabit Ethernet transceiver (21) in the kilomega network interface circuit (2) is selected the network chip of 88E1111-RCJ model for use; Network transformer (22) is selected the chip of LF9202A model for use; Network interface (23) is selected RJ45 network connector for use; Indicator light in the status lamp display circuit (24) is selected LED for use; Voltage protection circuit (25) is to be formed by polar capacitor, nonpolar electric capacity and inductor combination; wherein; polar capacitor is selected the 10uF/10V specification for use; nonpolar electric capacity is selected the 0.1uF specification for use; inductance is selected the 10uH specification for use; voltage protection circuit (25) has two; be respectively voltage protection circuit (25a) and voltage protection circuit (25b); physical circuit as shown in Figure 4; voltage protection circuit (25a) connection 2.5V DC power supply and while ground connection, voltage protection circuit (25b) connect 1.2V DC power supply and while ground connection.Network interface (23) is connected with P13, P14, P16, P17, P19, P20, P22, the P23 port of LF9202A chip; P12, the P11 of LF9202A model chip, P9, P8, P6, P5, P3, P2 port are connected with MDI_0_P, MDI_0_N, MDI_1_P, MDI_1_N, MDI_2_P, MDI_2_N, MDI_3_P, the MDI_3_N port of 88E1111-RCJ model chip respectively; 5 output pin LED_TX, LED_RX of 88E1111-RCJ model chip, LED_LINK100, LED_LINK1000, LED_DUPLEX are connected with status lamp display circuit (24), thereby the network state and the working method that can show kilomega network interface circuit (2), wherein, the network state of kilomega network interface circuit (2) comprises that network is logical and obstructed, and working method comprises working methods such as 10M net, 100M net and kilomega network; GTXCLK, the TX_CLK of 88E1111-RCJ model chip, TXEN, TXER, TXD0 ~ 7, RXCLK, RXDV, RXER, RXD0 ~ 7, CRS, COL, MDC, MDIO, INTn port are connected (shown in Figure 5) with data acquisition with the kilomega network interface circuit interface (41) of control circuit (4), thereby can realize the reception of kilomega network view data and the order control of kilomega network camera.Kilomega network interface circuit (2) provides clock signal by external crystal oscillator, and the external crystal oscillator frequency that kilomega network interface circuit (2) is connect is 25MHz, is the operating frequency of 125MHz through the frequency multiplication of phase locked loop of FPGA.The attainable maximum transmission rate of kilomega network interface circuit (2) is 656.25Mbps in the present embodiment.
2,100,000,000 network interface circuit (3)
100,000,000 network interfaces (47) carry out network service by 100,000,000 network interface circuit (3) and server (11), and it can give server (11) by the image code stream that ICP/IP protocol transmits after the compression, make that server (11) can the live preview image; Also can give server (11), be convenient to later fault detect by the image file that File Transfer Protocol transmits after compressing.100,000,000 network interfaces (47) that adopted in the present embodiment and 100,000,000 network interface circuit (3) are existing in the prior art, and specific implementation method can be with reference to the technical manual of DM642 type DSP.
3, data acquisition and control circuit (4)
Data acquisition and control circuit (4) respectively with kilomega network interface circuit (2), 100,000,000 network interface circuit (3), image compression circuit (5), serial ports hard-disk interface circuit (7), RS232 interface circuit (9), triggering control board (10) connects, data acquisition is connected reception and the transmission that realizes the kilomega network view data with control circuit (4) with kilomega network interface circuit (2), data acquisition is connected realization with control circuit (4) compressed file is uploaded to server (11) with 100,000,000 network interface circuit (3), data acquisition and control circuit (4) be connected with image compression circuit (5) realize giving image compression circuit (5) with image data transmission thus carry out data compression, data acquisition and control circuit (4) be connected with serial ports hard-disk interface circuit (7) realize compressed bit stream is transferred to serial ports hard-disk interface circuit (7) thus data are deposited, data acquisition and control circuit (4) are connected with RS232 interface circuit (9) and are used for receiving train and advance/set off detector (8) passing the order of coming, and data acquisition and control circuit (4) are connected with triggering control board (10) and are used for receiving train and advance/set off the triggering signal that detector (8) biography is come.Its structured flowchart as shown in Figure 5, the physical circuit figure of each part is shown in Fig. 6 ~ 9.Data acquisition and control circuit (4) are to be realized by FPGA and DSP in this enforcement, wherein, what FPGA selected for use is the EP2S60F1020C5N type fpga chip of ALTERA company, what DSP selected for use is the TMS320DM642 type dsp chip of TIX (TI), kilomega network interface circuit interface (41), serial ports hard-disk interface circuit interface (42) and triggering signal interface (43) are on same fpga chip, and VPORT interface (44), EMIF interface (45), UART interface (46), 100,000,000 network interfaces (47) link to each other with fpga chip.
4, image compression circuit (5)
The structured flowchart of image compression circuit (5) as shown in figure 10, the physical circuit figure of its each part is shown in Figure 11 ~ 17.Image compression circuit in the present embodiment (5) also is to realize that by FPGA the realization of its each electronic circuit module is finished according to international standard JPEG encryption algorithm, and operating frequency is 100MHz, by the frequency multiplication of phase locked loop output of FPGA.Data acquisition and control circuit (4) provide reset signal pRST, clock signal clk_100M, row useful signal LVAL, data useful signal Data_clk and view data Cam_Data[7..0 to Data Input Interface (51)], code stream parallel-to-serial converter (57) is connected with EMIF interface (45) with VPORT interface (44), shown in Fig. 7 ~ 8, thereby compressed code flow can be passed to DSP.The high energy of image compression circuit in the present embodiment (5) is realized the circuit of per second 60 frames, the compression of every frame 1,400,000 pixel black and white camera image data.
5, serial ports hard-disk interface circuit (7)
The structured flowchart of serial ports hard-disk interface circuit (7) as shown in figure 18, Figure 19 is its physical circuit figure.Serial ports hard-disk interface circuit (7) can deposit the view data after image compression circuit (5) compression in serial ports hard disk (6), also can read the view data in the serial ports hard disk (6) and the view data that reads is uploaded to data acquisition and control circuit (4).In the present embodiment; serial ports hard drive protocol chip (71) is selected JM20330 model chip for use, and the connector (72) of serial ports hard disk line is selected direct insertion connector for use, and voltage protection circuit (73) only is made up of nonpolar electric capacity; and nonpolar electric capacity is selected the 0.1uF specification for use, specifically as shown in figure 19.The connector (72) of serial ports hard disk line is by pin A+; A-; B+; B-respectively with the TXP of JM20330 model chip; TXN; RXP; the RXN port connects; voltage protection circuit (73) connects 3.3V DC power supply and ground connection; ATA_DD0 ~ 15 of JM20330 model chip; RESETn; DMARQ; DIOWn; DIORn; IORDY; DMACK; INTRQ; DA0 ~ 2; CS0n; the CS1n port is connected with serial ports hard-disk interface circuit interface (42); thereby realize the read-write of serial ports hard disk, view data deposits serial ports hard disk (6) by the high energy of serial ports hard disk line in real time with the speed of 80MBps.The external crystal oscillator of serial ports hard drive protocol chip (71) is 25MHz, is the serial ports hard-disc storage operating frequency of 125MHz through the frequency multiplication of phase locked loop of FPGA.
6, train advances/sets off detector (8)
Train advances/set off detector (8) can be realized adopting figure and trigger function and serial port command sending function take place, and its structured flowchart as shown in figure 20.Train advances/sets off detector (8) by triggering the generation module and ordering the generation module to be formed in the present embodiment, wherein, trigger the generation module and be connected with the triggering signal input interface (101) that triggers control board (10), module takes place and is connected with the RS232-A interface (91) of RS232 interface circuit (9) in order.
7, RS232 interface circuit (9)
RS232 interface circuit (9) can receive train and advance/set off the car that connects that detector (8) sends and begin, connecing car finishes and kilomega network camera parameter control command, wherein, kilomega network camera parameter control command comprised the camera exposure time, isoparametric control gains, above-mentioned parameter advances/sets off detector (8) by train and sends, by RS232 interface circuit (9) parameter is sent to data acquisition and control circuit (4) then, data acquisition and control circuit (4) are issued kilomega network camera (1) with the supplemental characteristic that receives by kilomega network camera interface (2), thereby realize the change to camera parameter.The structured flowchart of RS232 interface circuit (9) as shown in figure 21, its physical circuit figure is as shown in figure 22.In the present embodiment, RS232-A interface (91) adopts female serial ports connector, and multichannel RS232 Linear Driving/receiver (92) adopts MAX3243C model chip, and UART transceiver (93) adopts TL16C752B model chip, and its crystal oscillator is 29.4912 MHz.RS232-A interface (91) is connected with MAX3243C model pin of chip T1OUT, T2OUT, T3OUT, R1IN, R2IN, R3IN, R4IN, R5IN, MAX3243C model chip by pin T1IN, T2IN, T3IN, R1OUT, R2OUT, R3OUT, R4OUT, R5OUT respectively with the TL16C752B pin of chip
, TXA,
,
,
, RXA,
,
Connect; The TL16C752B chip by pin D0 ~ 7, A0 ~ 2,
, RESET,
,
,
,
Be connected with UART interface (46).
8, trigger control board (10)
Trigger control board (10) and pulse can be triggered input and be converted to dipulse and trigger output, be convenient to trigger line eliminate signal burr when longer, to reach the purpose of accurate control number of bursts, its structured flowchart as shown in figure 23.
9, server (11)
The staff can pass through server (11) and receive the jpeg image code stream, and real-time decoding and preview image can also send order to data acquisition and control circuit (4) by 100,000,000 network interface circuit (3), settings such as the time for exposure of change camera, gain.Server in the present embodiment (11) adopts and to be configured to: Intel Duo double-core CPU (I5-480), 1TB hard disk, 4GB internal memory, Windows Server 2003 operating systems, possess 100,000,000 network interfaces, Serv-U software has been installed, in Serv-U software, set information such as user name, and the specify image storing directory.
To describe the course of work of embedded train image detecting system of the present invention below in detail:
System of the present invention is installed in the row inspection station on rail next door, when train will reach row inspection station, train advances/sets off detector (8) and detects the magnet steel signal that is layed in rail, give RS232 interface circuit (9) by the car initiation command that connects of ordering the serial ports that module takes place to send a byte (0xFF), after data acquisition and control circuit (4) receive the initiation command that RS232 interface circuit (9) transmits, open kilomega network camera (1) by kilomega network camera interface circuit (2), simultaneously, data acquisition and control circuit (4) are by 100,000,000 network interface circuit (3), and adopt FTP communication protocol under certain path of server (11) newly-built one be 2 grades of subdirectories of directory name with current date and current time.
Pass through to be listed as in the process at inspection station at train, promptly connect in the car process, train advances/set off detector (8) thereby can constantly detect the magnet steel signal sends pulse triggering signal to triggering control board (10) by triggering the generation module.Because rail is far away from the train detection chamber, it is longer to trigger line, make train advance/set off the pulse triggering signal generation burr that detector (8) sends easily, trigger control board (10) the pulse triggering signal of receiving is converted to certain hour double trigger at interval by FPGA (102), and double trigger sent to data acquisition and control circuit (4), data acquisition and control circuit (4) receive that whenever a double trigger just transmits the signal of capturing a two field picture by kilomega network camera interface circuit (2) to kilomega network camera (1), view data after kilomega network camera (1) will be captured is uploaded to data acquisition and control circuit (4) by kilomega network camera interface circuit (2), data acquisition and control circuit (4) carry out the JPEG compression with the view data that receives by image compression circuit (5), form the compressed image code stream, this image code stream deposits serial ports hard disk (6) in by serial ports hard-disk interface circuit (7), simultaneously, image compression circuit (5) returns the compressed image code stream to image data acquiring and control circuit (4), code stream forms jpeg image file after adding jpeg file head and jpeg file tail, this image file is by 100,000,000 network interface circuit (3), is transferred in 2 grades of subdirectories that the server (11) at row inspection center sets up with File Transfer Protocol.
When train leaves row inspection station, train advances/sets off detector (8) and detects the magnet steel signal that is layed in rail, serial ports by the order generation module on the detector sends the car the finish command that connects of a byte (0xFD) and gives RS232 interface circuit (9), data acquisition and control circuit (4) are closed kilomega network camera (1) by kilomega network camera interface circuit (2) after receiving the finish command that RS232 interface circuit (9) transmits.
Before train arrives row inspection station and leave after the row inspection station, can also be by server (11) but carry out the image live preview checks whether the camera putting position correct, the operating state of test network and camera also.The course of work of image live preview is: server (11) sends the camera open command to data acquisition and control circuit (4) by 100,000,000 network interface circuit (3), data acquisition and control circuit (4) are opened kilomega network camera (1) by kilomega network camera interface circuit (2), gather with control circuit (4) and give server (11) by 100,000,000 network interface circuit (3) by the image code stream that ICP/IP protocol transmits after compressing, server (11) is realized real-time decoding and preview image.
System of the present invention is in work, because vibrations or to connect the improper netting twine that may exist loosening, fails and uploads onto the server in (11) thereby cause connecing image file in the car process.But owing to deposit the compressed image code stream in serial ports hard disk (6) by serial ports hard-disk interface circuit (7), therefore can say the word to data acquisition and control circuit (4) by 100,000,000 network interface circuit (3) by server (11), data acquisition and control circuit (4) read image code stream data in the serial ports hard disk (6) by serial ports hard-disk interface circuit (7), image code stream forms jpeg image file after adding jpeg file head and jpeg file tail, the image file that obtains is passed through 100,000,000 network interface circuit (3), be transferred in 2 grades of subdirectories that the server (11) at row inspection center sets up with File Transfer Protocol, thereby realize the network outage functions of retransmission.
Adopt embedded train image detecting system of the present invention to test at railway scene, Wuhan, through the operation of time more than 2 years, system of the present invention is the energy steady operation all, and tests respond well.Figure 24 and Figure 25 be on September 2nd, 2009 at the railway scene by 5 cameras certain train by the time the 1st group and the 66th group image of this train of obtaining, clear picture is good as seen from the figure.Table 1 is the comparison sheet of system of the present invention and existing train image detecting system based on industrial computer, as can be seen from the table, system of the present invention is easier, have littler volume, lower power consumption, the excellent stability of a system, higher output speed, adopts system of the present invention can obtain more distinct image.
Table 1 system of the present invention and based on the comparison of the train image detecting system of industrial computer
| ? | Embedded train image detecting system of the present invention | Train image detecting system based on industrial computer |
| Camera | The kilomega network camera | 1394 |
| Cable | ||
| 20 meters kilomega network netting twines | 2 ~ 6 1394a cables | |
| Repeater | Do not have | 2~5 |
| Image processing equipment | Embedded system | Industrial computer |
| Volume | 1U | 4U |
| Power consumption | 300W | 200W |
| The stability of a system | Never go offline | Often go offline |
| Image resolution ratio | 1400*1024 | 720*576 |
| The image frame per second | 60 | 25 |
Claims (5)
1. an embedded train image detecting system is characterized in that, comprising:
Kilomega network camera (1), kilomega network interface circuit (2), 100,000,000 network interface circuit (3), data acquisition and control circuit (4), image compression circuit (5), serial ports hard disk (6), serial ports hard-disk interface circuit (7), train advances/sets off detector (8), RS232 interface circuit (9), trigger control board (10) and server (11), wherein, data acquisition and control circuit (4) are by kilomega network interface circuit (2), 100,000,000 network interface circuit (3), serial ports hard-disk interface circuit (7), RS232 interface circuit (9) respectively with kilomega network camera (1), server (11), serial ports hard disk (6), train advances/sets off detector (8) and links to each other, trigger control board (10) while and data acquisition and control circuit (4), train advances/sets off detector (8) and links to each other, image compression circuit (5) while and data acquisition and control circuit (4), serial ports hard-disk interface circuit (7) links to each other;
Described kilomega network interface circuit (2) comprises Gigabit Ethernet transceiver (21), network transformer (22), network interface (23), status lamp display circuit (24) and voltage protection circuit (25), wherein, Gigabit Ethernet transceiver (21), network transformer (22), network interface (23) links to each other successively, the output connection status lamp display circuit (24) of Gigabit Ethernet transceiver (21), input connects voltage protection circuit (25), Gigabit Ethernet transceiver (21) also links to each other with kilomega network interface circuit interface (41), and network interface (23) links to each other with kilomega network camera (1);
Described data acquisition and control circuit (4) are made of interconnective FPGA and DSP, wherein, FPGA comprises kilomega network interface circuit interface (41), serial ports hard-disk interface circuit interface (42), triggering signal interface (43), DSP includes VPORT interface (44), EMIF interface (45), UART interface (46) and 100,000,000 network interfaces (47), kilomega network interface circuit interface (41) is connected with Gigabit Ethernet transceiver (21), serial ports hard-disk interface circuit interface (42) is connected with serial ports hard drive protocol chip (71), the input of triggering signal interface (43) is connected with triggering signal output interface (103), the output of kilomega network interface circuit interface (41) and triggering signal interface (43) all is connected with the input of image compression circuit (5), the input of VPORT interface (44) and EMIF interface (45) all is connected with the output of image compression circuit (5), the input of UART interface (46) links to each other with UART transceiver (93), and 100,000,000 network interfaces (47) are connected with 100,000,000 network interface circuit (3);
Described image compression circuit (5) is by the Data Input Interface (51) that links to each other successively, data pre-process circuit (52), metadata cache and 2 dimension dct transform circuit (53), Zigzag coding circuit (54), sample circuit (55), huffman coding circuit (56) and code stream parallel-to-serial converter (57) constitute, wherein, the input of Data Input Interface (51) and kilomega network interface circuit interface (41), triggering signal interface (43) connects, the output of code stream parallel-to-serial converter (57) and VPORT interface (44), EMIF interface (45) is connected with serial ports hard drive protocol chip (71);
Described serial ports hard-disk interface circuit (7) comprises the connector (72) and the voltage protection circuit (73) of serial ports hard drive protocol chip (71), serial ports hard disk line, wherein, serial ports hard drive protocol chip (71) is connected with voltage protection circuit (73), code stream parallel-to-serial converter (57), serial ports hard-disk interface circuit interface (42), its output is connected with the connector (72) of serial ports hard disk line, and serial ports hard disk line connector (72) is connected with serial ports hard disk (6);
Described RS232 interface circuit (9) is made of the RS232-A interface (91) that links to each other successively, multichannel RS232 Linear Driving/receiver (92) and UART transceiver (93), RS232-A interface (91) connects the input that train advances/set off detector (8) and multichannel RS232 Linear Driving/receiver (92), the output of multichannel RS232 Linear Driving/receiver (92) is connected with the receiving terminal of UART transceiver (93), and the transmitting terminal of UART transceiver (93) is connected with UART interface (46);
Described triggering control board (10) comprises triggering signal input interface (101), FPGA (102) and triggering signal output interface (103), and FPGA (102) links to each other with the output of triggering signal input interface (101) and the input of triggering signal output interface (103) respectively.
2. embedded train image detecting system according to claim 1 is characterized in that:
Described voltage protection circuit (25) is formed by polar capacitor, nonpolar electric capacity and inductor combination.
3. embedded train image detecting system according to claim 2 is characterized in that:
Described polar capacitor, nonpolar electric capacity, inductance are respectively 10uF/10V specification, 0.1uF specification, 10uH specification.
4. embedded train image detecting system according to claim 1 and 2 is characterized in that:
Described voltage protection circuit (73) only is made up of nonpolar electric capacity.
5. embedded train image detecting system according to claim 4 is characterized in that:
Described nonpolar electric capacity is the 0.1uF specification.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105894822A (en) * | 2016-06-24 | 2016-08-24 | 桂林金铱星科技发展有限公司 | Automatic capture system |
| CN110740297A (en) * | 2019-10-25 | 2020-01-31 | 浙江工贸职业技术学院 | automatic identification computer-based monitoring device and monitoring method |
| CN112584104A (en) * | 2020-12-09 | 2021-03-30 | 国网辽宁省电力有限公司检修分公司 | Low-power-consumption intelligent monitoring design method |
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| US20020067409A1 (en) * | 2000-12-06 | 2002-06-06 | Bio-View Ltd. | Data acquisition and display system and method |
| CN101710256A (en) * | 2009-07-06 | 2010-05-19 | 中国科学院长春光学精密机械与物理研究所 | High speed image data acquisition and processing card based on Camera Link interface |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020067409A1 (en) * | 2000-12-06 | 2002-06-06 | Bio-View Ltd. | Data acquisition and display system and method |
| CN101710256A (en) * | 2009-07-06 | 2010-05-19 | 中国科学院长春光学精密机械与物理研究所 | High speed image data acquisition and processing card based on Camera Link interface |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105894822A (en) * | 2016-06-24 | 2016-08-24 | 桂林金铱星科技发展有限公司 | Automatic capture system |
| CN110740297A (en) * | 2019-10-25 | 2020-01-31 | 浙江工贸职业技术学院 | automatic identification computer-based monitoring device and monitoring method |
| CN112584104A (en) * | 2020-12-09 | 2021-03-30 | 国网辽宁省电力有限公司检修分公司 | Low-power-consumption intelligent monitoring design method |
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