CN102111623A - System and method for partitioned color, double rate video transfer - Google Patents
System and method for partitioned color, double rate video transfer Download PDFInfo
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Abstract
Systems, methods and devices provide for fast and power efficient transfer of three color data words (e.g., a M-bit red color word, a M bit green color word and a M-bit blue color word) per pixel from a controller to a laser diode driver (LDD). First and second transfer words are produced based on the three color data words. The first transfer word is transferred from the controller to the LDD and stored at LDD in response to a low-to-high portion of a cycle of a data transfer clock, and the second transfer word is transferred and stored in response to a high-to-low portion of a cycle of the data transfer clock. The first, second and third color data words are reproduced by the LDD in dependence on the first and second received transfer words. First, second and third DACs of the LDD are driven with the first color data word, the second color data word, and the third color data word. Three light sources (e.g., red, green and blue laser diodes or LEDs) are driven with output currents of the DACs.
Description
Require priority
The application requires the priority of following U.S. Patent application:
The U.S. Patent application No.12/844 that is entitled as " system and method (SYSTEMS ANDMETHODS FOR PARTITIONED COLOR; DOUBLE RATE VIDEOTRANSFER) that is used for color piecemeal, dual rate video transmission " that on July 27th, 2010 was submitted to by Alexander Fairgrieve and D.Stuart Smith, 691 (file number ELAN-01248US1); And
The U.S. Patent application No.61/290 that is entitled as " system and method (SYSTEMS ANDMETHODS FOR PARTITIONED COLOR; DOUBLE RATE VIDEOTRANSFER) that is used for color piecemeal, dual rate video transmission " that on December 29th, 2009 was submitted to by Alexander Fairgrieve and D.Stuart Smith, 861 (file number ELAN-01248US0), more than two parts of applications incorporated herein by reference.
Technical field
Embodiments of the invention relate generally to from method, equipment and the system of parts to another parts (for example slave controller is to laser diode driver circuit) transmission color data word.
Background technology
Fig. 1 illustrates the exemplary micro projector display 100 that is sometimes referred to as micro-projector.This micro projector device 100 can be with integrated or attached such as, but not limited to the portable equipment of mobile phone, smart phone, portable computer (for example laptop computer or net book), personal digital assistant (PDA) or portable electronic device (for example DVD player).This micro projector device 100 is alternately with integrated or attached such as the non-portable equipment of desktop computer or media player (for example DVD player), but is not limited thereto.This micro projector device 100 also can be used for TV applications, digital image frames is used and other application.
With reference to Fig. 1, projecting apparatus display device 100 is shown as including video source 102, controller 104 (for example application-specific integrated circuit (ASIC) and/or microcontroller), laser diode driver circuit (LDD) 108 and voltage regulator 110.The type that depends on video source can comprise video simulation front end (AFE) (not shown) between video source 102 and controller 104, and this video AFE can comprise for example one or more analog to digital converters (ADC).Yet, be under the situation of digital video source in video source, may not need video AFE.This controller 106 can be carried out convergent-divergent and/or predistortion to these signals before vision signal is provided for LDD 108.The voltage transitions that voltage regulator 110 (for example four output scalable dc-dc boost-boost pressure controllers) can be provided voltage source (for example battery or AC power) becomes various voltage levels (for example four voltage level V1, V2, V3 and V4), is used for each parts power supply to projecting apparatus display device 100.
LDD 108 is shown as including three digital to analog converter DAC 109
1, 109
2And 109
3(can be referred to as DAC 109).This LDD also is shown as including serial line interface 122, and this serial line interface 122 can receive serial and enable (SEN) signal and serial clock signal (SClk) via the serial line interface of universal serial bus 103 slave controllers 104.In addition, bidirectional linked list data I/O (SDIO) circuit of universal serial bus 103 allows the register of controller 104 in LDD 108 to write data and fetches data from these register read.Can use alternative universal serial bus and interface, such as, but not limited to internal integrated circuit (12C) or serial peripheral interface (SPI) bus and interface.LDD 108 also comprises unshowned register etc.
The DAC 109 driving laser diodes 112 of LDD 108, laser diode 112 can comprise for example redness, green and blue laser diode, but are not limited thereto.Be used to drive under the situation of red (R), green (G) and blue (B) laser diode at LDD 108, LDD can be called as RGB three look laser diode driver circuits.Use such as light-emitting diode alternative light-emitting components such as (LED) also is possible.Therefore, as this term land used that makes in this article, laser diode driver circuit (LDD) can drive the light-emitting component that includes but not limited to laser diode (for example LDD alternately driving LED), except as otherwise noted.
Video data typically comprises three kinds of primary colors---red (R), green (G) and blue (B), these three kinds of primary colors are sent out as three kinds of color data words of certain length in digital system, and for example this length is respectively 10 bits under the situation of some micro projector.For each pixel, all three color data words must transfer to LDD 108 by slave controller 104.This can make data and clock rate and/or the parallel quantity that is connected (for example signal traces) high relatively.For example, be respectively under the situation of 10 bits, can use 30 parallel signal traces only to be used for slave controller 104 to LDD 108 transmission R, G and B data words at R, G and B data word.Alternatively, these 10 bits R, G and B data word can one by one send to LDD 108 by slave controller 104 on 10 same parallel signal traces, but this can need the data and the clock rate of 3 times of speed.
Summary of the invention
Some embodiment of the present invention relates generally to provide system, the method and apparatus of and power-efficient ground transmission three color data words (for example M bit red word, M bit green word and M bit blue word) quick to laser diode driver circuit (LDD) by the pixel slave controller.For example first of (the 3*M)/2 bit words transmission word is transferred to LDD and is stored in LDD to high part slave controller in response to the low of data transfer clock cycle, and for example second of (the 3*M)/2 bit words transmission word is transmitted and stores to lower part in response to the height in data transfer clock cycle, wherein M=10 and (3*M)/2=15 for example.First, second and the 3rd color data word are reproduced according to the first and second transmission words that received by LDD.First, second of LDD and the 3rd DAC are driven by the first color data word, the second color data word and the 3rd color data word.Three light sources (for example redness, green and blue laser diode) drive with the output current of DAC.
According to an embodiment, transmit and store the first transmission word to high part in response to data transfer clock signal cycle low and comprise and transmit and store all bits of the first color data word and some bits of the second color data word.In this embodiment, in response to the height in data transfer clock signal cycle to the lower part transmission with store the second transmission word and comprise transmission and store all bits of the 3rd color data word and the remaining bit of the second color data word.
According to an alternate embodiment, transmit and store the first transmission word to high part in response to data transfer clock signal cycle low and comprise and transmit and store some bits of the first color data word, some bits of the second color data word and some bits of the 3rd color data word.In this embodiment, in response to the height in data transfer clock signal cycle to the lower part transmission with store the second transmission word and comprise transmission and store the remaining bit of the first color data word, the remaining bit of the second color data word and the remaining bit of the 3rd color data word.
Embodiments of the invention also relate to laser diode driver circuit (LDD), this LDD comprises interface circuit, this interface circuit be arranged to receive data transfer clock signal, in response to the data transfer clock signal cycle low to high part receive and store the first transmission word and in response to the height in data transfer clock signal cycle to the lower part reception and store second and transmit word.In addition, this interface circuit is arranged to according to the first and second stored transmission words and produces the first color data word, the second color data word and the 3rd color data word, and wherein first, second is used to drive three DAC with the 3rd color data word.
According to an embodiment, one in the first and second transmission words that interface circuit was stored during the cycle of data transfer clock signal comprises all bits of the first color data word and some bits of the second color data word.In this embodiment, another in the transmission word stored during the cycle of data transfer clock signal of interface circuit comprises all bits of the 3rd color data word and the remaining bit of the second color data word.
According to another embodiment, one in the first and second transmission words that interface circuit was stored during the cycle of data transfer clock signal comprises some bits of the first color data word, some bits of the second color data word and some bits of the 3rd color data word.In this embodiment, another in the transmission word stored during the cycle of data transfer clock signal of interface circuit comprises the remaining bit of the first color data word, the remaining bit of the second color data word and the remaining bit of the 3rd color data word.
In an embodiment, this interface circuit comprises input data latch, multiplexer and output data latch.Thereby these input data latch are configured to store the first transmission word in response to low the latching to high part in data transfer clock signal cycle, thereby and latch to lower part in response to the height in data transfer clock signal cycle and to store second and transmit word.Multiplexer is configured to produce the first color data word, the second color data word and the 3rd color data word according to the first and second transmission words that received.Output data latch is configured to latch the first color data word, the second color data word and the 3rd color data word from multiplexer.In addition, output data latch is configured to utilize the first color data word drive the one DAC, utilizes the second color data word drive the 2nd DAC and utilizes the 3rd color data word drive the 3rd DAC.
Embodiments of the invention also relate to the system that comprises controller and laser diode driver circuit (LDD) etc.According to an embodiment, this controller is configured to each pixel acceptance is comprised the incoming video signal of first color data, second color data, the 3rd color data.In addition, this controller is configured to each pixel is produced the first transmission word and the second transmission word according to first color data, second color data and the 3rd color data.In addition, this controller is configured to via same many bit widths bus the first transmission word and the second transmission word are sent to laser diode driver circuit (LDD) during the one-period of data transfer clock signal.According to an embodiment, the LDD of this system be configured to receive data transfer clock signal, in response to the data transfer clock signal cycle low to high part receive and store the first transmission word and in response to the height in data transfer clock signal cycle to the lower part reception and store second and transmit word.In addition, LDD is configured to produce the first color data word, the second color data word and the 3rd color data word according to the first and second transmission words that received.In addition, this LDD is arranged to a DAC who utilizes the first color data word drive LDD, the 3rd DAC that utilizes the 2nd DAC of the second color data word drive LDD and utilize the 3rd color data word drive LDD.This type systematic also can comprise red light-emitting component, green luminousing element and blue light emitting device, and each in wherein red, green and the blue light emitting device is exported by the not same electric current among first, second and the 3rd DAC and driven.In certain embodiments, each in redness, green and the blue light emitting device comprises three different laser diodes.In other embodiments, each in redness, green and the blue light emitting device comprises three different light-emitting diodes.In certain embodiments, these light-emitting components can comprise the element that produces alternative and/or additional color.
Content part of the present invention has no intention to summarize all embodiment of the present invention.According to detailed description, accompanying drawing and the claim of following statement, of the present invention other will become apparent with alternate embodiment and feature, aspect and advantage.
Description of drawings
Fig. 1 is the high level block diagram of exemplary micro projector display (being sometimes referred to as micro-projector).
Fig. 2 A is used for illustrating each of three color data words is divided into two halves, transmits half of all three color data words and transmit half the exemplary sequential chart of the embodiment of the invention of remainder of all three color data words in response to the height of clock to lower part (for example at trailing edge) to high partly (for example at rising edge) in response to the low of clock.
Fig. 2 B is used for illustrating that with three color data words one is divided into two halves and sends another full color data word of a half-sum of this color data word and send the exemplary sequential chart of other embodiments of the invention of second half and the 3rd full color data word of this color data word in response to the height of clock to lower part (for example at trailing edge) to high partly (for example at rising edge) in response to the low of clock.
Fig. 3 illustrates and is modified to realize the exemplary micro projector display of specific embodiment of the present invention.
Fig. 4 A illustrates the input interface circuit of LDD according to an embodiment of the invention, and wherein this input interface circuit is decoded into three independence 10 bit words with its two 15 bit words that receive during the clock cycle, and each 10 bit words is used to drive different DAC.
Fig. 4 B is the exemplary sequential chart that is used for the interface circuit of key diagram 4A.
Fig. 4 C illustrates the exemplary additional detail according to the interface circuit of Fig. 4 A of an embodiment.
Fig. 5 A illustrates the output interface circuit that can be used for realizing the controller of the encoding scheme introduced among Fig. 2 A according to one embodiment of the invention.
Fig. 5 B illustrates the exemplary output interface circuit of the controller that can be used for realizing the encoding scheme introduced among Fig. 2 B according to another embodiment of the present invention.
Fig. 6 is the high level flow chart that is used for summarizing the whole bag of tricks of the present invention.
Description of reference numerals
Embodiment
As mentioned above, micro projector device 100 can be integrated with the portable set such as mobile phone.Because the small size of this type of portable equipment is so needs reduce the linking number between controller 104 and the LDD 108, with size and the number of pins that reduces these two chips.In addition, for cost and the power consumption that reduces these chips, need to keep data and clock speed low.For specific example, the problem that solve may be every 10ns slave controller chip 104 sends a video data word from 3 * 10 bits to LDD chip 108.If used the 100MHz clock, then need 30 parallel data pins to support this data traffic.This makes the high number of pins of application need such as micro projector, needs little overlay area chip with permission this unit to be assembled in the little space in this type of is used.Yet if data are transmitted by color order successively as three 10 bit words, clock rate has to rise to 300MHz, and this is for many application chips and Yan Taigao.
According to the embodiments of the invention of the following stated, between message transmission rate and linking number, exist compromise.In addition, according to the embodiment of the following description of the present invention, it is low by two edges that use data transfer clock data transfer clock speed to be remained.
According to a particular embodiment of the invention, the rgb video data are transmitted as two words rather than three words.For example, be two 15 bit words of transmission under the situation of every pixel 30 bits (R, G and B color each 10 bits) in the rgb video data, rather than each pixel is transmitted three independently 10 bit words between controller 104 and LDD 108.All three words of color data are divided into clock of two part permission uses.In addition, these two parts are identified easily, and need not any other synchronizing signal.
In a particular embodiment, this can be by being divided into two halves (can be called as two nibbles) with in three color data words each, and transmit half of all three color data words to high part (for example rising edge), and in response to the height of clock half to lower part (for example trailing edge) transmission remainder in response to the low of clock.For example, suppose that each color data word is 10, then each in R, G and the B data word can be divided into their 5 highest significant positions (MSB) and 5 least significant bits (LSB).5 MSB of R, G and B data can be combined (for example connecting together) to form the one 15 bit words (it can be called as the A word or the first transmission word); And 5 LSB of R, G and B data word can be combined (for example serial connection) to form the 2 15 bit words (it can be called as the B word or the second transmission word).The A word can transmit to high part in response to the low of clock, and the B word can transmit to lower part in response to the height of clock, otherwise or.Be used to transmit the exemplary sequential chart of the first and second transmission words shown in Fig. 2 A.Other combination techniques except that serial connection also are possible, and within the scope of the present invention.
In other embodiments, one of color data word (for example G data word) is divided into two halves, and half of this color data word is sent out with another complete color data word, and second half of this color data word is sent out with the 3rd complete color data word.For example, suppose that once more each color data word is 10 bits, the G data word can be divided into its 5 highest significant positions (MSB) and its 5 least significant bits (LSB).5 MSB of G data word can with 10 bit combinations (for example being connected in series) of R data word to form the one 15 bit words; And 5 LSB of G data word can with 10 bit combinations of B data word to form the 2 15 bit words.The one 15 bit words (can be called as the A word or the first transmission word) can be transmitted to high part in response to the low of clock, and the 2 15 bit words (can be called as B word or second and transmit word) can transmit to lower part in response to the height of clock, otherwise or.The exemplary sequential chart of this process is shown in Fig. 2 B.In alternate embodiment, replace the G data word is divided into two halves, also R or B data word can be divided into two halves.The other technologies that are used for generating two 15 bit transfer words based on three 10 bit color data words also are possible, and within the scope of the invention.More generally, it also is possible being used for generating two other technologies of transmitting words based on three or more color data words, and within the scope of the invention.
Each color data word can comprise more than 10 or the situation of 10 following bits also within the scope of the invention.In addition, different color data words have different bit numbers, for example the R data word be 9 bits, G data word be 10 bits and B data word be 11 bits also within the scope of the invention.For example, two 15 bit transfer words still can use the technology similar to the technology of above firm description to produce based on three color data words.In addition, the first and second transmission words do not need to have identical bit number.For example, if total bit number of different color data word is an odd number, one that then transmits in the word can be than another big 1 bit or little 1 bit.Yet, be illustrative purposes, and in order to continue, for the major part of the remaining part of this specification with reference to Fig. 2 A and the described exemplary embodiment of 2B, to suppose that three color data words are respectively 10 bits, and first and second each that transmit in the words are 15 bits.
Fig. 3 illustrates exemplary micro projector display 300, and it has been modified to realize specific embodiment of the present invention.As understanding, add output interface circuit 305 to controller 104, and add input interface circuit 307 to LDD 108 according to Fig. 3.As understanding according to Fig. 3, the output interface circuit 305 that 15 bit width buses 306 (for example 15 parallel signal traces) are used to slave controller 104 transmits 15 bits concurrently to the input interface circuit 307 of LDD 108.
According to specific embodiment, two 15 bit data word that output interface circuit 305 becomes will send during the single clock cycle with 10 bit R data words, 10 bit G data words and 10 bit B encoding of data words (one 15 bit words sends to high part in response to the low of clock, and the 2 15 bit words sends to lower part in response to the height of clock).The exemplary arrangement that is used to carry out this process and will be discussed as mentioned above hereinafter.Output interface circuit 305 can comprise latch, multiplexer and/or be used to realize 3 10 bit data word are encoded into other coding circuits of 2 15 bit data word.
According to specific embodiment, the input interface circuit 307 of LDD 108 is decoded into three independently 10 bit words with its two 15 bit words that receive during a clock cycle---and comprise 10 bit R data words, 10 bit G data words and 10 bit B data words, and utilize in three 10 bit color data words each to drive suitable DAC 109.For realizing this purpose, input interface circuit 207 can comprise for example latch, multiplexer and/or other decoder circuits.For example, with reference to Fig. 4 A, input interface circuit 307 can comprise first group of latch 414, multiplexer 424 and second group of latch 434.Also show input buffer 404 that is used for clock signal and the input buffer 402 that is used for 15 one-bit data signal among Fig. 4 A.Clock buffer 404 (be shown by inverter realize) provide clock signal (Clk) and inversion clock signal (ClkB) both, so data can be hunted down on two edges of clock signal.Preferably, dateout to two effective edges of the transmission of rising edge and trailing edge and clock signal along matched well.Where necessary, data buffer 402 provides the level locomotive function, and those logic level transition of self-controller 104 become the logic level of using in LDD 108 with future.Note, in the circuit of Fig. 4 A, the data wire of input multiplexer 424 (for example parallel signal line) is 15 bit widths, and in output place of multiplexer 424, and each bar in three data/address buss is 10 bit widths (for example three data/address buss comprise 10 parallel signal traces respectively).
The interface circuit 307 of multiplexer 424 permission LDD 108 is configured to carry out the decoding to more than one types of two 15 bit data word, thereby LDD can be worked together with using the different controllers that three 10 bit words are encoded into various types of codings of two 15 bit data word.In this type of embodiment, one or more pins of LDD 108 can accept to specify LDD should carry out the input of which kind of decoding scheme.Alternatively, the register via the programming of the serial port of LDD of LDD is used to specify LDD should carry out which kind of decoding scheme.If the interface circuit 307 of LDD 108 is configured to two 15 bit data word are only carried out one type decoding, then decoding circuit does not need to comprise multiplexer 424, and the hardwire suitably of the circuit between input data latch 414 and the output data latch 434.
If transmit control device chip 104 by the power voltage supply lower than the voltage of LDD 108, then according to one embodiment of the invention, in order to reduce power consumption, sends 15 parallel high-speed color digital data bits under the supply power voltage of transmit control device chip 104.Power loss when this has reduced the interconnection capacitance charging.Therefore, a kind of implementation will adopt from the supply power voltage of controller chip 104 the incoming level shifter buffer 402 of the interface circuit 307 of LDD 108 will be powered.For example, 15 Bit data lines 306 and Clk line can drive under the 1.8V level, because recent many high-speed controllers move under low relatively like this voltage.Although in fact LDD 108 can move under 3.3V, LDD 108 will receive this low-voltage data.This can be by comprising the supplemental powered pin (for example VSL pin) that is used for low-voltage, thereby make this circuit of interface circuit 307 inside of LDD 108 " know " that the logic threshold of data and clock input realizes.
With reference to Fig. 4 A, first group of latch 414 (being also referred to as data capture latch or data input latch device) can latch one 15 bit words to high part (for example at rising edge) in response to the low of clock, and latchs the 2 15 bit words in response to the height of clock to lower part (for example at trailing edge).This can be for example realizes by in response to the trailing edge of clock first word (being also referred to as the A word) being latched in one or more data capture latchs 414 (for example latch X among Fig. 4 A) and second word (being also referred to as the B word) being latched in one or more data capture latchs 414 (for example latch Y among Fig. 4 A) in response to the rising edge of clock, as understanding ground according to Fig. 4 B.Afterwards, when the next trailing edge of clock arrives, the data that are stored in the latch 414 will be decoded into three 10 bit color data words, and these three 10 bit color data words being stored in the data output latch 434, and are used to drive the DAC 109 of LDD 108 with ready.
Fig. 4 C illustrates the exemplary additional detail according to the circuit of Fig. 4 A after the data of an exemplary embodiment and clock buffer 402 and 404.
Fig. 5 A illustrates the exemplary output interface circuit 305 of the controller 104 that can be used for realizing the encoding scheme introduced among Fig. 2 A, and wherein 5 MSB of R, G and B data word are combined (for example serial connection) to form the one 15 bit words (can be called as the A word); 5 LSB of R, G and B data word are combined (for example serial connection) to form the 2 15 bit words (can be called as the B word).Fig. 5 B illustrates the exemplary output interface circuit 305 of the controller 104 that can be used for realizing the encoding scheme introduced among Fig. 2 B, and wherein 5 of the G data word MSB and 10 bit combinations (for example being connected in series) of R data word are to form the one 15 bit words (can be called as the A word); And 5 LSB of G data word and 10 bit combinations of B data word are to form the 2 15 bit words (can be called as the B word).In each embodiment, the A word can transmit (by suitable position is latched in the output latch) to high part in response to the low of clock, and the B word can transmit (by suitable position is latched into down in the output latch) to lower part in response to the height of clock cycle, otherwise or.
In Fig. 5 A and 5B, there are input latch 514 and the output latch 534 of being enabled and be configured to carry out especially required coding by selectivity.Some latchs are enabled by the Clk signal, and other latch is enabled by inversion clock signal ClkB.Suppose that each latch for example is configured to enable when high from low changing at the signal of enabling that offers latch, then some latchs can be enabled to high part in response to the low of Clk signal, and by anti-phase Clk signal (being ClkB) being offered the input of enabling of other latch, these other latchs can be enabled to lower part in response to the height of Clk signal.Can carry out the coding of more than one types (for example type of Fig. 2 A and 2B) if wish the output interface circuit 305 of controller 104, then can add multiplexer between input latch 514 and the output latch 534 to realize the switching between the type of coding.
In above-mentioned exemplary embodiment, each color data word is described to 10 bits.More generally, in certain embodiments, each color data word can be the M bit, wherein M equal 10, less than 10 or greater than 10, and M is preferably more than and equals 2 even number.In other embodiments, as mentioned above, each color data word does not need to have the bit of equal number.Each color data word does not need to have the even number bit yet.
In above-mentioned exemplary embodiment, describe three 10 bit words and be encoded into two 15 bit words, transfer to LDD for slave controller.More generally, in certain embodiments, three M bit words can be encoded into two (3*M)/2 bit transfer words.Vary in size and/or the total number of bits of different color data word is not among other embodiment of even number in for example different color data word, in the transmission word one can be greater than or less than another in the transmission word.
In above-mentioned exemplary embodiment, described two 15 bit words and be decoded as three 10 bit words by LDD.Yet more generally, two (3*M)/2 bit transfer words can be decoded into three M bit color data words.Even more generally, two transmission words can be decoded into three (or more a plurality of) color data words.
More than described and be used for three M bit data word are encoded into two (3*M)/2 bit data word for the exemplary embodiment of transmitting between controller and LDD.Yet, be used for three M bit data word are encoded into two (3*M)/2 bit data word for other embodiment that transmits also within the scope of the invention between controller and LDD.More generally, be used for three (or more a plurality of) color data word codes are become two transmission words for other embodiment that transmits also within the scope of the invention between controller and LDD.
The exemplary embodiment that two (3*M)/2 bit transfer words is decoded into three M bit color data words has more than been described.Yet the alternate embodiment that is used for two (3*M)/2 bit transfer words are decoded into three M bit color data words also within the scope of the invention.More generally, other embodiment that are used for two transmission words are decoded into three (or more a plurality of) color data words also within the scope of the invention.
In certain embodiments of the invention, LDD can be configured to the decoding of more than one types carried out in two transmission words, thereby makes LDD become the various controller of various types of codings of two transmission words to work three (or more a plurality of) color data word codes with using.In this type of embodiment, one or more pins of LDD can accept to specify LDD should carry out the input of which kind of decoding scheme.Alternatively, the register via the programming of the serial line interface of LDD of LDD is used to specify LDD should carry out which kind of decoding scheme.
Fig. 6 is the high level flow chart that is used for summarizing the whole bag of tricks of the present invention.Step 602,604 and 606 can be carried out by controller (for example 104), more specifically is to be carried out by the output interface circuit of controller (for example 305).Step 612,614 and 616 can be carried out by LDD (for example 108), more specifically is to be carried out by the input interface circuit of LDD (for example 307).Can understand the additional detail of each step shown in Fig. 6 based on the above discussion.
Though light-emitting component described herein is described to redness, green and blue, send also within the scope of the invention such as, but not limited to cyan, magenta and the yellow light-emitting component that removes other color light redness, green and the blueness.Light-emitting component produces color more than three kinds (for example red, green, blue and yellow) in each pixel, and the first and second transmission words produce also within the scope of the invention based on three above color data words (for example based on 4 color data words).In addition, if there are four color data words, then LDD can comprise four DAC.
Though above-mentioned specific embodiment of the present invention applies double data rate (DDR) (DDR) technology (wherein data are transmitted to lower part to high part and height in response to the low of clock cycle) to the low of clock cycle to the high part, these embodiment of the present invention just direct application of DDR technology far away.For example, transmit three M bit words in order to utilize conventional DDR technology on M bit width bus, a half clock cycle is essential.As example more specifically,, then can need a half clock cycle if conventional DDR technology is used for transmission 10 bit R data words, 10 bit G data words and 10 bit B data words on 10 bit width buses.As a comparison, use the embodiment of the invention described above, 30 bits or RGB data can be used as two (3*M)/2 bit transfer words and are transmitting on the bit width bus of (3*M)/2 during the single clock cycle.For example, utilize the above-mentioned compromise embodiments of the invention that provide between data transfer rate and the linking number, 10 bit R data words, 10 bit G data words and 10 bit B data words can transmitted on 15 bit width buses during the single clock cycle.
Foregoing description is the preferred embodiments of the present invention.Provide these embodiment for explanation and description purpose, but they are not intended to or limit the invention to disclosed precise forms exhaustive.Many modifications and variations for those of ordinary skills with obviously.
Select and described embodiment describing principle of the present invention and practical application thereof best, thereby make others skilled in the art understand the present invention.Small modifications and variations are considered within the scope and spirit of the invention.Scope of the present invention is intended to be limited by claims and equivalent technique scheme thereof.
Claims (23)
1. a laser diode driver circuit (LDD) comprising:
First digital to analog converter (DAC), a described DAC is configured to receive the first color data word, and produces first output current to drive the light source of first color according to the described first color data word;
The 2nd DAC, described the 2nd DAC is configured to receive the second color data word, and produces second output current to drive the light source of second color according to the described second color data word;
The 3rd DAC, described the 3rd DAC is configured to receive the 3rd color data word, and produces the 3rd output current to drive the light source of the 3rd color according to described the 3rd color data word; And
Interface circuit, described interface circuit is configured to
Receive data transfer clock signal, each cycle of wherein said data transfer clock signal comprises low to high part and high to lower part;
Receive and store the first transmission word in response to the described low of described data transfer clock signal cycle to high part;
Described height in response to the described data transfer clock signal cycle receives and stores the second transmission word to lower part;
Produce the described first color data word, the described second color data word and described the 3rd color data word according to the first and second transmission words of being stored; And
With the described DAC of the described first color data word drive;
With described the 2nd DAC of the described second color data word drive; And
With described the 3rd DAC of described the 3rd color data word drive.
2. LDD as claimed in claim 1 is characterized in that:
The described first color data word comprises a M bit words;
The described second color data word comprises the 2nd M bit words;
Described the 3rd color data word comprises the 3rd M bit words;
The described first transmission word comprises first (3*M)/2 bit words; And
The described second transmission word comprises second (3*M)/2 bit words.
3. LDD as claimed in claim 2 is characterized in that:
M=10; And
(3*M)/2＝15。
4. LDD as claimed in claim 1 is characterized in that:
Described first color is red;
Described second color is blue; And
Described the 3rd color is green.
5. LDD as claimed in claim 1 is characterized in that:
One in the described first and second transmission words that described interface circuit was stored during the cycle of described data transfer clock signal comprises
All bits of the described first color data word, and
Some bits of the described second color data word; And
In the described transmission word that described interface circuit was stored during the cycle of described data transfer clock signal another comprises
All bits of described the 3rd color data word, and
The remaining bit of the described second color data word.
6. LDD as claimed in claim 1 is characterized in that:
One in the described first and second transmission words that described interface circuit was stored during the cycle of described data transfer clock signal comprises
Some bits of the described first color data word,
Some bits of the described second color data word, and
Some bits of described the 3rd color data word; And
In the described transmission word that described interface circuit was stored during the cycle of described data transfer clock signal another comprises
The remaining bit of the described first color data word,
The remaining bit of the described second color data word, and
The remaining bit of described the 3rd color data word.
7. LDD as claimed in claim 1 is characterized in that, described interface circuit comprises:
Input data latch, described input data latch is configured to
Thereby described low the latching to high part in response to the described data transfer clock signal cycle stored the described first transmission word; And
Thereby latch to lower part in response to the described height in described data transfer clock signal cycle and to store the described second transmission word;
Multiplexer, described multiplexer are arranged to according to the first and second transmission words that received and produce the described first color data word, the described second color data word and described the 3rd color data word; And
Output data latch, described output data latch is arranged to
Latch the described first color data word from described multiplexer, the described second color data word and described the 3rd color data word;
With the described DAC of the described first color data word drive;
With described the 2nd DAC of the described second color data word drive; And
With described the 3rd DAC of described the 3rd color data word drive.
8. method that is used for laser diode driver circuit (LDD), described laser diode driver circuit comprises
First digital to analog converter (DAC), a described DAC is configured to receive the first color data word, and produces first output current driving the light source of first color according to the described first color data word,
The 2nd DAC, described the 2nd DAC is configured to receive the second color data word, and produces second output current driving the light source of second color according to the described second color data word, and
The 3rd DAC, described the 3rd DAC is configured to receive the 3rd color data word, and produces the 3rd output current driving the light source of the 3rd color according to described the 3rd color data word,
Described method comprises:
Receive data transfer clock signal, each cycle of wherein said data transfer clock signal comprises low to high part and high to lower part;
Receive and store the first transmission word in response to the described low of described data transfer clock signal cycle to high part;
Described height in response to the described data transfer clock signal cycle receives and stores the second transmission word to lower part;
Produce the described first color data word, the described second color data word and described the 3rd color data word according to the first and second transmission words that received;
With the described DAC of the described first color data word drive;
With described the 2nd DAC of the described second color data word drive; And
With described the 3rd DAC of described the 3rd color data word drive.
9. method as claimed in claim 8 is characterized in that:
The described first color data word comprises a M bit words;
The described second color data word comprises the 2nd M bit words;
Described the 3rd color data word comprises the 3rd M bit words;
The described first transmission word comprises first (3*M)/2 bit words; And
The described second transmission word comprises second (3*M)/2 bit words.
10. method as claimed in claim 9 is characterized in that:
M=10; And
(3*M)/2＝15。
11. method as claimed in claim 8 is characterized in that:
Described first color is red;
Described second color is blue; And
Described the 3rd color is green.
12. method as claimed in claim 8 is characterized in that:
Receive and storage described low the comprising to the high step that partly receives and store the described first transmission word in response to the described data transfer clock signal cycle
All bits of the described first color data word, and
Some bits of the described second color data word; And
Described height in response to the described data transfer clock signal cycle comprises reception and storage to the step that lower part received and stored the described second transmission word
All bits of described the 3rd color data word, and
The remaining bit of the described second color data word.
13. method as claimed in claim 8 is characterized in that:
Receive and storage described low the comprising to the high step that partly receives and store the described first transmission word in response to the described data transfer clock signal cycle
Some bits of the described first color data word,
Some bits of the described second color data word, and
Some bits of described the 3rd color data word; And
Described height in response to the described data transfer clock signal cycle comprises reception and storage to the step that lower part received and stored the described second transmission word
The remaining bit of the described first color data word,
The remaining bit of the described second color data word, and
The remaining bit of described the 3rd color data word.
14. method as claimed in claim 8 is characterized in that, also comprises:
Described first output current that is produced with a described DAC drives the light source of described first color;
Described second output current that is produced with described the 2nd DAC drives the light source of described second color; And
Described the 3rd output current that is produced with described the 3rd DAC drives the light source of described the 3rd color.
15. a system comprises:
Controller, described controller is configured to
Each pixel is accepted to comprise the incoming video signal of first color data, second color data and the 3rd color data;
Each pixel is produced the first transmission word and the second transmission word according to described first color data, described second color data and described the 3rd color data; And
During the one-period of data transfer clock signal, described first transmission word and the described second transmission word are sent to laser diode driver circuit (LDD) via same many bit widths bus.
16. system as claimed in claim 15 is characterized in that
Described first color data of each pixel, described second color data and described the 3rd color data comprise M bit first color data, M bit second color data and M bit the 3rd color data; And
The described first transmission word comprises first (3*M)/2 bit words;
The described second transmission word comprises second (3*M)/2 bit words; And
Described controller is configured to via same (3*M)/2 bit width bus described first and second (3*M)/2 bit words are sent to described LDD during the one-period of described data transfer clock signal.
17. system as claimed in claim 15, it is characterized in that, described controller comprises latch, and described latch is arranged to each pixel is produced described first transmission word and the described second transmission word according to described first color data, described second color data and described the 3rd color data.
18. system as claimed in claim 15, it is characterized in that, described controller also is configured at least one in described incoming video signal execution convergent-divergent and the predistortion, so that the scaled and/or predistortion of color data in described first transmission word and the described second transmission word.
19. system as claimed in claim 15 is characterized in that, also comprises:
Laser diode driver circuit (LDD), described laser diode driver circuit is configured to:
Receive described data transfer clock signal, each cycle of wherein said data transfer clock signal comprises low to high part and high to lower part;
Receive and store the described first transmission word in response to the described low of described data transfer clock signal cycle to high part;
Described height in response to the described data transfer clock signal cycle receives and stores the described second transmission word to lower part;
Produce described first color data, described second color data and described the 3rd color data according to the first and second transmission words that received; And
Drive the DAC of described LDD with described first color data;
Drive the 2nd DAC of described LDD with described second color data; And
Drive the 3rd DAC of described LDD with described the 3rd color data.
20. system as claimed in claim 19 is characterized in that, also comprises:
Red light-emitting component;
Green luminousing element; And
Blue light emitting device;
In wherein said redness, green and the blue light emitting device each is exported by the not same electric current among described first, second and the 3rd DAC and is driven.
21. system as claimed in claim 20 is characterized in that, each in described redness, green and the blue light emitting device comprises three different laser diodes or three different light-emitting diodes.
22. a method comprises:
Each pixel is accepted to comprise the incoming video signal of first color data, second color data and the 3rd color data;
Each pixel is produced the first transmission word and the second transmission word according to described first color data, described second color data and described the 3rd color data; And
During the one-period of data transfer clock signal, described first transmission word and the described second transmission word are sent to laser diode driver circuit (LDD) via same many bit widths bus.
23. method as claimed in claim 22 is characterized in that:
Described first color data of each pixel, described second color data and described the 3rd color data comprise M bit first color data, M bit second color data and M bit the 3rd color data; And
The described first transmission word comprises first (3*M)/2 bit words;
The described second transmission word comprises second (3*M)/2 bit words; And
Described transmission is sent to described LDD via same (3*M)/2 bit width bus with described first and second (3*M)/2 bit words during being included in the one-period of described data transfer clock signal.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US29086109P | 2009-12-29 | 2009-12-29 | |
| US61/290,861 | 2009-12-29 | ||
| US12/844,691 US8384832B2 (en) | 2009-12-29 | 2010-07-27 | Systems and methods for partitioned color, double rate video transfer |
| US12/844,691 | 2010-07-27 |
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| Publication Number | Publication Date |
|---|---|
| CN102111623A true CN102111623A (en) | 2011-06-29 |
| CN102111623B CN102111623B (en) | 2014-01-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201010623642.9A Active CN102111623B (en) | 2009-12-29 | 2010-12-28 | System and method for partitioned color, double rate video transfer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104639922A (en) * | 2015-02-06 | 2015-05-20 | 陈思源 | Digital projection device capable of realizing ultra-definition replay |
| CN108702554A (en) * | 2016-02-18 | 2018-10-23 | 罗伯特·博世有限公司 | It is used for transmission the method with the measured value of receiving sensor |
| CN111025991A (en) * | 2019-12-25 | 2020-04-17 | 深圳万讯自控股份有限公司 | High-density signal input and output circuit and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1274862A (en) * | 1999-05-25 | 2000-11-29 | 三星电子株式会社 | Method and apparatus for controlling power of laser diode |
| US20060227087A1 (en) * | 2005-04-01 | 2006-10-12 | Hajjar Roger A | Laser displays using UV-excitable phosphors emitting visible colored light |
| US7511771B2 (en) * | 2005-10-31 | 2009-03-31 | Symbol Technologies, Inc. | Color image projection system and method |
-
2010
- 2010-12-28 CN CN201010623642.9A patent/CN102111623B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1274862A (en) * | 1999-05-25 | 2000-11-29 | 三星电子株式会社 | Method and apparatus for controlling power of laser diode |
| US20060227087A1 (en) * | 2005-04-01 | 2006-10-12 | Hajjar Roger A | Laser displays using UV-excitable phosphors emitting visible colored light |
| US7511771B2 (en) * | 2005-10-31 | 2009-03-31 | Symbol Technologies, Inc. | Color image projection system and method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104639922A (en) * | 2015-02-06 | 2015-05-20 | 陈思源 | Digital projection device capable of realizing ultra-definition replay |
| CN108702554A (en) * | 2016-02-18 | 2018-10-23 | 罗伯特·博世有限公司 | It is used for transmission the method with the measured value of receiving sensor |
| CN111025991A (en) * | 2019-12-25 | 2020-04-17 | 深圳万讯自控股份有限公司 | High-density signal input and output circuit and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102111623B (en) | 2014-01-22 |
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