CN102074537B - Chip packaging cell - Google Patents

Chip packaging cell Download PDF

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Publication number
CN102074537B
CN102074537B CN 201010547855 CN201010547855A CN102074537B CN 102074537 B CN102074537 B CN 102074537B CN 201010547855 CN201010547855 CN 201010547855 CN 201010547855 A CN201010547855 A CN 201010547855A CN 102074537 B CN102074537 B CN 102074537B
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CN
China
Prior art keywords
chip packaging
packaging unit
chip
conductive structure
active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 201010547855
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Chinese (zh)
Other versions
CN102074537A (en
Inventor
黄祥铭
刘安鸿
李宜璋
蔡豪殷
何淑静
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ChipMOS Technologies Bermuda Ltd
ChipMOS Technologies Inc
Original Assignee
ChipMOS Technologies Bermuda Ltd
ChipMOS Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by ChipMOS Technologies Bermuda Ltd, ChipMOS Technologies Inc filed Critical ChipMOS Technologies Bermuda Ltd
Priority to CN 201010547855 priority Critical patent/CN102074537B/en
Publication of CN102074537A publication Critical patent/CN102074537A/en
Application granted granted Critical
Publication of CN102074537B publication Critical patent/CN102074537B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Abstract

The invention provides a chip packaging cell which is suitable for being electrically stacked with another chip packaging cell of the same structure. The chip packaging cell comprises a chip and two conductive structures, wherein each conductive structure is electrically connected with an active surface by virtue of a first surface via a first end area and buckles along one end face of the chip; and each second end area of the chip packaging cell is suitable for being electrically connected with a second surface of a corresponding conductive structure of another chip packaging cell by virtue of a first surface.

Description

Chip packaging unit
The application be the applicant on May 15th, 2008 submit to, application number is 200810098834.5, denomination of invention is divided an application for the application for a patent for invention of " chip packaging unit ",
Technical field
The invention relates to a kind of chip packaging unit; Particularly about can be applicable to a chip packaging unit that stacks encapsulating structure.
Background technology
Along with the progress of semiconductor technology, various encapsulation technologies have been widely used in the various electronic products.The technology that for example chip packaging unit of chip packaging unit and another basic identical structure is stacked in the electric connection mode, this prior art can be inserted more highdensity chip not increasing under the board area condition.Therefore when electronic product need to be saved circuit board and takes up space, chip packaging unit just became indispensable assembly.
Prior art has proposed to realize that the encapsulation that chip packaging unit is used stacks framework, and present known prior art discloses and utilizes a lead frame to be used as being electrically connected the intermediary layer of chip packaging unit, and please refer to the drawing 1 is so that explanation.
The schematic diagram of Fig. 1 example that to be a known chip packaging unit 1 stack with another chip packaging unit 1a, its chip packaging unit 1 has basic identical structure with another chip packaging unit 1a.Chip packaging unit 1 comprises a chip 10 and a lead frame 11.Have a first surface 12 and a second surface 13 at this lead frame 11, and this lead frame 11 includes a plurality of pin through holes (Pin Through Hole, PTH) 14, respectively this pin through hole 14 has corresponding respectively this solder joint projection 15 for 13 times at second surface, so forms a chip packaging unit 1.Respectively this solder joint projection 15 of one chip packaging unit 1 is electrically connected with a plurality of pin through holes of another chip packaging unit 1a 16, and its electric connection place is affixed with a tin cream 17, this tin cream 17 can assist and reinforced company's connecting structure firmly.And the chip packaging unit 1 after will stacking is electrically connected on the printed circuit board (PCB) 18.
Fig. 2 is the schematic diagram of the example of a known chip packaging unit 2 when stacking with another chip packaging unit 2a, and its chip packaging unit 2 has basic identical structure with another chip packaging unit 2a.The present embodiment and last embodiment difference are that a chip packaging unit 2 respectively uses respectively a plurality of solder joint projections 24 to be used as the electric connection mode on the first surface 22 of lead frame 21 and second surface 23.Its mode is for form respectively a solder joint projection 24 on the first surface 22 of respectively these a plurality of pin through holes 25 of chip packaging unit 2 and second surface 23, chip packaging unit 2a with another same structure stacks whereby, respectively this solder joint projection 24 and these pin through hole 25 electric connections place respectively with a tin cream 26 auxiliary with the reinforcement stabilized structures.And being electrically connected on the printed circuit board (PCB) 27 of stacking of chip packaging unit 2 after will stacking.
As a rule, stacking of chip packaging unit 1 needs to do electric connection by pin through hole 14 usefulness solder joint projections 15 on lead frame 11, but the thickness of solder joint projection 15 is quite thick, it has occupied the space that major part stacks, and makes this chip packaging unit 1 and the stacking structure that chip packaging unit 1a carries out have suitable thickness.Simultaneously solder joint projection 15 easily causes the crack at the contact place, causes quality related cost to increase.And general traditional die encapsulation unit is non-wafer-level package (Non Chip Scale Package), and the pin size of its chip after encapsulation is larger, causes its chip packaging unit area larger, causes the encapsulating structure internal heat dissipating bad when stacking.
In view of this, provide a kind of chip packaging unit of improvement, make the integral thickness reduction after stacking, and make contact place not easy fracture and then minimizing quality related cost, for this reason an industry problem demanding prompt solution.
Summary of the invention
The object of the present invention is to provide a kind of chip packaging unit, between chip packaging unit and chip packaging unit, adopt a lead frame, so that a conductive path to be provided.Come with stacking between affixed each chip packaging unit with the dull and stereotyped soldered ball of single face on this lead frame, suitablely electrically stack with the chip packaging unit with another basic identical structure.Whereby, can reach and lower the purpose that stacks rear chip packaging unit thickness, make the integral thickness reduction after stacking, reduce simultaneously process costs.
Another object of the present invention is to provide a kind of chip packaging unit, between chip packaging unit and chip packaging unit, adopt a lead frame or a flexible base plate, so that a conductive path to be provided.Come stacking between affixed each chip packaging unit with two-sided dull and stereotyped soldered ball on this lead frame, suitablely electrically stack with the chip packaging unit with another basic identical structure.Whereby, can reach and lower the purpose that stacks rear chip packaging unit thickness, make the integral thickness reduction after stacking, and reduce manufacturing cost.
For reaching above-mentioned purpose, the present invention discloses a kind of chip packaging unit, fits electrically to stack with the chip packaging unit with another basic identical structure.This chip packaging unit comprises a chip and two conductive structures.This chip has biend and is positioned at a active surface between this biend.Respectively this conductive structure has a first end zone the second end zone, a first surface and with this a first surface relative second surface relative with this first end zone.Respectively this conductive structure is electrically connected with this first surface and this active surface by this first end zone, and bends along a wherein end face of this chip.This first surface suitablely can be passed through in the second end of this chip packaging unit zone whereby, is electric connection with a second surface of the corresponding conductive structure of this another chip packaging unit.
The present invention also discloses a kind of chip packaging unit, fits electrically to stack with the chip packaging unit with another basic identical structure.This chip packaging unit comprises a chip and two conductive structures.This chip has biend and is positioned at a active surface between this biend and one non-active.Respectively this conductive structure has first end zone, the second end zone, a first surface relative with this first end zone reaches a second surface relative with this first surface.Respectively this conductive structure is by this first end zone, with this first surface and the electric connection of this active surface, and along the wherein end face of this chip, is bent on this non-active.This second surface suitablely can be passed through in the second end of this chip zone whereby, is electric connection with a second surface of the corresponding conductive structure of this another chip packaging unit.
Description of drawings
For above-mentioned purpose of the present invention, technical characterictic and advantage can be become apparent, the below will cooperate accompanying drawing that preferred embodiment of the present invention is elaborated, wherein:
Fig. 1 is the schematic diagram of the example that stacks of known chip packaging unit and another chip packaging unit;
Fig. 2 is known chip packaging unit and the schematic diagram of another chip packaging unit another different electric connection mode one examples when stacking;
Fig. 3 is the schematic diagram of an embodiment of the structure of chip packaging unit of the present invention;
Fig. 4 is the embodiment schematic diagram that the chip packaging unit of chip packaging unit of the present invention and another basic identical structure electrically stacks;
Fig. 5 is another embodiment schematic diagram of the another kind of chip packaging unit of the present invention;
Fig. 6 is that the chip packaging unit of chip packaging unit of the present invention and another basic identical structure electrically stacks another embodiment schematic diagram;
Fig. 7 is another embodiment schematic diagram of the structure of another chip packaging unit of the present invention;
Fig. 8 is another embodiment schematic diagram that the chip packaging unit of another chip packaging unit of the present invention and another basic identical structure electrically stacks; And
Fig. 9 is another embodiment schematic diagram of the structure of another chip packaging unit of the present invention.
The main element symbol description:
1 chip packaging unit 1a chip packaging unit
10 chips, 11 lead frames
12 first surfaces, 13 second surfaces
14 pin through holes, 15 solder joint projections
16 pin through holes, 17 tin creams
18 printed circuit board (PCB)s, 2 chip packaging units
2a chip packaging unit 21 lead frames
22 first surfaces, 23 second surfaces
24 solder joint projections, 25 pin through holes
26 tin creams, 27 printed circuit board (PCB)s
3 chip packaging units, 30 chips
31a conductive structure 31b conductive structure
32a end face 32b end face
33 active surfaces, 34 first ends zone
35 the second ends zone, 36 first surfaces
37 second surfaces, 38 liners
39 first connectors, 4 chip packaging units
40a conductive structure 40b conductive structure
41 second surfaces, 42 second connectors
43 heat abstractors, 44 printed circuit board (PCB)s
5 chip packaging units, 50 chips
51a conductive structure 51b conductive structure
52a end face 52b end face
54 non-active of 53 active surfaces
56 the second ends zone, 55 first ends zone
57 first surfaces, 58 second surfaces
59 liners, 6 chip packaging units
60 first connectors, 61 second connectors
62a conductive structure 62b conductive structure
63 second surfaces, 64 first strutting pieces
65 printed circuit board (PCB)s, 7 chip packaging units
70 flexible base plate 70a conductive structures
72 the second ends zone, 71 first ends zone
73 first surfaces, 74 second surfaces
76 non-active of 75 chips
77a end face 77b end face
78 active surfaces, 79 liners
8 chip packaging units, 80 first connectors
81 conductive structures, 82 second surfaces
83 second connectors, 84 first strutting pieces
85 printed circuit board (PCB)s, 9 chip packaging units
90 crystal grain, 91 conductive structures
92 weld pads, 93 first connectors
Embodiment
Below will explain content of the present invention by embodiment, it is about a kind of chip packaging unit, fit and electrically stack with the chip packaging unit with another basic identical structure, lower the purpose that stacks rear chip packaging unit thickness to reach, and improve in the prior art and come the shortcoming as conductive path with pin through hole, solder joint projection.Yet embodiments of the invention are not to limit the present invention to need can implement such as the described any specific environment of embodiment, application or particular form.Explanation about embodiment only is explaination purpose of the present invention, but not in order to limit the present invention.Need the expositor, in following examples and the accompanying drawing, omit and do not illustrate with the non-directly related assembly of the present invention; And for the purpose of asking easy understanding, the size relationship of each inter-module is to show with slightly exaggerative ratio.
Fig. 3 is the schematic diagram of an embodiment of chip packaging unit 3 of the present invention.Should be noted that, this chip packaging unit 3 is applicable to a little spacing solder ball array encapsulation (Fine pitch Ball Grid Array, FBGA), and it is a kind of encapsulated type of wafer-level package.Generally speaking, the Area Ratio of the area of chip and the front chip of encapsulation was less than 20 percent after wafer-level package was defined as and encapsulates.Chip packaging unit 3 comprises a chip 30 and two conductive structure 31a and 31b.This chip 30 has biend 32a and 32b and an active surface 33, and this active surface 33 is positioned between this biend 32a and 32b.Respectively this conductive structure 31a and 31b have a first end zone 34, a second end zone 35 relative with this first end zone 34, a first surface 36 and a second surface 37 relative with this first surface 36.Particularly, the material of each conductive structure 31a and 31b in the present embodiment, made by copper, but be not limited with this material in other embodiments, also can be used as material such as aluminium, gold, silver, chromium, palladium, tungsten, nickel and the platinum etc. of conductive structure 31a and 31b such as other metal, with the purpose of bringing into play electrical conduction and can supporting.Respectively this conductive structure 31a and 31b by this first end zone 34, are electrically connected with this first surface 36 and this active surface 33, and bend along a wherein end face 32a and the 32b of this chip 30.In the present embodiment, have a plurality of liners 38 on the active surface 33 of chip 30, namely by these liners, electrically connect is to chip 30 for conductive structure 31a and 31b.Therefore, conductive structure 31a and 31b can have the profile of microdactylia shape, with the distribution of corresponding these liners 38.
Please continue with reference to figure 3, after the conductive structure 31a of chip packaging unit 3 and 31b are bent into an obtuse angle along the wherein end face 32a of this chip 30 and 32b, the suitable both sides that can be positioned at the obtuse angle in its first end zone and the second end zone, so just can electrically stack with the chip packaging unit 4 of another basic identical structure after the bending, its content will describe in detail in Fig. 4.What need further specify is that a plurality of the first connectors 39 are formed at respectively this first end zone 34 in Fig. 3, so that the active surface 33 of this chip is electrically connected by these first connectors 39 this first surface 36 with this conductive structure 31a and 31b.Particularly in the present embodiment, this first connector 39 is the flat soldered balls of single face, is used as the electric connection of chip packaging unit 3 chips 30 and conductive structure 31a and 31b.
Please continue with reference to figure 4, its embodiment schematic diagram that to be chip packaging unit of the present invention 3 electrically stack with the chip packaging unit 4 of another basic identical structure, electrically stack by the chip packaging unit 4 of the chip packaging unit 3 after the bending with another basic identical structure, it stacks the second end zone 35 that mode is chip packaging unit 3, fit and to pass through this first surface 36, be electric connection with the corresponding conductive structure 40a of this another chip packaging unit 4 and the second surface 41 of 40b.
Furtherly, a plurality of the second connectors 42 are formed at respectively this second end zone 35 of this chip packaging unit 3, so that chip packaging unit 3 is electric connection by these second connectors 42 with the corresponding conductive structure 40a of this another chip packaging unit 4 and this second surface 41 of 40b.
In the present embodiment, this second connector 42 is flat tin balls, compares down with the solder joint projection that prior art uses, and flat tin ball thickness is relatively thin, but can once finish the manufacturing of all flat tin balls, be difficult for simultaneously occuring the situations such as the fracture of tin ball or bad connection.It should be noted that, optionally can install a heat abstractor 43 in the top of chip packaging unit 4, to help heat radiation, these heat abstractor 43 alternatives are considered according to technique and are determined whether adding.
This chip packaging unit 3 after stacking can be located on the printed circuit board (PCB) 44.Should be noted that respectively respectively this conductive structure 31a and the 31b of this chip packaging unit 3 are designed to have 50 ohms impedance match, can do impedance matching with other circuit, much more no longer the method and the structure that design 50 ohms impedance match are not emphasis of the present invention, to explain at this.
Fig. 5 is another embodiment schematic diagram of the another kind of chip packaging unit 5 of the present invention, and this chip packaging unit 5 comprises a chip 50 and two conductive structure 51a and 51b.In this embodiment this chip packaging unit 5 that must illustrate is a little spacing solder ball array encapsulation, has illustrated at last embodiment not repeat them here.This chip has biend 52a and 52b and is positioned at a active surface 53 between this biend 52a and 52b and one non-active 54.Respectively this conductive structure 51a and 51b have the relative the second end zone 56 in first end zone 55 and this first end zone 55, a first surface 57 and a second surface 58 relative with this first surface 57.The material of conductive structure 51a and 51b in the present embodiment, made by copper, but be not limited with this material in other embodiments, also can be used as material such as aluminium, gold, silver, chromium, palladium, tungsten, nickel and the platinum etc. of conductive structure 51a and 51b such as other metal, with the purpose of bringing into play electrical conduction and can supporting.Respectively this conductive structure 51a and 51b are electrically connected with this first surface 57 and this active surface 53 by this first end zone 55, and along wherein end face 52a and the 52b of this chip 50, are bent on this non-active 54.In the present embodiment, have a plurality of liners 59 on the active surface 53 of chip 50, namely by these liners, electrically connect is to chip 50 for conductive structure 51a and 51b.Therefore, conductive structure 51a and 51b can have the profile of microdactylia shape, with the distribution of corresponding these liners.
Please continue with reference to figure 5, conductive structure 51a in the present embodiment and 51b are a lead frame (Lead frame), but can be in other embodiments a flexible base plate, but be not limited with this material, for example other circuit board material also can be used as the material of conductive structure 51a and 51b, to bring into play the purpose of electrical conduction.The second end zone 56 of this chip 50 is fitted and can be passed through this second surface 58 whereby, is electric connection with the corresponding conductive structure 62a of this another chip packaging unit 6 and the second surface 63 of 62b, and its detailed content illustrates in Fig. 6.What need illustrate further is that a plurality of first connectors 60 of chip packaging unit 5 are formed at respectively this first end zone 55, so that this active surface 53 of this chip 50 is electrically connected by these first connectors 60 this first surface 57 with this conductive structure 51a and 51b.In the present embodiment respectively this first connector 60 are flat tin balls, can utilize once the mode of coating or transfer printing that flat tin sphere is formed in respectively this first end zone 55.The material of the first connector 60 is not defined as flat tin ball, and the tin ball that forms of alternate manner for example, but perhaps other electric conducting material are to bring into play electrical conduction and can connect the purpose of the first connector 60 and active surface 53.
Fig. 6 is another embodiment schematic diagram that the chip packaging unit 6 of chip packaging unit 5 of the present invention and another basic identical structure electrically stacks, and electrically stacks by the chip packaging unit 6 of the chip packaging unit 5 after the bending with another basic identical structure.Specifically, it stacks a plurality of the second connectors 61 that mode is chip packaging unit 5, be formed at respectively this second end zone 56, so that chip packaging unit 5 is electric connection by the corresponding conductive structure 62a of these another chip packaging units 6 of the second connector 61 and this and this second surface 63 of 62b.Chip packaging unit 5 in the present embodiment, this second connector 61 are flat tin balls, connecting material that can be when stacking as two chip packaging units, and as aforementioned, flat tin ball is not as restriction of the present invention.
This chip packaging unit 5 also comprises a plurality of the first strutting pieces 64, is formed between this second end 56 of respectively this conductive structure 51a and 51b and this chip 50 this non-active 54.This first strutting piece 64 can be used to support conductive structure 51a and the 51b in this example.It should be noted that this chip packaging unit 5 after stacking can be located on the printed circuit board (PCB) 65 and with its electric connection.Much more no longer and respectively respectively this conductive structure 51a of this chip packaging unit 5 and 51b are designed to have 50 ohm, can do impedance matching with other circuit, and the method and the structure that design 50 ohms impedance match are not emphasis of the present invention, to explain at this.
Fig. 7 is another embodiment schematic diagram of the structure of another chip packaging unit 7 of the present invention, this chip packaging unit 7 comprises a flexible base plate 70, it has a first surface 73 and a second surface 74 relative with this first surface 73, on first surface 73 and the second surface 74, respectively be formed with a patterned conductive layer, whereby, two conductive structures can be formed at respectively the both sides of this flexible base plate 70.Chip packaging unit 7 can be a little spacing solder ball array encapsulation, and its advantage does not repeat them here as aforementioned.
Take the conductive structure 70a in left side as example, it has first end zone 71 and relative one second end regions 72, first surface 73 and second surface 74.This conductive structure 70a is electrically connected with the active surface 78 of this first surface 73 with this chip 75 by this first end zone 71.This flexible base plate 70 and along biend 77a and the 77b of this chip 75 is bent to respectively on this active surface 78.In the present embodiment, have a plurality of liners 79 on the active surface 78 of chip 75, namely by these liners 79, electrically connect is to chip 75 for conductive structure 70a.
Please continue with reference to figure 7, chip packaging unit 7 also comprises a plurality of the first connectors 80, be formed at respectively on this first surface 73, be electrically connected with this conductive structure 70a by these a plurality of first connectors 80, and can between flexible base plate 70 and chip 75, inject the chip sticky material and come affixed this flexible base plate 70 and this chip 75.Respectively this first connector 80 is flat tin balls in this embodiment, and its advantage is not being given unnecessary details at this as aforementioned.Chip packaging unit 7 also comprises a plurality of the first strutting pieces 84, and take conductive structure 70a as example, first claims between the second end 72 that part 84 is formed at conductive structure 70a and chip 75 non-active 76.
Fig. 8 is another embodiment schematic diagram that the chip packaging unit 8 of another chip packaging unit 7 of the present invention and another basic identical structure electrically stacks.It stacks, and the conductive structure 70a of mode after for bending is suitable can to pass through this second surface 74, is electric connection with a second surface 82 of the corresponding conductive structure 81 of this another chip packaging unit 8.Further specify this embodiment chips encapsulation unit 7 and 8 s' electric connection mode, by a plurality of the second connectors 83, be formed on the second surface 74, so that chip packaging unit 7 is by these second connectors 83, be electric connection with this second surface 82 of the corresponding conductive structure 81 of this another chip packaging unit 8.In the chip packaging unit 7, respectively this second connector 83 is flat tin balls, and its advantage is not being given unnecessary details at this as aforementioned.
This chip packaging unit 7 after stacking can be located on the printed circuit board (PCB) 85 and with its electric connection.Much more no longer this conductive structure 70a is designed to have 50 ohms impedance match in this embodiment, can do impedance matching with other circuit, and the method and the structure that design 50 ohms impedance match are not emphasis of the present invention, to explain at this.
Fig. 9 is another embodiment schematic diagram of the structure of another chip packaging unit 9 of the present invention.Be that with the Main Differences part of previous embodiment the chip of chip packaging unit 9 is a crystal grain 90.Should be noted, take conductive structure 91 as example, adapt to the manufacture process needs, before conductive structure 91 bendings coat crystal grain 90, can utilize the weld pad 92 at crystal grain 90 to use electroless nickel plating gold process technology, form a plurality of the first connectors 93, be overmolding to a chip packaging unit 9 by conductive structure 91 bendings again.
By the chip packaging unit of aforementioned exposure, use lead frame and flexible base plate as the intermediary layer that is electrically connected, on technique, need not make too large change, can avoid the increase of manufacturing cost.
The present invention uses little spacing solder ball array encapsulation in chip packaging unit, and it is applicable to wafer-level package (Chip Scale Package), with prior art in comparison, this chip packaging unit area is less, and the pin size of chip is also less.General traditional die encapsulation unit easily causes the encapsulating structure internal heat dissipating bad when stacking.For heat dissipation problem, the present invention can place in the top heat abstractor to help heat radiation after chip packaging unit stacks.
In the prior art, the stacking structure of this chip packaging unit is used as being electrically connected the stacking structure that makes this chip packaging unit with the solder joint projection and has thicker thickness, and the present invention uses the relative attenuation of chip packaging unit thickness in little spacing solder ball array encapsulation technology.It mainly adopts flat tin ball at electrical joint, overcomes the shortcoming of prior art solder joint projection, relatively reduces the thickness that stacks of chip packaging unit.The solder joint projection easily causes the crack at the contact place simultaneously, causes quality related cost to increase.The flat tin ball of the present invention is not easy to occur the crack than prior art.
The above embodiments only are used for exemplifying enforcement aspect of the present invention, and explain technical characterictic of the present invention, are not to limit protection category of the present invention.Any be familiar with this operator can unlabored change or the arrangement of isotropism all belong to the scope that the present invention advocates, the scope of the present invention should be as the criterion with the application's claim scope.

Claims (3)

1. chip packaging unit suitablely electrically stacks with the chip packaging unit with another same structure, and this chip packaging unit comprises:
One chip has biend and is positioned at a active surface between this biend and one non-active; Two conductive structures, respectively this conductive structure has first end zone, the second end zone, a first surface relative with this first end zone reaches a second surface relative with this first surface; Wherein respectively this conductive structure is a flexible base plate, and by this first end zone, with this first surface and the electric connection of this active surface, and along the wherein end face of this chip, is bent on this non-active;
A plurality of the first connectors are formed at respectively this first end zone, and
A plurality of the second connectors are formed at respectively respectively this second end zone;
Whereby, this active surface of this chip is electrically connected by this first surface of these the first connectors and this conductive structure, and the second end of this chip zone, suitable can pass through these second connectors, be electric connection by a second surface of the corresponding conductive structure of this another chip packaging unit of second surface and this.
2. chip packaging unit according to claim 1, it is characterized in that respectively this first connector be a flat tin ball and respectively this conductive structure be one to be designed to have the flexible base plate of 50 ohms impedance match, this chip packaging unit also comprises a plurality of the first strutting pieces, is formed between this second end of this conductive structure respectively and this chip this non-active.
3. chip packaging unit according to claim 1, it is characterized in that respectively this first connector be a flat tin ball and respectively this conductive structure be one to be designed to have the lead frame of 50 ohms impedance match.
CN 201010547855 2008-05-15 2008-05-15 Chip packaging cell Expired - Fee Related CN102074537B (en)

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Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
CN 201010547855 CN102074537B (en) 2008-05-15 2008-05-15 Chip packaging cell

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CN 200810098834 Division CN101582401B (en) 2008-05-15 2008-05-15 Chip packaging unit

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CN102074537B true CN102074537B (en) 2013-02-13

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996587A (en) * 1989-04-10 1991-02-26 International Business Machines Corporation Integrated semiconductor chip package
CN1893063A (en) * 2005-07-07 2007-01-10 海力士半导体有限公司 Stack type package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996587A (en) * 1989-04-10 1991-02-26 International Business Machines Corporation Integrated semiconductor chip package
CN1893063A (en) * 2005-07-07 2007-01-10 海力士半导体有限公司 Stack type package

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