CN102054871A - High-speed semiconductor device structure and forming method thereof - Google Patents
High-speed semiconductor device structure and forming method thereof Download PDFInfo
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Abstract
The invention provides a high-speed semiconductor device structure and a forming method thereof. The structure comprises a substrate, a Ge-containing strained layer formed on the substrate, an Si cap layer formed on the Ge-containing strained layer, a T-shaped gate structure formed on a part of the Si cap layer and covering the groove, and a source electrode and a drain electrode formed on the two sides of the T-shaped gate structure, wherein the Ge-containing strained layer has a groove. In the positive channel metal oxide semiconductor (PMOS) device structure of the embodiment of the invention, the two strained SiGe layers or Si layers with low Ge content on and below the strained SiGe layer or the strained Ge layer with high Ge content are arranged, so that a hole potential well can be formed in the strained SiGe layer or the strained Ge layer with high Ge content, the migration rate of the current carrier is increased and the performance of the semiconductor device is greatly improved.
Description
Technical field
The present invention relates to semiconductor manufacturing and design field, particularly a kind of high-speed semiconductor device structure and forming method thereof.
Background technology
For a long time, it is constantly scaled that the characteristic size of metal-oxide semiconductor fieldeffect transistor (MOSFET) is being followed so-called Moore's Law (Moore ' s law) always, its operating rate is more and more faster, but, for for Si material itself, approached the dual limit of physics and technology.Thereby people have proposed various methods for the performance that constantly promotes the MOSFET device, thereby the development of MOSFET device has entered so-called back mole (More-Than-Moore) epoch.Based on heterojunction structure is wherein a kind of fruitful technology based on the high mobility raceway groove engineering of material systems such as Si-Ge and Si-C especially.The core concept of this technology is the semiconductor channel material, Si for example, and stress application is promptly introduced strain, changes its band structure therefrom improving its mobility of charge carrier rate, thereby strengthens the drive current of MOSFET, the operating rate of final boost device.On the other hand, the hole mobility of body silicon only is about half of electron mobility, be about 2 times of NMOSFET for the channel width that obtains identical driving force PMOSFET device, this has not only wasted the area of domain, and the increase of output parasitic capacitance has also reduced the operating rate of circuit, therefore, the hole mobility that how to improve the PMOS device significantly seems particularly outstanding.
Further, because the minimal noise coefficient of MOSFET device is proportional to gate resistance and source area resistance, so in order to obtain high speed, low noise MOSFET device, it is long at first to require to dwindle grid when keeping or reducing source, drain region resistance, and the long increase that reduces to bring gate resistance of grid, thereby make the noise factor of device increase.Therefore, in order to obtain high speed, low-noise device, be necessary to improve for present MOSFET device architecture.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention proposes a kind of high-speed low-noise device architecture of the T type grid lifting source drain structure based on strain SiGe channel.
For achieving the above object, one aspect of the present invention proposes a kind of high-speed semiconductor device structure, comprising: substrate; Be formed on and contain Ge component strained layer on the described substrate, wherein, the described Ge of containing component strained layer has groove; Be formed on the Si cap layer on the described Ge of the containing component strained layer; Be formed on the part of described Si cap layer, and cover the T type grid structure of described groove; And the source-drain electrode that is formed on described T type grid structure both sides.
In one embodiment of the invention, the described Ge of containing component strained layer is a Ge content gradually variational structure, and wherein, the described Ge component that contains Ge component strained layer core is the highest, and the described Ge component that contains Ge component strained layer upper and lower surface is minimum.
In one embodiment of the invention, the described Ge of containing component strained layer comprises: be formed on first on the described substrate and contain Ge component strained layer; Be formed on described first and contain second on the Ge component strained layer and contain Ge component strained layer, wherein, described second contains in the Ge component strained layer Ge component greater than the described first Ge component that contains in the Ge component strained layer; Be formed on described second and contain the 3rd on the Ge component strained layer and contain Ge component strained layer, wherein, described second contains in the Ge component strained layer Ge component greater than the described the 3rd Ge component that contains in the Ge component strained layer.
In one embodiment of the invention, to contain the thickness of Ge component strained layer identical for the degree of depth of described groove and the described the 3rd.
In one embodiment of the invention, also comprise: be formed on the source-drain electrode on described source-drain electrode top and the described Si cap layer.
The present invention has also proposed a kind of formation method of high-speed semiconductor device structure on the other hand, may further comprise the steps: form substrate; On described substrate, form and contain Ge component strained layer; The described Ge of the containing component of etching strained layer is to form groove in the described Ge of containing component strained layer; Form Si cap layer on the Ge component strained layer in described containing; Form T type grid structure on the part of described Si cap layer, wherein, described T type grid structure covers described groove; And at described T type grid structure both sides formation source-drain electrode.
In one embodiment of the invention, the described Ge of containing component strained layer is a Ge content gradually variational structure, and wherein, the described Ge component that contains Ge component strained layer core is the highest, and the described Ge component that contains Ge component strained layer upper and lower surface is minimum.
In one embodiment of the invention, describedly contain Ge component strained layer and further comprise forming on the substrate: on described substrate, to form first and contain Ge component strained layer; Contain on the Ge component strained layer described first and to form second and contain Ge component strained layer, wherein, described second contains in the Ge component strained layer Ge component greater than the described first Ge component that contains in the Ge component strained layer; Form the 3rd and contain Ge component strained layer with containing on the Ge component strained layer described second, wherein, described second contains in the Ge component strained layer Ge component greater than the described the 3rd Ge component that contains in the Ge component strained layer.
In one embodiment of the invention, described second to contain the Ge component that Ge ratio of component the described the 3rd contains in the Ge component strained layer in the Ge component strained layer big by 20%.Wherein, described second the etching stop layer when containing Ge component strained layer and being the described groove of etching.
In one embodiment of the invention, also comprise: forming source-drain electrode above the described source-drain electrode and on the described Si cap layer.
The present invention has following characteristics:
1, in the PMOS device architecture of the embodiment of the invention, by two low Ge component strain SiGe layers or Si layer in high-Ge component strain SiGe or strain Ge layer upper and lower settings, can in high-Ge component strain SiGe or strain Ge layer, produce the hole potential well, thereby can improve the mobility of charge carrier rate, greatly improve the performance of device.
2, in the PMOS device architecture of the embodiment of the invention,, improved the variation of answering of channel region high-Ge component strain SiGe layer, further promoted the performance of device by forming the high-Ge component strain SiGe or the strain Ge lifting source drain structure of groove type.
3, in the PMOS device architecture of the embodiment of the invention,, reduced the resistance of gate resistance and source-drain electrode area respectively significantly, thereby can improve the noise characteristic of device significantly by forming T type grid structure and lifting source drain structure.
4, in the PMOS device architecture of the embodiment of the invention, can also effectively solve surface state problem between gate dielectric layer and the channel layer by the Si cap layer that on high-Ge component strain SiGe or strain Ge layer, is provided with.In addition, when forming interconnection, this Si cap layer can also adopt ripe metal silicide technology, thereby avoids using the metal germanide.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the high-speed semiconductor device structure chart of the embodiment of the invention one;
Fig. 2 a and Fig. 2 b answer the variation comparison diagram for existing semiconductor device and embodiment of the invention semiconductor device structure;
Fig. 3 is the high-speed semiconductor device structure chart of the embodiment of the invention two;
Fig. 4 a and Fig. 4 b answer the variation comparison diagram for existing semiconductor device and the embodiment of the invention two semiconductor device structures;
Fig. 5-8 is the formation method flow diagram of the high-speed semiconductor device structure of the embodiment of the invention one;
Fig. 9-11 is the formation method flow diagram of the high-speed semiconductor device structure of the embodiment of the invention two.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition, first feature described below second feature it " on " structure can comprise that first and second features form the embodiment of direct contact, can comprise that also additional features is formed on the embodiment between first and second features, such first and second features may not be direct contacts.
The present invention forms on substrate earlier has the high-Ge component strain SiGe layer that the Ge component is distributed as gradient-structure, begin the Ge component from substrate and strain SiGe bed boundary one side and form low-Gao-low structure, deposit hard mask layer then, and utilize photoetching method to define window, adopt dry method or wet etching that the low Ge component strain SiGe layer on top layer, window place is etched away, form the structure of fluted body.Subsequently, hard mask layer is removed, and the Si layer that growth one deck is thin on the structure that forms is as passivation layer.Then, deposit gate medium and gate metal utilize etching or stripping technology to form the grid with T shape structure and pile up successively.At last, the technologies such as Metal Contact in formation source/drain region finally form the MOS device.
As shown in Figure 1, be the high-speed semiconductor device structure chart of the embodiment of the invention one.This high-speed semiconductor device comprises substrate 1100, body Si substrate for example, and Si substrate (SOI) on the insulating barrier, strain Si substrate (SSOI) etc. on the insulating barrier, and the high preferred orientation of this Si substrate can be (100), (110) or (111) etc.This device also comprises being formed on and contains Ge component strained layer 1200 on the substrate 1100, wherein, contain Ge component strained layer 1200 and have groove, and be formed on the Si cap layer 1300 that contains on the Ge component strained layer 1200, with on the part that is formed on Si cap layer 1300 and cover the T type grid structure 1400 of groove and the source-drain electrode that is formed on T type grid structure 1400 both sides.In one embodiment of the invention, contain Ge component strained layer 1200 and be Ge content gradually variational structure, wherein, the Ge component of core that contains Ge component strained layer 1200 is the highest, and it is minimum to contain the Ge component of Ge component strained layer 1200 upper and lower surfaces.For example, from substrate and strain SiGe bed boundary one side, the Ge component is increased to some maximums from zero gradual change earlier, is reduced to zero from this maximum gradual change then, and final formation has the Ge content gradually variational structure of low-Gao-low structure.This Ge content gradually variational structure critical thickness of strain SiGe layer on the one hand increases, and can reduce the defective introduced in the epitaxial growth greatly, makes that on the other hand the stress distribution structure of whole strain SiGe layer is more stable, helps the manufacturing of device.Also comprise the source-drain electrode 1500 that is formed on source-drain electrode top and the Si cap layer 1300, and be formed on gate electrode 1600 on the T type grid structure 1400, like this because the existence of Si cap layer 1300 can solve the surface state problem between gate dielectric layer and the channel layer, in addition, can also adopt ripe metal silicide technology, to avoid using the metal germanide.
In embodiments of the present invention, the thickness of Si cap layer 1300 can be 0.5nm to 10nm, and the thickness of preferred Si is 0.5nm to 5nm.In fact, Si cap layer 1300 has not only served as gate medium and the interface that contains Ge component strained layer 1200, and because when preparation source region and drain region metal silicide, the characteristic that Ge itself can serve as diffusion barrier makes contact resistance increase, and the existence of Si cap layer 1300 has weakened this bad influence significantly.
Further, be grown on the Si substrate owing to containing Ge component strained layer 1200 on the one hand, the lattice in the face is consistent with the lattice of Si, and the Ge lattice constant is bigger than Si, thereby has produced the compression strain in the face to containing Ge component strained layer 1200, and face produces elongation strain outward; On the other hand, when the upper surface of the Ge component strained layer after Si cap layer 1300 is grown in the formation groove and side, because containing Ge component strained layer 1200 sides has had elongation strain outside face, so after 1300 growth above it of Si cap layer, will produce elongation strain Si, thereby the Ge component strained layer 1200 that contains of below has further been applied compression stress.Can further prove this advantage of the present invention by emulation, with shown in Fig. 2 b (fluted), both concrete structure unanimities for example are: the thick Si of extension one deck 10nm on the Si substrate as Fig. 2 a (no groove)
1-xGe
xLayer, Ge component x is gradually reduced to 0.5 from 0; Subsequently, the thick strain Si of growth one deck 5nm
0.5Ge
0.5Layer; The strain Si of regrowth one deck 10nm
1-yGe
yLayer, Ge component y is gradually reduced to 0 from 0.5; The Si cap layer that one deck 5nm that grows at last is thick; Wherein, strain Si
0.5Ge
0.5Layer will serve as the channel layer of device.The concrete difference of Fig. 2 a and Fig. 2 b only is not form groove in Fig. 2 a structure, and forms the wide groove of 20nm earlier and then do Si cap layer growth in Fig. 2 b.From Fig. 2 a and Fig. 2 b as can be seen, introduced contain Ge component strained layer groove after, the variation of answering of channel layer will improve about 69% than the variation of answering of Fig. 2 a that does not form groove structure among Fig. 2 b.
As shown in Figure 3, be the high-speed semiconductor device structure chart of the embodiment of the invention two.This high-speed semiconductor device comprises substrate 2100, be formed on the Si resilient coating 2200 on the substrate 2100, be formed on first on the Si resilient coating 2200 and contain Ge component strained layer 2300, being formed on first contains second on the Ge component strained layer 2300 and contains Ge component strained layer 2400, with be formed on second and contain the 3rd on the Ge component strained layer 2400 and contain Ge component strained layer 2500, wherein, second contains in the Ge component strained layer 2400 the Ge component greater than the first Ge component that contains in the Ge component strained layer 2300, and second contains in the Ge component strained layer 2400 the Ge component greater than the 3rd Ge component that contains in the Ge component strained layer 2500.Comprise that also being formed on the 3rd contains the Si cap layer 2600 on the Ge component strained layer 2500 and be formed on the part of Si cap layer 2600 and cover the T type grid structure 2700 of groove, and the source-drain electrode that is formed on T type grid structure 2700 both sides.Also comprise the source-drain electrode 2800 that is formed on source-drain electrode top and the Si cap layer 2600, and be formed on gate electrode 2900 on the T type grid structure 2700, like this because the existence of Si cap layer 2600 can solve the surface state problem between gate dielectric layer and the channel layer, in addition, can also adopt ripe metal silicide technology, to avoid using the metal germanide.
Further, be grown in successively on the Si substrate owing to containing Ge component strained layer 2300, strained layer 2400 and strained layer 2500 on the one hand, lattice in the face is consistent with the lattice of Si, the Ge lattice constant is bigger than Si, thereby produced the compression strain in the face to containing Ge component strained layer 2300, strained layer 2400 and strained layer 2500, face produces elongation strain outward; On the other hand, when the upper surface of the Ge component strained layer after Si cap layer 2600 is grown in the formation groove and side, because containing Ge component strained layer 2500 sides has had elongation strain outside face, so after 2600 growth above it of Si cap layer, will produce elongation strain Si, thereby the Ge component strained layer 2400 that contains of below has further been applied compression stress.Can further prove this advantage of the present invention by emulation, with shown in Fig. 4 b (fluted), both concrete structures are: the thick strain Si of extension one deck 10nm on the Si substrate as Fig. 4 a (no groove)
0.75Ge
0.25Layer; Subsequently, the thick strain Si of growth one deck 5nm
0.35Ge
0.65Layer; The strain Si of regrowth one deck 10nm
0.75Ge
0.25Layer; The Si cap layer that one deck 5nm that grows at last is thick; Wherein, strain Si
0.35Ge
0.65Layer will serve as the channel layer of device.The concrete difference of Fig. 4 a and Fig. 4 b only is not form groove in Fig. 4 a structure, and forms the wide groove of 20nm earlier and then do Si cap layer growth in Fig. 4 b.From Fig. 4 a and 4b as can be seen, introduced contain Ge component strained layer groove after, the variation of answering of the channel layer of Fig. 4 b will improve about 81% than the variation of answering of Fig. 4 a that does not form groove structure.
Shown in Fig. 5-8, the formation method flow diagram for the high-speed semiconductor device structure of the embodiment of the invention one may further comprise the steps:
Step S101 provides substrate 1100, for example body Si substrate, perhaps SOI etc.Can certainly on substrate 1100, form the Si resilient coating.
Step S102 forms on substrate 1100 by low-temperature epitaxy and to contain Ge component strained layer 1200, as shown in Figure 5.In an embodiment of the present invention, this low-temperature epitaxy growth technology can adopt chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) technology, preferential high vacuum chemical vapour deposition (UHVCVD) method.If becoming to contain the Ge component of Ge component strained layer 1200 is Gradient distribution, then f is the lattice mismatch of equivalence, h
cRepresent general thickness.Make that f is the lattice mismatch of SiGe layer and Si, make h
c(nm of unit) is critical thickness, can obtain according to the People-Bean model:
h
cf
2≈(1.844×10
-3)ln(h
c/0.4)
In fact, during the hot expense of not considering that subsequent treatment process introduces, the critical thickness when deformation relaxations take place Ge component strained layer 1200 depends on Ge component, epitaxial growth temperature and growth rate, and critical thickness raises with growth temperature and reduces rapidly.Therefore, deformation relaxations take place in Ge component strained layer 1200 in the epitaxial process, and the processing temperature of this low-temperature epitaxy growth technology can be 200 ℃ to 650 ℃.In order further to control the surface roughness of Ge component strained layer 1200, equally also can in epitaxial process, control the growth temperature of Ge component strained layer 1200.
Step S103, etching contains Ge component strained layer 1200 to form groove in containing Ge component strained layer 1200, as shown in Figure 6.
Step S104 is containing formation Si cap layer 1300 on the Ge component strained layer 1200, as shown in Figure 7.
Step S105 forms T type grid structure 1400 on the part of Si cap layer 1300, wherein, T type grid structure 1400 covers described groove, as shown in Figure 8.
Step S106 forms source-drain electrode in T type grid structure 1400 both sides.
Particularly, can realize following several structure:
Exemplifying embodiment 1: the Si resilient coating that first extension one layer thickness is 20nm on Si substrate 1100, growth temperature is 525 ℃; The layer thickness of growing then is the strain Si of 15nm
0.5Ge
0.5Layer, growth temperature is 450 ℃.
Exemplifying embodiment 2: the Si resilient coating that first extension one layer thickness is 20nm on substrate 1100, growth temperature is 525 ℃; The voltage ratio layer thickness of growing by the control source of the gas is the strain Si of 10nm then
1-xGe
xLayer, Ge component x has increased 0.5 gradually from 0; And then, keeping the identical voltage ratio layer thickness of growing is the strain Si of 5nm
0.5Ge
0.5Layer; Subsequently, regulate the voltage ratio of source of the gas, continued growth one layer thickness is the strain Si of 10nm
1-yGe
yLayer, Ge component y is gradually reduced to 0 from 0.5; Whole SiGe thin film epitaxial growth temperature remains 450 ℃ always.
Exemplifying embodiment 3: the Si resilient coating that first extension one layer thickness is 20nm on substrate 1100, growth temperature is 525 ℃; The voltage ratio layer thickness of growing by the control source of the gas is the strain Si of 10nm then
1-xGe
xLayer, Ge component x have increased 0.5 gradually from 0, and growth temperature is 450 ℃; And then, reduce growth temperature to 350 ℃, and change voltage ratio, the layer thickness of growing is the strain Si of 2nm
0.15Ge
0.85Layer; Subsequently, rising growth temperature to 450 ℃ is regulated voltage ratio simultaneously, and continued growth one layer thickness is the strain Si of 10nm
1-yGe
yLayer, Ge component y is gradually reduced to 0 from 0.5.
Exemplifying embodiment 4: the Si resilient coating that first extension one layer thickness is 20nm on substrate 1100, growth temperature is 525 ℃; The voltage ratio layer thickness of growing by the control source of the gas is the strain Si of 10nm then
1-xGe
xLayer, Ge component x have increased 0.5 gradually from 0, and growth temperature is 450 ℃; And then, reduce growth temperature to 300 ℃, and change voltage ratio, the layer thickness of growing is the strain Ge layer of 2nm; Subsequently, rising growth temperature to 450 ℃ is regulated voltage ratio simultaneously, and continued growth one layer thickness is the strain Si of 10nm
1-yGe
yLayer, Ge component y is gradually reduced to 0 from 0.5.
Shown in Fig. 9-11, the formation method flow diagram for the high-speed semiconductor device structure of the embodiment of the invention two may further comprise the steps:
Step S201 provides substrate 2100, and forms resilient coating 2200 on substrate 2100.
Step S202 forms first and contains Ge component strained layer 2300 on resilient coating 2200.
Step S203 contains on the Ge component strained layer 2300 first and to form second and contain Ge component strained layer 2400, and wherein, second contains in the Ge component strained layer 2400 the Ge component greater than the first Ge component that contains in the Ge component strained layer 2300.In one embodiment of the invention, second contains Ge component strained layer 2400 and can be pure Ge layer.
Step S204 contains on the Ge component strained layer 2400 second and to form the 3rd and contain Ge component strained layer 2500, and wherein, second contains in the Ge component strained layer 2400 the Ge component greater than the 3rd Ge component that contains in the Ge component strained layer 2500, as shown in Figure 9.Especially, the above-mentioned epitaxy technology of mentioning can realize by low-temperature epitaxy growth technology.This low-temperature epitaxy growth technology can adopt chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) technology, preferential high vacuum chemical vapour deposition (UHVCVD) method.Contain Ge component strained layer 2300, second and contain Ge component strained layer the 2400 and the 3rd and contain in the Ge component strained layer 2500 for being grown in first on the resilient coating 2200, make that f is the lattice mismatch of SiGe layer and Si, make h
c(nm of unit) is critical thickness, can obtain according to the People-Bean model:
h
cf
2≈(1.844×10
-3)ln(h
c/0.4)
Wherein, first contains Ge component strained layer 2300, second contains Ge component strained layer the 2400 and the 3rd to contain Ge component strained layer 2500 both can be even component, also can be graded component.
Particularly, can realize following several structure:
Exemplifying embodiment 1: the Si resilient coating 2200 that first extension one layer thickness is 20nm on Si substrate 2100, growth temperature is 525 ℃; The layer thickness of growing then is the strain Si of 10nm
0.75Ge
0.25Layer, growth temperature is 525 ℃; Reduce epitaxial temperature again, the layer thickness of growing is the strain Si of 5nm
0.35Ge
0.65Layer, growth temperature is 400 ℃; Then, improve epitaxial temperature, the layer thickness of growing is the strain Si of 10nm
0.75Ge
0.25Layer, growth temperature is 525 ℃.
Exemplifying embodiment 2: the Si resilient coating 2200 that first extension one layer thickness is 20nm on Si substrate 2100, growth temperature is 525 ℃; The layer thickness of growing then is the strain Si of 5nm
0.5Ge
0.5Layer, growth temperature is 450 ℃; Reduce epitaxial temperature again, the layer thickness of growing is the strain Si of 2nm
0.15Ge
0.85Layer, growth temperature is 350 ℃; Then, improve epitaxial temperature, the layer thickness of growing is the strain Si of 5nm
0.5Ge
0.5Layer, growth temperature is 450 ℃.
Exemplifying embodiment 3: the Si resilient coating 2200 that first extension one layer thickness is 20nm on Si substrate 2100, growth temperature is 525 ℃; The layer thickness of growing then is the strain Si of 5nm
0.5Ge
0.5Layer, growth temperature is 450 ℃; Reduce epitaxial temperature again, the layer thickness of growing is the strain Ge layer of 2nm, and growth temperature is 300 ℃; Then, improve epitaxial temperature, the layer thickness of growing is the strain Si of 5nm
0.5Ge
0.5Layer, growth temperature is 450 ℃.
Exemplifying embodiment 4: the Si resilient coating 2200 that first extension one layer thickness is 20nm on Si substrate 2100, growth temperature is 525 ℃; The layer thickness of growing then is the strain Si of 5nm
0.5Ge
0.5Layer, growth temperature is 450 ℃; Reduce epitaxial temperature again, the layer thickness of growing is the strain Ge layer of 2nm, and growth temperature is 300 ℃; Then, improve epitaxial temperature to 450 ℃, and regulate the source of the gas voltage ratio, the layer thickness of growing is the strain Si of 10nm
1-yGe
yLayer, Ge component y is gradually reduced to 0 from 0.5.
Preferably, second to contain the Ge component that Ge ratio of component the 3rd contains in the Ge component strained layer 2500 in the Ge component strained layer 2400 big by 20%, the etching stop layer that such second contains Ge component strained layer 2400 when just can be etched recesses.
Step S205, etching the 3rd contains Ge component strained layer 2500 to form groove.Particularly, can contain deposit one deck hard mask layer on the Ge component strained layer 2500 the 3rd earlier, SiO2 layer for example, this SiO2 sacrifice layer can be used for defining in photoetching technique the graphical window of grid.Then, utilizing dry etching or/and wet-etching technology that the 3rd of the SiO2 layer at window place and top contained Ge component strained layer 2500 removes.Wherein, dry etching comprises the technology of present extensive use, for example reactive ion etching (RIE) and high-density plasma etching (HDP) etc., and these technology have selectivity concurrently simultaneously and anisotropy is had a few preferably.Especially, when containing Ge component strained layer 2500, etching the 3rd can adopt traditional Si etchant solution, for example KOH, TMAH and EDP etc.Differ by more than 20% because if the 3rd contains Ge component strained layer 2500 with the Ge component that channel region second contains Ge component strained layer 2400, contain Ge component strained layer 2400 this moment second is good etching stop layers.By optimizing the Pressure, Concentration, Temperature of wet etching liquid, the selection of the low Ge component of etching and high-Ge component SiGe layer can be greater than 100 than (be corrosion rate than), even can reach 1000 or higher.
Step S206 contains formation Si cap layer 2600 on the Ge component strained layer 2500 the 3rd, as shown in figure 10.The photoresist and the hard mask layer that are adopted during with photoetching are removed fully, adopt epitaxy technology growth one deck Si cap layer 2600 to serve as passivation layer again, and the thickness of Si cap layer 2600 can be 0.5nm to 10nm, and the thickness of preferred Si is 0.5nm to 5nm.In fact, Si cap layer 2600 has not only served as the interface of gate medium and strain SiGe layer, and because when preparation source region and drain region metal silicide, the characteristic that Ge itself can serve as diffusion barrier makes contact resistance increase, the existence of Si cap layer 2600 has weakened this bad influence significantly.
Step S207 forms T type grid structure 2700 on the part of Si cap layer 2600, wherein, T type grid structure 2700 covers described groove, as shown in figure 11.On Si cap layer 2600, form gate dielectric layer; On gate medium, place grid conducting layer, utilize photoetching to form grid and pile up with T shape structure in conjunction with lithographic technique; And form source region and drain region in both sides that grid pile up, wherein source region and drain region are contained Ge component strained layer 2400 channel layers by second and separate.It should be noted that in the present invention formed groove structure owing to contained in the Ge component strained layer 2500 the 3rd in advance, therefore, grid conducting layer is made into T shape structure easily.For example,, can adopt traditional peeling off (lift-off) technology, promptly earlier on substrate, apply photoresist, after steps such as overexposure, development, promptly can leave the window of a grid conducting layer for adopting metal as for the grid conducting layer; Depositing metal then, and metal is cured; Afterwards, the photoresist of grid conducting layer both sides is got rid of, promptly formed grid conducting layer with T shape structure.On the one hand, for traditional strip structure, T shape grid have lower gate resistance; Meanwhile, because source region and drain region are the structure of automatic lifting, the source region of device and the resistance in drain region become lower.Just because of having this two characteristics simultaneously concurrently, make the noise characteristic of device obtain significant the lifting.
Step S208 forms source-drain electrode.By there being Si cap layer 2600 protecting, so, gate dielectric layer can be silicon dioxide, because SiO2 and the very good and stable performance of Si interfacial characteristics, perhaps other high-k (High-k) gate medium, for example HfO
2, HfSiON, TiO
2Deng.Grid conducting layer comprises polysilicon and metal level.In addition, the formation in source region and drain region can be passed through the doping impurity method, perhaps by plated metal, makes metal form the method that Schottky (Schottky) contacts with the source/drain regions semiconductor.The doping impurity method can be injected or technology such as diffusion technology realizes for in-situ doped, the ion in the SiGe layer epitaxially grown process.The foreign ion that mixes activates methods such as can adopting conventional furnace temperature annealing, rapid thermal annealing (RTP), laser annealing.
Step S209 is forming source-drain electrode above the source-drain electrode and on the Si cap layer 2600, and forming gate electrode on T type grid structure 2700.
The present invention has following characteristics:
1, in the PMOS device architecture of the embodiment of the invention, by two low Ge component strain SiGe layers or Si layer in high-Ge component strain SiGe or strain Ge layer upper and lower settings, can in high-Ge component strain SiGe or strain Ge layer, produce the hole potential well, thereby can improve the mobility of charge carrier rate, greatly improve the performance of device.
2, in the PMOS device architecture of the embodiment of the invention,, improved the variation of answering of channel region high-Ge component strain SiGe layer, further promoted the performance of device by forming the high-Ge component strain SiGe or the strain Ge lifting source drain structure of groove type.
3, in the PMOS device architecture of the embodiment of the invention,, reduced the resistance of gate resistance and source-drain electrode area respectively significantly, thereby can improve the noise characteristic of device by forming T type grid structure and lifting source drain structure.
4, in the PMOS device architecture of the embodiment of the invention, can also effectively solve surface state problem between gate dielectric layer and the channel layer by the Si cap layer that on high-Ge component strain SiGe or strain Ge layer, is provided with.In addition, when forming interconnection, this Si cap layer can also adopt ripe metal silicide technology, thereby avoids using the metal germanide.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification that scope of the present invention is by claims and be equal to and limit to these embodiment.
Claims (13)
1. a high-speed semiconductor device structure is characterized in that, comprising:
Substrate;
Be formed on and contain Ge component strained layer on the described substrate, wherein, the described Ge of containing component strained layer has groove;
Be formed on the Si cap layer on the described Ge of the containing component strained layer;
Be formed on the part of described Si cap layer, and cover the T type grid structure of described groove; And
Be formed on the source-drain electrode of described T type grid structure both sides.
2. high-speed semiconductor device structure as claimed in claim 1, it is characterized in that the described Ge of containing component strained layer is a Ge content gradually variational structure, wherein, the described Ge component that contains Ge component strained layer core is the highest, and the described Ge component that contains Ge component strained layer upper and lower surface is minimum.
3. high-speed semiconductor device structure as claimed in claim 1 is characterized in that, the described Ge of containing component strained layer comprises:
Be formed on first on the described substrate and contain Ge component strained layer;
Be formed on described first and contain second on the Ge component strained layer and contain Ge component strained layer, wherein, described second contains in the Ge component strained layer Ge component greater than the described first Ge component that contains in the Ge component strained layer; With
Be formed on described second and contain the 3rd on the Ge component strained layer and contain Ge component strained layer, wherein, described second contains in the Ge component strained layer Ge component greater than the described the 3rd Ge component that contains in the Ge component strained layer.
4. high-speed semiconductor device structure as claimed in claim 3 is characterized in that, the thickness that the degree of depth of described groove and the described the 3rd contains Ge component strained layer is identical.
5. high-speed semiconductor device structure as claimed in claim 1 is characterized in that, also comprises:
Be formed on the source-drain electrode on described source-drain electrode top and the described Si cap layer.
6. the formation method of a high-speed semiconductor device structure is characterized in that, may further comprise the steps:
Form substrate;
On described substrate, form and contain Ge component strained layer;
The described Ge of the containing component of etching strained layer is to form groove in the described Ge of containing component strained layer;
Form Si cap layer on the Ge component strained layer in described containing;
Form T type grid structure on the part of described Si cap layer, wherein, described T type grid structure covers described groove; And
Form source-drain electrode in described T type grid structure both sides.
7. the formation method of high-speed semiconductor device structure as claimed in claim 6, it is characterized in that the described Ge of containing component strained layer is a Ge content gradually variational structure, wherein, the described Ge component that contains Ge component strained layer core is the highest, and the described Ge component that contains Ge component strained layer upper and lower surface is minimum.
8. the formation method of high-speed semiconductor device structure as claimed in claim 6 is characterized in that, described formation on substrate contains Ge component strained layer and further comprise:
On described substrate, form first and contain Ge component strained layer;
Contain on the Ge component strained layer described first and to form second and contain Ge component strained layer, wherein, described second contains in the Ge component strained layer Ge component greater than the described first Ge component that contains in the Ge component strained layer; With
Contain on the Ge component strained layer described second and to form the 3rd and contain Ge component strained layer, wherein, described second contains in the Ge component strained layer Ge component greater than the described the 3rd Ge component that contains in the Ge component strained layer.
9. the formation method of high-speed semiconductor device structure as claimed in claim 8 is characterized in that, described second to contain the Ge component that Ge ratio of component the described the 3rd contains in the Ge component strained layer in the Ge component strained layer big by 20%.
10. the formation method of high-speed semiconductor device structure as claimed in claim 9 is characterized in that, the etching stop layer that described second contains Ge component strained layer when being the described groove of etching.
11. the formation method of high-speed semiconductor device structure as claimed in claim 6 is characterized in that, also comprises:
Forming source-drain electrode above the described source-drain electrode and on the described Si cap layer.
12. a complementary type field-effect transistor structure is characterized in that, comprising:
N type field effect transistor; With
P type field effect transistor, wherein, described n type field effect transistor and p type field effect transistor are prepared from by each described method of claim 6-11.
13. an integrated circuit (IC) chip is characterized in that, having a semiconductor device on this chip at least is the described semiconductor structure of claim 1, perhaps is the described complementary type field-effect transistor structure of claim 12.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102208415A (en) * | 2011-05-17 | 2011-10-05 | 西安电子科技大学 | Structure of vertically crossed stacked gate and strain SiGeC quantum well channel CMOS (Complementary Metal Oxide Semiconductors) device |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6096590A (en) * | 1996-07-18 | 2000-08-01 | International Business Machines Corporation | Scalable MOS field effect transistor |
| CN1665000A (en) * | 2004-03-01 | 2005-09-07 | 国际商业机器公司 | Method of manufacture of finfet devices with T-shaped fins and devices manufactured thereby |
| CN101542700A (en) * | 2007-09-14 | 2009-09-23 | 忠北大学校产学协力团 | Room temperature-operating single-electron device and the fabrication method thereof |
| CN101819996A (en) * | 2010-04-16 | 2010-09-01 | 清华大学 | Semiconductor structure |
| CN101834206A (en) * | 2010-04-12 | 2010-09-15 | 清华大学 | Semiconductor device structure and forming method thereof |
-
2010
- 2010-10-27 CN CN 201010520406 patent/CN102054871A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6096590A (en) * | 1996-07-18 | 2000-08-01 | International Business Machines Corporation | Scalable MOS field effect transistor |
| CN1665000A (en) * | 2004-03-01 | 2005-09-07 | 国际商业机器公司 | Method of manufacture of finfet devices with T-shaped fins and devices manufactured thereby |
| CN101542700A (en) * | 2007-09-14 | 2009-09-23 | 忠北大学校产学协力团 | Room temperature-operating single-electron device and the fabrication method thereof |
| CN101834206A (en) * | 2010-04-12 | 2010-09-15 | 清华大学 | Semiconductor device structure and forming method thereof |
| CN101819996A (en) * | 2010-04-16 | 2010-09-01 | 清华大学 | Semiconductor structure |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN102208415A (en) * | 2011-05-17 | 2011-10-05 | 西安电子科技大学 | Structure of vertically crossed stacked gate and strain SiGeC quantum well channel CMOS (Complementary Metal Oxide Semiconductors) device |
| CN102931233B (en) * | 2011-08-08 | 2016-03-16 | 中芯国际集成电路制造(上海)有限公司 | Nmos pass transistor and forming method thereof |
| CN102931233A (en) * | 2011-08-08 | 2013-02-13 | 中芯国际集成电路制造(上海)有限公司 | N-channel metal oxide semiconductor (NMOS) transistor and forming method thereof |
| CN102738174A (en) * | 2012-07-16 | 2012-10-17 | 西安电子科技大学 | Three-strained fully planar SOI (silicon on insulator) BiCMOS (bipolar complementary metal oxide semiconductor) integrated device and preparation method |
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| CN102738174B (en) * | 2012-07-16 | 2015-12-02 | 西安电子科技大学 | A kind of three strain whole plane SOI BiCMOS integrated device and preparation methods |
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