CN102034718B - 半导体器件和在tsv转接板中形成开口腔以在wlcsmp中容纳半导体裸片的方法 - Google Patents

半导体器件和在tsv转接板中形成开口腔以在wlcsmp中容纳半导体裸片的方法 Download PDF

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CN102034718B
CN102034718B CN201010294420.7A CN201010294420A CN102034718B CN 102034718 B CN102034718 B CN 102034718B CN 201010294420 A CN201010294420 A CN 201010294420A CN 102034718 B CN102034718 B CN 102034718B
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semiconductor
semiconductor die
crystal wafer
conductive
semiconductor crystal
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CN102034718A (zh
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H·基
N·仇
H·辛
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

通过将半导体晶圆安装到临时载体而制造半导体器件。形成穿过该晶圆的多个TSV。形成部分穿过该晶圆的空腔。将第一半导体裸片安装到第二半导体裸片上。将该第一和第二裸片安装到该晶圆以便该第一裸片被置于该晶圆上方并被电连接到该TSV，且该第二裸片被置于该空腔内。在该晶圆和第一及第二裸片上方沉积密封剂。除去该密封剂的一部分以暴露该第一裸片的第一表面。除去该晶圆的一部分以暴露该TSV和该第二裸片的表面。该晶圆的剩余部分作为用于该第一和第二裸片的TSV转接板而工作。在该TSV转接板上方形成互连结构。

Description

半导体器件和在TSV转接板中形成开口腔以在WLCSMP中容纳半导体裸片的方法
技术领域
本发明一般涉及半导体器件，尤其涉及形成开口腔式(opencavity)TSV转接板(interposer)以在晶圆级芯片尺寸模块封装中容纳半导体裸片的半导体器件和方法。
背景技术
在现代电子产品中通常会发现半导体器件。半导体器件在电元件的数量和密度上都会变化。分立的半导体器件通常包含一种类型的电元件，例如，发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件典型地包含数百到数百万个电元件。集成半导体器件的例子包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池和数字微镜器件(DMD)。
半导体器件执行广范围的功能，诸如高速计算、发送和接收电磁信号、控制电子器件、将日光转换为电以及为电视显示器创建可视投影。在娱乐、通讯、能量转换、网络、计算机和消费品领域中都能发现半导体器件。在军用、航空、汽车、工业控制器和办公设备中也能发现半导体器件。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许它的导电率能够通过施加电场或基电流或经由掺杂工艺而被操纵。掺杂将杂质引入所述半导体材料中以操纵并控制该半导体器件的传导率。
半导体器件包含有源和无源式电结构。有源结构(包括双极和场效应晶体管)控制电流的流动。通过改变掺杂程度和施加电场或基电流，晶体管会促进或限制电流的流动。无源结构(包括电阻器、电容器和电感器)建立执行各种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，这使得半导体器件能够执行高速计算和其它有用的功能。
半导体器件通常使用两种复杂的制造工艺而被制造，即，前端制造和后端制造，每一种工艺都可能地涉及数百个步骤。前端制造涉及在半导体晶圆的表面上形成多个裸片(die)。每个小晶片典型地是完全相同的并包含通过将有源和无源元件电连接而形成的电路。后端制造涉及使单独的裸片从完成的晶圆中独立化(singulate)并封装该小晶片以提供结构支持和环境隔离。
半导体制造的一个目标是生产更小的半导体器件。更小的器件通常消耗更少的功率，具有更高的性能并能够更有效率地被制造。另外，更小的半导体器件具有更小的基底面，这对于更小的最终产品是期望的。更小的裸片尺寸可以通过前端工艺中的改进而被实现，该前端工艺中的改进产生具有更小的、密度更高的有源和无源元件的裸片。后端工艺可通过电互连和封装材料上的改进而产生具有更小的基底面的半导体器件封装。
晶圆级芯片尺寸模块封装(WLCSMP)典型地包含在有机衬底或转接板上方和之间堆叠的半导体裸片，为更高度的器件集成。具有上面和下面堆叠的半导体裸片的WLCSMP的例子可以在美国专利6921968、5977640和6906415中找到。下面的半导体裸片比有机衬底更薄，并且因此被容纳在密封剂(encapsulant)内。因此，从所述下面的半导体中适当地散热是困难的。固定的有机衬底在操作时需要当心以避免损坏所述薄的半导体裸片。另外，由于所述上面的和下面的半导体裸片和有机衬底之间的热膨胀系数(CTE)的不匹配，翘曲(warpage)是经常出现的问题。
发明内容
存在对于具有良好散热并且相对于翘曲而言很牢固的更薄的WLSCMP的需求。因此，在一个实施方式中，本发明是一种制造半导体器件的方法，所述方法包括以下步骤：将半导体晶圆安装到临时载体上，形成穿过该半导体晶圆的多个硅通孔(TSV)，形成部分穿过该半导体晶圆的空腔，将第一半导体裸片安装到第二半导体裸片上，将该第一和第二半导体裸片安装到该半导体晶圆上以便该第一半导体裸片被置于该半导体晶圆上方并被电连接到该TSV且该第二半导体裸片被置于该空腔内，在该半导体晶圆上方并围绕该第一和第二半导体裸片沉积密封剂，除去该密封剂的一部分以暴露该第一半导体裸片的第一表面，以及除去该半导体晶圆的一部分以暴露该TSV和该第二半导体裸片的第一表面。该半导体晶圆的剩余部分作为用于该第一和第二半导体裸片的TSV转接板而工作。该方法进一步包括在该TSV转接板上方形成第一互连结构的步骤。
在另一个实施方式中，本发明是一种制造半导体器件的方法，所述方法包括以下步骤：提供半导体晶圆，形成穿过该半导体晶圆的多个导电通孔，在该半导体晶圆中形成第一空腔，将第一半导体裸片安装到第二半导体裸片上，将该第一和第二半导体裸片安装到该半导体晶圆以便该第一半导体裸片被置于该半导体晶圆上方并被电连接到该导电通孔且该第二半导体裸片被置于该第一空腔内，在该半导体晶圆上方并围绕该第一和第二半导体裸片沉积密封剂，以及除去该半导体晶圆的一部分以暴露该导电通孔和该第二半导体裸片的第一表面。该半导体晶圆的剩余部分作为用于该第一和第二半导体裸片的转接板而工作。该方法进一步包括在该转接板上方形成第一互连结构的步骤。
在另一个实施方式中，本发明是一种制造半导体器件的方法，所述方法包括以下步骤：提供半导体晶圆，形成穿过该半导体晶圆的多个导电通孔，在该半导体晶圆中形成空腔，将第一半导体裸片安装到第二半导体裸片上，将该第一和第二半导体裸片安装到该半导体晶圆上以便该第一半导体裸片被置于该半导体晶圆上方并被电连接到该导电通孔且该第二半导体裸片被置于该空腔内，在该半导体晶圆和第一和第二裸片上方沉积密封剂，以及除去该半导体晶圆的一部分以暴露该导电通孔和该第二半导体裸片的第一表面。该半导体晶圆的剩余部分作为用于该第一和第二半导体裸片的转接板而工作。
在另一个实施方式中，本发明是一种半导体器件，所述半导体器件包括：转接板，该转接板具有穿过该转接板而形成的多个导电通孔和在该转接板中形成的空腔。第一半导体裸片被安装到该转接板。第二半导体裸片被安装到该第一半导体裸片上并被置于该空腔内。密封剂被沉积在该转接板和第一和第二半导体裸片上方。该第一半导体裸片的第一表面从该密封剂而被暴露，并且该第二半导体裸片的第一表面从该密封剂而被暴露。在该转接板上方形成第一互连结构。
附图说明
图1描绘了其表面安装有不同类型的封装的PCB；
图2a-2c描绘了被安装到该PCB的典型半导体封装的进一步的细节；
图3a-3i描绘了形成具有开口腔的WLCSMP的工艺，所述开口腔用于容纳半导体裸片，并通过TSV转接板而被互连；
图4描绘了具有容纳该半导体裸片并通过该TSV转接板而互连的开口腔的WLCSMP；
图5描绘了具有聚合物绝缘层的TSV转接板；
图6描绘了该WLCSMP，其中在该上面的半导体裸片的上方形成了热扩散器(spreader)和TIM层；
图7描绘了该WLCSMP，其中在该上面的半导体裸片的上方形成了EMI和RFI屏蔽层；
图8描绘了该WLCSMP，其中通过该密封剂形成了导电柱；
图9描绘了该WLCSMP，其中通过该密封剂形成了导电柱并在该密封剂上方形成了导电层；
图10描绘了该WLCSMP，其中通过该密封剂形成了导电柱并在该上面的半导体裸片的上方形成了互连结构；
图11描绘了该WLCSMP，其中通过该上面的半导体裸片形成了TSV并在该上面的半导体裸片的上方形成了互连结构；以及
图12描绘了该WLCSMP，其中通过该下面的半导体裸片形成了TSV并在该下面的半导体裸片的上方形成了互连结构。
具体实施方式
在下面的描述中，参考附图，在一个或多个实施方式中描述了本发明，在附图中同样的标号代表同样的或类似的元件。尽管本发明是依照实现本发明目标的最佳方式来描述的，然而本领域的技术人员将会理解，其意在涵盖替代、修改和等同，均包括在如所附权利要求以及由下述披露和附图所支持的它们的等同所限定的本发明的精神和范围内。
半导体器件通常是使用两种复杂的制造工艺而被制造的：前端制造和后端制造。前端制造涉及在半导体晶圆的表面上形成多个裸片。该晶圆上的每个裸片包含有源和无源电元件，它们被电连接以形成功能电子电路。有源电元件，诸如晶体管和二极管，具有控制电流的流动的能力。无源电元件，诸如电容器、电感器、电阻器和变压器，建立执行电子电路功能所必需的电压和电流之间的关系。
无源和有源元件是在半导体晶圆的表面上方通过一系列工艺步骤而被形成的，这些步骤包括掺杂、沉积、光刻、蚀刻和平坦化。掺杂是通过诸如离子注入或热扩散等技术将杂质引入该半导体材料中。该掺杂工艺改变有源器件中的半导体材料的导电率，将该半导体材料转换为绝缘体、导体或响应电场或基电流而动态改变该半导体材料的导电率。晶体管包含变化的类型和掺杂度的区域，这些区域根据需要而被布置(arrange)以使得该晶体管在施加该电场或基电流时能够促进或限制电流的流动。
有源和无源元件是由具有不同电特性的材料的层形成的。所述层可以通过各种沉积技术而被形成，该沉积技术部分地由被沉积的材料的类型确定。例如，薄膜沉积可涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电解电镀和无电镀工艺。每个层通常被图案化(patterned)以形成有源元件、无源元件或元件间的电连接的各部分。
该层可以使用光刻法而被图案化，光刻法涉及光敏材料(例如光刻胶(photoresist))在将被图案化的层的上方的沉积。使用光将图案(pattern)从光掩模传递到该光刻胶。使用溶剂除去光刻胶图案中经受光的部分，使得下层的将被图案化的部分暴露出来。除去该光刻胶的剩余部分，以留下图案化的层。可替代地，一些类型的材料通过将该材料直接沉积到区域或空隙中而被图案化，其中这些区域或空隙是通过前面的沉积/蚀刻工艺而形成的，所述前面的沉积/蚀刻工艺使用诸如无电镀和电解电镀等技术的。
在现有图案上方沉积材料的薄膜可能会扩大下面的图案并形成不均匀平坦的表面。需要均匀平坦的表面以制造更小和更密集地封装的有源和无源元件。平坦化可被用于从该晶圆的表面除去材料并产生均匀平坦的表面。平坦化涉及用抛光垫(polishingpad)抛光该晶圆的表面。在抛光期间研磨材料和腐蚀性化学品被添加到该晶圆的表面。研磨剂的机械作用和化学品的腐蚀作用的结合除去了任何不规则的形态，从而产生均匀平坦的表面。
后端制造指的是将完成的晶圆切割或独立化为单独的裸片然后封装该裸片用于结构支持和环境隔离。为了将该裸片独立出来，沿着该晶圆的非功能区域(被称为锯道或划痕)将该晶圆刻痕并断开。使用激光切割工具或锯条该晶圆被独立化。在独立化之后，单独的裸片被安装到封装衬底上，该衬底包括引脚或接触垫用于与其它系统元件的互连。然后在该半导体裸片上方形成的接触垫被连接到该封装内的接触垫。该电连接可以通过焊料凸起、柱状凸起(studbump)、导电膏或线焊(wirebond)而被实现。在该封装的上方沉积密封剂或其它模型材料以提供物理支撑和电绝缘。然后完成的封装被插入电系统中并使得该半导体器件的功能性对其它系统元件是可用的。
图1描绘了具有芯片载体衬底或印刷电路板(PCB)52的电子器件50，其中它的表面上安装了多个半导体封装。电子器件50可具有一种类型的半导体封装，或多种类型的半导体封装，取决于应用。图1中为了说明的目的而显示了不同类型的半导体封装。
电子器件50可以是一种独立系统，其使用该半导体封装以执行一种或更多种电功能。可替代地，电子器件50可以是一个更大的系统的子元件。例如，电子器件50可以是显卡、网络接口卡或能够插入计算机中的其它信号处理卡。该半导体封装可包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、射频电路、分立器件或其它半导体裸片或电元件。
在图1中，PCB52提供了用于安装在该PCB上的半导体封装的结构支撑和电互连的总的衬底。导电信号迹线(traces)54使用蒸发、电解电镀、无电镀、丝网印刷或其它合适的金属沉积工艺在PCB52的层的表面上方或内部而被形成。信号迹线54提供半导体封装、安装的元件和其它外部系统元件的每一个之间的电通信。迹线54还对每一个半导体封装提供电力和接地连接。
在一些实施方式中，半导体器件具有两个封装级别。第一级别封装是用于将该半导体裸片机械地并电气地附接到中间载体上的技术。第二级别封装涉及将该中间载体机械地并电气地附接到该PCB。在其它实施方式中，半导体器件可以只具有第一级别封装，其中该裸片被直接机械地和电气地安装到该PCB。
为了说明的目的，PCB52上显示了几种类型的第一级别封装，包括线焊封装56和倒装芯片58。此外，PCB52上显示了安装有几种类型的第二级别封装，包括球栅阵列(BGA)60、凸点芯片载体(BCC)62、双列直插封装(DIP)64、平面栅格阵列(LGA)66、多芯片模块(MCM)68、四线无引脚扁平封装(QFN)70以及四线扁平封装72。根据系统要求，半导体封装(配置有第一和第二级别封装类型的任何组合)以及其它电子元件的任何组合可以被连接到PCB52。在一些实施方式中，电子器件50包括单一附接的半导体封装，而其它实施方式要求多个互连的封装。通过结合单一衬底上方的一个或更多个半导体封装，制造商可以将预制元件合并到电子器件和系统中。因为该半导体封装包括复杂的功能性，所以电子器件可以使用更便宜的元件和流水线式制造过程制造。产生的器件不太可能失效，而且制造费用不高，从而导致消费者更低的花费。
图2a-2c显示了示例性半导体封装。图2a描绘了在PCB52上安装的DIP64的进一步的细节。半导体裸片74包括包含作为在该裸片内形成并根据该裸片的电气设计而电互连的有源器件、无源器件、导电层和介电层而被实现的模拟或数字电路的有源区域。例如，该电路可包括一个或更多个晶体管、二极管、电感器、电容器、电阻器和在该半导体裸片74的有源区域内形成的其它电路元件。接触垫76是一个或更多个导电材料(诸如铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)或银(Ag))层，并且电连接到半导体裸片74内形成的电路元件上。在DIP64的装配期间，使用金-硅共晶层或粘合剂材料(诸如热环氧树脂)将半导体裸片74安装到中间载体78上。该封装体包括绝缘封装材料，诸如聚合物或陶瓷。导体引脚80和丝焊82在半导体裸片74和PCB52之间提供电互连。密封剂84被沉积在该封装上方用于通过防止湿气和微粒进入该封装并污染裸片74或丝焊82而保护环境。
图2b描绘了安装在PCB52上的BCC62的进一步的细节。使用填充不足或环氧树脂粘着剂材料将半导体裸片88安装到载体90上方。丝焊94提供接触垫96和98之间的第一级别封装互连。模塑料或密封剂100被沉积在半导体裸片88和丝焊94上方以为该器件提供物理支撑和电绝缘。使用合适的金属沉积(诸如电解电镀或无电镀)在PCB52的表面上方形成接触垫102以阻止氧化。接触垫102被电连接到PCB52中的一个或更多个导电信号迹线54。凸起104在BCC62的接触垫98和PCB52的接触垫102之间而被形成。
在图2c中，使用倒装芯片型第一级别封装将半导体裸片58面朝下安装到中间载体106上。半导体裸片58的有源区域108包含作为根据该裸片的电气设计形成的有源器件、无源器件、导电层和介电层而被实现的模拟或数字电路。例如，该电路可包括一个或更多个晶体管、二极管、电感器、电容器、电阻器和有源区域108内的其它电路元件。半导体裸片58通过凸起110被电气地及机械地连接到载体106。
使用凸起112用BGA型第二级别封装将BGA60电气地及机械地连接到PCB52。通过凸起110、信号线114和凸起112将半导体裸片58电连接到PCB52中的导电信号迹线54。在半导体裸片58和载体106上方沉积模塑料或密封剂116以为该器件提供物理支撑和电绝缘。该倒装芯片半导体器件提供从半导体裸片58上的有源器件到PCB52上的传导路径之间的短的导电路径以便减少信号传播距离、下部电容并改善整体电路性能。在另一个实施方式中，可以使用倒装芯片型第一级别封装而不是中间载体106将半导体裸片58直接机械地及电气地连接到PCB52。
图3a-3c描绘了，相对于图1和2a-2c，形成具有用于容纳半导体裸片和通过TSV转接板而被互连的开口腔的WLCSMP的工艺。图3a显示了容纳用于结构支撑的基底衬底材料(诸如硅、锗、砷化镓、磷化铟或碳化硅)的半导体晶圆118。衬底或载体120包含临时的或保护性的基底材料，诸如硅、聚合物、聚合物复合物、金属、陶瓷、玻璃、玻璃钢、氧化铍或其它合适的低成本的、刚性的材料或块状半导体材料用于结构支撑。在载体120上方施加中间层或带121作为临时性粘着结合膜或蚀刻停止层。将半导体晶圆118安装到载体带121，其中表面123定向为远离该带。
在图3b中，使用激光打孔或蚀刻工艺(诸如深度活性离子蚀刻(DRIE))形成从表面123部分穿过半导体晶圆118的多个通孔。使用PVD、CVD、电解电镀、无电镀或其它合适的金属沉积工艺用Al、Cu、Sn、Ni、Au、Ag、钛(Ti)、W、多晶硅或其它合适的导电材料填充该通孔以形成导电的穿过硅通孔(TSV)122。可以围绕TSV122形成可选的绝缘层。在半导体晶圆118的表面123上方形成电路层124。电路层124包含由绝缘层126分隔开的导电层125。绝缘层126可以是一层或更多层二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、光刻胶或具有类似的绝缘和结构特性的其它材料。使用PVD、CVD、印刷、旋涂、喷涂、烧结或加热氧化形成绝缘层126。通过蚀刻工艺除去一部分绝缘层126。用PVD、CVD、溅射、电解电镀、无电镀或其它合适的金属沉积工艺使用图案化在绝缘层126的被除去部分中形成导电层125。导电层125可以是一层或更多层Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。将导电层125的一个部分电连接到TSV122。根据该半导体器件的设计和功能，导电层125的其他部分可以被电共用或电绝缘。可以在电路层124中形成一个或更多个集成的无源器件(IPD)，诸如电感器、电容器和电阻器，用于射频信号处理。
形成从表面123部分穿过半导体晶圆118的沟槽128，该沟槽128具有足够的宽度和深度以容纳半导体裸片。沟槽128可以是用锯条、激光打孔或DRIE形成的。在一个实施方式中，沟槽128具有大于半导体裸片134的x/y轴长度的宽度和大于半导体裸片134的厚度的深度。可以形成从表面123部分穿过半导体晶圆118的可选的沟槽130以用于切割锯空隙。沟槽130允许半导体晶圆118的侧面(后面称之为TSV转接板)在独立化之后由密封剂覆盖。
图3c显示了半导体裸片或元件132，该裸片132具有包含作为在该裸片之内形成并根据该裸片的电气设计和功能互连起来的有源器件、无源器件、导电层和介电层模拟或数字电路。例如，该电路可包括一个或更多个晶体管、二极管和在有效区域133内形成的其它电路元件以实现模拟电路或数字电路，诸如数字信号处理器(DSP)、ASIC、存储器或其它信号处理电路。半导体裸片132还可包含IPD，诸如电感器、电容器和电阻器，以进行射频信号处理。
使用蒸发、电解电镀、无电镀、球状滴(balldrop)或丝网印刷工艺在有源表面133上沉积导电凸起材料。该凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，伴随可选的焊剂溶液。例如，该凸起材料可以是共晶的Sn/Pb、高铅焊料或无铅焊料。通过将该材料加热到它的熔点以上而是该凸起材料回流以形成球状小珠或凸起136。凸起136代表在有源表面133上方可能形成的一种类型的互连结构。该互连结构还可以使用柱状凸起、微凸起、导电柱、导电膏或其它电气互连。
使用凸起136将半导体裸片或元件134安装和电连接到半导体裸片132。半导体裸片134具有有源表面135，该有源表面135包含作为根据该裸片的电气设计和功能在该裸片内形成并互连起来的有源器件、无源器件、导电层和介电层实现的模拟或数字电路。例如，该电路可包括一个或更多个晶体管、二极管和在该有源表面内形成的其它电路元件以实现模拟电路或数字电路，诸如DSP、ASIC、存储器或其它信号处理电路。半导体裸片134还可包含IPD，诸如电感器、电容器和电阻器，以进行射频信号处理。
结合起来的半导体裸片132-134被定位在半导体晶圆118上方并被对齐以将半导体裸片134放置在沟槽128上方。然后通过回流凸起136以将有源表面133机械及电连接到导电层125而将结合起来的半导体裸片132-134安装到半导体晶圆118，如图3d所示。半导体裸片134被容纳在沟槽128之内以减少封装高度。
在图3e中，使用膏状印刷、压缩铸模、传递模塑、液体密封剂铸模、真空层压、旋涂或其它合适的施加器在半导体晶圆118上方并围绕半导体裸片132和134沉积密封剂或模塑料140。密封剂140可以是聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或具有合适填料的聚合物。密封剂140是不导电的并在环境上保护该半导体器件免受外界元件和污染物的影响。
在图3f中，通过砂轮142除去一部分密封剂140以暴露半导体裸片132的背面143并减少该封装的高度。在另一个实施方式中，诸如在图9中描述的，砂轮142可以留下覆盖半导体裸片132的表面143的一部分密封剂140。
在图3g中，衬底或载体144包含临时或牺牲性基底材料，诸如硅、聚合物、聚合物复合物、金属、陶瓷、玻璃、玻璃钢、氧化铍或其它合适的低成本的、刚性的材料或块状半导体材料，以提供结构支撑。在载体144上方施加作为粘着结合膜或蚀刻停止层的中间层或带146。图3a-3f中所述的组件被反转并安装到载体带146。通过化学蚀刻、机械剥落、CMP、机械研磨、热烘烤、激光扫描或湿法剥离除去载体120和带121。
在图3h中，通过砂轮142除去半导体晶圆118的一部分表面147(对着表面123)以暴露TSV122和半导体裸片134的背面148并减少该封装的高度。半导体晶圆118的剩余部分组成具有用于电气互连的TSV122的转接板149。
在图3i中，在转接板149的表面151上方形成互连结构150。互连结构150包括在表面151上方形成的绝缘或钝化层152，诸如使用PVD、CVD、印刷、旋涂、喷涂、烧结或加热氧化形成的。绝缘层152可以是一层或更多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似的绝缘和结构特性的其它材料。通过蚀刻工艺除去一部分绝缘层152以暴露TSV122。
使用图案化和沉积工艺，诸如PVD、CVD、溅射、电解电镀和无电镀在TSV122和绝缘层152的除去部分上方形成导电层154。导电层154可以是一层或更多层Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。在导电层154上方可形成凸起下金属化(UBM)层。将导电层154的一个部分电连接到TSV122和电路层124。根据该半导体器件的设计和功能，导电层154的其它部分可以被电气共用或电气绝缘。
使用蒸发、电解电镀、无电镀、球状滴、或丝网印刷工艺在筑起互连结构150的上方沉积导电凸起材料并将其电连接到导电层154。该凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，伴随可选的焊剂溶液。例如，该凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的结合或粘着工艺将该凸起材料粘着于导电层154。在一个实施方式中，通过将该材料加热到它的熔点以上回流该凸起材料以形成球状小珠或凸起156。在一些应用中，第二次回流凸起156以改善与导电层154的电接触。还可以将该凸起压缩粘结到导电层154。凸起156代表在能够导电层154上方形成的一种类型的互连结构。该互连结构还可以使用柱状凸起、微凸起、导电柱、导电膏或其它电气互连。
通过化学蚀刻、机械剥落、CMP、机械掩模、热烘烤、激光扫描或湿法剥离除去载体144和带146。使用锯条或激光切割器件160将半导体裸片132和134独立化为单独的WLCSMP。图4显示了独立化之后的WLCSMP162。将无源元件164，诸如电阻器、电容器、电感器，或有源元件安装到转接板149。通过凸起136将半导体裸片134电连接到半导体裸片132。通过电路层124和包含TSV122的转接板149将半导体裸片132电连接到互连结构150。WLCSMP162具有用于容纳半导体裸片134的开口腔以减少该封装的高度。该研磨工艺还减少了WLCSMP162的高度。在一个实施方式中，由于沟槽130提供的额外的切割空隙，转接板149的侧面被密封剂140覆盖。替代地，没有沟槽130，转接板149的侧面可以被暴露。半导体裸片132的暴露表面143和半导体裸片134的暴露表面148提供了良好的热散逸。半导体裸片132和134和转接板149的类似的基底材料，例如硅，提供了热应力释放并使得WLCSMP162在面对该封装的各元件间的CTE不匹配时很坚固。相应地，WLCSMP162发生翘曲的情况减少。
在上述工艺的一种变形中，在图3h后，在转接板149的表面151上方形成互连结构170，如图5所示。互连结构170包括使用旋涂、薄膜层压、铸模或其它合适的沉积工艺在表面151上方形成的聚合物绝缘层172。聚合物绝缘层172可以是一层或更多层聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或具有类似的绝缘和结构特性的其它材料。通过蚀刻工艺除去一部分聚合物绝缘层172以暴露TSV122。
使用图案化和沉积工艺，诸如PVD、CVD、溅射、电解电镀和无电镀在TSV122和聚合物绝缘层172的除去部分上方形成导电层174。导电层174可以是一层或更多层Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。将导电层174的一部分电连接到TSV122和电路层124。根据该半导体器件的设计和功能，导电层174的其它部分可以被电气共用或电气绝缘。
使用蒸发、电解电镀、无电镀、球状滴、或丝网印刷工艺在筑起互连结构170的上方沉积导电凸起材料并将其电连接到导电层174。该凸起材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合，伴随可选的焊剂溶液。例如，该凸起材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的结合或粘着工艺将该凸起材料粘着于导电层174。在一个实施方式中，通过将该材料加热到它的熔点以上回流该凸起材料以形成球状小珠或凸起176。在一些应用中，第二次回流凸起176以改善与导电层174的电接触。还可以将该凸起压缩粘结到导电层174。凸起176代表在能够导电层174上方形成的一种类型的互连结构。该互连结构还可以使用柱状凸起、微凸起、导电柱、导电膏或其它电气互连。
图6显示了WLCSMP178，包括图3a-3i、4中描述的特征和用导热粘着剂安装到半导体裸片132的表面143和密封剂140的金属板180。金属板180也可以是由无电或电镀工艺形成的。金属板180作为热扩散器运转以从WLCSMP178散逸热能。金属板180可以是铝、铜或具有高导热率的另一种材料。可选的裸片附接粘着剂或热中间层(TIM)182将金属板180固定到半导体裸片132和密封剂140。金属板180增加了WLCSMP178的硬度。
图7显示了WLCSMP190，包括图3a-3i、4中描述的特征和用粘着剂安装到半导体裸片132的表面143和密封剂140的金属板192。金属板192也可以是通过无电或电镀工艺形成的。金属板192作为电磁干扰(EMI)或射频干扰(RFI)屏蔽层运转。金属板192可以是铜、铝、铁氧体或羰基铁、不锈钢、镍银、低碳钢、硅铁钢、箔、环氧树脂、导电树脂及其它能够阻挡或吸收EMI、RFI和其它器件间干扰的金属或合成物。该屏蔽层也可以是非金属材料，诸如碳黑或高岭土以减少EMI和RFI的影响。通过导电柱或销194、电路层124、转接板149中的TSV122、和互连结构150将金属板192接地。导电柱194可以是金销或铜柱或焊料。金属板192还作为热扩散器运转以从WLCSMP190散逸热能。
图8显示了WLCSMP196，包括图3a-3i、4中描述的特征和在密封剂140中形成的导电柱或销198。导电柱198可以是通过在密封剂140中激光打孔或蚀刻通孔并用导电材料(诸如铜、金或焊料)填充该通孔而形成的。导电柱198为堆叠的半导体封装提供额外的互连能力。
图9显示了WLCSMP200，包括图3a-3i和4所述的特征(除了图3f中所述的研磨操作留下覆盖半导体裸片132的表面143的密封剂140以外)。可以在密封剂140中通过激光打孔或蚀刻通孔并用导电材料(诸如Cu、Au或焊料)填充该通孔而形成导电柱或销202。在密封剂140中形成导电层204。导电柱202和导电层204为扇入堆叠半导体封装提供额外的互连能力。
图10显示了WLCSMP210，包括图3a-3i和4中所述的特征。另外，可以在密封剂140中通过激光打孔或蚀刻通孔并用导电材料(诸如Cu、Au或焊料)填充该通孔而形成导电柱或销212。在半导体裸片132的表面143和密封剂140上方形成互连结构214。互连结构214包括使用PVD、CVD、印刷、旋涂、喷涂、烧结或加热氧化形成的绝缘或钝化层216。绝缘层216可以是一层或更多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构特性的其它材料。使用图案化和沉积工艺(诸如PVD、CVD、溅射、电解电镀和无电镀)在绝缘层216中形成导电层218。导电层218可以是一层或更多层Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电层218的一个部分电连接到导电柱212。根据该半导体器件的设计和功能，导电层218的其它部分可以被电气共用或者电气绝缘。导电柱212和互连结构214为扇入堆叠半导体封装提供额外的互连能力。
图11显示了WLCSMP220，包括图3a-3i和4中所述的特征。另外，可以在密封剂140中通过激光打孔或蚀刻通孔并用导电材料(诸如Cu、Au或焊料)填充该通孔而形成导电柱或销222。在半导体裸片132的表面143和密封剂140上方形成互连结构224。互连结构224包括使用PVD、CVD、印刷、旋涂、喷涂、烧结或加热氧化形成的绝缘或钝化层226。绝缘层226可以是一层或更多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构特性的其它材料。通过蚀刻工艺除去一部分绝缘层226。使用图案化和沉积工艺(诸如PVD、CVD、溅射、电解电镀和无电镀)在绝缘层226的除去部分中形成导电层228。导电层228可以是一层或更多层Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料。导电柱222和导电层226为堆叠半导体封装提供额外的互连能力。
图12显示WLCSMP230，包括在图3a-3i和4中所述的特征。另外，可以通过在半导体裸片134中激光打孔或蚀刻通孔并用导电材料(诸如Cu或Au)填充该通孔而形成导电柱232。互连结构150在半导体裸片134的表面148上方延伸。半导体裸片134的表面158上方的导电柱232和互连结构150为堆叠半导体封装提供额外的互连能力。
尽管已经详细描述了本发明的一个或更多个实施方式，熟练的技术人员将能理解，可以对那些实施方式进行修改和改编而不违背下述权利要求中阐明的本发明的范围。

Claims (12)

1.一种制造半导体器件的方法，所述方法包括：
提供半导体晶圆；
形成穿过所述半导体晶圆的多个导电通孔；
在所述半导体晶圆中形成第一空腔；
将第一半导体裸片安装到第二半导体裸片上；
将所述第一和第二半导体裸片安装到所述半导体晶圆上以便所述第一半导体裸片被置于所述半导体晶圆上方并被电连接到所述导电通孔，且所述第二半导体裸片被置于所述第一空腔内；
在所述半导体晶圆上方并围绕所述第一和第二半导体裸片沉积密封剂；
除去所述半导体晶圆的一部分以暴露所述导电通孔和所述第二半导体裸片的第一表面，以致于所述半导体晶圆的剩余部分作为用于所述第一和第二半导体裸片的转接板而工作；以及
在所述转接板上方形成第一互连结构。
2.根据权利要求1所述的方法，其特征在于，所述方法进一步包括：
形成穿过围绕所述第一半导体裸片的所述密封剂的多个导电柱；以及
在所述密封剂中形成导电层。
3.根据权利要求1所述的方法，其特征在于，所述方法进一步包括除去所述密封剂的一部分以暴露所述第一半导体裸片的第一表面。
4.根据权利要求1所述的方法，其特征在于，所述方法进一步包括形成穿过所述第二半导体裸片的多个导电通孔。
5.根据权利要求1所述的方法，其特征在于，所述方法进一步包括在所述第一半导体裸片的第一表面上方形成金属板。
6.根据权利要求3所述的方法，其特征在于，所述方法进一步包括在所述第一半导体裸片的所述第一表面上方形成第二互连结构。
7.一种制造半导体器件的方法，所述方法包括：
提供半导体晶圆；
形成穿过所述半导体晶圆的多个导电通孔；
在所述半导体晶圆中形成空腔；
将第一半导体裸片安装到第二半导体裸片上；
将所述第一和第二半导体裸片安装到所述半导体晶圆上以致所述第一半导体裸片被布置在所述半导体晶圆之上并且被电连接至所述导电通孔以及所述第二半导体裸片被布置在所述空腔内；
在所述半导体晶圆和第一及第二半导体裸片上方沉积密封剂；以及
除去所述半导体晶圆的一部分以暴露所述导电通孔和所述第二半导体裸片的第一表面，以致于所述半导体晶圆的剩余部分作为用于所述第一和第二半导体裸片的转接板而工作。
8.根据权利要求7所述的方法，其特征在于，所述方法进一步包括在所述转接板上方形成互连结构。
9.根据权利要求7所述的方法，其特征在于，所述方法进一步包括除去所述密封剂的一部分以暴露所述第一半导体裸片的第一表面。
10.根据权利要求7所述的方法，其特征在于，所述方法进一步包括形成穿过围绕所述第一半导体裸片的所述密封剂的多个导电柱。
11.根据权利要求7所述的方法，其特征在于，所述方法进一步包括在所述第一半导体裸片的第一表面上方形成金属板。
12.根据权利要求7所述的方法，其特征在于，所述方法进一步包括在所述第一半导体裸片的第一表面上方形成互连结构。
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Families Citing this family (116)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200522293A (en) * 2003-10-01 2005-07-01 Koninkl Philips Electronics Nv Electrical shielding in stacked dies by using conductive die attach adhesive
US8169058B2 (en) * 2009-08-21 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
USRE48111E1 (en) 2009-08-21 2020-07-21 JCET Semiconductor (Shaoxing) Co. Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8383457B2 (en) * 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US10297550B2 (en) 2010-02-05 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC architecture with interposer and interconnect structure for bonding dies
US20110193235A1 (en) * 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Die Inside Interposer
US9385095B2 (en) * 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8455995B2 (en) 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
KR101765473B1 (ko) * 2010-06-21 2017-08-24 삼성전자 주식회사 인쇄 회로 기판 및 이를 포함하는 반도체 패키지
US20120001339A1 (en) * 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8076184B1 (en) * 2010-08-16 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
US8288201B2 (en) 2010-08-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming FO-WLCSP with discrete semiconductor components mounted under and over semiconductor die
US8518746B2 (en) * 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US8409922B2 (en) * 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US9059187B2 (en) 2010-09-30 2015-06-16 Ibiden Co., Ltd. Electronic component having encapsulated wiring board and method for manufacturing the same
US8895380B2 (en) 2010-11-22 2014-11-25 Bridge Semiconductor Corporation Method of making semiconductor assembly with built-in stiffener and semiconductor assembly manufactured thereby
US8367475B2 (en) * 2011-03-25 2013-02-05 Broadcom Corporation Chip scale package assembly in reconstitution panel process format
US20130075892A1 (en) * 2011-09-27 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Three Dimensional Integrated Circuit Fabrication
US20130082383A1 (en) * 2011-10-03 2013-04-04 Texas Instruments Incorporated Electronic assembly having mixed interface including tsv die
CN103168355B (zh) * 2011-10-12 2017-04-05 日本碍子株式会社 大容量模块的外围电路用的电路基板及包含使用该电路基板的外围电路的大容量模块
US9190391B2 (en) * 2011-10-26 2015-11-17 Maxim Integrated Products, Inc. Three-dimensional chip-to-wafer integration
US9006889B2 (en) * 2011-11-11 2015-04-14 Skyworks Solutions, Inc. Flip chip packages with improved thermal performance
US9123700B2 (en) 2012-01-06 2015-09-01 Micron Technology, Inc. Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias
US9548251B2 (en) * 2012-01-12 2017-01-17 Broadcom Corporation Semiconductor interposer having a cavity for intra-interposer die
JP2013160942A (ja) * 2012-02-06 2013-08-19 Sony Corp 半導体装置およびその製造方法、並びに電子機器
KR20130105175A (ko) * 2012-03-16 2013-09-25 삼성전자주식회사 보호 층을 갖는 반도체 패키지 및 그 형성 방법
TWI528876B (zh) 2012-03-22 2016-04-01 矽品精密工業股份有限公司 中介板及其電性測試方法
US9082780B2 (en) * 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US20130256895A1 (en) * 2012-03-30 2013-10-03 Michael Su Stacked semiconductor components with universal interconnect footprint
US10269863B2 (en) * 2012-04-18 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for via last through-vias
US8765549B2 (en) 2012-04-27 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor for interposers and methods of manufacture thereof
US9040346B2 (en) 2012-05-03 2015-05-26 Infineon Technologies Ag Semiconductor package and methods of formation thereof
JP5474127B2 (ja) * 2012-05-14 2014-04-16 株式会社野田スクリーン 半導体装置
US8878338B2 (en) 2012-05-31 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor for interposers and methods of manufacture thereof
US8853058B2 (en) * 2012-06-22 2014-10-07 Freescale Semiconductor, Inc. Method of making surface mount stacked semiconductor devices
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
TWI503928B (zh) * 2012-09-10 2015-10-11 矽品精密工業股份有限公司 半導體封裝件及其製法與中介板結構
US9443797B2 (en) 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
US9818734B2 (en) * 2012-09-14 2017-11-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
US9978654B2 (en) * 2012-09-14 2018-05-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP
KR101989516B1 (ko) * 2012-09-24 2019-06-14 삼성전자주식회사 반도체 패키지
US10269676B2 (en) * 2012-10-04 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced package-on-package (PoP)
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
CN103165543B (zh) * 2013-02-08 2015-11-18 日月光半导体制造股份有限公司 半导体元件及其制造方法与封装构造
US9177903B2 (en) 2013-03-29 2015-11-03 Stmicroelectronics, Inc. Enhanced flip-chip die architecture
JP2014222728A (ja) * 2013-05-14 2014-11-27 凸版印刷株式会社 半導体パッケージ
KR102077153B1 (ko) 2013-06-21 2020-02-14 삼성전자주식회사 관통전극을 갖는 반도체 패키지 및 그 제조방법
CN103346131A (zh) * 2013-06-25 2013-10-09 华进半导体封装先导技术研发中心有限公司 一种细间距pop式封装结构和封装方法
US9847315B2 (en) * 2013-08-30 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Packages, packaging methods, and packaged semiconductor devices
US9293409B2 (en) 2013-09-11 2016-03-22 Infineon Technologies Ag Method for manufacturing a semiconductor device, and semiconductor device
US9252054B2 (en) 2013-09-13 2016-02-02 Industrial Technology Research Institute Thinned integrated circuit device and manufacturing process for the same
US9299650B1 (en) * 2013-09-25 2016-03-29 Stats Chippac Ltd. Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9793242B2 (en) * 2013-12-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with die stack including exposed molding underfill
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US10121768B2 (en) 2015-05-27 2018-11-06 Bridge Semiconductor Corporation Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same
US11291146B2 (en) 2014-03-07 2022-03-29 Bridge Semiconductor Corp. Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same
US10354984B2 (en) 2015-05-27 2019-07-16 Bridge Semiconductor Corporation Semiconductor assembly with electromagnetic shielding and thermally enhanced characteristics and method of making the same
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
KR102258743B1 (ko) * 2014-04-30 2021-06-02 삼성전자주식회사 반도체 패키지의 제조 방법, 이에 의해 형성된 반도체 패키지 및 이를 포함하는 반도체 장치
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9402312B2 (en) 2014-05-12 2016-07-26 Invensas Corporation Circuit assemblies with multiple interposer substrates, and methods of fabrication
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
KR101563909B1 (ko) 2014-08-19 2015-10-28 앰코 테크놀로지 코리아 주식회사 패키지 온 패키지 제조 방법
US9666559B2 (en) * 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
FI126380B (en) * 2014-10-27 2016-11-15 Kone Corp The drive unit
TWI566339B (zh) * 2014-11-11 2017-01-11 矽品精密工業股份有限公司 電子封裝件及其製法
US9589936B2 (en) * 2014-11-20 2017-03-07 Apple Inc. 3D integration of fanout wafer level packages
US9941226B2 (en) 2014-12-15 2018-04-10 Industrial Technology Research Institute Integrated millimeter-wave chip package
RU2584575C1 (ru) * 2014-12-25 2016-05-20 Общество с ограниченной ответственностью "ЗЕЛНАС" Интерпозер и способ его изготовления
US9893017B2 (en) 2015-04-09 2018-02-13 STATS ChipPAC Pte. Ltd. Double-sided semiconductor package and dual-mold method of making same
KR20160122022A (ko) * 2015-04-13 2016-10-21 에스케이하이닉스 주식회사 인터포저를 갖는 반도체 패키지 및 제조 방법
US9437536B1 (en) * 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
US20160365334A1 (en) * 2015-06-09 2016-12-15 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
KR102408841B1 (ko) 2015-06-25 2022-06-14 인텔 코포레이션 패키지 온 패키지를 위한 리세싱된 전도성 컨택들을 갖는 집적 회로 구조체들
EP3314648A4 (en) * 2015-06-25 2019-01-09 Intel Corporation INTEGRATED CIRCUIT STRUCTURES WITH INTERPOSERS WITH SAVINGS
CN105140211A (zh) * 2015-07-14 2015-12-09 华进半导体封装先导技术研发中心有限公司 一种fan-out的封装结构及其封装方法
US11901274B2 (en) * 2015-09-25 2024-02-13 Intel Corporation Packaged integrated circuit device with recess structure
WO2017142978A1 (en) * 2016-02-15 2017-08-24 Transsip Inc Emi shielded integrated circuit packages and methods of making the same
US9941186B2 (en) * 2016-06-30 2018-04-10 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
US10600679B2 (en) * 2016-11-17 2020-03-24 Samsung Electronics Co., Ltd. Fan-out semiconductor package
US9935079B1 (en) 2016-12-08 2018-04-03 Nxp Usa, Inc. Laser sintered interconnections between die
WO2018125055A1 (en) * 2016-12-27 2018-07-05 Intel IP Corporation Packages of stacking integrated circuits
CN110024117B (zh) * 2016-12-29 2023-07-21 英特尔公司 用于系统级封装设备的与铜柱连接的裸管芯智能桥
CN110024108A (zh) * 2016-12-31 2019-07-16 英特尔公司 具有加强件的电子封装组装件
US9892920B1 (en) * 2017-01-05 2018-02-13 Lam Research Corporation Low stress bonding of silicon or germanium parts
JP6640780B2 (ja) * 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置
CN107910315B (zh) * 2017-11-10 2020-09-25 深圳市盛路物联通讯技术有限公司 芯片封装
US10546817B2 (en) * 2017-12-28 2020-01-28 Intel IP Corporation Face-up fan-out electronic package with passive components using a support
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
CN110660805B (zh) * 2018-06-28 2023-06-20 西部数据技术公司 包含分支存储器裸芯模块的堆叠半导体装置
KR102615701B1 (ko) 2018-06-14 2023-12-21 삼성전자주식회사 관통 비아를 포함하는 반도체 장치, 반도체 패키지 및 이의 제조 방법
US10985109B2 (en) 2018-12-27 2021-04-20 STATS ChipPAC Pte. Ltd. Shielded semiconductor packages with open terminals and methods of making via two-step process
CN110211954A (zh) * 2019-06-17 2019-09-06 上海先方半导体有限公司 一种多芯片封装结构及其制造方法
CN110211946A (zh) * 2019-06-17 2019-09-06 上海先方半导体有限公司 一种芯片封装结构及其制造方法
US11145638B2 (en) * 2019-09-16 2021-10-12 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
KR20210043103A (ko) 2019-10-11 2021-04-21 삼성전자주식회사 반도체 패키지
US11404380B2 (en) * 2019-12-19 2022-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11205629B2 (en) * 2020-01-21 2021-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US11291106B2 (en) * 2020-01-29 2022-03-29 Dell Products L.P. System and method for enhanced cooling
US11557565B2 (en) 2020-10-06 2023-01-17 Nxp Usa, Inc. Semiconductor device assembly and method therefor
US11502054B2 (en) 2020-11-11 2022-11-15 Nxp Usa, Inc. Semiconductor device assembly and method therefor
US20220157732A1 (en) * 2020-11-13 2022-05-19 Mediatek Inc. Semiconductor package and method of forming the same
CN112908867A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 2.5d封装结构及其制作方法
CN115020369A (zh) * 2021-03-03 2022-09-06 华为技术有限公司 电路板组件及其制造方法和电子设备
US11854922B2 (en) * 2021-06-21 2023-12-26 Texas Instruments Incorporated Semicondutor package substrate with die cavity and redistribution layer
US20230014046A1 (en) * 2021-07-13 2023-01-19 Mediatek Inc. Semiconductor devices with in-package PGS for coupling noise suppression
CN113764288A (zh) * 2021-08-02 2021-12-07 苏州通富超威半导体有限公司 一种芯片封装方法及封装结构

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7261596B2 (en) * 2005-01-05 2007-08-28 Shinko Electric Industries Co., Ltd. Shielded semiconductor device
CN101252125A (zh) * 2007-02-21 2008-08-27 育霈科技股份有限公司 具减缩结构的复数晶粒封装结构与其形成方法

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JPH08167630A (ja) * 1994-12-15 1996-06-25 Hitachi Ltd チップ接続構造
EP0732107A3 (en) 1995-03-16 1997-05-07 Toshiba Kk Screen device for circuit substrate
US5620928A (en) 1995-05-11 1997-04-15 National Semiconductor Corporation Ultra thin ball grid array using a flex tape or printed wiring board substrate and method
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US5977640A (en) 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
JP2001077301A (ja) * 1999-08-24 2001-03-23 Amkor Technology Korea Inc 半導体パッケージ及びその製造方法
JP2001077293A (ja) 1999-09-02 2001-03-23 Nec Corp 半導体装置
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6492726B1 (en) 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
KR100364635B1 (ko) * 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
US6798055B2 (en) 2001-03-12 2004-09-28 Micron Technology Die support structure
TW523887B (en) 2001-11-15 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor packaged device and its manufacturing method
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
US6680529B2 (en) 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US7548430B1 (en) 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US6906415B2 (en) 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US6659512B1 (en) 2002-07-18 2003-12-09 Hewlett-Packard Development Company, L.P. Integrated circuit package employing flip-chip technology and method of assembly
JP2004214249A (ja) * 2002-12-27 2004-07-29 Renesas Technology Corp 半導体モジュール
US6838776B2 (en) 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
TWI225299B (en) 2003-05-02 2004-12-11 Advanced Semiconductor Eng Stacked flip chip package
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US6864165B1 (en) * 2003-09-15 2005-03-08 International Business Machines Corporation Method of fabricating integrated electronic chip with an interconnect device
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
DE102004022884B4 (de) 2004-05-06 2007-07-19 Infineon Technologies Ag Halbleiterbauteil mit einem Umverdrahtungssubstrat und Verfahren zur Herstellung desselben
US7745918B1 (en) * 2004-11-24 2010-06-29 Amkor Technology, Inc. Package in package (PiP)
US7977579B2 (en) 2006-03-30 2011-07-12 Stats Chippac Ltd. Multiple flip-chip integrated circuit package system
JP2008016508A (ja) * 2006-07-03 2008-01-24 Nec Electronics Corp 半導体装置およびその製造方法
JP2008141059A (ja) 2006-12-04 2008-06-19 Nec Electronics Corp 半導体装置
KR100840788B1 (ko) 2006-12-05 2008-06-23 삼성전자주식회사 칩 적층 패키지 및 그 제조 방법
US20080174008A1 (en) * 2007-01-18 2008-07-24 Wen-Kun Yang Structure of Memory Card and the Method of the Same
US7553752B2 (en) * 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
US7619901B2 (en) 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
US7863096B2 (en) * 2008-07-17 2011-01-04 Fairchild Semiconductor Corporation Embedded die package and process flow using a pre-molded carrier
US8115292B2 (en) 2008-10-23 2012-02-14 United Test And Assembly Center Ltd. Interposer for semiconductor package
US8624370B2 (en) 2009-03-20 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with an interposer and method of manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7261596B2 (en) * 2005-01-05 2007-08-28 Shinko Electric Industries Co., Ltd. Shielded semiconductor device
CN101252125A (zh) * 2007-02-21 2008-08-27 育霈科技股份有限公司 具减缩结构的复数晶粒封装结构与其形成方法

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