CN101964630A - CMOS (Complementary Metal-Oxide-Semiconductor) inverter pair based method and circuit for designing high-speed chaotic oscillator - Google Patents
CMOS (Complementary Metal-Oxide-Semiconductor) inverter pair based method and circuit for designing high-speed chaotic oscillator Download PDFInfo
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- CN101964630A CN101964630A CN 201010275767 CN201010275767A CN101964630A CN 101964630 A CN101964630 A CN 101964630A CN 201010275767 CN201010275767 CN 201010275767 CN 201010275767 A CN201010275767 A CN 201010275767A CN 101964630 A CN101964630 A CN 101964630A
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Abstract
The invention discloses a CMOS (Complementary Metal-Oxide-Semiconductor) inverter pair based method and a circuit for designing a high-speed chaotic oscillator. In the invention, a negative resistance circuit consisting of a CMOS inverter pair is used for replacing a negative resistance circuit based on an operational amplifier in a Chua's circuit to generate chaotic oscillation; a CMOS inverter circuit consists of a chip CD4069 or consists of two PMOS (P-channel Metal Oxide Semiconductor) tubes and two NMOS (N-channel metal oxide semiconductor) tubes, inherits the characteristics of the traditional Chua's circuit and is used for generating chaotic oscillation signals; and when a CMOS inverter pair is used, i.e. two reversely connected inverters are used as a negative resistance circuit of an oscillator, the defect of lower working frequency of the traditional Chua's circuit can be overcome, and the inverter pair can work with a higher frequency, so that high-speed chaotic oscillation can be generated, and the working frequency reaches /MHz. The circuit can be designed and realized by using discrete devices, and the chip of the high-speed chaotic oscillator can be designed and realized by using a standard CMOS process, thus the circuit is beneficial to the manufacture and the production of chaotic signal sources in a large scale with low cost.
Description
Technical field
The present invention relates to a kind of method for designing and circuit of high speed chaotic oscillator, relate in particular to a kind of based on CMOS inverter right high speed chaotic oscillator method for designing and circuit.
Background technology
Chaos is a huge motive force of chaos circuit research in Application in Communication Systems.Along with spread spectrum communication application more and more widely, the application potential of chaos spread spectrum communication in commercial wireless communication receives much concern.A hot research direction of chaos spread spectrum communication at present is exactly to utilize the spread spectrum characteristic of chaotic signal self, is the chaotic carrier spread spectrum communication research that carrier wave carries out some innovation systems with the chaotic signal.In these researchs, the design of high speed chaotic oscillator is most important with realization.
Cai's circuit is one of the most classical chaotic oscillator, and a lot of scholars have carried out comparatively deep research to it.Negative resistance electronic circuit in traditional cai's circuit is based on that operational amplifier makes up more, the speed limit of operational amplifier the frequency of oscillation of cai's circuit, the chaotic signal fundamental frequency that makes traditional cai's circuit produce is many in the kHz magnitude.In order to make chaotic oscillation signal that cai's circuit produces 1MHz even higher frequency satisfying the requirement of broadband chaotic communication, possible method just is to use the high speed device with negative resistance charactertistic to substitute negative resistance electronic circuit in traditional cai's circuit.
Summary of the invention
In order to improve the frequency of the chaotic oscillation signal that cai's circuit produces, the object of the present invention is to provide a kind of based on CMOS inverter right high speed chaotic oscillator method for designing and circuit, use has the CMOS inverter of negative resistance charactertistic to the Method and circuits that the negative resistance circuit that substitutes in traditional cai's circuit carries out the design of high speed chaos circuit, makes cai's circuit produce high speed chaotic oscillation signal.
The technical solution used in the present invention is:
One. based on the right high speed chaotic oscillator method for designing of CMOS inverter:
1) uses the CMOS inverter that the negative resistance circuit that constitutes is substituted in the cai's circuit based on the negative resistance circuit of operational amplifier, produce chaotic oscillation.
2) method for designing of circuit parameter is: at first calculate " current-voltage " characteristic of the negative resistance circuit that constitutes by two differential pairs, get 1.1 times of values of absolute value of the impedance of negative resistance section central point as resistance R, then, inductance L, capacitor C
1, capacitor C
2Need satisfy condition:
C
1＝C
2/α (1)
L＝C
2R
2/β (2)
Wherein: α, β is the characteristic parameter of cai's circuit chaotic oscillation, during design in cai's circuit chaotic characteristic alpha-beta bifurcation diagram chaotic oscillation regional center part value, α, β get fixed after, get again and decide capacitor C
2After, by formula (1), (2) obtain capacitor C
1Value with inductance L.
Two. a kind of circuit based on the right high speed chaotic oscillator method for designing of CMOS inverter:
One end and the capacitor C of inductance L
2An end be connected in an end of resistance R, the other end of resistance R and capacitor C
1An end be connected the other end of inductance L, capacitor C with the end of CMOS inverter to circuit
2The other end and capacitor C
1The other end be connected with the other end of CMOS inverter circuit.
Described CMOS inverter is chip CD4069 to circuit, an end, the capacitor C of its first pin, the 4th pin and resistance R
1An end connect second pin, three-prong and capacitor C
1The other end connect, the 7th pin ground connection, the 8th pin connects power supply.
Described CMOS inverter comprises two PMOS pipes and two NMOS pipes to circuit; The one PMOS pipe is connected power supply with the source electrode of the 2nd PMOS pipe, the grid of the grid of a PMOS pipe, a NMOS pipe, the drain electrode of the 2nd PMOS pipe, the 2nd NMOS pipe drain electrode and resistance R and capacitor C
2An end connect the source ground of the source electrode of a NMOS pipe and the 2nd NMOS pipe, the grid and the capacitor C of the drain electrode of the drain electrode of a PMOS pipe, a NMOS pipe, the grid of the 2nd PMOS pipe and the 2nd NMOS pipe
2The other end connect.
The beneficial effect that the present invention has is:
This circuit has been inherited the characteristic of traditional cai's circuit, can produce the chaotic oscillation signal.Use the CMOS inverter right, the i.e. inverter of two reversal connections, negative resistance electronic circuit as oscillator, because the CMOS inverter is to overcoming the lower shortcoming of traditional cai's circuit operating frequency, work in higher frequency, so can produce chaotic oscillation at a high speed, operating frequency reach 1MHz and more than.This circuit both can use discrete device to design and realize, also can use the CMOS technology of standard to carry out the chip design and the realization of high speed chaotic oscillator, helped the manufacturing and the production of little cost chaos signal source in enormous quantities.
Description of drawings
Fig. 1 is a high speed chaotic oscillator schematic diagram of the present invention.
Fig. 2 is to use the high speed chaotic oscillator circuit diagram of discrete device design.
The high speed chaotic oscillator chaos attractor that Fig. 3 is to use oscilloscope to observe.
The high speed chaotic oscillator time-domain signal that Fig. 4 is to use oscilloscope to observe.
Fig. 5 is to use the high speed chaotic oscillator circuit diagram of standard CMOS integrated circuit technology design.
Embodiment
The invention will be further described below in conjunction with drawings and Examples.
As shown in Figure 1, chaotic oscillator of the present invention is on the basis of traditional cai's circuit, and the negative resistance circuit that uses the CMOS inverter that circuit is constituted substitutes in traditional cai's circuit based on the negative resistance circuit of operational amplifier, and generation speed is chaotic oscillation faster.
As shown in Figure 1, circuit structure of the present invention is: an end and the capacitor C of inductance L
2An end be connected in an end of resistance R, the other end of resistance R and capacitor C
1An end be connected the other end of inductance L, capacitor C with the end of CMOS inverter to circuit
2The other end and capacitor C
1The other end be connected with the other end of CMOS inverter circuit.
Selected CMOS inverter to the basis on, the parameter designing in the circuit relates to capacitor C 1, C2, inductance L, the value of resistance R.The specific design method is: at first calculate or emulation by CMOS inverter " current-voltage " relation to the negative resistance circuit that constitutes, promptly calculate or analogous diagram 1 in flow through an end of resistance R, capacitor C
2An end and the CMOS inverter to the electric current on the end connection line of circuit and CMOS inverter relation to the voltage at circuit two ends, this " current-voltage " closes and ties up to the bias point place and present negative resistance charactertistic.Get 1.1 times of values of absolute value of the impedance of negative resistance section central point as resistance R, then, inductance L, capacitor C
1, capacitor C
2Need satisfy condition:
C
1＝C
2/α(1)
L＝C
2R
2/β(2)
Wherein, α, β is the characteristic parameter of traditional cai's circuit chaotic oscillation, during design in traditional cai's circuit chaotic characteristic alpha-beta bifurcation diagram chaotic oscillation regional center part value, α, β get fixed after, to ask for according to frequency of oscillation again and decide capacitor C
2, by formula (1), (2) obtain capacitor C then
1Value with inductance L.
Chaotic oscillator circuit of the present invention can use discrete electric capacity on the one hand, and inductance, resistive element and inverter are realized chip, also can use the CMOS technology of standard to realize on the other hand.Wherein, inverter comprises inverter 1 and inverter 2 to circuit.
When using discrete electric capacity, inductance, when resistive element and inverter are realized chip, a concrete exemplary circuit figure who implements as shown in Figure 2, electric capacity, inductance, resistance uses the discrete component of directly buying on the market, the CMOS inverter uses the chip CD4069 of National Semiconductor company to circuit, this chip is a inverter group circuit based on CMOS technology, comprise 6 inverters, only used in this exemplary circuit that wherein inverter 1 and inverter 2 are to constitute the CMOS inverter to circuit, the pin one of CD4069 is the input of inverter 1 among Fig. 2, and pin two is the output of inverter 1, pin 3 is inputs of inverter 2, and pin 4 is inverters to 2 output.In addition, inverter pin 7 ground connection, pin 8 meets power supply VCC, and supply voltage requires to be provided with according to chip, uses 5V direct current supply in this exemplary circuit.Use the circuit parameter design method in the technical solution of the present invention, at first obtain the right negative resistance charactertistic of inverter that is made of two inverters, the value of trying to achieve resistance R is about 1k ohm.The selected α value in two scrollwork attractors zone in the alpha-beta bifurcation diagram is 33.9, and the β value is 103.Selected capacitor C 2 values are 6.8nF, and can calculate the inductance L value according to formula is 66uH, and capacitor C 1 value is 180pF.Consider the error of circuit parameter, in the time of debugging, can adjust the state of circuit to make it to enter chaos state by the value of regulating circuit R.The two scrollwork attractors that use oscilloscope to observe when Fig. 3 adjusts to 950 ohm for resistance R.The voltage timing waveform at resistance R two ends when Fig. 4 is corresponding pair of scrollwork attractor state.
When using the standard CMOS process design to realize chaotic oscillator circuit of the present invention, inductance L uses on-chip spiral inductor to realize, electric capacity uses MIM (Metal-Insulator-Metal, metal-insulator-metal) electric capacity on the sheet, and resistance uses Poly (polysilicon) resistance.As shown in Figure 5, described CMOS inverter comprises two PMOS pipes and two NMOS pipes to circuit; The one PMOS pipe is connected power supply with the source electrode of the 2nd PMOS pipe, the grid of the grid of a PMOS pipe, a NMOS pipe, the drain electrode of the 2nd PMOS pipe, the 2nd NMOS pipe drain electrode and resistance R and capacitor C
2An end connect the source ground of the source electrode of a NMOS pipe and the 2nd NMOS pipe, the grid and the capacitor C of the drain electrode of the drain electrode of a PMOS pipe, a NMOS pipe, the grid of the 2nd PMOS pipe and the 2nd NMOS pipe
2The other end connect.Fig. 5 is to use the chaotic oscillator of magnificent 0.6um standard CMOS process design, and wherein the method for designing of parameter is the same.AVDD is an external power supply voltage among the figure, AVSS ground connection.
Claims (4)
1. one kind based on the right high speed chaotic oscillator method for designing of CMOS inverter, it is characterized in that:
1) uses the CMOS inverter that the negative resistance circuit that constitutes is substituted in the cai's circuit based on the negative resistance circuit of operational amplifier, produce chaotic oscillation.
2) method for designing of circuit parameter is: at first calculate " current-voltage " characteristic of the negative resistance circuit that constitutes by two differential pairs, get 1.1 times of values of absolute value of the impedance of negative resistance section central point as resistance R, then, inductance L, capacitor C
1, capacitor C
2Need satisfy condition:
C
1＝C
2/α (1)
L＝C
2R
2/β (2)
Wherein: α, β is the characteristic parameter of cai's circuit chaotic oscillation, during design in cai's circuit chaotic characteristic alpha-beta bifurcation diagram chaotic oscillation regional center part value, α, β get fixed after, get again and decide capacitor C
2After, by formula (1), (2) obtain capacitor C
1Value with inductance L.
2. a kind of based on the right high speed chaotic oscillator circuit of CMOS inverter according to the described method for designing of claim 1 is characterized in that: an end and the capacitor C of inductance L
2An end be connected in an end of resistance R, the other end of resistance R and capacitor C
1An end be connected the other end of inductance L, capacitor C with the end of CMOS inverter to circuit
2The other end and capacitor C
1The other end be connected with the other end of CMOS inverter circuit.
3. according to claim 2 a kind of it is characterized in that: described CMOS inverter is chip CD4069 to circuit based on the right high speed chaotic oscillator circuit of CMOS inverter, an end, the capacitor C of its first pin (1), the 4th pin (4) and resistance R
1An end connect second pin (2), three-prong (3) and capacitor C
1The other end connect, the 7th pin (7) ground connection, the 8th pin (8) connects power supply.
4. according to claim 2 a kind of based on the right high speed chaotic oscillator circuit of CMOS inverter, it is characterized in that: described CMOS inverter comprises two PMOS pipes and two NMOS pipes to circuit; The one PMOS pipe is connected power supply with the source electrode of the 2nd PMOS pipe, the grid of the grid of a PMOS pipe, a NMOS pipe, the drain electrode of the 2nd PMOS pipe, NMOS pipe drain electrode and resistance R and capacitor C
2An end connect the source ground of the source electrode of a NMOS pipe and the 2nd NMOS pipe, the grid and the capacitor C of the drain electrode of the drain electrode of a PMOS pipe, a NMOS pipe, the grid of the 2nd PMOS pipe and the 2nd NMOS pipe
2The other end connect.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102757677A CN101964630B (en) | 2010-09-07 | 2010-09-07 | CMOS (Complementary Metal-Oxide-Semiconductor) inverter pair based method and circuit for designing high-speed chaotic oscillator |
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|---|---|---|---|
| CN2010102757677A CN101964630B (en) | 2010-09-07 | 2010-09-07 | CMOS (Complementary Metal-Oxide-Semiconductor) inverter pair based method and circuit for designing high-speed chaotic oscillator |
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|---|---|
| CN101964630A true CN101964630A (en) | 2011-02-02 |
| CN101964630B CN101964630B (en) | 2012-05-30 |
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| CN2010102757677A Expired - Fee Related CN101964630B (en) | 2010-09-07 | 2010-09-07 | CMOS (Complementary Metal-Oxide-Semiconductor) inverter pair based method and circuit for designing high-speed chaotic oscillator |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1199968A (en) * | 1997-05-16 | 1998-11-25 | 中国科学院电子学研究所 | Deformed cai's circuit |
| US6980656B1 (en) * | 1998-07-17 | 2005-12-27 | Science Applications International Corporation | Chaotic communication system and method using modulation of nonreactive circuit elements |
-
2010
- 2010-09-07 CN CN2010102757677A patent/CN101964630B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1199968A (en) * | 1997-05-16 | 1998-11-25 | 中国科学院电子学研究所 | Deformed cai's circuit |
| US6980656B1 (en) * | 1998-07-17 | 2005-12-27 | Science Applications International Corporation | Chaotic communication system and method using modulation of nonreactive circuit elements |
| US20080008320A1 (en) * | 1998-07-17 | 2008-01-10 | Science Applications International Corporation | Chaotic Communication System with Modulation of Nonlinear Elements |
Non-Patent Citations (1)
| Title |
|---|
| 《重庆工商大学学报》 20070228 罗小华等 基于变型蔡氏电路的混沌特性 第24卷, 第1期 2 * |
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