CN101923145B - Power detection circuit, portable device and method for preventing data loss - Google Patents
Power detection circuit, portable device and method for preventing data loss Download PDFInfo
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- CN101923145B CN101923145B CN 200910145958 CN200910145958A CN101923145B CN 101923145 B CN101923145 B CN 101923145B CN 200910145958 CN200910145958 CN 200910145958 CN 200910145958 A CN200910145958 A CN 200910145958A CN 101923145 B CN101923145 B CN 101923145B
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Abstract
The invention provides a power detection circuit, a portable device and a method for preventing data loss. The power detection circuit comprises a data locking circuit, a discharging unit and a switching circuit, wherein the data locking circuit is used for receiving the voltage input by a power input end; the discharging unit is coupled between the power input end and the common receiving voltage to determine whether the first end and the second end thereof are short-circuited or not according to whether power detection signals are enabled or not; and the switching circuit is coupled between the power input end and the internal circuit of the portable device. During a testing period, when power detection signals are enabled, the first end and the second end of the switching circuit are open-circuited. In the testing period, if power low signals which are received by the switching circuit and are output by the data locking circuit are converted from a first state into a second state, the open-circuited state of the first end and the second end of the switching circuit is kept. In the invention, a combinational logic circuit is used for detecting the external power voltage input by batteries, and a capacitor can be used for keeping data stored in a register or/and a random access memory for a long time.
Description
Technical field
The invention relates to a kind of battery supply testing circuit of mancarried device, further, the method that the invention relates to a kind of power sense circuit, mancarried device and prevent Missing data.
Background technology
Along with the progress of science and technology, electronic technology by the earliest vacuum tube, transistor, proceeds to integrated circuit (IC) chip.Its purposes very extensively, also therefore, electronic product also gradually become indispensable daily necessities in modern's life.Many article gradually by the electronization.The purpose of electronization is nothing but to wish to allow people use convenience.Whether power supply exists, and has determined whether whole system can work.Especially utilize battery as the mancarried device of power supply.
Whether mancarried device in the past, low-voltage commonly used detect and decide power supply to remove, and power supply restores again, again by power supply reset (power on reset, POR) come restarting systems.Mostly need the fixing low-voltage detection circuit of power consumption, allow system when being lower than operating voltage, can the hold reset state.
Fig. 1 is the circuit diagram of low-voltage detection circuit of the prior art.Please refer to Fig. 1, this low-voltage detection circuit comprises comparer 101, on-off circuit 102, resistance R 101, R102 and generating circuit from reference voltage 103.For convenience of description, this circuit has also illustrated internal circuit 104 and power input 105 and capacitor C101.On-off circuit 102 is coupled between internal circuit 104 and the power input 105, and internal circuit 104 must just can receive outer power voltage VSRC by on-off circuit 102.In general, on-off circuit 102 is to implement with the P transistor npn npn.In general generating circuit from reference voltage 103, is to implement to produce the reference voltage that does not drift about with temperature and power supply with energy gap reference voltage circuit (Bandgap reference circuit) in order to produce reference voltage VREF.Resistance R 101 and R102 produce power supply dividing potential drop VDIV in order to outer power voltage VSRC is carried out dividing potential drop.The positive input terminal of comparer 101 receives above-mentioned reference voltage VREF, and the negative input end of comparer 101 receives power supply dividing potential drop VDIV.More specifically, the power supply of above-mentioned generating circuit from reference voltage 103 and above-mentioned comparer 101 all is to use internal power source voltage VKEEP, but not the outer power voltage VSRC that power input is inputted.
The electric weight of battery descended along with service time, and outer power voltage VSRC also follower descends.When outer power voltage VSRC dropped to some specific voltages, the expression battery did not have electricity soon, continued to use again, and the outer power voltage VSRC that battery is supplied will descend rapidly.At this moment, the power supply dividing potential drop VDIV that the negative input end of comparer 101 receives will drop to lower than reference voltage VREF, and therefore, the voltage of the comparison signal CP of the output terminal of comparer 101 output transfers positive saturation voltage to by negative saturation voltage.102 of on-off circuits are by emergency cut-off, and simultaneously, internal circuit 104 also can be according to comparison signal, and closing does not need the mac function used.The user then can take advantage of this moment, loses no time to change new battery.
For most system, this does not have very large problem.For some application, universal remote controller for example, the main flow of universal remote controller is still and uses static RAM as the memory element of storage current state at present.Power supply when battery electric quantity is not enough, although the function of telepilot is closed, low-voltage detection circuit is fixedly power consumption then, so stored electric charge of capacitor C101, can't keep the time more of a specified duration, may cause at last having little time to change battery, the data of static RAM just disappear.The user then needs to redefine this universal remote controller.Cause the inconvenience in the use.
Summary of the invention
A purpose of the present invention is to provide a kind of power sense circuit, is applicable to mancarried device, and this power sense circuit can reach extremely low static power consumption, therefore can prolong the time of system cut-off when changing battery.
Another object of the present invention is to provide a kind of mancarried device, when battery electric power is not enough, still can keep more permanent basic power supply.
Another purpose of the present invention is to provide a kind of method that prevents Missing data, and when battery removed, the data that still can keep for a long time static RAM inside did not run off.
In view of this, a purpose of the present invention is exactly a kind of power sense circuit is provided, and is applicable to mancarried device, and this mancarried device comprises power input, and this power sense circuit comprises data interlock circuit, discharge cell and on-off circuit.The data interlock circuit couples power input, the voltage of inputting in order to receive power input.Discharge cell comprises first end, the second end and control end, the first end of discharge cell couples power input, the second end of discharge cell couples and connects altogether voltage, the control end of discharge cell receives power detection signal, wherein, when power detection signal enables, the second terminal shortcircuit of the first end of discharge cell and discharge cell.On-off circuit comprises first end, the second end, the first control end and the second control end, and the first end of on-off circuit couples power input, and the first control end of on-off circuit couples the data interlock circuit, and the second control end of on-off circuit receives power detection signal.At a test period, power detection signal enables, the second end open circuit of the first end of on-off circuit and on-off circuit, if in test period, the low signal of power supply that the received data interlock circuit of the first control end of on-off circuit is exported transfers the second state to by the first state, then keeps the first end of on-off circuit and the second end open circuit of on-off circuit.
The present invention proposes a kind of mancarried device in addition, this mancarried device comprises power input, mac function, random access memory, microprocessor and power sense circuit, wherein, microprocessor couples random access memory, mac function, in order to control the running of mac function and random access memory.Power sense circuit comprises data interlock circuit, discharge cell and on-off circuit.The data interlock circuit couples power input, the voltage of inputting in order to receive power input.Discharge cell comprises first end, the second end and control end, the first end of discharge cell couples power input, the second end of discharge cell couples and connects altogether voltage, the control end of discharge cell receives power detection signal, wherein, when power detection signal enables, the second terminal shortcircuit of the first end of discharge cell and discharge cell.On-off circuit comprises first end, the second end, the first control end and the second control end.The first end of on-off circuit couples power input, the first control end of on-off circuit couples the data interlock circuit, the second control end of on-off circuit receives power detection signal, and the second end of on-off circuit couples random access memory, mac function and microprocessor.At a test period, power detection signal enables, the second terminal shortcircuit of the first end of discharge cell and discharge cell, and the second end of the first end of on-off circuit and on-off circuit opens circuit.If in test period, the low signal of power supply that the received data interlock circuit of the first control end of on-off circuit is exported transfers the second state to by the first state, then keeping the first end of on-off circuit and the second end of this on-off circuit opens circuit, and microprocessor stops the running of above-mentioned functions block, lower power consumption, keep the voltage of the second end of this on-off circuit, and then avoid the stored data of above-mentioned random access memory to run off.
According to the described power sense circuit of preferred embodiment of the present invention and mancarried device, above-mentioned data interlock circuit comprises phase inverter and the first N-type transistor.The input end of phase inverter couples power input.The transistorized grid of the first N-type couples the output terminal of phase inverter, and transistorized the first source-drain electrode of the first N-type couples power input, and transistorized the second source-drain electrode of the first N-type couples and connects altogether voltage.Aforementioned discharge cell comprises the second N-type transistor in addition.The transistorized grid of the second N-type receives power detection signal, and transistorized the first source-drain electrode of the second N-type couples power input, and transistorized the second source-drain electrode of the second N-type couples and connects altogether voltage.
According to the described power sense circuit of preferred embodiment of the present invention and mancarried device, the aforementioned switches circuit comprises P transistor npn npn and logical OR lock.The first source-drain electrode of P transistor npn npn couples power input, and the second source-drain electrode of P transistor npn npn is the second end of on-off circuit.The logical OR lock comprises first input end, the second input end and an output terminal.The output terminal of logical OR lock couples the grid of P transistor npn npn, and the first input end of logical OR lock couples the output terminal of phase inverter, and the second input end of logical OR lock receives power detection signal.As a same reason, the aforementioned switches circuit also can comprise P transistor npn npn and logic not b gate.The first source-drain electrode of P transistor npn npn couples power input, and the second source-drain electrode of P transistor npn npn is the second end of on-off circuit.The logic not b gate comprises first input end, the second input end and output terminal, the output terminal of logic not b gate couples the grid of P transistor npn npn, the first input end of logic not b gate couples the input end of phase inverter, and the second input end of logical OR lock receives power detection signal.
The present invention proposes a kind of method that prevents Missing data in addition, be applicable to mancarried device, this mancarried device comprises random access memory, power input, microprocessor and mac function, the method comprises the following steps: between power input and power supply relay on-off circuit to be set, wherein power input couples random access memory, microprocessor and mac function by the power supply relay, to provide power supply to upper random access memory, microprocessor and mac function; In the power supply relay capacitor is set; At power input the data interlock circuit is set; Each schedule time, the supply voltage of detection power input, this detecting step comprises: the cut-off said switching circuit; Trial discharges and recharges the supply voltage of power input to connecing altogether voltage; And judge whether the low signal of power supply that the data interlock circuit is exported changes, wherein, when the supply voltage of power input is discharged and recharged to connecing altogether voltage, the low signal of the power supply that the data interlock circuit is exported is changed; When the low signal of the power supply of data interlock circuit is changed, then comprise the following steps: to continue the cutoff switch circuit; And by microprocessor, closing function block.
Spirit of the present invention is to carry out voltage detecting with the outer power voltage that combinational logic circuit cleverly comes battery is inputted, because general logical circuit does not have static power consumption in theory, therefore can see, remove in battery supply, during again replying electric power, the not power consumption of whole power sense circuit.Also therefore we can come with electric capacity the stored data of long-time holding register (Register) or random access memory (RAM).
For above and other purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the circuit diagram of low-voltage detection circuit of the prior art;
Fig. 2 is the circuit system calcspar of the mancarried device of first embodiment of the invention;
Fig. 3 is the circuit system calcspar of the mancarried device of second embodiment of the invention;
Fig. 4 is the circuit system calcspar of the mancarried device of third embodiment of the invention;
Fig. 5 is the process flow diagram of the method that prevents Missing data of the embodiment of the invention.
Drawing reference numeral:
101: comparer
102: on-off circuit
R101, R102: resistance
103: generating circuit from reference voltage
104: internal circuit
105,201: power input
C101, C201: capacitor
VSRC: outer power voltage
VREF: reference voltage
VDIV: power supply dividing potential drop
VKEEP: internal power source voltage
202: mac function
203: static RAM
204: microprocessor
205: power sense circuit
2051: discharge cell
2052: the data interlock circuit
2053: on-off circuit
SRC_DET: power detection signal
SRC_LOSS: the low signal of power supply
VSS: connect altogether voltage
301,401:P type metal oxide semiconductor field effect transistor
302: the logical OR lock
303,305,404,406:N type metal oxide semiconductor field effect transistor
304,403,405: phase inverter
402: the logic not b gate
S501～S510: the step of the embodiment of the invention
Embodiment
Fig. 2 is the circuit system calcspar of the mancarried device of first embodiment of the invention.Please refer to Fig. 2, this mancarried device comprises the power sense circuit 205 of power input 201, mac function 202, static RAM 203, microprocessor 204 and the embodiment of the invention.Power sense circuit 205 comprises data interlock circuit 2051, discharge cell 2052 and on-off circuit 2053.For embodiments of the invention can spirit according to the present invention be implemented for those skilled in the art of the present technique, in this Fig. 2, also additionally illustrated capacitor C201, power detection signal SRC_DET, the low signal SRC_LOSS of power supply, cell voltage VSRC, internal power source voltage VKEEP and met altogether voltage VSS.Above-mentioned mac function 202, static RAM 203 and microprocessor 204 all are as power supply with internal power source voltage VKEEP.
When normal operation, the low signal SRC_LOSS of power detection signal SRC_DET and power supply signal is all disabled state, and on-off circuit 2053 is short-circuit condition, and therefore, internal power source voltage VKEEP current potential can keep identical with cell voltage VSRC.When beginning to test, microprocessor 204 can send power detection signal SRC_DET.At this moment, on-off circuit 2053 can be controlled by power detection signal SRC_DET and open circuit, and discharge cell 2051 also can be controlled and short circuit by power detection signal SRC_DET.When if battery is connected on power input 201, discharge cell 2051 can't pull down to cell voltage VSRC and meet altogether voltage VSS, and data interlock circuit 2052 will not have any action.As power detection signal SRC_DET again during anergy, then on-off circuit 2053 is replied and is short-circuit condition, and discharge cell 2051 is replied and is off state, and therefore, it is identical with cell voltage VSRC that the current potential of internal power source voltage VKEEP will keep.
If battery is not connected on power input 201, when beginning to test, microprocessor 20 can send power detection signal SRC_DET, after cell voltage VSRC can be pulled to and meet altogether voltage VSS, data interlock circuit 2052 can fasten the VSRC=VSS state, and enables the low signal SRC_LOSS of power supply.In addition, on-off circuit 2053 can be opened circuit by power detection signal SRC_DET and the low signal SRC_LOSS control of power supply.Meeting all stopped the mac function 202 of all power consumptions in the mancarried device with running at once after microprocessor 204 was received the low signal SRC_LOSS of the power supply that enables, and made mancarried device enter halted state.This moment, internal power source voltage VKEEP only was supplied to microprocessor 204 and static RAM 203, capacitor C201 can keep the VKEEP current potential for a long time, make cell voltage VSRC not the time, the working storage of microprocessor 204 and static RAM 203 stored data can maintain.When battery takes back again, then cell voltage VSRC current potential can rise, data interlock circuit 2052 meeting change states are to remove the low signal SRC_LOSS of power supply, and microprocessor 204 receives that the low signal SRC_LOSS of the power supply of anergy just can make mancarried device get back to normal operation.
As can be seen from the above-described embodiment, employed element is all DLC (digital logic circuit) in power sense circuit 205.Because the characteristic of DLC (digital logic circuit) is ideally, be not have static power consumption, only have dynamic power consumption.Therefore, after above-mentioned data interlock circuit 2052 locks state, just can extra power consumption not arranged.In other words, when cell voltage disappeared, except power sense circuit 205 had minimum leakage current, other did not have any power consumption.Therefore exist the data of static RAM 203 can be by permanent preservation.Review prior art, comparer 101, resistance R 101, R102 and generating circuit from reference voltage 103 all can have static power consumption, cause the user usually to have the situation that has little time to change battery.Above-described embodiment just in time can improve this defective.
In order to allow those skilled in the art of the present technique can implement the present invention, below with more detailed circuit spirit of the present invention is described.
Fig. 3 is the circuit system calcspar of the mancarried device of second embodiment of the invention.Please refer to Fig. 3, in this embodiment, on-off circuit 2053 is to implement with a P-type mos (MOS) field effect transistor 301 and logical OR lock 302.Data interlock circuit 2052 is to implement with N-type MOS transistor 303 and phase inverter 304.Discharge cell 2051 is to implement with N-type MOS transistor 305.
Same reason, SRC_DET enables when power detection signal, and when namely power detection signal SRC_DET transferred sieve and high voltage to by logic low-voltage, logical OR lock 302 received logic high voltage, and its output terminal also can the output logic high voltage.The grid of P type MOS transistor 301 receives logic high voltage, and its operation can enter cut-off region.At the same time, N-type MOS transistor 305 can be switched on.If this moment, battery was removed just, cell voltage VSRC will pulled down to and meet altogether voltage VSS (in general, connecing altogether voltage is ground voltage).When will pulleding down to, cell voltage VSRC meets altogether voltage VSS, the output terminal meeting output logic high voltage of phase inverter 304, and in other words, the low signal SRC_LOSS of power supply can be converted to logic high voltage by logic low-voltage.The grid of N-type MOS transistor 303 receives logic high voltage, can continue conducting and make VSRC be locked in ground voltage VSS.Simultaneously, logical OR lock 302 receives the logic high voltage of the low signal SRC_LOSS of power supply, and its output terminal will the output logic high voltage, and P type MOS transistor 301 just can continue to maintain cut-off region.Microprocessor 204 is received behind the logic high voltage of the low signal SRC_LOSS of power supply and can be at once the running of the mac function 202 of all power consumptions in the mancarried device all to be stopped, making mancarried device enter halted state.This moment, internal power source voltage VKEEP only was supplied to microprocessor 204 and static RAM 203, capacitor C201 can keep the VKEEP current potential for a long time, make cell voltage VSRC not the time, the working storage of microprocessor 204 and static RAM 203 stored data can maintain.
Fig. 4 is the circuit system calcspar of the mancarried device of third embodiment of the invention.Please refer to Fig. 4, in this embodiment, on-off circuit 2053 is to implement with P type MOS transistor 401, logic not b gate 402 and phase inverter 403.Data interlock circuit 2052 is to implement with N-type MOS transistor 404 and phase inverter 405.Discharge cell 2052 is to implement with N-type MOS transistor 406.
The operation of the circuit of similar Fig. 3, same, SRC_DET enables when power detection signal, when namely power detection signal SRC_DET transfers sieve and high voltage to by logic low-voltage, phase inverter 403 receives logic high voltage, meeting output logic low-voltage, logic not b gate 402 receives logic low-voltage, and its output terminal can output logic high voltage.The grid of P type MOS transistor 401 receives logic high voltage, and its operation can enter cut-off region.At the same time, N-type MOS transistor 406 can be switched on.If this moment, battery was removed just, cell voltage VSRC will pulled down to and meet altogether voltage VSS (in general, connecing altogether voltage is ground voltage).When will pulleding down to, cell voltage VSRC meets altogether voltage VSS, the output terminal meeting output logic high voltage of phase inverter 405, and in other words, the low signal SRC_LOSS of power supply can be converted to logic high voltage by logic low-voltage.The grid of N-type MOS transistor 404 receives logic high voltage, can continue conducting and make VSRC be locked in ground voltage VSS.
More different from the embodiment of Fig. 3 is that another input end of logic not b gate 402 is couple to the input end of phase inverter 405.When logic not b gate 402 received the logic low-voltage of input end of phase inverter 405, its output terminal will the output logic high voltage, and P type MOS transistor 401 just can continue to maintain cut-off region.Microprocessor 204 is received behind the logic high voltage of the low signal SRC_LOSS of power supply and can be at once the running of the mac function 202 of all power consumptions in the mancarried device all to be stopped, making mancarried device enter halted state.This moment, internal power source voltage VKEEP only was supplied to microprocessor 204 and random access memory 203, capacitor C201 can keep the VKEEP current potential for a long time, make cell voltage VSRC not the time, the working storage of microprocessor 204 and static RAM 203 stored data can maintain.
Can be known by above-mentioned two embodiment, data interlock circuit 2052, discharge cell 2051 and on-off circuit 2053 in fact are can be along with the difference of logical design, and change to some extent.For example say, if power detection signal SRC_DET is logic high voltage at ordinary times, logic low-voltage during detection, then discharge cell 2051 can be designed to a N-type MOS transistor and phase inverter, wherein the input end of phase inverter receives power detection signal SRC_DET, the output terminal of phase inverter couples the grid of N-type MOS transistor, and the phase inverter 403 of the on-off circuit 2053 of Fig. 4 then can remove.Therefore, above-mentioned logical design does not use to limit spirit of the present invention.
In addition, by above-mentioned several embodiment, can be generalized into a method that prevents Missing data.Fig. 5 is the process flow diagram of the method that prevents Missing data of the embodiment of the invention.Please refer to Fig. 5, the step of the method is as follows:
Step S501: beginning.
Step S502: between power input and power supply relay, on-off circuit is set, wherein, power input couples this static RAM, this microprocessor and this mac function by the power supply relay, to provide power supply to this static RAM, microprocessor and mac function.
Step S503: capacitor is set in the power supply relay.
Step S504: the data interlock circuit is set at power input.
Above-mentioned several step in the embodiment significantly instruction of above-mentioned Fig. 2 to Fig. 4, does not repeat them here.
Step S505: begin test.
Step S506: cutoff switch circuit.
Step S507: attempt the supply voltage of power input is discharged and recharged to connecing altogether voltage.
Step S508: judge whether the low signal SRC_LOSS of power supply that the data interlock circuit is exported changes.In general, the low signal SRC_LOSS of the power supply that this data interlock circuit is exported, meeting is along with the state of the supply voltage of power input changes.When the supply voltage of power input discharges and recharges to connecing altogether voltage, the low signal SRC_LOSS of the power supply of data interlock circuit will for example be changed to logic low-voltage by logic high voltage, or change into logic high voltage by logic low-voltage originally, this is for the selection of design, therefore do not repeat them here.When being judged as when being, enter step S509.No when being judged as, enter step S511 and again detect.
Step S509: when the low signal of the power supply of this data interlock circuit is changed, then continue the cutoff switch circuit.
Step S510: by microprocessor, the closing function block.
Step S511: wait for a schedule time, enter step S505.
In sum, spirit of the present invention is to be to carry out voltage detecting with the outer power voltage that combinational logic circuit cleverly comes battery is inputted, because general logical circuit does not have static power consumption in theory, therefore can see, be removed in battery, during again replying electric power, the not power consumption of whole power sense circuit.Therefore we can come with electric capacity the stored data of long-time holding register (Register) or static RAM (SRAM).
The specific embodiment that proposes in the detailed description of preferred embodiment is only in order to convenient explanation technology contents of the present invention, but not with narrow sense of the present invention be limited to above-described embodiment, in the situation that does not exceed spirit of the present invention and claim, the many variations of doing is implemented, and all belongs to scope of the present invention.Therefore protection scope of the present invention is worked as with being as the criterion that claim was defined.
Claims (10)
1. a power sense circuit is applicable to mancarried device, and described mancarried device comprises power input, it is characterized in that, described power sense circuit comprises:
The data interlock circuit couples described power input, the voltage of inputting in order to receive described power input;
Discharge cell, comprise first end, the second end and control end, the first end of described discharge cell couples described power input, the second end of described discharge cell couples and connects altogether voltage, the control end of described discharge cell receives power detection signal, wherein, when described power detection signal enables, the second terminal shortcircuit of the first end of described discharge cell and described discharge cell; And
On-off circuit, comprise first end, the second end, the first control end and the second control end, the first end of described on-off circuit couples described power input, the first control end of described on-off circuit couples described data interlock circuit, the second control end of described on-off circuit receives described power detection signal
Wherein, at a test period, described power detection signal enables, the second end open circuit of the first end of described on-off circuit and described on-off circuit, if in test period, the low signal of power supply that the received described data interlock circuit of the first control end of described on-off circuit is exported transfers the second state to by the first state, then keeps the first end of described on-off circuit and the second end open circuit of described on-off circuit
Wherein, the employed assembly of described power sense circuit is all DLC (digital logic circuit).
2. power sense circuit as claimed in claim 1 is characterized in that, described data interlock circuit comprises:
The first phase inverter comprises input end and output terminal, and wherein, the input end of described the first phase inverter couples described power input; And
The first N-type transistor, comprise grid, the first source-drain electrode and the second source-drain electrode, wherein, the transistorized grid of described the first N-type couples the output terminal of described the first phase inverter, transistorized the first source-drain electrode of described the first N-type couples described power input, and transistorized the second source-drain electrode of described the first N-type couples the described voltage that connects altogether.
3. power sense circuit as claimed in claim 2 is characterized in that, described on-off circuit comprises:
The P transistor npn npn comprises grid, the first source-drain electrode and the second source-drain electrode, and wherein, the first source-drain electrode of described P transistor npn npn couples described power input, and the second source-drain electrode of described P transistor npn npn is the second end of described on-off circuit; And
The logical OR lock, comprise first input end, the second input end and output terminal, wherein, the output terminal of described logical OR lock couples the grid of described P transistor npn npn, the first input end of described logical OR lock couples the output terminal of described the first phase inverter, and the second input end of described logical OR lock receives described power detection signal.
4. power sense circuit as claimed in claim 2 is characterized in that, described on-off circuit comprises:
The second phase inverter comprises input end and output terminal, and wherein, the input end of described the second phase inverter receives described power detection signal;
The P transistor npn npn comprises grid, the first source-drain electrode and the second source-drain electrode, and the first source-drain electrode of described P transistor npn npn couples described power input, and the second source-drain electrode of described P transistor npn npn is the second end of described on-off circuit; And
The logic not b gate, comprise first input end, the second input end and output terminal, wherein, the output terminal of described logic not b gate couples the grid of described P transistor npn npn, the first input end of described logic not b gate couples the input end of described the first phase inverter, and the second input end of described logic not b gate couples the output terminal of described the second phase inverter.
5. power sense circuit as claimed in claim 1 is characterized in that, described discharge cell comprises:
The second N-type transistor, comprise grid, the first source-drain electrode and the second source-drain electrode, wherein, the transistorized grid of described the second N-type receives described power detection signal, transistorized the first source-drain electrode of described the second N-type couples described power input, and transistorized the second source-drain electrode of described the second N-type couples the described voltage that connects altogether.
6. a mancarried device is characterized in that, described mancarried device comprises:
Power input;
Mac function;
Random access memory;
Microprocessor couples described random access memory, described mac function, in order to control the running of described mac function and described random access memory; And
Power sense circuit comprises:
The data interlock circuit couples described power input, the voltage of inputting in order to receive described power input;
Discharge cell, comprise first end, the second end and control end, the first end of described discharge cell couples described power input, the second end of described discharge cell couples and connects altogether voltage, the control end of described discharge cell receives power detection signal, wherein, when described power detection signal enables, the second terminal shortcircuit of the first end of described discharge cell and described discharge cell; And
On-off circuit, comprise first end, the second end, the first control end and the second control end, the first end of described on-off circuit couples described power input, the first control end of described on-off circuit couples described data interlock circuit, the second control end of described on-off circuit receives described power detection signal, the second end of described on-off circuit couples described random access memory, described mac function and described microprocessor
Wherein, at a test period, described power detection signal enables, the second terminal shortcircuit of the first end of described discharge cell and described discharge cell, and the second end of the first end of described on-off circuit and described on-off circuit opens circuit, if in test period, the low signal of power supply that the received described data interlock circuit of the first control end of described on-off circuit is exported transfers the second state to by the first state, then keeping the first end of described on-off circuit and the second end of described on-off circuit opens circuit, and microprocessor stops the running of described mac function to avoid the stored data of described random access memory to run off
Wherein, the employed assembly of described power sense circuit is all DLC (digital logic circuit).
7. mancarried device as claimed in claim 6 is characterized in that, described data interlock circuit comprises:
The first phase inverter comprises input end and output terminal, and wherein, the input end of described the first phase inverter couples described power input; And
The first N-type transistor, comprise grid, the first source-drain electrode and the second source-drain electrode, wherein, the transistorized grid of described the first N-type couples the output terminal of described the first phase inverter, transistorized the first source-drain electrode of described the first N-type couples described power input, and transistorized the second source-drain electrode of described the first N-type couples the described voltage that connects altogether.
8. mancarried device as claimed in claim 7 is characterized in that, described on-off circuit comprises:
The P transistor npn npn comprises grid, the first source-drain electrode and the second source-drain electrode, and wherein, the first source-drain electrode of described P transistor npn npn couples described power input, and the second source-drain electrode of described P transistor npn npn is the second end of described on-off circuit; And
The logical OR lock, comprise first input end, the second input end and output terminal, the output terminal of described logical OR lock couples the grid of described P transistor npn npn, the first input end of described logical OR lock couples the output terminal of described the first phase inverter, and the second input end of described logical OR lock receives described power detection signal.
9. mancarried device as claimed in claim 7 is characterized in that, described on-off circuit comprises:
The second phase inverter comprises input end and output terminal, and wherein, the input end of described the second phase inverter receives described power detection signal;
The P transistor npn npn comprises grid, the first source-drain electrode and the second source-drain electrode, and the first source-drain electrode of described P transistor npn npn couples described power input, and the second source-drain electrode of described P transistor npn npn is the second end of described on-off circuit; And
The logic not b gate, comprise first input end, the second input end and output terminal, wherein, the output terminal of described logic not b gate couples the grid of described P transistor npn npn, the first input end of described logic not b gate couples the input end of described the first phase inverter, and the second input end of described logic not b gate couples the output terminal of described the second phase inverter.
10. mancarried device as claimed in claim 6 is characterized in that, described discharge cell comprises:
The second N-type transistor, comprise grid, the first source-drain electrode and the second source-drain electrode, wherein, the transistorized grid of described the second N-type receives described power detection signal, transistorized the first source-drain electrode of described the second N-type couples described power input, and transistorized the second source-drain electrode of described the second N-type couples the described voltage that connects altogether.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910145958 CN101923145B (en) | 2009-06-15 | 2009-06-15 | Power detection circuit, portable device and method for preventing data loss |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910145958 CN101923145B (en) | 2009-06-15 | 2009-06-15 | Power detection circuit, portable device and method for preventing data loss |
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| Publication Number | Publication Date |
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| CN101923145A CN101923145A (en) | 2010-12-22 |
| CN101923145B true CN101923145B (en) | 2013-01-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200910145958 Expired - Fee Related CN101923145B (en) | 2009-06-15 | 2009-06-15 | Power detection circuit, portable device and method for preventing data loss |
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| Country | Link |
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| CN (1) | CN101923145B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818781A (en) * | 1995-11-13 | 1998-10-06 | Lexar | Automatic voltage detection in multiple voltage applications |
| CN2432731Y (en) * | 2000-05-30 | 2001-05-30 | 麦肯积体电路股份有限公司 | Power supply voltage detecting circuit |
| CN1825732A (en) * | 2005-02-25 | 2006-08-30 | 冲电气工业株式会社 | Power supply switch circuit, microcomputer, terminal device and switch controlling method |
| CN1996025A (en) * | 2006-09-01 | 2007-07-11 | 威盛电子股份有限公司 | Power supply level detector |
-
2009
- 2009-06-15 CN CN 200910145958 patent/CN101923145B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818781A (en) * | 1995-11-13 | 1998-10-06 | Lexar | Automatic voltage detection in multiple voltage applications |
| CN2432731Y (en) * | 2000-05-30 | 2001-05-30 | 麦肯积体电路股份有限公司 | Power supply voltage detecting circuit |
| CN1825732A (en) * | 2005-02-25 | 2006-08-30 | 冲电气工业株式会社 | Power supply switch circuit, microcomputer, terminal device and switch controlling method |
| CN1996025A (en) * | 2006-09-01 | 2007-07-11 | 威盛电子股份有限公司 | Power supply level detector |
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| CN101923145A (en) | 2010-12-22 |
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