CN101887357B - 指令集架构中的变量寄存器和立即数字段编码 - Google Patents
指令集架构中的变量寄存器和立即数字段编码 Download PDFInfo
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- CN101887357B CN101887357B CN201010178234.7A CN201010178234A CN101887357B CN 101887357 B CN101887357 B CN 101887357B CN 201010178234 A CN201010178234 A CN 201010178234A CN 101887357 B CN101887357 B CN 101887357B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30156—Special purpose encoding of instructions, e.g. Gray coding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30178—Runtime instruction translation, e.g. macros of compressed or encrypted instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
Abstract
Description
Claims (37)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US12/464,027 | 2009-05-11 | ||
US12/464,027 US9274796B2 (en) | 2009-05-11 | 2009-05-11 | Variable register and immediate field encoding in an instruction set architecture |
Publications (2)
Publication Number | Publication Date |
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CN101887357A CN101887357A (zh) | 2010-11-17 |
CN101887357B true CN101887357B (zh) | 2015-09-09 |
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Application Number | Title | Priority Date | Filing Date |
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CN201010178234.7A Active CN101887357B (zh) | 2009-05-11 | 2010-05-11 | 指令集架构中的变量寄存器和立即数字段编码 |
Country Status (2)
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US (3) | US9274796B2 (zh) |
CN (1) | CN101887357B (zh) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9274796B2 (en) | 2009-05-11 | 2016-03-01 | Arm Finance Overseas Limited | Variable register and immediate field encoding in an instruction set architecture |
US8966253B1 (en) | 2010-06-01 | 2015-02-24 | Xilinx, Inc. | Method and apparatus for authenticating a programmable device bitstream |
US8799453B2 (en) | 2010-10-20 | 2014-08-05 | Microsoft Corporation | Managing networks and machines for an online service |
US8751656B2 (en) | 2010-10-20 | 2014-06-10 | Microsoft Corporation | Machine manager for deploying and managing machines |
US8296267B2 (en) | 2010-10-20 | 2012-10-23 | Microsoft Corporation | Upgrade of highly available farm server groups |
US8386501B2 (en) * | 2010-10-20 | 2013-02-26 | Microsoft Corporation | Dynamically splitting multi-tenant databases |
US9075661B2 (en) | 2010-10-20 | 2015-07-07 | Microsoft Technology Licensing, Llc | Placing objects on hosts using hard and soft constraints |
US8417737B2 (en) | 2010-10-20 | 2013-04-09 | Microsoft Corporation | Online database availability during upgrade |
US8850550B2 (en) | 2010-11-23 | 2014-09-30 | Microsoft Corporation | Using cached security tokens in an online service |
US9721030B2 (en) | 2010-12-09 | 2017-08-01 | Microsoft Technology Licensing, Llc | Codeless sharing of spreadsheet objects |
US8909941B1 (en) * | 2011-03-31 | 2014-12-09 | Xilinx, Inc. | Programmable integrated circuit and a method of enabling the detection of tampering with data provided to a programmable integrated circuit |
US9128701B2 (en) | 2011-04-07 | 2015-09-08 | Via Technologies, Inc. | Generating constant for microinstructions from modified immediate field during instruction translation |
US9244686B2 (en) | 2011-04-07 | 2016-01-26 | Via Technologies, Inc. | Microprocessor that translates conditional load/store instructions into variable number of microinstructions |
US8880857B2 (en) | 2011-04-07 | 2014-11-04 | Via Technologies, Inc. | Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor |
US9317288B2 (en) | 2011-04-07 | 2016-04-19 | Via Technologies, Inc. | Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline |
US8924695B2 (en) | 2011-04-07 | 2014-12-30 | Via Technologies, Inc. | Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor |
US9141389B2 (en) | 2011-04-07 | 2015-09-22 | Via Technologies, Inc. | Heterogeneous ISA microprocessor with shared hardware ISA registers |
US9898291B2 (en) | 2011-04-07 | 2018-02-20 | Via Technologies, Inc. | Microprocessor with arm and X86 instruction length decoders |
US9378019B2 (en) | 2011-04-07 | 2016-06-28 | Via Technologies, Inc. | Conditional load instructions in an out-of-order execution microprocessor |
US9336180B2 (en) | 2011-04-07 | 2016-05-10 | Via Technologies, Inc. | Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode |
US8880851B2 (en) | 2011-04-07 | 2014-11-04 | Via Technologies, Inc. | Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline |
US9043580B2 (en) | 2011-04-07 | 2015-05-26 | Via Technologies, Inc. | Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA) |
US9032189B2 (en) | 2011-04-07 | 2015-05-12 | Via Technologies, Inc. | Efficient conditional ALU instruction in read-port limited register file microprocessor |
US9274795B2 (en) | 2011-04-07 | 2016-03-01 | Via Technologies, Inc. | Conditional non-branch instruction prediction |
US9176733B2 (en) | 2011-04-07 | 2015-11-03 | Via Technologies, Inc. | Load multiple and store multiple instructions in a microprocessor that emulates banked registers |
US9645822B2 (en) | 2011-04-07 | 2017-05-09 | Via Technologies, Inc | Conditional store instructions in an out-of-order execution microprocessor |
US9292470B2 (en) | 2011-04-07 | 2016-03-22 | Via Technologies, Inc. | Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program |
US9146742B2 (en) | 2011-04-07 | 2015-09-29 | Via Technologies, Inc. | Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA |
CN102231180B (zh) * | 2011-07-30 | 2014-05-28 | 张鹏 | 处理器指令编码可重定义的方法 |
US9436474B2 (en) * | 2012-07-27 | 2016-09-06 | Microsoft Technology Licensing, Llc | Lock free streaming of executable code data |
US9811335B1 (en) * | 2013-10-14 | 2017-11-07 | Quicklogic Corporation | Assigning operational codes to lists of values of control signals selected from a processor design based on end-user software |
US10620957B2 (en) * | 2015-10-22 | 2020-04-14 | Texas Instruments Incorporated | Method for forming constant extensions in the same execute packet in a VLIW processor |
US10346162B2 (en) | 2015-11-17 | 2019-07-09 | International Business Machines Corporation | Selective instruction replacement for assembly language programs |
US10437883B2 (en) * | 2015-11-24 | 2019-10-08 | Cisco Technology, Inc. | Efficient graph database traversal |
CN107463355B (zh) * | 2017-07-28 | 2020-03-31 | 珠海市杰理科技股份有限公司 | 立即数压缩编码方法和系统 |
US10846089B2 (en) * | 2017-08-31 | 2020-11-24 | MIPS Tech, LLC | Unified logic for aliased processor instructions |
CN110045960B (zh) * | 2018-01-16 | 2022-02-18 | 腾讯科技(深圳)有限公司 | 基于芯片的指令集处理方法、装置及存储介质 |
US10970228B2 (en) * | 2018-12-14 | 2021-04-06 | Micron Technology, Inc. | Mapping table compression using a run length encoding algorithm |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5740461A (en) * | 1994-05-03 | 1998-04-14 | Advanced Risc Machines Limited | Data processing with multiple instruction sets |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5636352A (en) | 1994-12-16 | 1997-06-03 | International Business Machines Corporation | Method and apparatus for utilizing condensed instructions |
US6496920B1 (en) * | 1998-03-18 | 2002-12-17 | Qiuzhen Zou | Digital signal processor having multiple access registers |
US7051189B2 (en) | 2000-03-15 | 2006-05-23 | Arc International | Method and apparatus for processor code optimization using code compression |
US7162621B2 (en) | 2001-02-21 | 2007-01-09 | Mips Technologies, Inc. | Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration |
US6826681B2 (en) | 2001-06-18 | 2004-11-30 | Mips Technologies, Inc. | Instruction specified register value saving in allocated caller stack or not yet allocated callee stack |
WO2003065165A2 (en) * | 2002-01-31 | 2003-08-07 | Arc International | Configurable data processor with multi-length instruction set architecture |
US20050091474A1 (en) * | 2003-10-24 | 2005-04-28 | Microchip Technology Incorporated | Fuse configurable alternate behavior of a central processing unit |
JP2008083873A (ja) * | 2006-09-26 | 2008-04-10 | Yamaha Corp | デジタル信号処理装置 |
US7836285B2 (en) | 2007-08-08 | 2010-11-16 | Analog Devices, Inc. | Implementation of variable length instruction encoding using alias addressing |
US9274796B2 (en) | 2009-05-11 | 2016-03-01 | Arm Finance Overseas Limited | Variable register and immediate field encoding in an instruction set architecture |
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2009
- 2009-05-11 US US12/464,027 patent/US9274796B2/en active Active
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2010
- 2010-05-11 CN CN201010178234.7A patent/CN101887357B/zh active Active
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2016
- 2016-02-01 US US15/012,084 patent/US9928065B2/en active Active
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2018
- 2018-02-19 US US15/898,752 patent/US10776114B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5740461A (en) * | 1994-05-03 | 1998-04-14 | Advanced Risc Machines Limited | Data processing with multiple instruction sets |
Also Published As
Publication number | Publication date |
---|---|
US20100287359A1 (en) | 2010-11-11 |
US20180173531A1 (en) | 2018-06-21 |
CN101887357A (zh) | 2010-11-17 |
US20160147535A1 (en) | 2016-05-26 |
US9928065B2 (en) | 2018-03-27 |
US9274796B2 (en) | 2016-03-01 |
US10776114B2 (en) | 2020-09-15 |
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