CN101874296A - 利用成对凸柱进行倒装芯片互连 - Google Patents

利用成对凸柱进行倒装芯片互连 Download PDF

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Publication number
CN101874296A
CN101874296A CN200880117714A CN200880117714A CN101874296A CN 101874296 A CN101874296 A CN 101874296A CN 200880117714 A CN200880117714 A CN 200880117714A CN 200880117714 A CN200880117714 A CN 200880117714A CN 101874296 A CN101874296 A CN 101874296A
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Prior art keywords
projection
microelectronic element
substrate
front surface
metal
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CN200880117714A
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CN101874296B (zh
Inventor
J·权
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Priority to CN201510507995.5A priority Critical patent/CN105140134A/zh
Publication of CN101874296A publication Critical patent/CN101874296A/zh
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Abstract

一种封装微电子组件，包括具有前表面(122)和远离前表面(122)延伸的多个第一固态凸柱(110)的微电子元件(104)。每个第一凸柱(110)具有在前表面(122)方向上的宽度和从前表面(122)延伸的高度，其中高度(H2)是宽度(W1)的至少一半。还存在基板(102)，基板(102)具有顶表面(101)和从顶表面(102)延伸且结合到第一固态金属凸柱(110)的多个第二固态金属凸柱(108)。

Description

利用成对凸柱进行倒装芯片互连
相关申请的交叉引用
本发明要求于2007年9月28日提交的美国临时专利申请No.60/995,849的提交日的权益，该申请的全部内容以引用的方式结合到本文中。
技术领域
本发明涉及微电子设备和封装用于微电子封装和组装的微电子部件。
背景技术
微电子装置通常包括半导体材料(例如硅或砷化镓)的薄片，常常称为裸片或半导体芯片。半导体芯片常常作为单个的预封装单元来提供。在一些单元设计中，半导体芯片被安装在基板或芯片载具上，基板或载具继而安装在诸如印刷电路板的电路面板上。
有源电路制造在半导体芯片的一个面部上。为了利于电连接到有源电路，芯片在相同的面部上配置有键合焊盘。键合焊盘通常放置成规则阵列，或者在裸片的边缘周围，或者对于许多记忆装置来说在裸片中心处。键合焊盘通常由大约0.5μm厚的导电材料制成，例如金或铝。键合焊盘的尺寸随着装置类型而不同，但是典型地在一侧上为数十个至数百个微米。
倒装芯片互连通常用于将半导体芯片上的键合焊盘导电地连接到基板上的触头焊盘上的方案中。在倒装芯片互连中，金属块通常放置在每个键合焊盘上。接着，裸片被倒置以便金属块同时提供键合焊盘与基板之间的电通路以及裸片到基板的机械附连。
存在倒装芯片工艺的许多变型，但是一种常见配置是使用用于金属块的焊料并将焊料熔合作为将金属块紧固到键合焊盘和基板上的方法。当焊料熔化时，焊料流动以形成截头球体。
虽然进行倒装芯片互连有一定的优势，但是仍存在改良的需求，以便使得封装厚度最小化同时增强接头可靠性。本发明的这些益处是通过在下文中所描述的微电子封装的结构来实现的。
发明内容
根据本发明的实施例，存在一种包括微电子元件的封装微电子元件，该微电子元件具有前表面和远离前表面延伸的多个第一固态金属凸块。每个凸柱具有在前表面方向上的宽度和从前表面延伸的高度，其中高度是宽度的至少一半。还存在基板，该基板具有顶表面和多个第二固态金属凸柱，该多个第二固态金属凸柱从顶表面延伸且用可熔合金属结合到第一固态金属凸柱。第二凸柱具有顶表面和远离基板的所述顶表面以陡峭角度延伸的边缘表面。
该实施例的凸柱可被蚀刻且主要包括铜。此外，凸块下金属化层可位于第一凸块下面。第一凸柱的直径与第一凸柱之间的间距(pitch)的比率可以不大于3∶4。此外，第一凸柱的直径可小于每个第一凸柱之间的间距的一半。
在一个实施例中，封装微电子元件包括微电子元件，该微电子元件具有前表面和多个第一固态金属凸柱，该多个第一固态金属凸柱远离前表面延伸。每个凸柱具有在前表面方向上的宽度和从前表面延伸的高度，其中高度是宽度的至少一半。还存在基板，该基板具有顶表面和多个第二固态金属凸柱，该多个第二固态金属凸柱从顶表面延伸且结合到第一固态金属凸柱。在该实施例中，第一和第二凸柱扩散连接在一起。
第一凸柱的直径与第一凸柱间的间距的比率可不大于3∶4。微电子元件的前表面与基板的顶表面之间的距离可大于80微米。此外，每个第一凸柱的直径等于每个第二金属凸柱的直径。最后，底部填充材料可沉积在微电子元件的前表面与基板的顶表面之间。
在又另其它实施例中，封装微电子元件包括微电子元件，该微电子元件具有前表面和远离前表面延伸的多个第一固态金属凸柱。每个凸柱具有在前表面方向上的宽度和从前表面延伸的高度。凸柱主要包括除了焊料、铅或锡之外的金属。还存在基板，该基板具有顶表面。多个第二固态金属凸柱从顶表面延伸且用可熔合金属结合到第一固态金属凸柱。第一或第二固态金属凸柱的直径与多个第一或第二固态金属凸柱之间的间距的比率不大于3∶4。
在该实施例的备选方式中，基板可以是多层基板。此外，第一凸柱的直径可以小于每个第一凸柱之间的间距的一半。此外，每个所述第一凸柱的直径等于第二金属凸柱的直径。
在另一实施例中，封装微电子元件包括微电子元件，该微电子元件具有前表面和远离前表面延伸的多个第一固态金属凸柱。每个凸柱具有在前表面方向上的宽度和从前表面延伸的高度。存在基板，该基板具有顶表面。多个第二固态金属凸柱从顶表面延伸且结合到第一固态金属凸柱。第一凸柱的间距在50至200微米的范围内变化，且微电子元件的底表面与基板的顶表面之间的距离大于80微米。
在该实施例的备选方式中，可熔合金属可用来将第二凸柱结合到第一凸柱。每个第一凸柱的直径等于第二金属凸柱的直径。此外，第一凸柱的直径可小于每个第一凸柱之间的间距的一半。
在另一实施例中，封装微电子元件包括微电子元件、基板和多个支柱，该支柱在微电子元件与基板之间延伸。多个支柱的每个包括附连到微电子元件的第一金属凸柱部分、附连到基板的第二金属凸柱部分以及金属熔合部分，其中第一和第二金属部分结合在一起。多个支柱的长度不小于50微米。第一和第二金属凸柱部分的高度是宽度的至少一半。
在该实施例的备选方式中，微电子元件的前表面与基板的顶表面之间的距离大于80微米。基板还可是多层基板。
每个第一凸柱的直径可等于第二金属凸柱的直径。第一凸柱的直径可小于每个第一凸柱之间的间距的一半。此外，第一和第二凸柱可被蚀刻。
一种制造封装微电子元件组件的方法，包括提供微电子元件，该微电子元件具有多个导电凸柱，该导电凸柱远离微电子元件的第一表面延伸。凸柱具有顶表面和远离顶表面以陡峭角度延伸的边缘表面。可熔合的金属帽部附连到多个导电凸柱中每个的末端。接下来的步骤包括将微电子元件的凸柱与从基板第一表面延伸的多个凸柱至少大致对齐。最后的步骤包括将微电子元件的凸柱与基板的凸柱结合。
在备选的方法中，步骤(c)包括将可熔合金属加热到熔点，其中可熔合金属流动到凸柱边缘表面的暴露部分上。
在另一备选的方法中，钝化层和凸块下金属化层沉积在微电子元件上。
下述段落描述本文的各种实施例：
1.一种封装微电子元件，包括：
微电子元件，该微电子元件具有前表面和远离前表面延伸的多个第一焊料金属凸块，每个凸柱具有在前表面方向上的宽度和从前表面延伸的高度，其中高度是所述宽度的至少一半；和
基板，所述基板具有顶表面和多个第二固态金属凸柱，该多个第二固态金属凸柱从顶表面延伸且用可熔合金属结合到第一固态金属凸柱，所述凸柱具有顶表面和远离所述顶表面以陡峭角度延伸的边缘表面。
2.根据段落1的封装微电子元件，其中所述第一凸块或第二凸柱包括铜。
3.根据段落1的封装微电子元件，其中所述可熔合金属选自主要包括焊料、锡或共熔材料的组。
4.根据段落1的封装微电子元件，其中所述第一凸块之间的间距在从50至200微米的范围内变化。
5.根据段落1的封装微电子元件，其中所述第一凸块的直径与所述第一凸柱之间的间距的比率不大于3∶4。
6.根据段落1的封装微电子元件，其中所述微电子元件的前表面与所述基板的所述顶表面之间的距离大于80微米。
7.根据段落1的封装微电子元件，还包括在所述第一凸块下面的凸块下金属化层。
8.根据段落1的封装微电子元件，其中所述基板是多层基板。
9.根据段落1的封装微电子元件，其中所述第一凸块中的每个的直径等于所述第二凸柱的直径。
10.根据段落1的封装微电子元件，其中所述第一凸块的直径小于所述每个第一凸柱之间的间距的一半。
11.根据段落1的封装微电子元件，还包括在所述微电子元件的所述前表面与所述基板的所述顶表面之间的底部填充材料。
12.根据段落1的封装微电子元件，还包括位于所述微电子元件的所述前表面上面的焊料掩膜层。
13.根据段落1的封装微电子元件，其中所述第一或第二凸柱被蚀刻。
14.根据段落1的封装微电子元件，其中所述第一或第二凸柱被电镀。
15.根据段落1的封装微电子元件，其中所述前表面是有源表面。
16.根据段落1的封装微电子元件，其中迹线沿着所述微电子元件的所述前表面延伸。
17.根据段落1的封装微电子元件，其中所述基板还包括第二表面，且其中过渡件延伸经过所述基板，以便在所述第二凸柱与暴露在所述基板的所述底表面处的电路之间提供连接。
18.一种封装微电子元件，包括：
微电子元件，该微电子元件包括前表面和远离前表面延伸的多个第一固态金属凸柱，每个凸柱具有在前表面方向上的宽度和从前表面延伸的高度，其中高度是所述宽度的至少一半；和
基板，所述基板具有顶表面和多个第二固态金属凸柱，所述多个第二固态金属凸柱从顶表面延伸且结合到第一固态金属凸柱，其中所述第一和第二凸柱扩散连接(diffusion-bonded)到一起。
19.根据段落18的封装微电子元件，其中所述第一或第二凸柱包括铜。
20.根据段落18的封装微电子元件，其中所述第一凸柱之间的间距在从50至200微米的范围内变化。
21.根据段落18的封装微电子元件，其中所述第一凸柱的直径与所述第一凸柱之间的间距的比率不大于3∶4。
22.根据段落18的封装微电子元件，其中所述微电子元件的所述前表面与所述基板的所述顶表面之间的距离大于80微米。
23.根据段落18的封装微电子元件，还包括位于所述第一凸柱下面的凸块下金属化层。
24.根据段落18的封装微电子元件，其中所述基板是多层基板。
25.根据段落18的封装微电子元件，其中所述第一凸柱的每个的直径等于所述第二金属凸柱的每个的直径。
26.根据段落18的封装微电子元件，其中所述第一凸柱的直径小于每个所述第一凸柱之间的间距的一半。
27.根据段落18的封装微电子元件，还包括在所述微电子元件的所述前表面与所述基板的所述顶表面之间的底部填充材料。
28.根据段落18的封装微电子元件，还包括在所述微电子元件的所述前表面上面的焊料掩膜层。
29.根据段落18的封装微电子元件，其中所述第一或第二凸柱被蚀刻。
30.根据段落18的封装微电子元件，其中所述第一或第二凸柱被电镀。
31.根据段落18的封装微电子元件，其中所述前表面是有源表面。
32.根据段落18的封装微电子元件，其中迹线沿着所述微电子元件的所述前表面延伸。
33.根据段落18的封装微电子元件，其中所述基板还包括第二表面，且其中过渡件延伸经过所述基板，以便在所述第二凸柱与所述基板的所述顶表面处暴露的电路之间提供连接。
34.一种封装微电子元件，包括：
微电子元件，该微电子元件包括前表面和远离前表面延伸的多个第一固态金属凸柱，每个凸柱具有前表面方向上的宽度和从前表面延伸的高度，所述凸柱主要包括除了焊料、铅或锡之外的金属；和
基板，该基板具有顶表面和多个第二固态金属凸柱，该多个第二固态金属凸柱从顶表面延伸且用可熔合金属结合到第一固态金属凸柱，
其中所述第一或第二固态金属凸柱的直径与所述多个第一或第二固态金属凸柱之间的间距的比率不大于3∶4。
35.根据段落34的封装微电子元件，其中所述第一或第二凸柱包括铜。
36.根据段落34的封装微电子元件，其中所述可熔合金属选自主要包括焊料、锡或共熔材料的组。
37.根据段落34的封装微电子元件，其中所述第一凸柱之间的间距在从50至200微米的范围内变化。
38.根据段落34的封装微电子元件，其中所述微电子元件的所述前表面与所述基板的所述顶表面之间的距离大于80微米。
39.根据段落34的封装微电子元件，还包括位于所述第一凸柱下面的凸块下金属化层。
40.根据段落34的封装微电子元件，其中所述基板是多层基板。
41.根据段落34的封装微电子元件，其中每个所述第一凸柱的直径等于所述第二金属凸柱中每个的直径。
42.根据段落34的封装微电子元件，其中所述第一凸柱的直径小于每个所述第一凸柱之间的间距的一半。
43.根据段落34的封装微电子元件，还包括在所述微电子元件的所述前表面与所述基板的所述顶表面之间的底部填充材料。
44.根据段落34的封装微电子元件，还包括在所述微电子元件的所述前表面上面的焊料掩膜层。
45.根据段落34的封装微电子元件，其中所述第一或第二凸柱被蚀刻。
46.根据段落34的封装微电子元件，其中所述第一或第二凸柱被电镀。
47.根据段落34的封装微电子元件，其中所述前表面是有源表面。
48.根据段落34的封装微电子元件，其中迹线沿着所述微电子元件的所述前表面延伸。
49.根据段落34的封装微电子元件，其中所述基板还包括第二表面，且其中过渡件延伸经过所述基板，以便在所述第二凸柱与在所述基板的所述底表面暴露的电路之间提供连接。
50.一种封装微电子元件，包括：
微电子元件，该微电子元件具有前表面和远离前表面延伸的多个第一固态金属凸柱，每个凸柱具有在前表面方向上的宽度和从前表面延伸的高度；和
基板，该基板具有顶表面和多个第二固态金属凸柱，该多个第二固态金属凸柱从顶表面延伸且结合到第一固态金属凸柱，其中，所述第一凸柱的间距在从50至200微米的范围内变化，且所述微电子元件的所述底表面与所述基板的所述顶表面之间的距离大于80微米。
51.根据段落50的封装微电子元件，其中所述第一或第二凸柱包括铜。
52.根据段落50的封装微电子元件，其中可熔合金属被用来将所述第二凸柱结合到所述第一凸柱。
53.根据段落50的封装微电子元件，其中所述可熔合金属选自主要包括焊料、锡或共熔材料的组。
54.根据段落50的封装微电子元件，其中所述第一凸柱的直径与所述第一凸柱之间的间距的比率不大于3∶4。
55.根据段落50的封装微电子元件，其中所述微电子元件的所述前表面与所述基板的所述顶表面之间的距离大于80微米。
56.根据段落50的封装微电子元件，还包括位于所述第一凸柱下面的凸块下金属化层。
57.根据段落50的封装微电子元件，其中所述基板是多层基板。
58.根据段落50的封装微电子元件，其中每个所述第一凸柱的直径等于所述第二金属凸柱的直径。
59.根据段落50的封装微电子元件，其中所述第一凸柱的直径小于每个所述第一凸柱之间的间距的一半。
60.根据段落50的封装微电子元件，还包括在所述微电子元件的所述前表面与所述基板的所述顶表面之间的底部填充材料。
61.根据段落50的封装微电子元件，还包括在所述微电子元件的所述前表面上面的焊料掩膜层。
62.根据段落50的封装微电子元件，其中所述第一或第二凸柱被蚀刻。
63.根据段落50的封装微电子元件，其中所述第一或第二凸柱被电镀。
64.根据段落50的封装微电子元件，其中所述前表面是有源表面。
65.根据段落50的封装微电子元件，其中迹线沿着所述微电子元件的所述前表面延伸。
66.根据段落50的封装微电子元件，其中所述基板还包括第二表面，且其中过渡件延伸经过所述基板，以便在所述第二凸柱与所述基板的所述底表面暴露的电路之间提供连接。
67.一种封装微电子元件，包括：
微电子元件，该微电子元件具有前表面和远离前表面延伸的多个第一固态金属凸柱，每个凸柱具有在前表面方向上的宽度和从前表面延伸的高度；和
基板，该基板具有顶表面和多个第二固态金属凸柱，该多个第二固态金属凸柱从顶表面延伸且结合到第一固态金属凸柱，
其中所述多个所述第一和第二固态金属凸柱主要包括铜。
68.根据段落67的封装微电子元件，其中可熔合金属被用来结合第一和第二凸柱。
69.根据段落68的封装微电子元件，其中可熔合金属选自主要包括焊料、锡或共熔材料的组。
70.根据段落67的封装微电子元件，其中所述第一凸柱之间的间距在从50至200微米的范围内变化。
71.根据段落67的封装微电子元件，其中所述第一凸柱的直径与所述第一凸柱之间的间距的比率不大于3∶4。
72.根据段落67的封装微电子元件，其中所述微电子元件的所述前表面与所述基板的所述顶表面之间的距离大于80微米。
73.根据段落67的封装微电子元件，还包括在所述第一凸柱下面的凸块下金属化层。
74.根据段落67的封装微电子元件，其中所述基板是多层基板。
75.根据段落67的封装微电子元件，其中每个所述第一凸柱的直径等于所述第二金属凸柱的直径。
76.根据段落67的封装微电子元件，其中所述第一凸柱的直径小于每个所述第一凸柱之间的间距的一半。
77.根据段落67的封装微电子元件，还包括在所述微电子元件的所述前表面与所述基板的所述顶表面之间的底部填充材料。
78.根据段落67的封装微电子元件，还包括在所述微电子元件的所述前表面上面的焊料掩膜层。
79.根据段落67的封装微电子元件，其中所述第一或第二凸柱被蚀刻。
80.根据段落67的封装微电子元件，其中所述第一或第二凸柱被电镀。
81.根据段落67的封装微电子元件，其中所述前表面是有源表面。
82.根据段落67的封装微电子元件，其中迹线沿着所述微电子元件的所述前表面延伸。
83.根据段落67的封装微电子元件，其中所述基板还包括第二表面，且其中过渡件延伸经过所述基板，以便在所述第二凸柱与在所述基板的所述底表面处暴露的电路之间提供连接。
84.一种封装微电子元件，包括：
微电子元件；基板；以及在所述微电子元件与所述基板之间延伸的多个支柱，每个所述多个支柱包括附连到所述微电子元件的第一金属凸柱部分、附连到所述基板的第二金属凸柱部分、以及金属熔合部分，其中所述第一和第二金属部分结合在一起，所述多个支柱的长度不小于50微米，且所述第一和第二金属凸柱部分的所述高度是所述宽度的至少一半。
85.根据段落84的封装微电子元件，其中所述第一或第二凸柱包括铜。
86.根据段落84的封装微电子元件，其中所述第一凸柱之间的间距在从50至200微米的范围内变化。
87.根据段落84的封装微电子元件，其中所述第一凸柱的直径与所述第一凸柱之间的间距的比率不大于3∶4。
88.根据段落84的封装微电子元件，其中所述微电子元件的所述前表面与所述基板的所述顶表面之间的距离大于80微米。
89.根据段落84的封装微电子元件，还包括在所述第一凸柱下面的凸块下金属化层。
90.根据段落84的封装微电子元件，其中所述基板是多层基板。
91.根据段落84的封装微电子元件，其中每个所述第一凸柱的直径等于所述第二金属凸柱的直径。
92.根据段落84的封装微电子元件，其中所述第一凸柱的直径小于每个所述第一凸柱之间的间距的一半。
93.根据段落84的封装微电子元件，还包括在所述微电子元件的所述前表面与所述基板的所述顶表面之间的底部填充材料。
94.根据段落84的封装微电子元件，还包括在所述微电子元件的所述前表面上面的焊料掩膜层。
95.根据段落84的封装微电子元件，其中所述第一或第二凸柱被蚀刻。
96.根据段落84的封装微电子元件，其中所述第一或第二凸柱被电镀。
97.根据段落84的封装微电子元件，其中所述前表面是有源表面。
98.根据段落84的封装微电子元件，其中迹线沿着所述微电子元件的所述前表面延伸。
99.根据段落84的封装微电子元件，其中所述基板还包括第二表面，且其中过渡件延伸经过所述基板，以便在所述第二凸柱与在所述基板的所述底表面暴露的电路之间提供连接。
附图说明
图1A和1B是根据一个实施例的微电子组件的部件的截面图。
图1C是描绘了结合到一起的图1A和1B的截面图。
图2是描绘了根据图1A-1C的实施例的微电子组件的截面图。
图2A是图2的一部分的分解截面图。
图3是描绘了根据图2所示实施例的变型的完成后微电子组件的截面图。
图4是描绘了根据图2所示实施例的变型的完成后微电子组件的截面图。
图5是描绘了根据另一实施例的微电子组件的部件的截面图。
图6是描绘了图5所示实施例的变型的微电子组件的部件的截面图。
图7是描绘了根据一个实施例的完成后微电子组件的截面图。
图8是描绘了根据另一实施例的完成后微电子组件的截面图。
图9是描绘了根据另一实施例的完成后微电子组件的截面图。
图10是描绘了根据一个实施例的完成后微电子组件的截面图。
图11是描绘了根据另一实施例的完成后微电子组件的截面图。
图12是描绘了根据另一实施例的完成后微电子组件的截面图。
图13是描绘了根据另一实施例的完成后微电子组件的截面图。
具体实施方式
现在参考图1A-1C，其中描绘了图2所示封装微电子组件100的部件的截面图。如图所示，封装微电子组件100包括基板102、处于向下或倒装位置的微电子元件104、以及将基板102与微电子元件结合的导电杆106。导电杆包括导电凸块或凸柱108，导电凸块或凸柱108凸起高于基板102的表面105，导电凸块或凸柱108与凸起高于微电子元件104的表面107的导电凸块或凸柱110对齐。导电杆106通过增加微电子元件104和基板102之间的直立或竖直距离来向芯片到基板上的封装提供增加的高度，且同时允许导电杆106之间的中心间的水平距离或间距P减少。如将在下文进一步详细说明的那样，在基板102与微电子元件104之间的距离增加的能力可有助于减少导电杆处的应力、可有助于容易应用底部填充(underfill)材料112(见图2A)，以及允许要使用的底部填充物的更大变化。
参考图1A，基板102优选地包括介电元件102A。介电元件102A具有顶表面101和相反朝向的底表面103。多个导电迹线109可沿着顶表面或底表面或者两者延伸。介电元件102A可以是刚性或柔性的。介电元件102可包括聚酰亚胺或其它聚合物片材。虽然介电元件102的厚度可变化，但是介电元件102A大多数情况下常常达2毫米。基板102可包括其它导电元件，例如暴露于底表面103的外触头(未示出)。键合迹线可使用在共同受让的美国公布申请No.11/014,439中所述的方法来形成，该公开以引用的方式结合到本文中。在所述的具体实施例中，导电元件(未示出)布置在基板102的顶表面101上。然而，在其它实施例中，导电元件还可沿着基板102的底表面103延伸、位于顶表面101和底表面103两者上或者在基板102的内部。因此，如本文中所使用的，关于第一特征布置在第二特征“上”的声明不应当理解为需要将第一特征放置在第二特征的表面上。此外，描述性词语，例如“顶”、“底”、“上”、“下”，仅用于描述目的。
固态金属凸块或凸柱108还从基板102的顶表面101延伸，以形成导电杆106的第一部分(图2和2A)。导电凸柱108具有顶表面111和边缘表面113，边缘表面113远离基板102的顶表面以陡峭角度延伸，使得在边缘表面113会合基板102的顶表面101处产生明显的角度。例如，在所示的实施例中，在基板102的顶表面101与导电凸柱108的边缘表面113之间形成大于90度的角度。角度将取决于导电凸柱108的形状而不同。例如，圆柱形凸柱在基板102的顶表面101与导电凸柱108之间可具有90度的角度。在于2006年12月19日提交的名为“Chip Capacitor Embedded PWB”的临时申请No.60/875,730、于2007年8月15日提交的名为“Multilayer Substrate with Interconnection Viasand Method of Manufacturing the Same”的临时申请No.60/964,916以及于2007年8月15日提交的名为“Interconnection Element with PostsFormed by Plating”的临时申请No.60/964,823中描述了示例性工艺和凸柱，上述所有文献均以引用的方式结合到本文中。例如，导电凸柱108可通过蚀刻工艺来形成，如在本文中将更详细描述的那样。备选地，导电凸柱108可通过电镀来形成，其中凸柱108通过将金属经由诸如感光层的介电层中的图形化开口镀到基金属层上而形成。
导电凸柱108的尺寸可在较大范围内变化，但最常见地从介电元件102A的顶表面103延伸的每个导电凸柱108的高度H1是至少50微米且可延伸高达300毫米。这些导电凸柱108可具有大于其直径或宽度W1的高度H1。然而，高度H1还可小于宽度W1，例如高度H1是宽度W1大小的至少一半。
导电凸柱108可由任何导电材料制成，导电材料例如铜、铜合金、金及其组合。导电凸柱108可包括焊料润湿型(wettable)的至少暴露金属层。例如，凸柱可包括铜，其中金层在凸柱的表面上。此外，导电凸柱108可包括至少一个金属层，所述金属层的熔化温度大于要结合的焊料的熔化温度。例如，这种导电凸柱108可包括铜层或者完全由铜形成。
导电凸柱108还可采用许多不同的形状，包括截头圆锥形。每个导电凸柱108的底部114和顶部116可大致成圆形或者具有不同的形状，例如椭圆形。导电凸柱108的底部114的直径通常在约50-300μm，而顶部116的直径通常在约25-200μm。每个导电凸柱108可具有邻近于介电基板102的底部114和远离介电基板的顶部116。此外，导电凸柱距介电元件102A的顶表面101的高度H1(除了任何焊料掩膜之外)通常在小至30μm和高达200μm的范围内。
如图所示，焊料掩膜118(图2)可布置在基板102上且邻近导电凸柱108。焊料掩膜118有助于在回流相期间防止焊料在邻近杆106之间回流和桥接。
参考图1B，微电子元件104具有前表面122和后表面124。微电子元件104优选地是在其封装和与另一元件互连之前的半导体芯片等等。例如，微电子元件是裸片。
一种示例性导电凸柱和制造能够从微电子元件等等延伸的导电凸柱的方法在Advanpak Solutions Pte.Ltd.(″Advanpak″)的网站、以及受让给Advanpak的美国专利No.6,681,982、No.6,592,109和No.6,578,754中进行了描述，上述专利以引用的方式结合到本文中。例如，导电凸柱110可通过蚀刻工艺来形成。备选地，导电凸柱110可通过电镀来形成，其中凸柱110通过将金属经由诸如感光层的介电层中印制的开口镀到基金属层上而形成。类似于从基板延伸的导电凸柱108，从微电子元件104延伸的凸柱110可具有顶表面111和从边缘表面113，边缘表面113从微电子元件的上述顶表面122以陡峭角度延伸开来，使得在微电子元件与导电凸柱之间形成明显的角度。
为了在导电凸柱110与微电子元件104之间提供金属触头，可在微电子元件104的前表面122上提供凸块下金属化层120。凸块下金属化层120通常由包括钛、钛-钨、铬的材料组成。凸块下金属化层120操作成导电杆106的导电金属触头。钝化层119也可使用本领域已知的方法来提供在微电子元件104的前表面122上位于微电子元件104与凸块下金属化层120之间。
参考图1B、1C和2，从微电子元件104延伸的导电凸柱110的尺寸也可在较大范围内变化，但是最常见地，每个导电凸柱110的高度H2不小于50微米。导电凸柱110的高度H2可大于其宽度W2。然而，高度也可小于宽度W2，例如为宽度的至少一半。
导电凸柱110优选地由铜或铜合金制成，但是还可包括其它导电材料，例如金或金与铜的组合。此外，导电凸柱110可包括至少一个金属层，该金属层的熔化温度大于要结合的焊料的熔化温度。例如，这种凸柱可包括铜层或者完全由铜形成。
在具体的实施例中，导电凸柱110可以是圆柱形，以便凸柱底部126和凸柱顶部128的直径大致相等。在一个实施例中，导电凸柱的底部126和顶部128的直径可在约30-150μm。每个导电凸柱110可具有邻近于基板102的底部126和远离基板102的顶部128。备选地，导电凸柱110可采用各种形状，例如截头圆锥形、矩形或杆形。
焊料130的涂层或帽部可附连到导电凸柱110的顶部128或者导电凸柱未附连到微电子元件104的部分。焊料130的帽部可具有与导电凸柱110相同的直径或宽度W2，从而变成导电凸柱110的延伸部。在一个示例中，焊料130的帽部可具有在约25-80μm的范围内变化的高度H3。
应当理解的是，导电凸柱110从微电子元件104的前表面122延伸的高度H2可等于导电凸柱108从介电元件102A的顶表面101延伸的高度H1(图1A)。但是备选地，高度可不同，使得导电凸柱110的高度H2可小于或大于导电凸柱108的高度H1。在具体描述的示例中，从微电子元件104延伸的导电凸柱110可具有长度为50μm的高度H2，而从基板延伸的导电凸柱108可具有55μm的高度H1(图2)。
为了将微电子元件104和基板102导电地连接在一起，微电子元件104上的导电凸柱110必须连接到基板102上的导电凸柱108。参考图1C，微电子元件104被倒置，使得微电子元件104的导电凸柱110和基板102的导电凸柱108彼此相互对齐且十分接近。微电子元件104上的焊料130帽部进行回流，以允许焊料润湿微电子元件104上的导电凸柱110和基板102上的导电凸柱108的表面。如图2-2A所示，焊料将润湿到导电凸柱的暴露表面并形成从微电子元件延伸到基板的导电杆106。焊料所结合的微电子元件104和基板102上的导电杆108、110的增加表面区域可有助于减少在焊料接口处的电流密度。电流密度的这种减少可有助于减少电迁移并提供更好的耐用性。
如图所示，导电杆106包括导电地互连导电凸柱的焊料。在一个示例中，在从微电子元件延伸的导电凸柱底部与从基板延伸的底部暴露部分之间延伸的导电杆的直立或高度H在80-100μm的范围内。
如图2和2A所示，导电杆106的壁132可以是凸形或桶形，其中导电杆的中点区域M(即，在微电子元件的导电凸柱110与基板的导电凸柱108之间)具有宽度W，该宽度W大于分别邻近基板102的顶表面101和微电子元件104的前表面102的导电杆106的部分的宽度W1和W2。
如图2A进一步所示，触头焊盘117可使用已知的方法形成在微电子元件104和基板102上。在一个实施例中，远离基板102延伸的下部凸柱108以及下部触头焊盘117可通过分离的蚀刻步骤来形成，例如于2008年6月28公布的国际申请PCT序号No.WO 2008/076428中所公开的，该申请以引用的方式结合到本文中。例如，具有顶部和底部金属层123以及中间蚀刻止挡层或内部金属层121的三金属基板可用来形成导电凸柱108和触头焊盘117。在一个这种工艺中，三层或更多层的金属结构的暴露金属层根据光刻图案光敏层进行蚀刻，以形成导电凸柱108，蚀刻工艺停止于结构的内部金属层121上。内部金属层121包括不同于顶部和底部金属层123的一种或多种金属，内部金属层的这种组成使得其不能由用来蚀刻顶部金属层123的蚀刻剂附连。例如，导电凸柱108所蚀刻的顶部金属层123主要包括铜，底部金属层123也可主要包括铜，而内部金属层121主要包括镍。镍提供相对于铜的良好选择性，以避免与金属层附连的镍层被蚀刻以形成导电凸柱108。为了形成触头焊盘117，可根据另一光刻图案光敏层来进行另一蚀刻步骤。凸柱108可与其它导电特征(例如，过渡件115)进一步互连，其它导电特征继而与其它导电特征(未示出)进一步互连。
参考图3，导电杆106’的壁232也可以是直的，使得宽度W5基本等于分别邻近于基板102’的顶表面101’和微电子元件104’的前表面122’的导电杆106’的宽度W4、W4’。应当理解的是，宽度W4、W4’不需要是相等的。备选地，导电杆106’的壁232’取决于要实现的直立程度可以是凹形的(见图4)。
根据本发明的导电杆106允许在介电元件与微电子元件之间的更大直立高度同时允许暴露于微电子元件104的前表面122的每个导电凸柱110之间的间距P(见图1B、2)以及暴露于基板102的顶表面101的每个导电凸柱108之间的间距P都明显减少。在一个实施例中，间距P可以小至50μm或大至200μm。应当理解的是，通过将导电杆108、110彼此相互对齐，每个导电凸柱108、110之间的间距P将相等。
间距P还可以是导电凸柱108、110的直径或宽度W1、W2的函数，使得导电凸柱的底部直径W1、W2高达间距P的75％。换句话说，直径W1、W2与间距P的比率可高达3∶4。例如，如果间距P是145μm，那么导电凸柱108、110的直径W1、W2可以变化成高达108μm或间距P的75％。
增加的直立高度减少了低-k介电材料的应变，该应变可存在于微电子元件中。此外，增加的直立有助于使得通常与小间距相关的问题(例如，电迁移和拥挤)最小化。这是因为导电杆106能够润湿导电凸柱108、110的表面。
参考图5-6，示出了将微电子元件上的导电凸块结合到基板上的导电凸块的备选配置。参考图5，不是将焊料帽部230放置在从微电子元件204延伸的导电凸柱210的顶部228上，而是焊料帽部230可放置在从基板202延伸的导电凸柱208的顶部216处。在一个实施例中，焊料帽部230的宽度或直径W5大致等于导电凸柱208的底部214的直径W6。因此，焊料帽部230延伸超出从基板202延伸的导电凸柱208的顶部216。然而，一旦焊料回流，导电杆将优选地采用图2中所示的导电杆形状。
参考图6，在又另一备选配置中，焊料帽部330可放置在从微电子元件304和基板302两者延伸的导电凸柱310、308上。导电凸柱310、308放置成彼此相互十分接近。施加热量从而使得焊料帽部330回流、润湿并熔合导电凸柱308、310。一旦回流，导电杆306将优选地类似于图2中所示的导电杆306。
参考图7，示出了微电子封装的备选配置。该配置类似于图2中所示的配置，唯一的不同在于，在邻近从基板延伸的导电凸柱处不存在焊料掩膜。在该备选配置中，过渡件307可用来将导电杆406导电地连接到电子电路(未示出)，电子电路暴露于基板402的底表面上，与基板402的顶表面401相反。使用过渡件307省去了焊料掩膜的需要。
参考图8，示出了备选的实施例，其中在导电凸柱之间进行金属对金属键合而不使用焊料。相反，通过将导电凸柱508、510变形使之彼此相互接合来在导电凸柱508、510之间形成键合。导电凸柱508、510优选地由延展性材料制成，延展性材料具有极小的弹性或弹性回复，例如大体上的纯金。此外，导电凸柱508、510可通过在凸柱与盖件材料之间的共熔键合或阳极键合而键合在一起。例如，导电凸柱508、510的顶部516、517可涂覆小量锡、硅、锗或与金形成相对低熔合金的其它材料，且凸柱可完全由金形成或在其表面上具有金涂层。当导电凸柱508、510彼此相互接合并被加热时，在导电凸柱508、510的材料与导电凸柱的顶部516上的材料之间的扩散形成熔点比在凸柱与壁的接口处单一元素的熔点更低的合金。当组件保持在升高温度时，进一步扩散使得合金元素从接口扩散开来进入到凸柱的金块体中，藉此升高在接口处材料的熔化温度并使得接口固化，从而在部件之间形成固态连接。
参考图9，该图与图8一致，除了导电凸柱608、610均优选地包括铜且在导电凸柱之间不存在低熔点金属(例如焊料或锡)的情况下彼此相互直接熔合之外。优选地，为了实现强键合，在导电凸柱608、610结合到端子之前，导电凸柱608、610的结合表面必须是清洁的且大致无氧化物(例如，自然氧化物)。通常，可执行特征为进行蚀刻或微蚀刻的表面的工艺，以去除贵金属(例如，铜、镍、铝和其它)的表面氧化物，表面蚀刻工艺被执行而通常不会影响位于其下方的凸块或金属层的厚度。该清洁工艺仅在实际结合工艺前不久最佳地实施。在不影响凸块与电容端子之间要实现的键合强度的前提下，在结合工艺之前，在部件在清洁后被保持在处于约30至70百分比相对湿度的正常湿度环境的状况下，清洁工艺通常可实施数个小时(例如，六个小时)。
如图10-11所示，在施行结合导电凸柱608、610的工艺期间，间隔器结构726被放置在基板602的顶表面601上。间隔器结构626可由一种或多种材料(例如，聚酰亚胺、陶瓷)或者一种或多种金属(例如，铜)形成。微电子元件604被放置在间隔器结构626上方，使得微电子元件604的导电凸柱610的顶部628位于基板602的导电凸柱608的顶部616上面，导电凸柱610从微电子元件604延伸。参考图10，间隔器结构626、微电子元件604和基板602被插入在一对板640之间，且同时在以箭头636指示的方向上施加热量和压力给导电凸柱。如图9所示，施加给板640的压力具有这样的影响：将导电凸柱的高度减少至高度H6，高度H6低于初始制得导电凸柱608、610的初始高度H5(图10)。在该步骤期间所施加压力的示例性范围在约20kg/cm2至约150kg/cm2之间。例如，结合工艺在从约140摄氏度至约500摄氏度范围内的温度下进行。
结合工艺将导电凸柱608、610压缩到使得导电凸柱608、610的前顶表面下方的金属在热量和压力下接触并结合的程度。由于该结合工艺，导电凸柱608、610的高度可按照1微米或更多来减少。当导电凸柱608、610主要包括铜时，导电凸柱之间的接头也主要包括铜，从而形成包括凸块和端子的连续铜结构。因此，如图9所示，板和间隔器结构被去除，剩下具有由导电凸柱608、610的导电接头形成的导电杆606的子组件250。
参考图12，示出了根据本发明的另一备选实施例。在此唯一的区别在于，不是使用单层基板，可使用多层基板，例如在2007年8月15日提交的名为“Interconnection Element with Posts Formed by Plating”的美国申请No.60/964,823、在2007年8月15日提交的名为“MultilayerSubstrate With Interconnection Vias and Method of Manufacturing theSame”的美国申请No.60/964,916、以及在2007年6月29日提交的名为“Multilayer Wiring Element Having Pin Interface”的美国申请No.11/824,484中描述的多层基板，上述申请以引用的方式结合到本文中。如图所示，多层基板702以倒装的方式与微电子元件704结合，例如具有有源装置、无源装置或者有源或无源装置于其上的半导体芯片。导电凸柱710的顶部716如本文所述结合到从微电子元件延伸的导电凸柱710，导电凸柱710的顶部716从多层基板的顶表面701突出。如图所示，多层基板702的导电凸柱708可直接结合到从微电子元件的前表面延伸的导电凸柱710，例如通过在凸柱顶部160处加工后的金属(例如，金)与存在于导电焊盘和凸柱中的另一金属之间形成扩散连接来实现。备选地，导电凸柱708、710可通过可熔合金属(例如，焊料、锡或共熔组合物)而结合到一起，可熔合金属将凸柱和焊盘润湿以形成润湿或焊接的接头。例如，可熔合金属可通过暴露在微电子元件704的前表面722处的以焊料凸块(未示出)的形式来提供，凸块被提供在导电凸柱顶部的一个或两个顶部末端。
导电杆还可用在叠层式封装中，例如在共同拥有的于2007年8月3日提交的名为“Die Stack Package Fabricated at the Wafer Level withPad Extensions Applied To Reconstituted Wafer Elements”的美国申请No.60/963,209、于2007年8月9日提交的名为“Wafer Level StackedPackages with Individual Chip Selection”的美国申请No.60/964,069、于2007年7月27日提交的名为“Reconstituted Wafer Stack Packagingwith After-Applied Pad Extensions”的美国申请No.60/962,200、以及于2007年6月20日提交的名为“Reconstituted Wafer Level Stacking”的美国申请No.60/936,617中所描述的这种封装。
例如，参考图13，在备选的实施例中，叠层式封装组件包括第一子组件800和第二子组件802。第一和第二子组件事实上与图2中所示的封装微电子元件相同，除了基板806、806’进一步延伸出以便容纳在第一和第二子组件的基板806、806’之间延伸的导电杆808。导电杆808还包括从基板延伸的导电凸柱812，导电杆808连接到延伸经过第二子组件上基板的顶表面和底表面的过渡件814。
虽然本发明参考具体的实施例进行描述，但是应当理解的是，这些实施例仅为了描述本发明的原理和应用。因此，应当理解的是，在不偏离由所附权利要求书限定的本发明精神和范围的前提下可作出描述性实施例的许多变型且可构想出其它配置。

Claims (28)

1.一种封装微电子元件，包括：
微电子元件，所述微电子元件具有前表面和远离前表面延伸的多个第一固态金属凸块，每个所述凸柱具有在前表面的方向上的宽度和从前表面延伸的高度，其中高度是所述宽度的至少一半；和
基板，所述基板具有顶表面和多个第二固态金属凸柱，所述多个第二固态金属凸柱从顶表面延伸且用可熔合金属结合到第一固态金属凸柱，所述第二凸柱具有顶表面和远离所述顶表面以陡峭角度延伸的边缘表面。
2.根据权利要求1所述的封装微电子元件，其特征在于，所述多个第一和第二固态金属凸柱主要包括铜。
3.根据权利要求1所述的封装微电子元件，其特征在于，所述第一凸块的直径与所述第一凸柱之间的间距的比率不大于3∶4。
4.根据权利要求1所述的封装微电子元件，还包括位于所述第一凸块下面的凸块下金属化层。
5.根据权利要求1所述的封装微电子元件，其特征在于，所述第一凸块的直径小于每个所述第一凸块之间的间距的一半。
6.根据权利要求1所述的封装微电子元件，其特征在于，所述第一凸块或第二凸柱被蚀刻。
7.一种封装微电子元件，包括：
微电子元件，所述微电子元件具有前表面和远离前表面延伸的多个第一固态金属凸柱，每个凸柱具有在前表面方向上的宽度和从前表面延伸的高度，其中高度是所述宽度的至少一半；和
基板，所述基板具有顶表面和多个第二固态金属凸柱，所述多个第二固态金属凸柱从顶表面延伸且结合到第一固态金属凸柱，其中所述第一和第二凸柱扩散连接在一起。
8.根据权利要求7所述的封装微电子元件，其特征在于，所述第一凸柱的直径与所述第一凸柱之间的间距的比率不大于3∶4。
9.根据权利要求7所述的封装微电子元件，其特征在于，所述微电子元件的所述前表面与所述基板的所述顶表面之间的距离大于80微米。
10.根据权利要求7所述的封装微电子元件，其特征在于，所述第一凸柱的每个的直径等于所述第二金属凸柱的每个的直径。
11.根据权利要求7所述的封装微电子元件，还包括在所述微电子元件的所述前表面与所述基板的所述顶表面之间的底部填充材料。
12.一种封装微电子元件，包括：
微电子元件，所述微电子元件具有前表面和远离前表面延伸的多个第一固态金属凸柱，每个凸柱具有在前表面方向上的宽度和从前表面延伸的高度，所述凸柱主要包括除了焊料、铅或锡之外的金属；和
基板，所述基板具有顶表面和多个第二固态金属凸柱，所述多个第二固态金属凸柱从顶表面延伸且用可熔合金属结合到第一固态金属凸柱，
其中所述第一或第二固态金属凸柱的直径与所述多个第一或第二固态金属凸柱之间的间距的比率不大于3∶4。
13.根据权利要求12所述的封装微电子元件，其特征在于，所述第一凸柱的每个的直径等于所述第二金属凸柱的直径。
14.根据权利要求12所述的封装微电子元件，其特征在于，所述基板是多层基板。
15.根据权利要求12所述的封装微电子元件，其特征在于，所述第一凸柱的直径小于所述第一凸柱中每个之间的间距的一半。
16.一种封装微电子元件，包括：
微电子元件，所述微电子元件具有前表面和远离前表面延伸的多个第一固态金属凸柱，每个凸柱具有在前表面方向上的宽度和从前表面延伸的高度；和
基板，所述基板具有顶表面和多个第二固态金属凸柱，所述多个第二固态金属凸柱从顶表面延伸且结合到第一固态金属凸柱，其中所述第一凸柱的间距在50至200微米的范围内变化，且所述微电子元件的所述底表面与所述基板的所述顶表面之间的距离大于80微米。
17.根据权利要求16所述的封装微电子元件，其特征在于，可熔合金属被用来将所述第二凸柱结合到所述第一凸柱。
18.根据权利要求16所述的封装微电子元件，其特征在于，所述第一凸柱中每个的直径等于所述第二金属凸柱的直径。
19.根据权利要求16所述的封装微电子元件，其特征在于，所述第一凸柱的直径小于所述第一凸柱中每个之间的间距的一半。
20.一种封装微电子元件，包括：
微电子元件；基板；以及在所述微电子元件与所述基板之间延伸的多个支柱，所述多个支柱中的每个包括附连到所述微电子元件的第一金属凸柱部分、附连到所述基板的第二金属凸柱部分、以及金属可熔合部分，其中所述第一金属部分和第二金属部分结合在一起，所述多个支柱的长度不大于50微米，且所述第一金属凸柱部分和第二金属凸柱部分的所述高度是所述宽度的至少一半。
21.根据权利要求20所述的封装微电子元件，其特征在于，所述微电子元件的所述前表面与所述基板的所述顶表面之间的距离大于80微米。
22.根据权利要求20所述的封装微电子元件，其特征在于，所述基板是多层基板。
23.根据权利要求20所述的封装微电子元件，其特征在于，所述第一凸柱中每个的直径等于所述第二金属凸柱的直径。
24.根据权利要求20所述的封装微电子元件，其特征在于，所述第一凸柱的直径小于所述第一凸柱中每个之间的间距的一半。
25.根据权利要求20所述的封装微电子元件，其特征在于，所述第一凸柱或第二凸柱被蚀刻。
26.一种组装封装微电子元件的方法，包括：
(a)提供微电子元件，所述微电子元件具有远离其第一表面延伸的多个导电凸柱，所述凸柱具有顶表面和远离所述顶表面以陡峭角度延伸的边缘表面，且可熔合金属面部附连到所述多个导电凸柱的末端；
(b)将微电子元件的凸柱与从基板的第一表面延伸的多个凸柱至少大致对齐；以及
(c)将微电子元件的凸柱与基板的凸柱结合。
27.根据权利要求26所述的方法，其特征在于，步骤(c)包括将可熔合金属加热到熔化温度，其中可熔合金属流动到凸柱边缘表面的暴露部分上。
28.根据权利要求26所述的组装方法，其特征在于，钝化层和凸块下金属化层沉积在所述微电子元件上。
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