CN101813744B - Parallel test system and parallel test method - Google Patents
Parallel test system and parallel test method Download PDFInfo
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- CN101813744B CN101813744B CN 200910009566 CN200910009566A CN101813744B CN 101813744 B CN101813744 B CN 101813744B CN 200910009566 CN200910009566 CN 200910009566 CN 200910009566 A CN200910009566 A CN 200910009566A CN 101813744 B CN101813744 B CN 101813744B
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Abstract
The invention relates to a parallel test system and a parallel test method, in particular to a parallel test system and a parallel test method which are applied to an open test system for carrying out a parallel test. In the invention, a simple parallel test conversion device for parallel test macro instructions is provided, so that the open test system can carry out the parallel test without using a complex pre-compiler, thus the test cost can be reduced and the test efficiency can be improved.
Description
Technical field
The present invention relates to a kind of parallel test system and parallel test method, particularly relate to and a kind ofly be applied to open test macro and carry out the parallel test system and the parallel test method of parallel testing.
Background technology
Existing test macro that tester table adopted and the mode that is used for semiconductor test generally is divided into two kinds; One for using the test macro of GUI (GUI); Its employed test procedure is built in this system; The user also can't or write promptly so-called enclosed test macro to its correct; Another kind then is to open to the user to carry out test procedure or test the system that firmware code (code) is write, and semiconductor element is tested promptly so-called open test macro according to test procedure or test firmware code that the user write again.
Because semiconductor element is popularized and diversification; The semiconductor element of increasing kind is developed; Therefore, tester table often need be tested various semiconductor element, and need use different test procedures to different semiconductor elements.Therefore, use this closed system of test macro of GUI (GUI) obviously not apply use, the proportion on open test macro uses then increases day by day.Yet; Most open test macro can only provide the test of single semiconductor element, only can test a semiconductor element at one time, and previous semiconductor elements such as need are for before test finishes; Just can test next semiconductor element; Be so-called test (Serial Test) in proper order, but and can't test promptly so-called parallel testing (Parallel Test) at one time simultaneously to a plurality of semiconductor elements.Therefore; General employed open test macro is because only can test in proper order; And can't can simultaneously a plurality of semiconductor elements be tested as enclosed test macro; Promptly carry out parallel testing, so open test macro causes tested performance downslide significantly than closed test macro.
Yet; If will implement parallel testing with existing open system by force; Compiler (pre-compiler) is handled the problem of the data that produced when simultaneously a plurality of semiconductor elements being carried out parallel testing and signal transmission before the extra increase by, and in order to the management testing flow process.But, in order to deal with various test procedures or the test firmware code that the user writes, and consider various testing processs and state; It is very huge and complicated causing required preceding compiler; Be very time-consuming and difficult in exploitation, and on safeguarding, huge burden arranged, therefore; Make whole open test macro become complicated equally and easy care not, institute is so that whole measuring examination cost significantly increases.
Secondly; The open test macro of compiler before this use; When parallel testing carries out; Each semiconductor element adopts the correspondence table that records corresponding relation between semiconductor element pin (device pin) and the TCH test channel (device channel) to be all same and for what fix, therefore, causes the cabling design on employed test carrier plate of tester table (load board) and the probe (probe card) to be restricted; And therefore can't make each semiconductor element in the parallel testing all obtain the shortest and data optimal and signaling path, cause the signal quality of open test macro bad.For instance; When the open test macro with compiler before using carries out parallel testing; The corresponding respectively and fixing TCH test channel of use of each test zone (site); For example first test zone uses the TCH test channel of numbering 1-10; And second test zone uses the TCH test channel of numbering 11-20 because each test zone all uses same correspondence table, so the pin of the semiconductor element in first test zone respectively the TCH test channel of reference numeral 1-4 test; Make the TCH test channel that the pin of the semiconductor element in second test zone only can reference numeral 11-14 test; And can't change according to different test carrier plates or the cabling on probe design, more can't make the corresponding different TCH test channel of semiconductor element in each test zone, and obtain the shortest and data optimal and signaling path.
This shows that above-mentioned existing parallel test system and parallel test method obviously still have inconvenience and defective, and demand urgently further improving in product structure, method and use.In order to solve the problem of above-mentioned existence; Relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly; But do not see always that for a long time suitable design is developed completion; And common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of new parallel test system and parallel test method; Open test macro can be switched with test patterns such as parallel testing in test in proper order; Test in proper order and parallel testing and in same test macro, provide; And need not to use huge and complicated preceding compiler, more can make the corresponding best TCH test channel of pin difference of each semiconductor element in the parallel testing, and make it obtain the shortest and data optimal and signaling path; And then cause the reduction of testing cost and real one of current important research and development problem that belongs to of increase of tested performance, also becoming the current industry utmost point needs improved target.
Summary of the invention
Fundamental purpose of the present invention is; Overcome the defective that existing parallel test system exists, and a kind of new parallel test system is provided, technical matters to be solved is to make it can carry out parallel testing to the test procedure that the user write; And need not to use huge and complicated preceding compiler; And each semiconductor element data optimal and the signaling path in the parallel testing is provided, and then reduce testing cost and increase tested performance, be very suitable for practicality.
Another object of the present invention is to; Overcome the defective that existing parallel test method exists; And a kind of new parallel test method, technical matters to be solved are provided is to make it in open test macro, convert the test procedure that the user write into the parallel testing flow process; And simultaneously several semiconductor elements are tested simultaneously; And each semiconductor element data optimal and signaling path are provided, and then reduce testing cost and increase tested performance, thereby be suitable for practicality more.
The object of the invention and solve its technical matters and adopt following technical scheme to realize.A kind of parallel test system according to the present invention proposes in order to switch between test and the parallel testing in proper order, comprises: a test control device, in order to the flow process and the running of control semiconductor element test; One parallel testing conversion equipment, in order to test in proper order and parallel testing between switching; And a test execution device, in order to accepting the test pattern that test instruction that this test control device provides and this parallel testing conversion equipment are provided, and carry out test according to this test instruction and this test pattern.
Wherein this parallel testing conversion equipment comprises: a parallel testing is carried out and the finishing control unit; In order to the test procedure that will write according to the user or a firmware code and the testing process of setting up; Convert parallel testing to and a plurality of semiconductor elements are carried out parallel testing, and control beginning, execution and the end of this parallel testing; One parallel testing DAQ storage unit in order to resulting data behind the parallel testing is captured and deposits, and supplies the follow-up test flow process to carry out the computing and the judgement of data; And test execution and a finishing control unit in proper order, test in proper order and test in order to testing process is converted to by parallel testing, and control this beginning of testing in proper order, carry out and end.
The object of the invention and solve its technical matters and also can adopt following technical measures further to realize.
Aforesaid parallel test system, it more comprises together pacing examination banner unit, and in order to setting the synchronism detection banner according to test mode, testing process or test result at that time, and decision will be carried out synchronism detection or test in proper order to those semiconductor elements.
Aforesaid parallel test system; It more comprises the automatic extension of TCH test channel unit, in order to the test event extension in this testing process and the TCH test channel (device channel) that corresponds to all semiconductor elements that are set with synchronism detection banner examination to carry out parallel testing.
Aforesaid parallel test system, it more comprises a metric data storage unit, in order to behind parallel testing, the test result and the metric data of each semiconductor element is deposited.
Aforesaid parallel test system, wherein said parallel testing are carried out with the finishing control unit and are more comprised the huge collection instruction of following parallel testing:
Aforesaid parallel test system, wherein said test execution in proper order and finishing control unit more comprise the following huge collection instruction of testing in proper order:
MacroSerialTestStart () // test beginning in proper order
Computing after //User ' s Operation//the obtain data
The EOT of MacroSerialTestEnd () // in proper order.
The object of the invention and solve its technical matters and also adopt following technical scheme to realize.A kind of parallel test method that proposes according to the present invention can comprise following steps: begin to carry out a test procedure in conversion testing pattern between test and the parallel testing in proper order; Set up a testing process according to this test procedure, wherein this testing process comprises each item test event; Convert this testing process to parallel testing flow process that a pair of a plurality of semiconductor element carries out synchronism detection; Carry out this parallel testing flow process; Collect data and test result that this parallel testing flow process is measured; And end parallel testing flow process.
The object of the invention and solve its technical matters and also can adopt following technical measures further to realize.
Aforesaid parallel test method, it more comprises together pacing examination banner and sets step, carries out the semiconductor element of synchronism detection in order to set the synchronism detection banner in needs, indicates by this or the selected semiconductor element of testing of put down.
Aforesaid parallel test method, it more comprises a TCH test channel extension step, in order to these test event extensions and correspond to all TCH test channels that are set with the semiconductor element of synchronism detection banner (device channel), and carries out parallel testing.
Aforesaid parallel test method; It more comprises one provides deposit data district step; In order to providing each this corresponding deposit data district of semiconductor element, and a deposit data step, in order to the data that each this semiconductor element measured are deposited to this corresponding deposit data district with test result.
Aforesaid parallel test method; It more comprises a computing and determining step; Metric data and test result in order to capture each this deposit data district are carried out computing and judgement; And judge whether each this semiconductor element carries out follow-up test or test branch, and and one reset synchronism detection banner step, each this semiconductor element that again needs is carried out follow-up test or test branch carries out the synchronism detection banner again and sets.
Aforesaid parallel test method, wherein said parallel test method can instruct by the huge collection of following parallel testing and accomplish:
The present invention compared with prior art has tangible advantage and beneficial effect.Can know that by above technical scheme major technique of the present invention thes contents are as follows:
For achieving the above object; The invention provides a kind of parallel test system; According to above-mentioned purpose; The present invention provides a kind of parallel test system; It not only can be tested in proper order, more can carry out parallel testing, its comprise a test control device in order to flow process and the running of the test of control semiconductor element, one in order to test in proper order and parallel testing between the parallel testing conversion equipment and of switching carry out the test execution device of test in order to accept the test pattern that test instruction that this test control device provides and this parallel testing conversion equipment provided.This parallel test system is by a simple parallel testing conversion equipment; For example huge collection instruction etc.; And can with the user the test procedure write or test firmware code; Simultaneously several semiconductor elements are tested with the parallel testing flow process, and each semiconductor element data optimal and signaling path are provided, and reduce testing cost and increase tested performance.
In addition, for achieving the above object, the present invention also provides a kind of parallel test method, and according to above-mentioned purpose, the present invention provides a kind of parallel test method, and the test procedure that the user write is carried out parallel testing.At first, begin to carry out the test procedure that a user writes, test procedure is set up a testing process according to this again, then, converts this testing process to testing process that a pair of a plurality of semiconductor element carries out synchronism detection.Then, begin to carry out parallel testing, and collect data and test result that parallel testing measured, last, treat that all semiconductor element tests finish after, promptly finish parallel testing.This delegation's method of testing is by simple steps; For example one carry out the parallel testing execution and finish huge collection instruction etc.; And with the user the test procedure write or test firmware code with the parallel testing flow performing; And each semiconductor element data optimal and signaling path are provided, and reduce testing cost and increase tested performance.
By technique scheme, parallel test system of the present invention and parallel test method have advantage and beneficial effect at least:
1, the present invention's effect of contrasting prior art is to provide a kind of and is applied to open test macro and carries out the parallel test system and the parallel test method of parallel testing; The preceding compiler that replaces bulky complex with a simple parallel testing conversion equipment or the instruction of huge collection; Promptly can be with test procedure that the user write or test firmware code with a simple parallel testing conversion equipment or a step; For example a huge collection instructs or carries out huge collection instruction step etc.; Replace complicated and preceding keymake huge and the exploitation difficulty, and testing process converts the parallel testing flow process in proper order, and then will reduce testing cost and increase testing efficiency.
2, in addition; Another effect that the present invention contrasts prior art is; A kind of parallel test system and parallel test method are provided, and it provides different correspondence table according to each semi-conductive position with state, and makes each semiconductor element pin correspond to best TCH test channel; In response to different test carrier plates or probe data optimal and signaling path are provided by this, and reduce restriction test carrier plate or the design of probe upward wiring.
In sum, the present invention provides a kind of parallel test system and parallel test method, particularly relevantly a kind ofly is applied to open test macro and carries out the parallel test system and the parallel test method of parallel testing.The present invention comprises the parallel testing conversion equipment that the huge collection of a simple parallel testing instructs with one; And make open test macro can carry out parallel testing; And need not use a complicated preceding compiler (pre-compiler), therefore, can reduce testing cost and improve tested performance.The present invention has obvious improvement technically, and has tangible good effect, really is the new design of a novelty, progress, practicality.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of instructions, and for let of the present invention above-mentioned with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
Figure 1A is the rough schematic of the parallel test system of one embodiment of the invention.
Figure 1B is the rough schematic of the parallel test system of another embodiment of the present invention.
Fig. 2 is the rough schematic of the parallel testing conversion equipment of another embodiment of the present invention.
Fig. 3 is the process flow diagram of the parallel test method of one embodiment of the invention.
10,10 ': parallel test system 20,20 ': test control device
30: parallel testing conversion equipment 40: the test execution device
32: parallel testing is carried out and finishing control unit 33: parallel testing data acquisition storage unit
34: test execution and finishing control unit 35 in proper order: synchronism detection banner unit
36: the automatic extension of TCH test channel unit 37: metric data storage unit
300: begin to carry out the test procedure step that the user writes
302: set up a testing process step according to test procedure
304: convert testing process to the parallel testing process step
306: carry out the parallel testing process step
308: collect data and test result step that the parallel testing flow process is measured
310: finish the parallel testing process step
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; Below in conjunction with accompanying drawing and preferred embodiment; To parallel test system and its embodiment of parallel test method, structure, method, step, characteristic and the effect thereof that proposes according to the present invention, specify as after.
Relevant aforementioned and other technology contents, characteristics and effect of the present invention can be known to appear in the following detailed description that cooperates with reference to graphic preferred embodiment.Through the explanation of embodiment, when can being to reach technological means that predetermined purpose takes and effect to get one more deeply and concrete understanding to the present invention, yet the appended graphic usefulness that only provides reference and explanation be not to be used for the present invention is limited.
See also shown in Figure 1A; Be the rough schematic of the parallel test system 10 of one embodiment of the invention, parallel test system 10 comprise one in order to the test control device of the flow process of control semiconductor element test and running 20, one in order to test in proper order and parallel testing between the parallel testing conversion equipment 30 and the test execution device 40 in order to the execution semiconductor element test that switch.Wherein, the test pattern that test instruction that test execution device 40 is provided according to test control device 20 and test procedure and parallel testing conversion equipment 30 are provided, and semiconductor element is tested.
30 of parallel testing conversion equipments provide test (Serial Test) and two kinds of test patterns of parallel testing (Parallel Test) in proper order, and the switching between these two kinds of test patterns is provided.See also shown in Figure 2ly, parallel testing conversion equipment 30 is carried out by a parallel testing that test execution and 34 of finishing control unit are formed in proper order with finishing control unit 32, a parallel testing data acquisition storage unit 33 and.Wherein, parallel testing is carried out and finishing control unit 32, in order to the testing process that test control device 20 is set up according to the test procedure that the user write, convert to one can test several semiconductor elements simultaneously parallel testing.Parallel testing data acquisition storage unit 33; Then in order to acquisition and test result and the metric data of depositing each semiconductor element in the parallel testing; Carry out operation of data and judgement for the follow-up test flow process, promptly carry out computing and the basis for estimation whether follow-up test continues of the metric data of each semiconductor element.Test execution and finishing control unit 34 then are to test in proper order in order to convert testing process to only single semiconductor element is surveyed at one time examination by parallel testing in proper order, and control beginning, execution and the end of test in proper order.
In addition; Parallel testing conversion equipment 30 has together pacing examination banner unit 35; In order to according to test mode, testing process or test result at that time; And one or more semiconductor element is set the synchronism detection banner, and to carry out synchronism detection and indicate with those semiconductor elements of decision, promptly indicate and will test in proper order with decision or the semiconductor element of parallel testing.
Secondly; Parallel testing conversion equipment 30 also has the automatic extension of TCH test channel unit 36, in order to the test event extension in the testing process and correspond to all TCH test channels that are set with the semiconductor element of synchronism detection banner (device channel) to carry out parallel testing.Wherein, The automatic extension of TCH test channel unit 36 comprises several different correspondence table; Each correspondence table is all put down in writing each pin (pin) of semiconductor element and the corresponding relation between each TCH test channel (device channel); And the corresponding relation that each correspondence table is put down in writing is neither identical, makes that carrying out each semiconductor element finds suitable correspondence table according to its position and state, makes each pin can form best or the shortest signaling path with corresponding TCH test channel; Or can cooperate the cabling design on employed test carrier plate or the probe, and reduce the test carrier plate or the restriction of probe upward wiring design.
Moreover parallel testing conversion equipment 30 also has a metric data storage unit 37, in order among parallel testing or afterwards, the test result and the metric data of each semiconductor element is deposited.Comprise several data access district (not shown) at metric data storage unit 37, the corresponding semiconductor element in each data access district, and store the metric data and the test result of pairing semiconductor element.
In the present embodiment; In parallel test system 10; Parallel testing conversion equipment 30 is between test control device 20 and test execution device 40; And the conversion between the performed testing process of the testing process of being set up as test control device 20 and test execution device 40, and test control device 20 and the stream oriented device of parallel testing conversion equipment 30 for separating.But in other embodiment shown in B figure, the parallel testing conversion equipment 30 in the parallel test system 10 ' is the part for test control device 20 ', and is arranged in the test control device 20 '.
Aforementioned parallel test system 10 and 10 ' function mode are following: the user after test control device 20 or 20 ' writes test procedure or test firmware code; Test control device 20 or 20 ' can be set up the testing process that a pair of single semiconductor element is tested according to test procedure or test firmware code; And be sent in the parallel testing conversion equipment 30, and test control device 20 or 20 ' can directly be assigned the execution test instruction to test execution device 40 or via 30 pairs of test execution devices 40 of parallel testing conversion equipment simultaneously.
Then; Parallel testing in the parallel testing conversion equipment 30 is carried out with finishing control unit 32 can convert this testing process to a parallel testing flow process automatically; The synchronism detection banner is then set in each semiconductor element or be set in the semiconductor element that need carry out parallel testing in synchronism detection banner unit 35, and as the semi-conductive sign of carrying out synchronism detection.Parallel testing carry out with 32 of finishing control unit by this together the setting of pacing examination banner select with those semiconductor elements of sign and will carry out parallel testing.
Then; The automatic extension of TCH test channel unit 36 can be with the automatic extension of test event in the testing process; And corresponding these test events of the TCH test channel that makes each semiconductor element that is set with the synchronism detection banner; And each semiconductor element that is set with the synchronism detection banner is according to each different correspondence table, and makes its each pin all corresponding one can cooperate the cabling design on test carrier plate or the probe and obtain TCH test channel the shortest and the optimum signal pipeline.Therefore; Parallel test system 10 of the present invention and 10 ' can not be subject to the cabling design on test carrier plate or the probe; Or design causes restriction to the cabling on test carrier plate or the probe, and can be to be applicable to various test carrier plates and probe, even uses each TCH test channel to cooperate the cabling on test carrier plate and the probe neatly; And obtain to shorten the pipeline of test signal, and then obtain preferable signal quality.
Then; The test pattern that test instruction that test execution device 40 provides according to test control device 20 or 20 ' and parallel testing conversion equipment 30 provide; With the automatic extension of the TCH test channel unit corresponding TCH test channel of 36 extensions the semiconductor element that several are set with the synchronism detection banner is tested simultaneously, do not set the semiconductor element of synchronism detection banner and then test synchronously.In parallel testing or afterwards; Metric data storage unit 37 is collected the metric data and the test result of each semiconductor element respectively; And it is stored in the corresponding data access district of each semiconductor element respectively, promptly in the indivedual exclusive data access districts of each semiconductor element.
After treating that parallel testing finishes; 33 of parallel testing data acquisition storage units can capture the metric data and the test result of each semiconductor element and carry out computing and judgement, and determine whether each semiconductor element carries out the next item down purpose test, follow-up testing process or step, or whether tests branch.For instance; If the metric data and the test result of the semiconductor element of parallel testing data acquisition storage unit 33 acquisitions meet the critical value that test procedure sets; For example surpass a certain specific voltage or electric current; Then carry out this semiconductor element is tested branch, or, then stop follow-up test flow process or test event if judge that by the metric data of semiconductor element and test result this semiconductor element is poor products.
By the time after all parallel testings were all accomplished, if also need test in proper order, test control device 20 or 20 ' then transmitted test instruction in proper order and gives parallel testing conversion equipment 30 and test execution device 40.After test control device 20 or 20 ' receives test instruction in proper order; Synchronism detection banner unit 35 can reset together pacing examination banner to semiconductor element; But only a semiconductor element is set the synchronism detection banner at one time, that is before a semiconductor element is accomplished test, can not set the synchronism detection banner in another semiconductor element; Therefore, test execution device 40 only can be tested same semiconductor element at one time.Certainly, parallel test system 10 of the present invention and 10 ' also can be accordinged to testing requirement, and in test at the beginning, just carries out above-mentioned test in proper order.
In addition, parallel testing of the present invention carry out with finishing control unit 32 in can comprise the huge collection of a simple parallel testing instruct the beginning of controlling parallel testing, execution, with finish, and the metric data and the test result of collection parallel testing, for example:
Wherein, User ' s Test Item 1 and User ' s Test Item 2 are respectively the different test event in the test procedure that the user writes; Though have only two projects in the present embodiment, not as limit, but can a testing requirement and increase and decrease.
Moreover, in test execution in proper order of the present invention and the finishing control unit 34, also can comprise one simply test in proper order huge collection instruct the beginning of controlling test in proper order, execution, with finish, and the computing of the metric data of test in proper order, for example:
MacroSerialTestStart () // test beginning in proper order
Computing after //User ' s Operation//the obtain data
The EOT of MacroSerialTestEnd () // in proper order
Therefore; According to the foregoing description; Parallel test system of the present invention not only can be tested the test procedure that the user write in proper order, more can carry out parallel testing, and with the bulky complex of the existing convention of a simple parallel testing conversion equipment and be difficult for the preceding compiler of development and maintenance; And each semiconductor element data optimal and the signaling path in the parallel testing is provided, reduce testing cost by this and increase tested performance.
In addition; It can be to be used for various open test macros that the present invention more provides a kind of parallel testing conversion equipment; And test in proper order and parallel testing between switching, and various open test macros not only can be tested in proper order, more can carry out parallel testing; And shorten the test duration, and increase tested performance.The composition of this parallel testing conversion equipment is as shown in Figure 2, and it is described in preamble, therefore, repeats no more at this.
Secondly, the present invention more provides a kind of parallel testing mode, can in an open test macro, carry out parallel testing, and without any need for huge and complicated preceding compiler.See also shown in Figure 3ly, it is the process flow diagram of the parallel test method of one embodiment of the invention.At first, write a test procedure or test firmware code behind tester table the user, tester table can begin to carry out this test procedure or test firmware code (step 300).Wherein, This test procedure or test firmware code are write with c programming language; But not as limit, but can be according to the demand of test procedure or the kind of tester table and the program language of taking to be fit to write, and this test procedure includes multinomial test event.
Then, tester table test procedure is according to this set up the testing process (step 302) that a pair of single semiconductor element is tested, and this testing process includes each item test event in the test procedure.Then; Again this testing process is changed; And convert the parallel testing flow process (step 304) that can test a plurality of semiconductor elements simultaneously to, then, begin to carry out this parallel testing flow process and a plurality of semiconductor elements are carried out synchronism detection (step 306).Then; When carrying out the parallel testing flow process or afterwards, collect the metric data and the test result (step 308) of each semiconductor element of participating in parallel testing, then; After each semiconductor element is all accomplished test, finish this parallel testing flow process (step 310).
In addition; This parallel test method more comprises together pacing examination banner and sets step; Convert in the parallel testing process step (step 304) at testing process; More comprise together pacing examination banner and set step, carry out the semiconductor element of synchronism detection in needs, indicate by this or the selected semiconductor element of testing of put down and set the synchronism detection banner.Moreover; Testing process converts that (step 304) also comprises a TCH test channel extension step in the parallel testing process step to; In order to the extension of each item test event and correspond to the TCH test channel (device channel) that all are set with the semiconductor element of synchronism detection banner examination; And make each semiconductor element that is set with the examination of synchronism detection banner can correspondingly implement various test events, and carry out parallel testing.
TCH test channel extension step then comprises one provides the correspondence table step; Make each semiconductor element that is set with the synchronism detection banner according to each different correspondence table, and make each pin all corresponding one can cooperate the cabling design on test carrier plate or the probe and obtain TCH test channel the shortest and the optimum signal pipeline.Each pin (pin) of each each semiconductor element of correspondence table record and the corresponding relation between each TCH test channel, and provide the shortest test signal pipeline of each semiconductor element to come parallel testing with the best.Therefore; Make parallel test method of the present invention not only can not be subject to the cabling design on test carrier plate or the probe; Or design causes restriction to the cabling on test carrier plate or the probe; Even use each TCH test channel to cooperate the cabling on test carrier plate and the probe neatly, and obtain to shorten the pipeline of test signal, and then obtain preferable signal quality.
In addition; The metric data of each semiconductor element of collection participation parallel testing and the step (step 308) of test result more comprise one provides deposit data district step; In order to provide each semiconductor element that is set with the synchronism detection banner corresponding deposit data district, promptly provide each semiconductor element that carries out parallel testing indivedual exclusive deposit data districts.Secondly, collect the metric data of each semiconductor element of participating in parallel testing and the step (step 308) of test result and also comprise a deposit data step, and the metric data of each semiconductor element is deposited to corresponding deposit data district with test result.
Parallel test method of the present invention more comprises a computing and determining step; It carries out computing and judgement by the metric data of corresponding this semiconductor element of exclusive deposit data district acquisition of each semiconductor element and test result; And the specification that test procedure provided of writing according to the user; Judge the test mode of each semiconductor element, and judge whether each semiconductor element will carry out follow-up test or test branch.Moreover; Parallel test method of the present invention more comprises one and resets synchronism detection banner step; And the semiconductor element that again needs is carried out follow-up test or test branch carries out the synchronism detection banner again and sets, and indicates and the selected semiconductor element that need carry out follow-up test or test branch.
In addition; Parallel test method of the present invention can be by the huge collection instruction of a simple parallel testing; Control parallel testing beginning, execution, with finish, and the metric data and the test result of collecting parallel testing, this parallel testing is huge to be collected instruction and describes in preamble; Therefore, repeat no more at this.
This parallel test method more can be accomplished parallel testing; Then test in proper order, it comprises a testing procedure in proper order, in order to test in proper order; And also comprise a single synchronism detection banner and set step; In at one time, only semiconductor element is set the synchronism detection banner, and indicate or the selected semiconductor element of testing in proper order and testing.This in proper order testing procedure can test the instruction of huge collection simply in proper order by one; Control in proper order test beginning, execution, with finish, and and the computing of the metric data of test in proper order, this one tests in proper order and hugely collects instruction and describe in preamble; Therefore, repeat no more at this.
Therefore; Provided by the present inventionly be applied to open test macro and carry out parallel testing conversion equipment, parallel test system and the parallel test method of parallel testing; Can be with test procedure that the user write or test firmware code with a simple parallel testing conversion equipment or a step; For example a huge collection instructs or carries out huge collection instruction step etc.; Replace complicated and preceding keymake huge and the exploitation difficulty, and testing process converts the parallel testing flow process in proper order, and then will reduce testing cost and increase testing efficiency.In addition; The present invention can provide different correspondence table with state according to each semi-conductive position; And make each semiconductor element pin correspond to best TCH test channel; In response to different test carrier plates or probe data optimal and signaling path are provided by this, and reduce restriction test carrier plate or the design of probe upward wiring.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction; Though the present invention discloses as above with preferred embodiment; Yet be not in order to limiting the present invention, anyly be familiar with the professional and technical personnel, in not breaking away from technical scheme scope of the present invention; When the method for above-mentioned announcement capable of using and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations; In every case be the content that does not break away from technical scheme of the present invention, to any simple modification, equivalent variations and modification that above embodiment did, all still belong in the scope of technical scheme of the present invention according to technical spirit of the present invention.
Claims (9)
1. parallel test system in order to switch between test and the parallel testing in proper order, is characterized in that it comprises:
One test control device is in order to the flow process and the running of control semiconductor element test;
One parallel testing conversion equipment, in order to the switching between the test pattern and parallel testing pattern in proper order to be provided, wherein this parallel testing conversion equipment comprises:
One parallel testing is carried out and the finishing control unit; In order to the test procedure that will write according to the user or a firmware code and the testing process of setting up; Convert parallel testing to and a plurality of semiconductor elements are carried out parallel testing, and control beginning, execution and the end of this parallel testing;
One parallel testing DAQ storage unit in order to resulting data behind the parallel testing is captured and deposits, and supplies the follow-up test flow process to carry out the computing and the judgement of data; And
One test execution and finishing control unit in proper order tested in proper order and tested in order to testing process is converted to by parallel testing, and controls this beginning of testing in proper order, carries out and end; And
One test execution device; In order to accept the test pattern that test instruction that this test control device provides and this parallel testing conversion equipment are provided; And according to this test instruction and this test pattern execution test; Wherein, this parallel testing conversion equipment is arranged between this test control device and this test execution device, but this parallel testing conversion equipment is the stream oriented device that separates with this test control device; Or this parallel testing conversion equipment is arranged at this test control device, and is the part of this test control device.
2. parallel test system according to claim 1; It is characterized in that it more comprises together pacing examination banner unit; In order to setting the synchronism detection banner according to test mode, testing process or test result at that time, and which semiconductor element decision will carry out synchronism detection or test in proper order to.
3. parallel test system according to claim 2; It is characterized in that it more comprises the automatic extension of TCH test channel unit, in order to the test event extension in this testing process and the TCH test channel that corresponds to all semiconductor elements that are set with the synchronism detection banner to carry out parallel testing.
4. parallel test system according to claim 3 is characterized in that it more comprises a metric data storage unit, in order to behind parallel testing, the test result and the metric data of each semiconductor element is deposited.
5. parallel test method can is characterized in that it comprises following steps in conversion testing pattern between test and the parallel testing in proper order:
Begin to carry out a test procedure;
Set up a testing process according to this test procedure, wherein this testing process comprises each item test event;
Convert this testing process to parallel testing flow process that a pair of a plurality of semiconductor element carries out synchronism detection;
With state different correspondence table is provided according to each semi-conductive position, and makes each semiconductor element pin correspond to best TCH test channel, and data optimal and signaling path are provided;
Carry out this parallel testing flow process;
Collect data and test result that this parallel testing flow process is measured; And
Finish the parallel testing flow process.
6. parallel test method according to claim 5; It is characterized in that it more comprises together pacing examination banner and sets step; Carry out the semiconductor element of synchronism detection in order to set the synchronism detection banner in needs, indicate by this or the selected semiconductor element that carries out parallel testing.
7. parallel test method according to claim 6; It is characterized in that it more comprises a TCH test channel extension step; In order to these test event extensions and correspond to the TCH test channel that all are set with the semiconductor element of synchronism detection banner, and carry out parallel testing.
8. parallel test method according to claim 7; It is characterized in that it more comprises one deposit data district step is provided; In order to provide each this semiconductor element corresponding deposit data district; And a deposit data step, in order to the data that each this semiconductor element measured are deposited to this corresponding deposit data district with test result.
9. parallel test method according to claim 8; It is characterized in that it more comprises a computing and determining step; Metric data and test result in order to capture each this deposit data district are carried out computing and judgement; And judge whether each this semiconductor element carries out follow-up test or test branch, and and one reset synchronism detection banner step, each this semiconductor element that again needs is carried out follow-up test or test branch carries out the synchronism detection banner again and sets.
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