CN101714557A - Y方向没有od间隙影响的标准单元 - Google Patents
Y方向没有od间隙影响的标准单元 Download PDFInfo
- Publication number
- CN101714557A CN101714557A CN200910178122A CN200910178122A CN101714557A CN 101714557 A CN101714557 A CN 101714557A CN 200910178122 A CN200910178122 A CN 200910178122A CN 200910178122 A CN200910178122 A CN 200910178122A CN 101714557 A CN101714557 A CN 101714557A
- Authority
- CN
- China
- Prior art keywords
- active area
- spacer bar
- semiconductor substrate
- border
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Abstract
一种集成电路结构包括:半导体衬底;位于半导体衬底中的第一有源区;位于半导体衬底中并具有和所述第一有源区相反导电类型的第二有源区。栅极带位于第一有源区和第二有源区上方,并与所述第一有源区和所述第二有源区分别形成第一金属氧化物半导体器件和第二金属氧化物半导体器件。第一间隔条位于所述半导体衬底中并连接到所述第一有源区上。至少部分的所述第一间隔条与部分的所述第一有源区相邻并分离开。第二间隔条位于所述半导体衬底中并连接到所述第二有源区上。至少部分的所述第二间隔条与部分的所述第二有源区相邻并分离开。
Description
技术领域
本发明通常涉及一种半导体器件,尤其涉及一种金属氧化物半导体(MOS)器件,并且甚至涉及一种MOS器件的应力改善。
背景技术
在过去几十年里,半导体器件,例如金属氧化物半导体(MOS)器件的尺寸以及内在特性的减少已使得集成电路每单位功能的速度、性能、密度和成本得到持续改善。根据MOS器件的设计及其内在特征中的一个,调整位于MOS器件源极和漏极之间的栅极下方的沟道区长度,改变了与沟道区有关的电阻,从而影响MOS器件的性能。特别是,沟道区长度的缩短减小了MOS器件的源-漏极电阻,当足够的电压被提供到MOS器件的栅极时,假设其他特性维持相对不变,这样则可能使得源极与漏极之间的电流增加。
为了进一步增强MOS器件的性能,可以将应力引入到MOS器件的沟道区中,以改善其载流子迁移率,这样接下来导致饱和电流的改善,因此改善了速度。通常,理想的是沿源-漏方向(沟道长度方向)在n型MOS(NMOS)器件的沟道区中感应拉伸应力,以及沿沟道长度方向在p型MOS(PMOS)器件的沟道区中感应压力。另一方面,PMOS和NMOS器件均受益于沿沟道宽度方向的拉伸应力。
可以各种方式将应力施加给MOS器件,例如通过应力蚀刻停止层和/或应力浅沟槽隔离(STI)区。图1显示了部分标准单元的设计版图,该标准单元包括PMOS器件2和NMOS器件4。PMOS器件2包括有源区6和位于有源区6上方的栅极10。NMOS器件4包括有源区8和位于有源区8上方的栅极10。PMOS器件2和NMOS器件4的沟道区分别包括位于栅极10下方的部分有源区6和8。
假设存在通过STI区14与有源区6分离开的另一个有源区12,其中有源区12和有源区6之间的间隙为S1、STI区14通常将压力施加到有源区6上,并因而不利地影响PMOS器件2的驱动电流。此外,由STI区14施加的压力大小受间隙S1的数值影响,并且S1越大,压力将越大。在利用标准单元设计形成的半导体芯片上,通常存在许多相对地随机放置的标准单元,因此对于一个标准单元的间隙S1可以显著区别于对于另一个标准单元的间隙1。这导致MOS器件的驱动电路显著变化,此外用于某些MOS器件的一些间隙S1可以很大,以至于相应MOS器件的驱动电流被影响到某些设计不能接受的程度。因此需要新的标准单元来解决上述问题。
发明内容
根据本发明的一个方面,提供了一种集成电路结构包括半导体衬底;位于半导体衬底中的第一有源区;位于半导体衬底中并具有和所述第一有源区相反导电类型的第二有源区。栅极带位于第一有源区和第二有源区上方,并与所述第一有源区和所述第二有源区分别形成第一金属氧化物半导体器件和第二金属氧化物半导体器件。第一间隔条位于所述半导体衬底中并连接到所述第一有源区。至少部分的所述第一间隔条与部分的所述第一有源区相邻并分离开。第二间隔条位于所述半导体衬底中并连接到所述第二有源区。至少部分的所述第二间隔条与部分的所述第二有源区相邻并分离开。
根据本发明的另一方面,一种集成电路结构包括:半导体衬底;位于所述半导体衬底中的第一有源区;和位于所述半导体衬底中并具有和所述第一有源区相反导电类型的第二有源区。栅极带位于所述第一有源区和所述第二有源区上方,并与所述第一有源区和所述第二有源区分别形成第一金属氧化物半导体器件和第二金属氧化物半导体器件。第一间隔条位于所述半导体衬底中,并具有和所述第一有源区相同导电类型。所述第一间隔条为和所述第一有源区相邻并分离的有源区。第二间隔条位于所述半导体衬底中,并具有和所述第二有源区相同导电类型,其中所述第二间隔条为和所述第二有源区相邻并分离的附加有源区。
根据本发明的再一方面,一种集成电路结构,包括具有第一边界、第二边界、第三边界和第四边界的标准单元。所述第一边界和所述第二边界位于所述标准单元的相对两端,以及所述第三边界和所述第四边界位于所述标准单元的相对两端。所述标准单元包括半导体衬底;位于所述半导体衬底中的有源区;位于所述有源区上方的栅极带;以及作为所述半导体衬底中附加有源区的间隔条。所述间隔条与全部的所述第三边界、部分的所述第一边界以及部分的所述第二边界邻接。所述间隔条和所述有源区属于第一导电类型。绝缘区形成在所述半导体衬底中,其中所述绝缘区位于至少部分的所述第一有源区和至少部分的所述第一间隔条之间,并与它们邻接。
本发明的优点包括:一个金属氧化物半导体(MOS)器件的有源区和相邻有源区之间的间隙(沿Y方向)可调整,以及MOS器件的性能更可预知。
附图说明
为了更全面地理解本发明及其优点,现在将结合附图给出下面的详细说明,其中:
图1显示了传统标准单元,其中该标准单元的MOS器件中有源区与相邻有源区之间的间隙根据标准单元的位置来确定;
图2A、图2B和图2C为本发明实施例在制造过程中间阶段的俯视图和剖视图;
图3显示了具有与有源区断开的间隔条的实施例;
图4和图5为包括多个并联连接反相器的标准单元实施例;
图6显示了分接头(tap)单元的版图;
图7显示了填充单元(filler cell)的版图;
图8显示了包括标准单元、分接头单元和填充单元的电路结构,其中各个单元被设置为多个行;以及
图9显示了仿真结果。
具体实施方式
下面,将对本发明的优选实施例的实现及使用做出讨论。但是,应当了解本发明提供许多可应用的发明概念,这些发明概念可以体现在各种特定环境下。文中讨论的特定实施例仅阐述了本发明的实现及使用的特定方式,并不用来限制本发明的保护范围。
本发明提出了一种包括用来对施加到金属氧化物半导体(MOS)器件上的应力进行调节的间隔条的新型集成电路,下面将对本发明优选实施例及其变化进行讨论。在本发明的所有不同视图及实施例中,相似的参考数字将用于指示相似的元件。
图2A显示了本发明的一个实施例,该实施例提供了具有某种逻辑功能的标准单元20的一部分。图示的标准单元20包括例如形成反相器的PMOS器件30和NMOS器件40,虽然标准单元20可以包括更多的MOS器件(该图中未显示,可以参考图4和图5)。标准单元20的上边界和下边界利用箭头21做出标记,以及左边界和右边界利用箭头21’做出标记。PMOS器件30包括有源区32和位于有源区32上方的部分栅极带22。NMOS器件40包括有源区42和位于有源区42上方的部分栅极带22。如现有技术可知,位于栅极带22相对侧的部分有源区32形成PMOS器件30的源极和漏极区,并且位于栅极带22相对侧的部分有源区42形成NMOS器件40的源极和漏极区。
有源区32被重掺杂为p型,以及有源区42被重掺杂为n型。接触孔插塞102形成在各个MOS器件30和40的源极和漏极区上方,并将该源极和漏极区连接到金属化层(图中未显示)的上层金属线上。
间隔条34和44形成在标准单元20的边界上。图2B和2C显示了图2A所示结构的剖视图,其中图2B、2C分别为沿图2A上2B-2B线和2C-2C线的剖视图。图2B和图2C显示间隔条34和44为衬底100的一部分,并且由浅沟槽隔离(STI)区24和其他STI区限定。间隔条34和44也被称作为有源区或者伪有源区。此外,间隔条34和44可以分别与有源区32及42同时形成,并包括与有源区32及42大体相同的材料,虽然它们也可以不同时形成并包括不同的材料。在随后的自对准的硅化物工艺(salicideprocess)中,硅化物区104也可以形成在间隔条34和44上,其中硅化物区104从有源区32上方到有源区36和34(参考图2B)上方连续延伸,并且从有源区42上方到有源区46和44上方连续延伸。
返回参考图2A,在一个实施例中,每个间隔条34和44具有一部分(例如大约一半)位于标准单元20的内部,并且另一部分位于标准单元20的外部。位于标准单元20外侧的部分间隔条34和44可以实际上位于与标准单元20相邻的其他标准单元中。因此,如果标准单元20被认为是与其他标准单元分离,则间隔条34和44邻近边界21,从而当从Y方向(PMOS器件30和NMOS器件40的沟道宽度方向)将其他标准单元与标准单元20相邻放置时,它们的间隔条34和44将分别与标准单元20的间隔条34和44相邻。优选地,间隔条34和44与标准单元20的左边界21’和由边界21’邻近,从而当沿X方向(PMOS器件30和NMOS器件40的沟道长度方向)放置其他标准单元与标准单元20相邻时,它们的间隔条34和44将分别与标准单元20的间隔条34和44相邻。但是,可以认识到标准单元20可以包括更多的MOS器件,并且间隔条34和44将相应地进一步延伸。在选择实施例中,间隔条34和44通过STI区互相分离开。因此,沿Y方向,标准单元20将不会与相邻标准单元分享共用的间隔条。
间隔条34可以与有源区36相邻。因此,间隔条34、有源区32以及有源区36可以形成连续的有源区(参考图2B)。在一个实施例中,间隔条34和/或有源区36可以被掺杂为p型,其中掺杂物可以在PMOS器件30的源极和漏极区形成的同时被引入。在替代的实施例中,当形成PMOS器件30的源极和漏极区时,可以不对间隔条34和/或有源区36进行掺杂。因此,间隔条34与有源区36可以为n型,并具有和各自n阱33(参考图2B和2C)大体相同的杂质浓度,其中PMOS器件30位于n阱33中。有源区36优选具有较小宽度W1(见图2A),宽度W1优选小于标准单元20宽度W2的大约百分之二十。此外,宽度W1可以小于有源区32宽度W3的大约百分之三十。
请注意,间隔条34不同于传统的可以靠近PMOS器件30形成的引出(pickup)区。由于传统引出区需要具有和PMOS器件30形成其中的n阱相同的导电类型,因此传统引出区必须被重掺杂有n型杂质。优选地,标准单元20中没有引出区形成,虽然可以形成一个引出区。
类似地,间隔条44可以邻近有源区46。因此,间隔条44、有源区42和有源区46形成连续的有源区(还参考图2B)。在一个实施例中,间隔条44和/或间隔条46被掺杂为n型,其中掺杂物可以在NMOS器件40的源极和漏极区形成的同时被引入。在替代实施例中,当形成NMOS器件40的源极和漏极区时,可以不对间隔条44和/或有源区46进行掺杂。因此,间隔条44与有源区46可以为p型,并具有和各自p阱(图中未显示)或p型衬底100(参考图2B和2C)相同的杂质浓度,其中NMOS器件40位于p阱或p型衬底100中。
间隔条34和有源区32具有预定固定间隙S2。这可以有利地控制STI区24施加到有源区32的应力,而不管应力为拉伸应力还是压缩应力。作为比较,如果没有形成间隔条34,STI区24可以沿间隙S2’的Y方向延时,直至到达另一个有源区(或者伪有源区)26。这种情况下,应力的大小取决于标准单元20在对应芯片中的放置位置。由于间隙S2’可以根据标准单元20的定位显著变化,因此由SIT区24提供的应力大小也显著变化,并因而对应MOS器件的性能是不可预知的。但是,随着间隔条34和44的形成,应力是可控制的,并且因而PMOS器件30和NMOS器件40的性能是可预知的。
如图3所示,间隔条34和/或44可以与对应的有源区32和42分离。除有源区36和46由STI区24替代之外,图3所示实施例与图2A、图2B及图2C显示的实施例基本相同。间隔条34(其可以是p型的)可以因此电浮置在底层n阱区22(参考图2B和图2C)中,虽然其可以电连接到其他结构或电压电源上,例如接地。类似地,间隔条44(其可以是n型的)可以因此电浮置在底层p阱区(图中未显示)或p型衬底100(参考图2B和2C)中,虽然其可以电连接到其他结构或电压电源上,例如接地。
图4显示了由四个并联连接的反相器构成的标准单元20。与图2A和2B显示的实施例类似,形成的间隔条34和44用于限制有源区32和42与它们各自相邻的有源区之间的间隙。间隔条34和44分别通过有源区36和46连接到有源区32和42上。图5显示了与图4类似的结构,除了间隔条34和44与对应有源区32和42分离开。
图6显示了分接头(tap)单元60,分接头单元60可以作为用于n阱区和p阱区(或p型衬底)的引出单元。图6还显示了一个附加标准单元20,以显示分接头单元60如何可以与标准单元20相邻。分接头单元60包括重掺杂n型区62和重掺杂p型区64。n型区62作为用于图2B和图2C显示n阱区33的引出区,其中n阱区中定位有PMOS器件30,并且p型区64作为用于p阱(图中未显示)或p型衬底100(如图2B和图2C显示)的引出区,其中p阱或p型衬底100中定位有NMOS器件40。n型区62可以与p型的间隔条34邻接。在另一实施例中,形成p型区63与间隔条34及n型区62邻接。在又一个实施例中,标记为63的区域为STI区,其中STI区将n型区62和间隔条34隔开。类似地,p型区64可以和n型的间隔条44邻近。在其他实施例中,形成n型区65以与间隔条44及p型区64邻接。在又一个实施例中,标记为65的区域为STI区,其中该STI区将p型区64和间隔条44隔开。
图7显示了填充单元70,其用于填充不使用的芯片区域。该图还显示了一个附加标准单元20,以显示填充单元70如何能够与标准单元20邻接。填充单元70包括伪栅极带(通常称作为多晶硅栅)72和伪有源区74及76。优选地,为了工艺方便,伪有源区74为p型,同时伪有源区76为n型,虽然它们也可以被掺杂为相同的导电类型。间隔条34和44可以安装在填充单元70内,从而当填充单元70靠近标准单元20放置时,间隔条34和44自动连接,以形成从填充单元70向标准单元20中延伸的延伸带。
图8显示了如何集成标准单元20、分接头单元60以及填充单元70。图8包括三行单元,其中第一行与第二行单元共享一个共用的间隔条44。类似地,间隔条34也由第二行与第三行单元共享。可以注意到,位于标准单元20、分接头单元60以及填充单元70中的间隔条34贯穿整个行形成一个长间隔条,并且位于标准单元20、分接头单元60以及填充单元70中的间隔条44也贯穿整个行形成一个长间隔条。因此,沿Y方向任一PMOS器件与相邻有源区之间的间隙由安装的间隔条34和44所限制,并因而间隙在可控范围内浮动,而不管相邻行中具有何种结构。
虽然上文实施例中描述了间隔条形成在标准单元中,但是它们也可以形成在非标准单元的其他结构中。此外,间隔条34和44能够互相平行地依次形成,并且/或者与标准单元的栅极带22基本上垂直。
本发明的实施例具有多个优点。通过限制Y方向相邻有源区之间的间隙,MOS器件的性能变化被限制在可预知的范围内。图9显示了在包括五个不同电路的基准电路上执行的仿真结构。X轴表示相邻有源区之间的Y向间隙(OD间隙),并且Y轴表示基准电路的速度。可以注意到,当允许间隙在大约0.3μm到大约0.6μm之间波动时,基准电路的速度在大约1.568GHz和大约1.58GHz之间变化。但是,利用本发明实施例,基准电路的速度可以固定在大约1.58GHz。本发明的实施例不需要额外的掩模和工艺步骤,因此在不需要额外制造成本的情况下可以获得本发明的优点。
虽然关于示例实施例及其优点已经详细说明,应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下,可以对这些实施例进行各种变化、替换和修改。此外,本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容,作为本领域的普通技术人员将容易地理解,对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤,其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果,依照本发明可以对它们进行应用。因此,本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。
Claims (15)
1.一种集成电路结构,包括:
半导体衬底;
位于所述半导体衬底中的第一有源区;
位于所述半导体衬底中并具有和所述第一有源区相反导电类型的第二有源区;
位于所述第一有源区和所述第二有源区上方的栅极带,所述栅极带与所述第一有源区和所述第二有源区分别形成第一金属氧化物半导体器件和第二金属氧化物半导体器件;
位于所述半导体衬底中并连接到所述第一有源区的第一间隔条,其中至少部分的所述第一间隔条与部分的所述第一有源区相邻并分离开;以及
位于所述半导体衬底中并连接到所述第二有源区的第二间隔条,其中至少部分的所述第二间隔条与部分的所述第二有源区相邻并分离开。
2.如权利要求1所述的集成电路结构,其中所述第一间隔条和所述第一有源区为第一导电类型,所述第二间隔条和所述第二有源区为与所述第一导电类型相反的第二导电类型。
3.如权利要求2所述的集成电路结构,还包括:
位于所述半导体衬底中并具有与所述第一间隔条及所述第一有源区相同导电类型的第三有源区;以及
位于所述半导体衬底中并具有与所述第二间隔条及所述第二有源区相同导电类型的第四有源区,其中所述第三有源区位于所述第一间隔条和所述第一有源区之间并与所述第一间隔条和所述第一有源区邻接,并且所述第四有源区位于所述第二间隔条和所述第二有源区之间并与所述第二间隔条和所述第二有源区邻接。
4.如权利要求1所述的集成电路结构,其中所述第一有源区和所述第一间隔条通过第一浅沟槽隔离区互相完全分离,并且其中所述第二有源区和所述第二间隔条通过第二浅沟槽隔离区互相完全分离。
5.一种集成电路结构,包括:
半导体衬底;
位于所述半导体衬底中的第一有源区;
位于所述半导体衬底中并具有和所述第一有源区相反导电类型的第二有源区;
位于所述第一有源区和所述第二有源区上方的栅极带,所述栅极带与所述第一有源区和所述第二有源区分别形成第一金属氧化物半导体器件和第二金属氧化物半导体器件;
位于所述半导体衬底中并具有和所述第一有源区相同导电类型的第一间隔条,其中所述第一间隔条为和所述第一有源区相邻并分离的有源区;以及
位于所述半导体衬底中并具有和所述第二有源区相同导电类型的第二间隔条,其中所述第二间隔条为和所述第二有源区相邻并分离的附加有源区。
6.如权利要求1或5所述的集成电路结构,其中所述第一间隔条、所述第二间隔条、所述第一金属氧化物半导体器件以及所述第二金属氧化物半导体器件位于标准单元的边界中。
7.如权利要求6所述的集成电路结构,其中每个所述第一间隔条和所述第二间隔条与所述标准单元的三个边界邻接。
8.如权利要求5所述的集成电路结构,还包括位于所述第一有源区和所述第一间隔条之间并与所述第一有源区和所述第一间隔条邻接的第一浅沟槽隔离区,以及位于所述第二有源区和所述第二间隔条之间并与所述第二有源区和所述第二间隔条邻接的第二浅沟槽隔离区。
9.如权利要求1或5的集成电路结构,还包括分接头单元(tap),所述分接头单元包括用于阱区的引出区,其中所述第一有源区位于所述阱区内,并且其中所述分接头单元还包括与所述第一间隔条邻接并具有相同导电类型的第三间隔条。
10.如权利要求1或5所述的集成电路结构,还包括填充单元,所述填充单元包括伪栅极带和伪有源区,其中所述填充单元还包括与所述第一间隔条邻接并具有相同导电类型的第三间隔条。
11.一种集成电路结构,包括:
包括第一边界、第二边界、第三边界和第四边界的标准单元,其中所述第一边界和所述第二边界位于所述标准单元的相对端,以及所述第三边界和所述第四边界位于所述标准单元的相对端,并且其中所述标准单元包括:
半导体衬底;
位于所述半导体衬底中的第一有源区;
位于所述第一有源区上方的栅极带;
作为所述半导体衬底中附加有源区的第一间隔条,其中所述第一间隔条与全部的所述第三边界、部分的所述第一边界以及部分的所述第二边界邻接,并且其中所述第一间隔条和所述第一有源区属于第一导电类型;以及
位于所述半导体衬底中的第一绝缘区,其中所述第一绝缘区位于至少部分的所述第一有源区和至少部分的所述第一间隔条之间,并与至少部分的所述第一有源区和至少部分的所述第一间隔条邻接。
12.如权利要求11所述的集成电路结构,还包括:
位于所述半导体衬底中的第二间隔条,其中所述第二间隔条与全部的所述第四边界、部分的所述第一边界以及部分的所述第二边界邻接,并且其中所述第二间隔条和第二有源区属于和所述第一导电类型相反的第二导电类型;
位于所述半导体衬底中的二绝缘区,其中所述第二绝缘区位于至少部分的所述第二有源区和至少部分的所述第二间隔条之间,并与至少部分的所述第二有源区和至少部分的所述第二间隔条邻接;以及位于所述第一间隔条上方并与所述第一间隔条邻接的硅化物区。
13.如权利要求11所述的集成电路结构,还包括分接头单元,所述分接头单元包括与所述第一间隔条邻接并形成直线间隔条的第二间隔条。
14.如权利要求11所述的集成电路结构,还包括填充单元,所述填充单元包括:
伪栅极带;
伪有源区;以及
与所述第一间隔条邻接并形成直线间隔条的第二间隔条。
15.如权利要求11所述的集成电路结构,还包括:
位于所述半导体衬底中并具有和所述第一间隔条及所述第一有源区相同导电类型的第二有源区,其中所述第二有源区位于部分的所述第一间隔条和部分的所述第一有源区之间,并与部分的所述第一间隔条和部分的所述第一有源区邻接。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10100208P | 2008-09-29 | 2008-09-29 | |
US61/101,002 | 2008-09-29 | ||
US12/345,372 US7808051B2 (en) | 2008-09-29 | 2008-12-29 | Standard cell without OD space effect in Y-direction |
US12/345,372 | 2008-12-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101714557A true CN101714557A (zh) | 2010-05-26 |
CN101714557B CN101714557B (zh) | 2011-12-28 |
Family
ID=42056467
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2009101781229A Active CN101714557B (zh) | 2008-09-29 | 2009-09-27 | Y方向没有od间隙影响的标准单元 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7808051B2 (zh) |
CN (1) | CN101714557B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104733458A (zh) * | 2013-12-20 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Cmos反相器 |
CN110494978A (zh) * | 2017-04-14 | 2019-11-22 | 高通股份有限公司 | 采用电耦合源极区和电源轨来放宽相邻mos标准单元之间的源极-漏极端到端间距的金属氧化物半导体(mos)标准单元 |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8558278B2 (en) * | 2007-01-16 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained transistor with optimized drive current and method of forming |
US7943961B2 (en) * | 2008-03-13 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain bars in stressed layers of MOS devices |
JP5147654B2 (ja) | 2008-11-18 | 2013-02-20 | パナソニック株式会社 | 半導体装置 |
KR101606930B1 (ko) * | 2008-12-30 | 2016-03-28 | 주식회사 동부하이텍 | 반도체소자 및 그 제조방법 |
US8217469B2 (en) * | 2009-12-11 | 2012-07-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact implement structure for high density design |
US8426265B2 (en) | 2010-11-03 | 2013-04-23 | International Business Machines Corporation | Method for growing strain-inducing materials in CMOS circuits in a gate first flow |
US8901615B2 (en) * | 2012-06-13 | 2014-12-02 | Synopsys, Inc. | N-channel and P-channel end-to-end finfet cell architecture |
US8837192B2 (en) | 2012-10-19 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company Limited | N-bit rom cell |
US8701055B1 (en) * | 2012-12-07 | 2014-04-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Macro cell based process design kit for advanced applications |
US9123565B2 (en) * | 2012-12-31 | 2015-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Masks formed based on integrated circuit layout design having standard cell that includes extended active region |
US8759885B1 (en) | 2013-04-30 | 2014-06-24 | Freescale Semiconductor, Inc. | Standard cell for semiconductor device |
US8916441B2 (en) * | 2013-05-14 | 2014-12-23 | Globalfoundries Inc. | FinFET device and methods of fabrication |
US9419134B2 (en) | 2014-01-13 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain enhancement for FinFETs |
US9318476B2 (en) | 2014-03-03 | 2016-04-19 | Qualcomm Incorporated | High performance standard cell with continuous oxide definition and characterized leakage current |
US10068918B2 (en) | 2015-09-21 | 2018-09-04 | Globalfoundries Inc. | Contacting SOI subsrates |
US9577639B1 (en) * | 2015-09-24 | 2017-02-21 | Qualcomm Incorporated | Source separated cell |
CN114898790A (zh) * | 2016-01-29 | 2022-08-12 | 三星电子株式会社 | 用于选择性地执行隔离功能的半导体器件及其布局替代方法 |
US20170323902A1 (en) * | 2016-05-06 | 2017-11-09 | Globalfoundries Inc. | Method, apparatus, and system for improved cell design having unidirectional metal layout architecture |
US9871047B1 (en) * | 2017-01-20 | 2018-01-16 | United Microelectronics Corp. | Memory structure and a method for forming the same |
KR102285790B1 (ko) | 2017-07-04 | 2021-08-04 | 삼성전자 주식회사 | 필러 셀을 포함하는 집적 회로 |
US11106854B2 (en) * | 2018-08-21 | 2021-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transition cells for advanced technology processes |
US10909298B1 (en) * | 2020-04-15 | 2021-02-02 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Well contact cell with doped tap region separated from active region, and methods to form same |
US11527527B2 (en) * | 2020-05-21 | 2022-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tap cell, integrated circuit structure and forming method thereof |
US11803683B2 (en) * | 2021-01-28 | 2023-10-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of and system for manufacturing semiconductor device |
Family Cites Families (174)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4069094A (en) | 1976-12-30 | 1978-01-17 | Rca Corporation | Method of manufacturing apertured aluminum oxide substrates |
JPS551103A (en) | 1978-06-06 | 1980-01-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor resistor |
US4497683A (en) | 1982-05-03 | 1985-02-05 | At&T Bell Laboratories | Process for producing dielectrically isolated silicon devices |
US4631803A (en) | 1985-02-14 | 1986-12-30 | Texas Instruments Incorporated | Method of fabricating defect free trench isolation devices |
US4892614A (en) | 1986-07-07 | 1990-01-09 | Texas Instruments Incorporated | Integrated circuit isolation process |
JPH0640583B2 (ja) | 1987-07-16 | 1994-05-25 | 株式会社東芝 | 半導体装置の製造方法 |
US4946799A (en) | 1988-07-08 | 1990-08-07 | Texas Instruments, Incorporated | Process for making high performance silicon-on-insulator transistor with body node to source node connection |
JPH0394479A (ja) | 1989-06-30 | 1991-04-19 | Hitachi Ltd | 感光性を有する半導体装置 |
US5155571A (en) | 1990-08-06 | 1992-10-13 | The Regents Of The University Of California | Complementary field effect transistors having strained superlattice structure |
JP3019430B2 (ja) | 1991-01-21 | 2000-03-13 | ソニー株式会社 | 半導体集積回路装置 |
US5525828A (en) | 1991-10-31 | 1996-06-11 | International Business Machines Corporation | High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields |
US5338960A (en) | 1992-08-05 | 1994-08-16 | Harris Corporation | Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures |
US5461250A (en) | 1992-08-10 | 1995-10-24 | International Business Machines Corporation | SiGe thin film or SOI MOSFET and method for making the same |
US5273915A (en) | 1992-10-05 | 1993-12-28 | Motorola, Inc. | Method for fabricating bipolar junction and MOS transistors on SOI |
KR0147452B1 (ko) | 1993-11-30 | 1998-08-01 | 사토 후미오 | 불휘발성 반도체기억장치 |
KR950034754A (ko) | 1994-05-06 | 1995-12-28 | 윌리엄 이. 힐러 | 폴리실리콘 저항을 형성하는 방법 및 이 방법으로부터 제조된 저항 |
US5534713A (en) | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
US5479033A (en) | 1994-05-27 | 1995-12-26 | Sandia Corporation | Complementary junction heterostructure field-effect transistor |
US5447884A (en) | 1994-06-29 | 1995-09-05 | International Business Machines Corporation | Shallow trench isolation with thin nitride liner |
US6433382B1 (en) | 1995-04-06 | 2002-08-13 | Motorola, Inc. | Split-gate vertically oriented EEPROM device and process |
US5629544A (en) | 1995-04-25 | 1997-05-13 | International Business Machines Corporation | Semiconductor diode with silicide films and trench isolation |
US5783850A (en) | 1995-04-27 | 1998-07-21 | Taiwan Semiconductor Manufacturing Company | Undoped polysilicon gate process for NMOS ESD protection circuits |
US5955766A (en) | 1995-06-12 | 1999-09-21 | Kabushiki Kaisha Toshiba | Diode with controlled breakdown |
US5708288A (en) | 1995-11-02 | 1998-01-13 | Motorola, Inc. | Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method |
EP1008927A4 (en) | 1996-03-15 | 2007-04-18 | Hitachi Ltd | DISPLAY DEVICE AND WORKING METHOD FOR THE USE THEREOF |
DE69624107T2 (de) * | 1996-07-18 | 2003-06-05 | St Microelectronics Srl | Flash-EEPROM-Zelle mit einziger Polysiliziumschicht und Verfahren zur Herstellung |
TW335558B (en) | 1996-09-03 | 1998-07-01 | Ibm | High temperature superconductivity in strained SiSiGe |
US6399970B2 (en) | 1996-09-17 | 2002-06-04 | Matsushita Electric Industrial Co., Ltd. | FET having a Si/SiGeC heterojunction channel |
US5789807A (en) | 1996-10-15 | 1998-08-04 | International Business Machines Corporation | On-chip power distribution for improved decoupling |
US5811857A (en) | 1996-10-22 | 1998-09-22 | International Business Machines Corporation | Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications |
US5763315A (en) | 1997-01-28 | 1998-06-09 | International Business Machines Corporation | Shallow trench isolation with oxide-nitride/oxynitride liner |
US5714777A (en) | 1997-02-19 | 1998-02-03 | International Business Machines Corporation | Si/SiGe vertical junction field effect transistor |
US5906951A (en) | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
DE19720008A1 (de) | 1997-05-13 | 1998-11-19 | Siemens Ag | Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung |
US6027988A (en) | 1997-05-28 | 2000-02-22 | The Regents Of The University Of California | Method of separating films from bulk substrates by plasma immersion ion implantation |
US5894152A (en) | 1997-06-18 | 1999-04-13 | International Business Machines Corporation | SOI/bulk hybrid substrate and method of forming the same |
WO1998059365A1 (en) | 1997-06-24 | 1998-12-30 | Massachusetts Institute Of Technology | CONTROLLING THREADING DISLOCATION DENSITIES IN Ge ON Si USING GRADED GeSi LAYERS AND PLANARIZATION |
US6221709B1 (en) | 1997-06-30 | 2001-04-24 | Stmicroelectronics, Inc. | Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor |
US6096591A (en) | 1997-06-30 | 2000-08-01 | Advanced Micro Devices, Inc. | Method of making an IGFET and a protected resistor with reduced processing steps |
US6103599A (en) | 1997-07-25 | 2000-08-15 | Silicon Genesis Corporation | Planarizing technique for multilayered substrates |
US6495900B1 (en) | 1997-11-12 | 2002-12-17 | Micron Technology, Inc. | Insulator for electrical structure |
EP0923116A1 (en) | 1997-12-12 | 1999-06-16 | STMicroelectronics S.r.l. | Process for manufacturing integrated multi-crystal silicon resistors in MOS technology and integrated MOS device comprising multi-crystal silicon resistors |
US6100153A (en) | 1998-01-20 | 2000-08-08 | International Business Machines Corporation | Reliable diffusion resistor and diffusion capacitor |
US5972722A (en) | 1998-04-14 | 1999-10-26 | Texas Instruments Incorporated | Adhesion promoting sacrificial etch stop layer in advanced capacitor structures |
JP3265569B2 (ja) | 1998-04-15 | 2002-03-11 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6558998B2 (en) | 1998-06-15 | 2003-05-06 | Marc Belleville | SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit |
JP3403076B2 (ja) | 1998-06-30 | 2003-05-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6100204A (en) | 1998-07-28 | 2000-08-08 | Advanced Micro Devices, Inc. | Method of making ultra thin gate oxide using aluminum oxide |
US6387739B1 (en) | 1998-08-07 | 2002-05-14 | International Business Machines Corporation | Method and improved SOI body contact structure for transistors |
US6008095A (en) | 1998-08-07 | 1999-12-28 | Advanced Micro Devices, Inc. | Process for formation of isolation trenches with high-K gate dielectrics |
US6015993A (en) | 1998-08-31 | 2000-01-18 | International Business Machines Corporation | Semiconductor diode with depleted polysilicon gate structure and method |
JP2000132990A (ja) | 1998-10-27 | 2000-05-12 | Fujitsu Ltd | 冗長判定回路、半導体記憶装置及び冗長判定方法 |
US5965917A (en) | 1999-01-04 | 1999-10-12 | Advanced Micro Devices, Inc. | Structure and method of formation of body contacts in SOI MOSFETS to elimate floating body effects |
US6258664B1 (en) | 1999-02-16 | 2001-07-10 | Micron Technology, Inc. | Methods of forming silicon-comprising materials having roughened outer surfaces, and methods of forming capacitor constructions |
TW403969B (en) | 1999-04-09 | 2000-09-01 | United Microelectronics Corp | Method for manufacturing metal oxide semiconductor |
US6358791B1 (en) | 1999-06-04 | 2002-03-19 | International Business Machines Corporation | Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby |
US6362082B1 (en) | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
US6737710B2 (en) | 1999-06-30 | 2004-05-18 | Intel Corporation | Transistor structure having silicide source/drain extensions |
US6339232B1 (en) | 1999-09-20 | 2002-01-15 | Kabushika Kaisha Toshiba | Semiconductor device |
US6303479B1 (en) | 1999-12-16 | 2001-10-16 | Spinnaker Semiconductor, Inc. | Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts |
US7391087B2 (en) | 1999-12-30 | 2008-06-24 | Intel Corporation | MOS transistor structure and method of fabrication |
US6541343B1 (en) | 1999-12-30 | 2003-04-01 | Intel Corporation | Methods of making field effect transistor structure with partially isolated source/drain junctions |
US6255175B1 (en) | 2000-01-07 | 2001-07-03 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with minimized parasitic Miller capacitance |
TW503439B (en) | 2000-01-21 | 2002-09-21 | United Microelectronics Corp | Combination structure of passive element and logic circuit on silicon on insulator wafer |
US6475838B1 (en) | 2000-03-14 | 2002-11-05 | International Business Machines Corporation | Methods for forming decoupling capacitors |
US6396137B1 (en) | 2000-03-15 | 2002-05-28 | Kevin Mark Klughart | Integrated voltage/current/power regulator/switch system and method |
JP3504212B2 (ja) | 2000-04-04 | 2004-03-08 | シャープ株式会社 | Soi構造の半導体装置 |
US6420264B1 (en) | 2000-04-12 | 2002-07-16 | Ultratech Stepper, Inc. | Method of forming a silicide region in a Si substrate and a device having same |
US6420218B1 (en) | 2000-04-24 | 2002-07-16 | Advanced Micro Devices, Inc. | Ultra-thin-body SOI MOS transistors having recessed source and drain regions |
US6281059B1 (en) | 2000-05-11 | 2001-08-28 | Worldwide Semiconductor Manufacturing Corp. | Method of doing ESD protective device ion implant without additional photo mask |
DE10025264A1 (de) | 2000-05-22 | 2001-11-29 | Max Planck Gesellschaft | Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung |
JP2001338988A (ja) | 2000-05-25 | 2001-12-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
US6555839B2 (en) | 2000-05-26 | 2003-04-29 | Amberwave Systems Corporation | Buried channel strained silicon FET using a supply layer created through ion implantation |
KR100393205B1 (ko) | 2000-05-30 | 2003-07-31 | 삼성전자주식회사 | 자기정렬 콘택구조를 가진 메모리영역과 샐리사이디드된듀얼 게이트 구조의 로직영역이 병합된 mml 반도체소자 및 그 제조방법 |
JP3843708B2 (ja) | 2000-07-14 | 2006-11-08 | 日本電気株式会社 | 半導体装置およびその製造方法ならびに薄膜コンデンサ |
JP2002043576A (ja) | 2000-07-24 | 2002-02-08 | Univ Tohoku | 半導体装置 |
US6429061B1 (en) | 2000-07-26 | 2002-08-06 | International Business Machines Corporation | Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation |
FR2812764B1 (fr) | 2000-08-02 | 2003-01-24 | St Microelectronics Sa | Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu |
JP2002076287A (ja) | 2000-08-28 | 2002-03-15 | Nec Kansai Ltd | 半導体装置およびその製造方法 |
JP4044276B2 (ja) | 2000-09-28 | 2008-02-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6413802B1 (en) | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
KR100767950B1 (ko) | 2000-11-22 | 2007-10-18 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치 및 그 제조 방법 |
AU2002228779A1 (en) | 2000-12-04 | 2002-06-18 | Amberwave Systems Corporation | Cmos inverter circuits utilizing strained silicon surface channel mosfets |
US7206854B2 (en) * | 2000-12-11 | 2007-04-17 | General Instrument Corporation | Seamless arbitrary data insertion for streaming media |
US6414355B1 (en) | 2001-01-26 | 2002-07-02 | Advanced Micro Devices, Inc. | Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness |
US6894324B2 (en) | 2001-02-15 | 2005-05-17 | United Microelectronics Corp. | Silicon-on-insulator diodes and ESD protection circuits |
US6518610B2 (en) | 2001-02-20 | 2003-02-11 | Micron Technology, Inc. | Rhodium-rich oxygen barriers |
US6475869B1 (en) | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
US6646322B2 (en) | 2001-03-02 | 2003-11-11 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6603156B2 (en) | 2001-03-31 | 2003-08-05 | International Business Machines Corporation | Strained silicon on insulator structures |
US6867101B1 (en) | 2001-04-04 | 2005-03-15 | Advanced Micro Devices, Inc. | Method of fabricating a semiconductor device having a nitride/high-k/nitride gate dielectric stack by atomic layer deposition (ALD) and a device thereby formed |
US6645861B2 (en) | 2001-04-18 | 2003-11-11 | International Business Machines Corporation | Self-aligned silicide process for silicon sidewall source and drain contacts |
US6593181B2 (en) | 2001-04-20 | 2003-07-15 | International Business Machines Corporation | Tailored insulator properties for devices |
US6586311B2 (en) | 2001-04-25 | 2003-07-01 | Advanced Micro Devices, Inc. | Salicide block for silicon-on-insulator (SOI) applications |
JP2002329861A (ja) | 2001-05-01 | 2002-11-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6489684B1 (en) | 2001-05-14 | 2002-12-03 | Taiwan Semiconductor Manufacturing Company | Reduction of electromigration in dual damascene connector |
US6952040B2 (en) | 2001-06-29 | 2005-10-04 | Intel Corporation | Transistor structure and method of fabrication |
US6576526B2 (en) | 2001-07-09 | 2003-06-10 | Chartered Semiconductor Manufacturing Ltd. | Darc layer for MIM process integration |
US7138649B2 (en) | 2001-08-09 | 2006-11-21 | Amberwave Systems Corporation | Dual-channel CMOS transistors with differentially strained channels |
AU2002331077A1 (en) | 2001-08-13 | 2003-03-03 | Amberwave Systems Corporation | Dram trench capacitor and method of making the same |
US6690082B2 (en) | 2001-09-28 | 2004-02-10 | Agere Systems Inc. | High dopant concentration diffused resistor and method of manufacture therefor |
US6521952B1 (en) | 2001-10-22 | 2003-02-18 | United Microelectronics Corp. | Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection |
US6555883B1 (en) | 2001-10-29 | 2003-04-29 | Power Integrations, Inc. | Lateral power MOSFET for high switching speeds |
US6621131B2 (en) | 2001-11-01 | 2003-09-16 | Intel Corporation | Semiconductor transistor having a stressed channel |
US6703271B2 (en) | 2001-11-30 | 2004-03-09 | Taiwan Semiconductor Manufacturing Company | Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer |
US6657259B2 (en) | 2001-12-04 | 2003-12-02 | International Business Machines Corporation | Multiple-plane FinFET CMOS |
JP2003179157A (ja) | 2001-12-10 | 2003-06-27 | Nec Corp | Mos型半導体装置 |
US6657276B1 (en) | 2001-12-10 | 2003-12-02 | Advanced Micro Devices, Inc. | Shallow trench isolation (STI) region with high-K liner and method of formation |
US6600170B1 (en) | 2001-12-17 | 2003-07-29 | Advanced Micro Devices, Inc. | CMOS with strained silicon channel NMOS and silicon germanium channel PMOS |
FI119215B (fi) | 2002-01-31 | 2008-08-29 | Imbera Electronics Oy | Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli |
JP2003282726A (ja) | 2002-03-27 | 2003-10-03 | Nec Electronics Corp | 半導体装置及びその製造方法 |
US6784101B1 (en) | 2002-05-16 | 2004-08-31 | Advanced Micro Devices Inc | Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation |
JP4136452B2 (ja) | 2002-05-23 | 2008-08-20 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US7138310B2 (en) | 2002-06-07 | 2006-11-21 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
US6900521B2 (en) | 2002-06-10 | 2005-05-31 | Micron Technology, Inc. | Vertical transistors and output prediction logic circuits containing same |
US6812103B2 (en) | 2002-06-20 | 2004-11-02 | Micron Technology, Inc. | Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects |
US6680240B1 (en) | 2002-06-25 | 2004-01-20 | Advanced Micro Devices, Inc. | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
US6617643B1 (en) | 2002-06-28 | 2003-09-09 | Mcnc | Low power tunneling metal-oxide-semiconductor (MOS) device |
US6740535B2 (en) | 2002-07-29 | 2004-05-25 | International Business Machines Corporation | Enhanced T-gate structure for modulation doped field effect transistors |
US6686247B1 (en) | 2002-08-22 | 2004-02-03 | Intel Corporation | Self-aligned contacts to gates |
US6969618B2 (en) | 2002-08-23 | 2005-11-29 | Micron Technology, Inc. | SOI device having increased reliability and reduced free floating body effects |
JP4030383B2 (ja) | 2002-08-26 | 2008-01-09 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
DE10240423B4 (de) | 2002-09-02 | 2007-02-22 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterelement mit einem Feldeffekttransistor und einem passiven Kondensator mit reduziertem Leckstrom und einer verbesserten Kapazität pro Einheitsfläche und Verfahren zu dessen Herstellung |
US6573172B1 (en) | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
US6828211B2 (en) | 2002-10-01 | 2004-12-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control |
US6730573B1 (en) | 2002-11-01 | 2004-05-04 | Chartered Semiconductor Manufacturing Ltd. | MIM and metal resistor formation at CU beol using only one extra mask |
US7022561B2 (en) | 2002-12-02 | 2006-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS device |
US6734527B1 (en) | 2002-12-12 | 2004-05-11 | Advanced Micro Devices, Inc. | CMOS devices with balanced drive currents based on SiGe |
US6720619B1 (en) | 2002-12-13 | 2004-04-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices |
US6919233B2 (en) | 2002-12-31 | 2005-07-19 | Texas Instruments Incorporated | MIM capacitors and methods for fabricating same |
US6924181B2 (en) | 2003-02-13 | 2005-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd | Strained silicon layer semiconductor product employing strained insulator layer |
US6921913B2 (en) | 2003-03-04 | 2005-07-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel transistor structure with lattice-mismatched zone |
US6794764B1 (en) | 2003-03-05 | 2004-09-21 | Advanced Micro Devices, Inc. | Charge-trapping memory arrays resistant to damage from contact hole information |
US6845034B2 (en) | 2003-03-11 | 2005-01-18 | Micron Technology, Inc. | Electronic systems, constructions for detecting properties of objects, and assemblies for identifying persons |
US6900502B2 (en) | 2003-04-03 | 2005-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel on insulator device |
US6762448B1 (en) | 2003-04-03 | 2004-07-13 | Advanced Micro Devices, Inc. | FinFET device with multiple fin structures |
US6882025B2 (en) | 2003-04-25 | 2005-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained-channel transistor and methods of manufacture |
US6867433B2 (en) | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
US7045849B2 (en) | 2003-05-21 | 2006-05-16 | Sandisk Corporation | Use of voids between elements in semiconductor structures for isolation |
US6936506B1 (en) | 2003-05-22 | 2005-08-30 | Advanced Micro Devices, Inc. | Strained-silicon devices with different silicon thicknesses |
US7081395B2 (en) | 2003-05-23 | 2006-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials |
US6982433B2 (en) | 2003-06-12 | 2006-01-03 | Intel Corporation | Gate-induced strain for MOS performance improvement |
US20040266116A1 (en) | 2003-06-26 | 2004-12-30 | Rj Mears, Llc | Methods of fabricating semiconductor structures having improved conductivity effective mass |
US20040262683A1 (en) | 2003-06-27 | 2004-12-30 | Bohr Mark T. | PMOS transistor strain optimization with raised junction regions |
US20050012087A1 (en) | 2003-07-15 | 2005-01-20 | Yi-Ming Sheu | Self-aligned MOSFET having an oxide region below the channel |
US7078742B2 (en) | 2003-07-25 | 2006-07-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel semiconductor structure and method of fabricating the same |
US6940705B2 (en) | 2003-07-25 | 2005-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor with enhanced performance and method of manufacture |
US6936881B2 (en) | 2003-07-25 | 2005-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor that includes high permittivity capacitor dielectric |
US6891192B2 (en) | 2003-08-04 | 2005-05-10 | International Business Machines Corporation | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
US6830962B1 (en) | 2003-08-05 | 2004-12-14 | International Business Machines Corporation | Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes |
US7101742B2 (en) | 2003-08-12 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors and methods of manufacture |
US20050035410A1 (en) | 2003-08-15 | 2005-02-17 | Yee-Chia Yeo | Semiconductor diode with reduced leakage |
US7112495B2 (en) | 2003-08-15 | 2006-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
US20050035369A1 (en) | 2003-08-15 | 2005-02-17 | Chun-Chieh Lin | Structure and method of forming integrated circuits utilizing strained channel transistors |
US7071052B2 (en) | 2003-08-18 | 2006-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resistor with reduced leakage |
US6939814B2 (en) | 2003-10-30 | 2005-09-06 | International Business Machines Corporation | Increasing carrier mobility in NFET and PFET transistors on a common wafer |
US6872610B1 (en) | 2003-11-18 | 2005-03-29 | Texas Instruments Incorporated | Method for preventing polysilicon mushrooming during selective epitaxial processing |
US7662689B2 (en) | 2003-12-23 | 2010-02-16 | Intel Corporation | Strained transistor integration for CMOS |
US20050186722A1 (en) | 2004-02-25 | 2005-08-25 | Kuan-Lun Cheng | Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions |
US7224068B2 (en) | 2004-04-06 | 2007-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stable metal structure with tungsten plug |
US7115974B2 (en) | 2004-04-27 | 2006-10-03 | Taiwan Semiconductor Manfacturing Company, Ltd. | Silicon oxycarbide and silicon carbonitride based materials for MOS devices |
US7220630B2 (en) | 2004-05-21 | 2007-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for selectively forming strained etch stop layers to improve FET charge carrier mobility |
US20050266632A1 (en) | 2004-05-26 | 2005-12-01 | Yun-Hsiu Chen | Integrated circuit with strained and non-strained transistors, and method of forming thereof |
US7064066B1 (en) | 2004-12-07 | 2006-06-20 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode |
KR100585180B1 (ko) | 2005-02-21 | 2006-05-30 | 삼성전자주식회사 | 동작 전류가 개선된 반도체 메모리 소자 및 그 제조방법 |
US7164163B2 (en) | 2005-02-22 | 2007-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained transistor with hybrid-strain inducing layer |
US7470943B2 (en) | 2005-08-22 | 2008-12-30 | International Business Machines Corporation | High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same |
US20070078712A1 (en) * | 2005-09-30 | 2007-04-05 | Yahoo! Inc. | Systems for inserting advertisements into a podcast |
JP2007311491A (ja) | 2006-05-17 | 2007-11-29 | Toshiba Corp | 半導体集積回路 |
US8558278B2 (en) | 2007-01-16 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained transistor with optimized drive current and method of forming |
WO2009032953A2 (en) * | 2007-09-04 | 2009-03-12 | Tapioca Mobile, Inc. | Delivering merged advertising and content for mobile devices |
US7943961B2 (en) | 2008-03-13 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain bars in stressed layers of MOS devices |
US20100169458A1 (en) * | 2008-12-31 | 2010-07-01 | David Biderman | Real-Time or Near Real-Time Streaming |
US8165343B1 (en) * | 2011-09-28 | 2012-04-24 | Unicorn Media, Inc. | Forensic watermarking |
-
2008
- 2008-12-29 US US12/345,372 patent/US7808051B2/en active Active
-
2009
- 2009-09-27 CN CN2009101781229A patent/CN101714557B/zh active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104733458A (zh) * | 2013-12-20 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Cmos反相器 |
CN104733458B (zh) * | 2013-12-20 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | Cmos反相器 |
CN110494978A (zh) * | 2017-04-14 | 2019-11-22 | 高通股份有限公司 | 采用电耦合源极区和电源轨来放宽相邻mos标准单元之间的源极-漏极端到端间距的金属氧化物半导体(mos)标准单元 |
Also Published As
Publication number | Publication date |
---|---|
US7808051B2 (en) | 2010-10-05 |
US20100078725A1 (en) | 2010-04-01 |
CN101714557B (zh) | 2011-12-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101714557B (zh) | Y方向没有od间隙影响的标准单元 | |
CN101800228B (zh) | 半导体装置 | |
US7902600B2 (en) | Metal oxide semiconductor device | |
KR930001899B1 (ko) | 반도체 장치 | |
US7485925B2 (en) | High voltage metal oxide semiconductor transistor and fabricating method thereof | |
US8704300B1 (en) | Semiconductor device and fabricating method thereof | |
CN101339947A (zh) | 半导体器件 | |
US10043716B2 (en) | N-well/P-well strap structures | |
US8809905B2 (en) | Vertical BJT and SCR for ESD | |
US20130161739A1 (en) | Dummy gate for a high voltage transistor device | |
JP2007116049A (ja) | 半導体装置 | |
US20130161740A1 (en) | Lateral High-Voltage Transistor with Buried Resurf Layer and Associated Method for Manufacturing the Same | |
CN100563027C (zh) | 高电压金属氧化物半导体装置 | |
CN101673711A (zh) | 半导体集成电路器件及其制造方法 | |
US8237201B2 (en) | Layout methods of integrated circuits having unit MOS devices | |
CN101379614B (zh) | 用于形成绝缘体上半导体(soi)体接触器件的方法和设备 | |
CN103296063A (zh) | 用于高电压mos晶体管的装置和方法 | |
US8723256B1 (en) | Semiconductor device and fabricating method thereof | |
TW201840003A (zh) | 具有可調整臨界電壓之高壓空乏型mos元件及其製造方法 | |
US9012979B2 (en) | Semiconductor device having an isolation region separating a lateral double diffused metal oxide semiconductor (LDMOS) from a high voltage circuit region | |
US8283726B2 (en) | System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors | |
TWI312192B (en) | Semiconductor device and manufacture method thereof | |
US20120261738A1 (en) | N-Well/P-Well Strap Structures | |
CN102208449A (zh) | 一种soi体接触mos晶体管及其形成方法 | |
US8476619B2 (en) | Semiconductor device and method for fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |