CN101656250A - 具有立体匹配互连板的紧密封装半导体芯片 - Google Patents

具有立体匹配互连板的紧密封装半导体芯片 Download PDF

Info

Publication number
CN101656250A
CN101656250A CN200910165254A CN200910165254A CN101656250A CN 101656250 A CN101656250 A CN 101656250A CN 200910165254 A CN200910165254 A CN 200910165254A CN 200910165254 A CN200910165254 A CN 200910165254A CN 101656250 A CN101656250 A CN 101656250A
Authority
CN
China
Prior art keywords
chip
interconnected plate
semiconductor packages
semiconductor
contact zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200910165254A
Other languages
English (en)
Other versions
CN101656250B (zh
Inventor
刘凯
孙明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chongqing Wanguo Semiconductor Technology Co., Ltd.
Original Assignee
Alpha and Omega Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha and Omega Semiconductor Inc filed Critical Alpha and Omega Semiconductor Inc
Publication of CN101656250A publication Critical patent/CN101656250A/zh
Application granted granted Critical
Publication of CN101656250B publication Critical patent/CN101656250B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H01L2224/4101—Structure
    • H01L2224/4103—Connectors having different sizes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

一个半导体封装，是对于一个电路基底上的两个相邻半导体芯片的封装。芯片在沿着它们的纵向边缘分开，并有一个内部芯片间距。一个立体匹配电连接连接第二芯片的顶部金属接触区和第一芯片的底部表面，立体匹配电连接适配表面之间的立体差，立体匹配电连接包括：a)一个L形电路路径，该路径是电路基底的一部分，从第一芯片的一条纵向边缘横向延伸并且将一个中间接触区靠近第二芯片的一条纵向边缘。b)一个互联板连接第二芯片的顶部金属接触区面积和中间接触区，适配两个接触面的立体高度差。因此，半导体封装减少了芯片横向边缘之间的直接横向电路路径的内部芯片间距。

Description

具有立体匹配互连板的紧密封装半导体芯片
技术领域
本发明涉及电子系统封装领域，特别涉及一种半导体芯片的物理级封装。
背景技术
本发明与以下专利申请有关：
由Lei Shi等人申请的美国专利申请号11/906,136“具有桥连接板互连接的半导体封装”，公开号US20080087992，此后以美国申请11/906136称呼；
由Ming Sun等人申请的美国专利申请号11/799,467“具有凹陷型互连板的半导体封装”，此后以美国申请11/799467称呼。
由于功率金属氧化物半导体场效应晶体(metal-oxide-semiconductorfield effect transistor，简称MOSFET)器件的高集成密度、极低的静态漏电流和不断改进的功率处理能力，它们被广泛的用在功率电子产品中，例如开关式电源和电源转换器，功率MOSFET器件的一个重要优势是其封装尺寸随着消费者的需求的驱使而不断减小，尤其体现在便携式电子设备中。
发明内容
本发明公开了一种半导体封装，其包括：
一个电路基底；
两个半导体芯片，其底部表面与电路基底的上面电连接，所述半导体芯片进一步包括：
第一芯片的边界为第一芯片第一纵向边缘和第一芯片第二纵向边缘，第一芯片第一横向边缘和第一芯片第二横向边缘；第二芯片的边界为第二芯片第一纵向边缘和第二芯片第二纵向边缘，第二芯片第一横向边缘和第二芯片第二横向边缘；第一芯片和第二芯片位置邻近并且是相互独立的，沿着它们各自第一芯片第二纵向边缘和第二芯片第一纵向边缘，设有内部芯片间距；
一个立体匹配电连接，连接第二芯片表面上的顶部金属接触区和第一芯片底部表面，用来适配表面之间的高度差异，所述立体匹配电连接进一步包括：
a)一个电路路径，该路径是电路基底的一部分，作为第一芯片的底部表面到电路基底上的中间接触区的电路径，所述的电路径进一步包括L形路径，该路径从第一芯片第二横向边缘靠近第一芯片第二纵向边缘的位置横向延伸，将中间接触区靠近第二芯片第二横向边缘；
b)一个互联板连接第二芯片顶部金属接触区和中间接触区，所述中间接触为三维的，用来适配接触区之间的立体高度差；
因而，半导体封装减少了第一芯片第二纵向边缘和第二芯片第一纵向边缘之间的横向电路路径的内部芯片间距。
作为上述的半导体封装的一个优选实施方式，所述互联板还包括一个桥部分，设置在桥部分两边的谷部分，设置在谷部分、桥部分或平面之间连接部分两边的平面部分。
作为上述的半导体封装的一个优选实施方式，所述互联板还包括用来与第二芯片顶部金属接触区接触的凹点。
作为上述的半导体封装的另一个优选实施方式，至少有一个所述第一芯片和第二芯片还包括至少一个额外的顶部金属接触区，相应地，半导体封装还包括一个额外的互联板连接额外顶部金属接触区和电路基底，该互联板是三维的用来适配他们之间存在的立体高度差。
作为上述的半导体封装的另一个优选实施方式，还包括一个桥部分，设置在桥部分两边的谷部分，设置在谷部分、桥部分或平面之间连接部分两边的平面部分，裸露在模塑料外的互联板的顶部表面为桥部分，用来散热。
作为上述的半导体封装的一个优选实施方式，所述电路基底设有第一芯片垫和第二芯片垫分别用来定位和连接第一芯片和第二芯片，相应地，L形路径是从第一芯片垫和第一芯片的上表面的顶部金属接触区的延伸，通过一个互联板与引线框引脚连接。
作为上述的半导体封装的另一个优选实施方式，大部分用模塑料封装，仅暴露顶部表面的互联板用来散热。
作为上述的半导体封装的另一个优选实施方式，所述电路基底是绝缘衬底，该绝缘衬底设有一个第一导电表面和一个第二导电表面分别用来定位和连接所述第一芯片和所述第二芯片，相应地，所述L形路径是从第一导电表面延伸出来的导电电路路径。
作为上述的半导体封装的一个更加优选实施方式，所述的第一芯片和第二芯片都是MOSFET器件，它们的底表面分别漏接触，他们的顶部表面分别为金属源接触和金属栅接触，以立体匹配电连接方式连接第二芯片的金属源接触区和第一芯片的漏接触区，不需要倒装晶片工艺。MOSFET的栅通过互联线或互联板连接电路基底。
本发明还提供了一种有效连接多个、独立和三维互联板的方法，每个都是设定好尺寸设置在具有一对连接半导体顶部的匹配电路基底上，该方法包括：
a)制作一个多板载体框，具有多个互联板完整的支撑和多个临时支撑成分；
b)通过破坏临时支撑成分将独立的互联板从多个载体框中分离出来；
c)将每个互联板设置在设配电路基底上；每个互联板进一步包括一个从半导体芯片顶部到中间接触区的互联板，其中的中间接触区包括从其他半导体芯片底部延伸出来的L形电路路径。
作为上述的制作方法的一个改进实施方式，制作多板载体边框进一步包括用一个样板刀三维制作互联板。
作为上述的制作方法的一个优选实施方式，分开多板载体边框还包括用冲孔工具将其分开。
作为上述的制作方法的一个优选实施方式，分开多板载体框还包括分开每个电路基底上的相互独立的互联板，于此同时将独立互联板从多板载体边框中分开。
作为上述的制作方法的一个优选实施方式，将每个互联板设置到匹配电路基底上的同时用多个顶部支撑板。
作为上述方法的一个优选实施方式，进一步包括封装至少电路基底的一部分，多个半导体芯片和互联板。
本发明的这些方面、他们的很多实施例以及本发明描述的其他部分将给本领域技术人员做进一步说明。
本发明的半导体封装减少了芯片横向边缘之间的直接横向电路路径的内部芯片间距。
附图说明
参考所附附图，以更加充分的描述本发明的实施例。然而，所附附图仅用于说明和阐述，并不构成对本发明范围的限制。
图1是一组相连的低压(low-side，LS)和高压(high-side，HS)功率MOSFET电路结构图；
图2是现有技术同封装半导体芯片引线框，本发明中的LS和HS功率MOSFET的互联键合线与之对应；
图3A是本发明在引线框中的同封装半导体芯片，用立体匹配互联板进行LS和HS功率MOSFET互联；
图3B是图3A的透视图；
图4是本发明同封装半导体芯片在引线框中对应的LS和HS功率MOSFET用立体匹配互联板进行全封装互联。
图5和图3B相同，除了每个立体匹配互联板还包括微凹形用来连接对应的顶部金属接触区；
图6A与图3A相同，但是去掉了立体连接板和互联线，更清楚的看到L形路线和引线框的中间接触区；
图6B是多板载体框架用来有效的将多个、分离的和三维成型立体连接板连接到上面有连接的半导体芯片的适配电路基底上。
图6C是顶视图，用来说明用图6B中多板载体边框连接立体互联板；
图6D是图6C的透视图，使半导体芯片和立体互联板浮在上面，露出引线框，半导体芯片和立体匹配互联板。
具体实施方式
上述和下述之说明以及附图仅仅用于集中描述本发明的一个或多个实施例以及若干可选功能和/或可选实施例。这些描述和附图仅做阐述之用而非限制本发明。因此，本领域的技术人员可以轻易的对本发明作出修改、变形和替换。然而这些修改、变形和替换应该认为仍落在本发明的范围之内。
图1是一组相连的低压(low-side，LS)和高压(high-side，HS)功率MOSFET电路结构图。低压(LS)的源1a接地，一般情况下，高压(HS)的漏极2c直接或间接的与电源正极相连。低压(LS)漏极1c与高压(HS)源极2c连接。本领域的技术人员知道，通常选择性的给低压(LS)的栅极1b和高压(HS)的栅极2b加高压使低压(LS)MOSFET1和高压(HS)MOSFET2导通，这样的拓扑结构存在于很多整流器和调节器中。
低压(LS)MOSFET 1和高压(HS)MOSFET 2制造简单并且成本低，与之对应的相关制造半导体芯片，器件的漏极接触通常位于底部衬底表面，其源极接触通常占据衬底顶部表面，其栅极接触占据衬底顶部表面的一小部分。这样，没有复杂昂贵的倒装芯片工艺，图2描述了已有技术中，对于低压(LS)MOSFET 1和高压(HS)MOSFET 2的半导体封装5的顶视图，如图，分别为低压(LS)芯片10和高压(HS)芯片20、引线框8，因此，LS芯片10设有一个LS芯片顶部金属源极接触区10a，一个LS芯片顶部金属栅极接触区10b和一个LS芯片底部金属漏极接触区10c，类似的，HS芯片设有一个HS芯片顶部金属源极接触区20a，一个HS芯片顶部金属栅极接触区20b和一个HS芯片底部金属漏极接触区20c。注意LS芯片10的边缘分别为第一LS芯片纵向边缘11，第二LS芯片纵向边缘13，第一LS芯片横向边缘12和第二LS芯片横向边缘14，类似的，HS芯片20的边缘分别为第一HS芯片纵向边缘21，第二HS芯片纵向边缘23，第一HS芯片横向边缘22和第二HS芯片横向边缘24。引线框8包括大量的物理和电学上分离的引线部分8a，8b(进一步包括8f)，8c，8d和8e。引线部分8a-8e可能但不是必需是共面。底部表面，例如，LS芯片10和HS芯片20的漏极接触区分别电连接到引线部分8a和引线部分8b。LS芯片顶部金属源极接触区10a通过横向LS终端连接线16连接引线部分8e，LS芯片顶部金属栅极接触区10b通过横向连接线9a连接引线部分8c。HS芯片顶部金属栅极接触区20b通过纵向连接线9b连接引线部分8d。LS芯片底部金属漏极接触区10c电连接到引线部分8a的顶部表面，横向LS-HS互联线18，连接引线部分8a和HS芯片顶部金属源极接触区20a，从而是实现LS芯片底部金属漏极接触区10c和HS芯片顶部金属源极接触区20a之间所需的连接，最后用密封材料6封装部分或整个的LS芯片10和HS芯片20，仅露出引线部分8ah8f外围部分用于外部的连接。
和封装有关的一个重要参数为内部芯片间距IDA，它是指第二LS芯片纵向边缘13和第一LS芯片横向边缘12。内部芯片间距IDA制约了已有技术中半导体封装5的横向方向的最小封装尺寸。对于给定的封装尺寸，内部芯片间距IDA限制了芯片的尺寸，因而增加了器件的导通电阻。下面已有的基本参数限定了内部芯片间距IDA的对应的基本最小值：
最小横向芯片-引线框边缘A1，是指第二LS芯片纵向边缘13和其最近的引线框部分8a纵向边缘之间的横向间距。
最小横向芯片-引线框边缘A2，是指第一HS芯片纵向边缘21和其最近的引线框部分8b纵向边缘之间的横向间距。
最小横向引线框-引线框间距A3，是指引线框部分8a和引线框部分8b之间的横向间距。
关系：
IDA～A1+A+A3，
横向LS-HS互连线18的实施使得横向芯片-引线框边缘A1和横向引线框-引线框间距A3大于他们各自的基本最小值，因为产品设备的互连线对于地互连端规定了更高的横向芯片-引线框边缘A1，对于最小需要的互联环支撑物规定了更大的横向引线框-引线框间距A3。
为了减小内部芯片间距IDA，从而相应减小现有技术中半导体封装5沿横向方向的尺寸，图3A和其透视图图3B描述了本发明带有一个内部芯片间距IDB的半导体封装50。图2所示的横向LS-HS互联线18被一个立体匹配电连接所取代，该电连接用来连接HS芯片顶部金属源极20a和LS芯片底部金属漏极10c，这样方便适应20a和10c表面之间的立体差。具体来说，立体匹配电连接包含如下：
一个L形引线框路径54是引线部分8a的一部分，因为电路径是从LS芯片底部金属漏极接触区10c到引线框部分8a上面的裸露的中间接触区52。L形引线框路径54从靠近第二LS芯片横向边缘14的第二LS芯片纵向边缘13横向延伸出来，使中间接触区52靠近第二HS芯片横向边缘24。
一个立体互联板56以中间接触区52连接HS芯片顶部金属源极20a，立体互联板56进一步三维结构连接从而适应20a和52表面立体差。
下面是规定内部芯片间距IDB基本最小值的基本参数：
最小横向芯片-引线框边缘B1，是指第二LS芯片纵向边缘13和其最近的引线部分8a的纵向边缘之间的间距。
最小横向芯片-引线框边缘B2，是指第一HS芯片纵向边缘21和其最近的引线部分8a的纵向边缘之间的间距。
最小横向引线边框-引线边框之间的间距B3，是指引线边框部分8a和引线边框部分8b之间的横向间距。
其关系为：
IDB＝B1+B2+B3，
L形引线框路径54和立体互联板56不再需要横向芯片-引线框边缘B1和横向引线框-引线框B3间距大于他们各自的基本最小值，因而本发明有效的减小了内部芯片间距，如下：
IDB＜IDA
减小的内部芯片间距IDB使元件包装尺寸减小，二者取其一，对于相同的封装尺寸，LS芯片10和HS芯片20可以做大，从而减小导通电阻。
进一步注意到，将中间接触区52靠近HS芯片横向边缘24，引线框8a的L形引线框路径54起重要的作用，由于本发明减小了内部芯片间距和相应的第二LS芯片纵向边缘13和第一HS芯片纵向边缘21之间的横向电路路径的半导体封装尺寸。同样的，已有半导体封装技术中的横向LS终端连线16也被本发明半导体封装50中的立体互联板58所代替，具有减小寄生阻抗的优点，所述的代替不是本发明减小内部芯片的主要部分。用互联板56取代图2中的连线18减小了高压芯片20和低压芯片10之间的感应系数。
图4描述了本发明半导体封装50的另一个实施例，除了立体板56和58，其余的封装互联也是用立体互联板来完成。具体来讲，一个立体互联板60用来连接LS芯片顶部金属栅极接触区10b和引线框8c，一个立体互联板62用来连接HS芯片顶部金属栅极接触区20b到引线框8d。本领域的技术人员现在应该更清楚的知道，立体互联板56和立体互联板58还包括一个桥部分，桥部分任何一侧的谷部分，谷部分、桥部分或平面之间连接部分的任何一侧平面部分，US Application 11、906，136中有进一步详述。本发明的半导体封装50可以大部分封装于密封材料6中，仅留下互联板的桥部分用来散热。同样的，如图5所描述的，立体互联板56和58其中一个或者都可以进一步包括接触凹点70和72用来分别连接LS芯片顶部金属源接触区10a和HS芯片顶部金属源接触区20a，US Application 11/799,467有进一步的描述。
图6A和图3A相同，只是移去了立体互联板56、58和连线9a、9b，从而更清楚的显示L型引线框路径54和引线框8a中间接触区52，为了避免多余模糊的细节，这里没有显示引线框8a和8b上的用于设置连接LS芯片10和HS芯片20的大量的芯片垫。
现在本技术领域的技术人员应该知道，一般而言，引线框8可以在本发明半导体封装范围内被大量其他种类的电路基底所取代，例如，印刷电路板可以取代引线框8。印刷电路板可以包括一个绝缘衬底，一个导电表面和一个导电表面分别用于设置和连接LS芯片10和HS芯片20。相应地，L型引线框路径54由导电表面延伸出来的一个导电电路路径构成。
图6B到图6D描述了一个多板载体边框73和与此相关的有效连接多个，单个和三维的立体互联板56、58、60和62到上面有半导体芯片的匹配电路基底上。这样，匹配电路基底为引线框8，设置在上面的半导体芯片为LS芯片10和HS芯片20。
如图6B所示，一个多板载体边框73由多个互联板56、58、60和62、大量集成连接杆74和76构成，更为细化，互联板可进一步与其他连接棒相互连接，制作多板载体边框73进一步包括上面的三维成形互联板，接着，用插枝连接杆74和76将独立的互联板56、58、60和62从多板载体边框73中隔离。可以通过冲压工具将其分开，然后每个互联板可以用真空工具将其定位在适配电路基底上，细化工艺步骤，互联板可独立和同时附着在匹配电路基底上。另外一个工艺细化，每个电路基底上的独立互联板可以左置放置在一起分开多板载体边框，然后将每个互联板设置到适配的电路基底后，每个电路基底上的单个互联板相互分开。最后，匹配电路基底和其封装半导体芯片、互联板用模塑料封装。
在本发明的内容中，每个互联板进一步包括半导体芯片顶部到中间接触区的互联板连接部分，中间接触区包括L形由从其他半导体芯片下面延伸出来的电路路径。图6c是顶视图描述用图6B的多板载体边框连接的多个立体互联板56、58、60和62，图6D是图6C的透视图，将半导体芯片10，20和立体互联板56，58，60和62向上浮动进一步露出边框8、半导体芯片、L形边框路径54和立体互联板。
现在本领域的技术人员应该了解，所描述的许多实例通过简单的修改也可用到其他具体应用上，虽然上面的描述了很多特征，但是其特征并不构成对本发明范围的限制。仅仅是提供本发明相关实例的说明。例如，本发明半导体封装系统预期用到各种各样的半导体芯片上，而不仅仅是本发明所描述的金属氧化物半导体(MOSFET)芯片中。
在描述和图形中，参照具体的结构给出了大量的实施例。本技术领域的技术人员应该知道本发明可以应用到其他实施方式上，并且其他实施方式的实施不需要再经过试验。本专利文献的目的在于本发明的范围不仅仅限于上述描述的具体实施例，而是为了说明以下权利要求，在权利要求范围内，对等值含义和范围做出的部分或全部修改，都被认为包含在本发明的精神和范围内。

Claims (23)

1、一种半导体封装，其特征在于，包括：
一个电路基底；
多个半导体芯片，所述半导体芯片的底部表面与上面的电路基底是电连接，所述半导体芯片进一步包括：
第一芯片的边界为第一芯片第一纵向边缘和第一芯片第二纵向边缘，另外加上第一芯片第一横向边缘和第一芯片第二横向边缘；
第二芯片的边界为第二芯片第一纵向边缘和第二芯片第二纵向边缘，另外加上第二芯片第一横向边缘和第二芯片第二横向边缘；
所述第一芯片和第二芯片位置邻近并且是独立的，沿着它们各自第一芯片第二纵向边缘和第一芯片第一纵向边缘，设有内部芯片间距；
一个立体匹配电连接，连接第二芯片表面上的顶部金属接触区和第二芯片底部表面，用来适配表面之间的差异，所述立体匹配电连接进一步包括：
a)一个电路路径方式，该路径是电路基底的一部分，作为第一芯片的底部表面到电路基底上的中间接触区的电路径，所述的电路径方式由L形路径从第一芯片第二横向边缘靠近第一芯片第二纵向边缘的位置横向延伸，将中间接触区靠近第二芯片第二横向边缘；
b)一个互联板连接第二芯片顶部金属接触区和中间接触区，所述中间接触为三维的，用来适配接触区之间的立体高度差；
因而，半导体封装减少了第一芯片第二纵向边缘和第二芯片第一纵向边缘之间的横向电路路径的内部芯片间距。
2、根据权利要求1所述的半导体封装，其特征在于，所述互联板还包括一个桥部分，设置在桥部分两边的谷部分，设置在谷部分、桥部分或平面之间连接部分两边的平面部分。
3、根据权利要求1所述的半导体封装，其特征在于，所述互联板还包括用来与顶部金属接触区接触的凹点。
4、根据权利要求1所述的半导体封装，其特征在于，至少有一个所述第一芯片和第二芯片还包括至少一个额外的顶部金属接触区，相应地，半导体封装还包括一个额外的互联板连接额外顶部金属接触区和电路基底，该互联板是三维的用来适配他们之间存在的立体高度差。
5、根据权利要求1所述的半导体封装，其特征在于，所述电路基底是一个引线框，该引线框还包括第一芯片垫和第二芯片垫用来分别定位和连接所述的第一芯片和所述的第二芯片，相对应的，所述L形路径是所述第一芯片垫的延伸。
6、根据权利要求5所述的半导体封装，其特征在于，用互联板将第一芯片上表面的顶部金属接触区与引线框引脚电连接。
7、根据权利要求6所述的半导体封装，其特征在于，还包括一个模塑料，所述半导体封装大部分封装在模塑料中，第一芯片上面的互联板顶部表面露出模塑料用来散热。
8、根据权利要求7所述的半导体封装，其特征在于，第一芯片上面的互联板还包括一个桥部分，设置在桥部分两边的谷部分，设置在谷部分、桥部分或平面之间连接部分两边的平面部分，互联板裸露的顶部表面为桥部分一个部分。
9、根据权利要求7所述的半导体封装，其特征在于，所述电路基底是印刷电路板，还包括绝缘衬底，第一导电表面和第一导电表面2分别用来定位和连接所述第一芯片和所述第二芯片，相应地，所述L形路径是从第一导电表面延伸出来的导电电路路径。
10、根据权利要求1所述的半导体封装，其特征在于，所述的第一芯片和第二芯片都是MOSFET器件，它们的底表面分别漏接触，他们的顶部表面分别为金属源接触和金属栅接触，立体匹配电连接连接第二芯片的金属源接触区和第一芯片的漏接触区，不需要倒装晶片工艺。
11、根据权利要求10所述的半导体封装，其特征在于，所述第一芯片是低压金属氧化物半导体场效应晶体管(MOSFET)器件，所述第二芯片是高压金属氧化物半导体场效应晶体管(MOSFET)器件
12、根据权利要求10所述的半导体封装，其特征在于，所述MOSFET的栅通过互联线连接电路基底。
13、根据权利要求10所述的半导体封装，其特征在于，所述MOSFET的栅通过互联板连接电路基底。
14、根据权利要求1所述的半导体封装，其特征在于，所述第一芯片表面上的顶部金属接触区通过互联板连接电路基底。
15、根据权利要求1所述的半导体封装，其特征在于，还包括一个模塑料覆盖至少电路基底的一个部分，多种半导体芯片和立体匹配电连接。
16、一种有效连接多个、独立和三维互联板的方法，每个都是设定好尺寸设置在具有一对连接半导体顶部的匹配电路基底上，该方法包括：
a)制作一个多板载体框，具有多个互联板完整的支撑和多个临时支撑成分；
b)通过破坏临时支撑成分将独立的互联板从多个载体框中分离出来；
c)将每个互联板设置在设配电路基底上；其特征在于，
每个互联板进一步包括一个从半导体芯片顶部到中间接触区的互联板，其中的中间接触区包括从其他半导体芯片底部延伸出来的L形电路路径。
17、根据权利要求16所述的方法，其特征在于，制作多板载体边框还包括用至少一个集成临时支撑成分连接至少一对相互连接的互联板。
18、根据权利要求16所述的方法，其特征在于，在连接每个互联板中还包括同时连接所有互联板。
19、根据权利要求16所述的方法，其特征在于，分开多个引线边框包括使每个连接在一起的电路基底独立；进一步包括，步骤c)，d)之后分开每个电路基底的独立的互联板。
20、根据权利要求16所述的方法，其特征在于，分开多板载体框还包括分开每个电路基底上的相互独立的互联板。
21、根据权利要求16所述的方法，其特征在于，制作多板载体边框进一步包括用一个样板刀三维制作互联板。
22、根据权利要求16所述的方法，其特征在于，分开多板载体边框还包括用冲孔工具将其分开。
23、根据权利要求16所述的方法，其特征在于，还包括：
e)封装至少电路基底的一部分，多个半导体芯片和互联板。
CN2009101652548A 2008-08-07 2009-08-06 具有立体匹配互连板的紧密封装半导体芯片 Active CN101656250B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/188,160 US7776658B2 (en) 2008-08-07 2008-08-07 Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates
US12/188,160 2008-08-07

Publications (2)

Publication Number Publication Date
CN101656250A true CN101656250A (zh) 2010-02-24
CN101656250B CN101656250B (zh) 2011-10-19

Family

ID=41652144

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009101652548A Active CN101656250B (zh) 2008-08-07 2009-08-06 具有立体匹配互连板的紧密封装半导体芯片

Country Status (3)

Country Link
US (2) US7776658B2 (zh)
CN (1) CN101656250B (zh)
TW (1) TWI406372B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222660A (zh) * 2010-04-16 2011-10-19 万国半导体有限公司 双引线框架多芯片共同封装体及其制造方法
CN102969290A (zh) * 2011-08-29 2013-03-13 富晶电子股份有限公司 封装结构
CN103137586A (zh) * 2011-12-02 2013-06-05 Nxp股份有限公司 电路连接器装置及其方法
CN103996628A (zh) * 2010-04-16 2014-08-20 万国半导体有限公司 双引线框架多芯片共同封装体的制造方法
CN104282646A (zh) * 2013-07-01 2015-01-14 瑞萨电子株式会社 半导体器件
CN112992819A (zh) * 2021-04-26 2021-06-18 佛山市国星光电股份有限公司 一种封装器件及其制作方法

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8373257B2 (en) * 2008-09-25 2013-02-12 Alpha & Omega Semiconductor Incorporated Top exposed clip with window array
US8062932B2 (en) * 2008-12-01 2011-11-22 Alpha & Omega Semiconductor, Inc. Compact semiconductor package with integrated bypass capacitor and method
US8169088B2 (en) * 2009-07-02 2012-05-01 Monolithic Power Systems, Inc. Power converter integrated circuit floor plan and package
US7994615B2 (en) * 2009-08-28 2011-08-09 International Rectifier Corporation Direct contact leadless package for high current devices
US8093695B2 (en) * 2009-09-04 2012-01-10 International Rectifier Corporation Direct contact leadless flip chip package for high current devices
US8722466B2 (en) * 2010-03-12 2014-05-13 Alpha & Omega Semiconductor, Inc. Semiconductor packaging and fabrication method using connecting plate for internal connection
US8513784B2 (en) * 2010-03-18 2013-08-20 Alpha & Omega Semiconductor Incorporated Multi-layer lead frame package and method of fabrication
US8154108B2 (en) * 2010-03-29 2012-04-10 Alpha And Omega Semiconductor Incorporated Dual-leadframe multi-chip package and method of manufacture
TWI462254B (zh) * 2010-04-16 2014-11-21 Alpha & Omega Semiconductor 雙引線框架多晶片共同封裝體及其製造方法
CN103824841B (zh) * 2010-05-05 2016-09-21 万国半导体有限公司 用连接片实现连接的半导体封装
CN103824784B (zh) * 2010-05-05 2016-10-12 万国半导体有限公司 用连接片实现连接的半导体封装的方法
CN102237343B (zh) * 2010-05-05 2014-04-16 万国半导体有限公司 用连接片实现连接的半导体封装及其制造方法
JP2012069764A (ja) * 2010-09-24 2012-04-05 On Semiconductor Trading Ltd 回路装置およびその製造方法
US8269330B1 (en) * 2011-04-22 2012-09-18 Cyntec Co., Ltd. MOSFET pair with stack capacitor and manufacturing method thereof
KR101832306B1 (ko) * 2011-05-30 2018-02-26 엘지이노텍 주식회사 발광소자 패키지
ITMI20111219A1 (it) * 2011-06-30 2012-12-31 St Microelectronics Srl Sistema con dissipatore di calore condiviso
ITMI20111208A1 (it) 2011-06-30 2012-12-31 St Microelectronics Srl Sistema con dissipatore di calore stabilizzato
ITMI20111213A1 (it) 2011-06-30 2012-12-31 St Microelectronics Srl Dispositivo elettronico a semi-ponte con dissipatore di calore ausiliario comune
ITMI20111214A1 (it) 2011-06-30 2012-12-31 St Microelectronics Srl Dispositivo di potenza a spessore ridotto
ITMI20111216A1 (it) 2011-06-30 2012-12-31 St Microelectronics Srl Dispositivo elettronico di potenza ad elevata dissipazione di calore e stabilita?
ITMI20111217A1 (it) 2011-06-30 2012-12-31 St Microelectronics Srl Sistema contenitore/dissipatore per componente elettronico
ITMI20111218A1 (it) 2011-06-30 2012-12-31 St Microelectronics Srl Dispositivo di potenza ad elevata velocita? di commutazione
TWI493680B (zh) * 2012-05-23 2015-07-21 尼克森微電子股份有限公司 功率半導體封裝體及其製造方法
US9653386B2 (en) * 2014-10-16 2017-05-16 Infineon Technologies Americas Corp. Compact multi-die power semiconductor package
US10128170B2 (en) * 2017-01-09 2018-11-13 Silanna Asia Pte Ltd Conductive clip connection arrangements for semiconductor packages
WO2019049213A1 (ja) * 2017-09-05 2019-03-14 新電元工業株式会社 半導体装置
US10453779B2 (en) 2017-09-05 2019-10-22 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465875B2 (en) * 2000-03-27 2002-10-15 International Rectifier Corporation Semiconductor device package with plural pad lead frame
JP4102012B2 (ja) * 2000-09-21 2008-06-18 株式会社東芝 半導体装置の製造方法および半導体装置
CN1357919A (zh) * 2000-12-11 2002-07-10 台湾通用器材股份有限公司 功率型半导体芯片的封装装置及封装方法
ATE498908T1 (de) * 2003-06-18 2011-03-15 Nxp Bv Verfahren zur herstellung einer halbleitervorrichtung mit einem leiterrahmen und vorrichtung hierzu
JP4489485B2 (ja) * 2004-03-31 2010-06-23 株式会社ルネサステクノロジ 半導体装置

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222660A (zh) * 2010-04-16 2011-10-19 万国半导体有限公司 双引线框架多芯片共同封装体及其制造方法
CN103996628A (zh) * 2010-04-16 2014-08-20 万国半导体有限公司 双引线框架多芯片共同封装体的制造方法
CN102969290A (zh) * 2011-08-29 2013-03-13 富晶电子股份有限公司 封装结构
CN103137586A (zh) * 2011-12-02 2013-06-05 Nxp股份有限公司 电路连接器装置及其方法
CN103137586B (zh) * 2011-12-02 2016-02-03 Nxp股份有限公司 电路连接器装置及其方法
CN104282646A (zh) * 2013-07-01 2015-01-14 瑞萨电子株式会社 半导体器件
CN104282646B (zh) * 2013-07-01 2018-01-16 瑞萨电子株式会社 半导体器件
CN112992819A (zh) * 2021-04-26 2021-06-18 佛山市国星光电股份有限公司 一种封装器件及其制作方法
CN112992819B (zh) * 2021-04-26 2022-03-18 佛山市国星光电股份有限公司 一种封装器件及其制作方法

Also Published As

Publication number Publication date
CN101656250B (zh) 2011-10-19
US7776658B2 (en) 2010-08-17
US7906375B2 (en) 2011-03-15
TWI406372B (zh) 2013-08-21
US20100273294A1 (en) 2010-10-28
TW201007905A (en) 2010-02-16
US20100032819A1 (en) 2010-02-11

Similar Documents

Publication Publication Date Title
CN101656250B (zh) 具有立体匹配互连板的紧密封装半导体芯片
US7999364B2 (en) Method and flip chip structure for power devices
CN100362656C (zh) 包含漏极夹的半导体管芯封装及其制造方法
CN102714201B (zh) 半导体封装和方法
CN100411500C (zh) 包括具有互连结构阵列的基板的多片模块
US8933550B2 (en) Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors
US6710439B2 (en) Three-dimensional power semiconductor module and method of manufacturing the same
CN104603948A (zh) 垂直堆叠的功率fet和具有低导通电阻的同步降压转换器
TWI512937B (zh) Flip - mounted package for integrated switching power supply and its flip - chip packaging method
CN202042483U (zh) 一种功率半导体器件的封装结构
US7633140B2 (en) Inverted J-lead for power devices
CN103107171B (zh) 一种倒装芯片的半导体器件
CN104681525B (zh) 一种多芯片叠层的封装结构及其封装方法
US11257739B2 (en) Semiconductor package with integrated passive electrical component
US9040357B2 (en) Semiconductor packaging method using connecting plate for internal connection
TWI596728B (zh) 具有單列直插引線模塊的半導體功率器件及其製備方法
CN101473423B (zh) 双侧冷却集成晶体管模块及制造方法
JP6534677B2 (ja) スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ
CN114743957A (zh) 芯片封装模组及其制备方法、电源模块、电子设备
TWI469311B (zh) 聯合封裝的功率半導體元件
KR20150090616A (ko) 전력반도체 모듈
US20230027138A1 (en) Power module
WO2017015542A1 (en) Backside stacked die in an integrated circuit (ic) package
CN205488099U (zh) 半导体装置
TWI443801B (zh) 用連接片實現連接的半導體封裝及其製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170714

Address after: Chongqing city Beibei district and high tech Industrial Park the road No. 5 of 407

Patentee after: Chongqing Wanguo Semiconductor Technology Co., Ltd.

Address before: Bermuda Hamilton No. 22 Vitoria street Canon hospital

Patentee before: Alpha & Omega Semiconductor Inc.

PE01 Entry into force of the registration of the contract for pledge of patent right
PE01 Entry into force of the registration of the contract for pledge of patent right

Denomination of invention: Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates

Effective date of registration: 20191210

Granted publication date: 20111019

Pledgee: Chongqing Branch of China Development Bank

Pledgor: Chongqing Wanguo Semiconductor Technology Co., Ltd.

Registration number: Y2019500000007