CN101651106B - Manufacturing method of stacked chip package structure - Google Patents

Manufacturing method of stacked chip package structure Download PDF

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Publication number
CN101651106B
CN101651106B CN2008102109624A CN200810210962A CN101651106B CN 101651106 B CN101651106 B CN 101651106B CN 2008102109624 A CN2008102109624 A CN 2008102109624A CN 200810210962 A CN200810210962 A CN 200810210962A CN 101651106 B CN101651106 B CN 101651106B
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China
Prior art keywords
chip
weld pad
bonding wire
substrate
area
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CN2008102109624A
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Chinese (zh)
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CN101651106A (en
Inventor
李淳玮
蔡铭海
段吉运
简圣辉
白忠巧
刘裕文
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Kunyuan Technology Co Ltd
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Kunyuan Technology Co Ltd
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Abstract

The invention discloses a manufacturing method of a stacked chip package structure. The method comprises the following steps: providing a substrate first; adhering a first chip and a second chip above the substrate, wherein, the second chip is stacked above the first chip; connecting a first bonding wire between a second bonding pad of the second chip and a first area of a first bonding pad of the first chip; and connecting a second bonding wire between a second area of the first bonding pad of the first chip and metal contacts of the substrate. Accordingly, the manufacturing method can help greatly reduce the overall volume, effectively solve the problem of various bonding wires, and reduce the occupying volume of bonding pads of the substrate and the number of the bonding pads, thus reducing the complexity of substrate circuit layout.

Description

The manufacturing approach of stacked chip package structure
Technical field
The present invention relates to a kind of manufacturing approach of stacked chip package structure, refer to configuration especially about bonding wire in the semiconductor die package technology.
Background technology
Because the development trend of electronic product towards more and more compact, directly also makes in order to the protection semiconductor chip and provides the packaging structure of external circuit connection to need compactization too.Existing in the past common multichip package structure is a side-by-side, and it is that plural chip is installed on the real estate each other abreast.Yet the side-by-side structure can cause substrate area also must enlarge because of number of chips increases thereupon, and this mode causes the bulky of electronic component easily, can't meet the consumer and expect.
Moreover, along with development of technology, just develop with stacked mode about the multilayer chiop, see also Fig. 1.This mode solves original two dimensional surface too huge problem of electronic component during layout type side by side, effectively significantly reduces entire area.But during along with multiple-level stack, the bonding wire circuit is also got over various thereupon, so that bonding wire is easy to generate staggered and causes short circuit during routing technology, so just is not easy to increase chip-stacked space again.Again and, along with the increase of chip-stacked quantity, the shared area of substrate metal contact also must increase thereupon, causes the design limit easily, increases the complexity of base plate line layout.
In addition,, also there is prior art to develop and the mode that solder joint piles up serial connection for overcoming the various problem of bonding wire circuit of above-mentioned stacked chips, as shown in Figure 2.It is to lay respectively at the identical weld pad of function on two stacked chips with two, utilizes the ball bonding instrument that it is electrically piled up and is connected to same chip pad.Though so can effectively solve the various problem of bonding wire circuit, also follow more problems.Its processing step is roughly following; Chip 82 is on substrate 85 under fixing respectively earlier and go up chip 81, reaching; And the routing of going up bonding wire 83 is to get to down chip 82 by last chip 81 in proper order, and then bonding wire 84 is in the folded substrate 85 of getting to again of following chip 82 same bond pad locations strings by last bonding wire 83 down.
In view of the above, to be (1) chip aluminium pad damage because of repeating to apply pressure to same point existing shortcoming easily.It must repeat to apply secondary actuating pressure in the second solder joint place of bonding wire 83 when carrying out bonding wire 84 routings; That is when down the same point on the aluminium pad 821 of chip 82 is born the actuating pressure of capillary for the second time again; Chip aluminium pad is damaged, even cause opening circuit of chip circuit unusual.
In addition, see also Fig. 3, (2) when carrying out bonding wire 84 routings, often cause error to produce skew because of machine or control problem equally under the folded situation of bonding wire string, cause and can't carry out the routing welding over against same central point fully.It is not smooth adding surface, original solder joint top, when the second time, capillary 86 applied actuating pressure, and the application point off-centring of actuating pressure.Again because the common golden bond strength of gold goal and aluminium pad far below the common golden bond strength of gold goal and gold goal; When so chip aluminium pad 821 receives the actuating pressure of the capillary 86 offsetting dips second time instantly; Golden bond strength is relatively poor peels off because of common to cause ground floor gold goal 831 and following chip aluminium pad 821 easily, and causes the two disengaging and produce and open circuit.
In addition, the bank of the folded second layer of (3) string is more wayward.Please continue to consult Fig. 3, when the bonding wire 84 of the folded second layer of string, regular meeting adds because of the convexity of ground floor gold goal 831 due to the error of machinery equipment; And can't carry out the routing operation in predetermined center; Cause the point of application of capillary 86 of second layer bonding wire not steady, and it is controlled to cause bonding wire 84 banks to be difficult for, and can't carry out the routing operation according to predetermined bonding wire route; And have unsettled situation to take place, severe patient even can cause bonding wire to be entangled with and open circuit.
Hence one can see that; How reaching a kind of stacked chips structure can significantly dwindle whole volume, bonding wire bank and control, reduce the complexity of base plate line layout easily and avoid chip and the aluminium pad damages easily; It is various more can effectively to solve the bonding wire circuit, is a kind of the pressing on the industry really.
Summary of the invention
The present invention is a kind of manufacturing approach of stacked chip package structure, and it includes following steps: a substrate (A) is provided, and the upper surface of substrate is provided with at least one metallic contact.(B) set one first chip, and one second chip in substrate top but expose at least one metallic contact.Wherein, the upper surface of first chip is provided with at least one first weld pad, and at least one first weld pad includes the first area that abuts one another, an and second area again.In addition, second chip is stacked at first chip top but exposes at least one first weld pad, and the upper surface of second chip is provided with at least one second weld pad.(C) connect one first be wired in second chip at least one second weld pad, and the first area of at least one first weld pad of first chip between; And, connect one second be wired at least one first weld pad of first chip second area, and at least one metallic contact of substrate between.Therefore, the present invention can significantly dwindle whole volume, more can effectively solve the various problem of bonding wire circuit, and can reduce the required weld pad quantity of substrate, reduces the complexity of base plate line layout through this.
Preferably, in the step of the present invention (B) more set at least one lower floor chip is arranged between the substrate and first chip, but expose at least one metallic contact.And the upper surface of at least one lower floor chip can be provided with at least one lower floor weld pad, and it is not also covered in by first chip.In addition, in the step (B) again more set at least one interlayer chip is arranged between first chip and second chip, but expose at least one first weld pad.The upper surface of at least one interlayer chip is provided with at least one interlayer pad, and it is not also covered in by second chip.Moreover, in the step (B) also more set at least one upper strata chip is arranged in second chip top, but expose at least one second weld pad.And the upper surface of at least one upper strata chip is provided with at least one upper strata weld pad.
Moreover first solder joint of first bonding wire of step of the present invention (C) can be electrically connected to second weld pad of second chip, and second solder joint of first bonding wire can be electrically connected to the first area of first weld pad.That is the routing order of the present invention's first bonding wire can be got to the first area of first weld pad of below first chip by second weld pad of top second chip.
In addition, first solder joint of first bonding wire of step of the present invention (C) also can be electrically connected to the first area of first weld pad, and second solder joint of first bonding wire can be electrically connected to second weld pad of second chip.That is the routing of first bonding wire of the present invention order can be got to second weld pad of top second chip by the first area of first weld pad of below first chip.
In addition, first solder joint of second bonding wire of step of the present invention (C) can be electrically connected to the second area of first weld pad, and second solder joint of second bonding wire can be electrically connected to the metallic contact of substrate.That is the routing of second bonding wire of the present invention order can be got to the metallic contact of lower substrate by the second area of first weld pad of top first chip.
Again and, first solder joint of second bonding wire of step of the present invention (C) also can be electrically connected to the metallic contact of substrate, and second solder joint of second bonding wire can be electrically connected to the second area of first weld pad.That is the routing order of second bonding wire of the present invention can be got to the second area of first weld pad of top first chip by the metallic contact of lower substrate.
Wherein, also include a step (D) after the step of the present invention (C), encapsulation coats first chip, this second chip, first bonding wire, second bonding wire and substrate at least a portion in an adhesive body.In addition, first weld pad of the present invention, and second weld pad can be respectively an aluminium pad.
Description of drawings
Fig. 1 is the sketch map of existing chip stack structure;
Fig. 2 is that the solder joint of existing stacked chips piles up the sketch map of serial connection;
Fig. 3 is the sketch map that existing solder joint piles up capillary contact when being connected in series;
Fig. 4 is the sketch map of the present invention's one preferred embodiment;
Fig. 5 is the sketch map of the present invention's one preferred embodiment first weld pad;
Fig. 6 is the flow chart of the present invention's one preferred embodiment;
Fig. 7 is the flow chart of the present invention's one preferred embodiment (B) step;
Fig. 8 is the sketch map of second embodiment of the invention;
Fig. 9 is the flow chart of second embodiment of the invention (B) step.
Main element symbol 1, explanation
1 substrate, 10,20 upper surfaces, 11,12 metallic contacts
2 first chips, 21 first weld pads, 211 first areas
212 second areas, 3 second chips, 31 second weld pads
41 first bonding wires, 411,421 first solder joints, 412,422 second solder joints
42 second bonding wires, 5 lower floor's chips, 51 lower floor's weld pads
6 interlayer chips, 61 interlayer pad, 7 upper strata chips
Chip 82 substrates on the 71 upper strata weld pads 81
84 times bonding wire 85 substrates of bonding wire on 83
821 times chip aluminium pad 831 ground floor gold goals 86 capillaries
A, B, B1, B2, B3, B4, B5, B6, B7, C, D step
Embodiment
Please consult Fig. 4 simultaneously, reach Fig. 6, Fig. 4 is the sketch map of the preferred embodiment of the manufacturing approach of a kind of stacked chip package structure of the present invention, the flow chart of Fig. 6 the present invention one preferred embodiment.The present invention is applicable to the stacking and packaging construction of any IC chip, and storage card integrated circuit etc. for example, present embodiment promptly are to be that example is explained with the SD storage card, but not as limit.Step of the present invention is following: at first, a substrate 1 is provided, and the upper surface 10 of substrate 1 is provided with a metallic contact 11, as the golden finger that is commonly called as (finger).Then, one first chip 2 of adhering respectively, and one second chip 3 in substrate 1 top but expose metallic contact 11, and generally adopt thermoset epoxy material (thermosetting epoxy material) in order to the material of adhesion.Yet it is that adhesion first chip 2 is adhered second chip 3 on first chip 2 subsequently again on substrate 1 earlier in the present embodiment, and its steps flow chart is as shown in Figure 7.
Wherein, the upper surface 20 of first chip 2 is provided with one first weld pad 21, and first weld pad 21 is to adopt the aluminium pad.And first weld pad 21 includes the first area 211 that abuts one another and electrically connect, an and second area 212, and also as shown in Figure 5, Fig. 5 is the sketch map of the present invention's one preferred embodiment first weld pad.Wherein, second chip 3 is stacked at first chip, 2 tops but exposes first weld pad 21, and the upper surface of second chip 3 also is provided with second weld pad 31, and second weld pad 31 also adopts the aluminium pad.
Then, connect (be commonly called as beat gold thread connect) one first bonding wire 41 in second weld pad 31 of second chip 3, and the first area 211 of first weld pad 21 of first chip 2 between.In present embodiment, first solder joint 411 (1 of first bonding wire 41 StBond claims ball bond or ball bonding (Ball Bond) again) be the first area 211 that is electrically connected to first weld pad 21, and second solder joint 412 (2 of first bonding wire 41 NdBond claims that again impression engages or seam welds (Stitch Bond)) be second weld pad 31 that is electrically connected to second chip 3.That is the routing of first bonding wire 41 is second weld pad 31 of being got to top second chip 3 by the first area 211 of first weld pad 21 of below first chip 2 in proper order.But the routing of first bonding wire 41 order also can be got to the first area 211 of first weld pad 21 of below first chip 2 by second weld pad 31 of top second chip 3 not with limit.
And, connect one second bonding wire 42 in the second area 212 of first weld pad 21 of first chip 2, and the metallic contact 11 of substrate 1 between.In present embodiment, first solder joint 421 of second bonding wire 42 is that second solder joint 422 that is electrically connected to second area 212, the second bonding wires 42 of first weld pad 21 is the metallic contacts 11 that are electrically connected to substrate 1.That is the routing of second bonding wire 42 is the metallic contact 11 of being got to lower substrate 1 by the second area 212 of first weld pad 21 of top first chip 2 in proper order.But the routing of second bonding wire 42 order can be got to the second area 212 of first weld pad 21 of top first chip 2 by the metallic contact 11 of lower substrate 1 not with limit.
See also Fig. 5; Show among the figure that first weld pad 21 has above-mentioned first area 211, reaches second area 212; And preceding first solder joint 411 that has first bonding wire 41 on the first area 211 that disclosed; First solder joint 421 that has second bonding wire 42 on the second area 212, first solder joint, 411,421 central points of its two bonding wire have a central point apart apart from d.And central point is apart from the error of d in order to absorb manufacturing tolerance, machinery equipment or to produce because of control, in order to avoid two solder joints overlapping.In view of the above, the present invention can solve the problem of existing string stitch welding point fully, can not cause weld pad to damage easily because of repeating to apply pressure to same point.Moreover, can be because of capillary error, offset problem yet, and cause applying the actuating pressure of offsetting dip and cause peeling off, opening circuit of weld pad and solder joint.In addition, also because the substrate of its connection is smooth weld pad,, can carry out the routing operation according to original predefined paths fully so the bank of bonding wire is stable.
Yet the sequencing of first bonding wire 41 and second bonding wire 42 can also be made a call to second bonding wire 42 earlier also not as limit, carries out the installation work of first bonding wire 41 thereafter again.In addition, accomplish encapsulation step at last again, that is encapsulation coats first chip 2, second chip 3, first bonding wire 41, second bonding wire 42 and substrate 1 at least a portion in an adhesive body.Again and, the bonding wire that present embodiment is adopted is a gold thread, and the gold thread line directly can be 0.7 (18 μ m), 0.8 (20 μ m) or 0.9mil (23 μ m).Certainly along with the development gold thread line footpath of process equipment can be more and more thinner, and thin more gold thread also can be applicable to method of the present invention fully.
Please consult Fig. 8 simultaneously, reach Fig. 9, wherein Fig. 8 is the sketch map of second embodiment of the invention, and Fig. 9 is the flow chart of second embodiment of the invention (B) step.The difference of second embodiment and above-mentioned preferred embodiment is, second embodiment increases lower floor's chip 5, an interlayer chip 6, an and upper strata chip 7, and also is suitable for the IC chip stacking construction of difference in functionality through explanation the present invention.Wherein lower floor's chip 5 is adhered between the substrate 1 and first chip 2, but it exposes metallic contact 11,12 again.And interlayer chip 6 is adhered between first chip 2 and second chip 3, but exposes first weld pad 21.As for, upper strata chip 7 is adhered to second chip, 3 tops, but exposes second weld pad 31.
Right its step of piling up is as shown in Figure 9, at first adheres lower floor's chip 5 on substrate 1.Then adhere first chip 2 on lower floor's chip 5, and the upper surface of lower floor's chip 5 is provided with at least one lower floor weld pad 51, and it is not also covered in by first chip 2.Interlayer chip 6 adhere again on first chip 2, and the upper surface of interlayer chip 6 is provided with at least one interlayer pad 61.Then, second chip 3 of adhering is in interlayer chip 6 tops, and the interlayer pad 61 of interlayer chip 6 is not also covered in by second chip 3.Adhesion upper strata chip 7 is in second chip, 3 tops, and the upper surface of upper strata chip 7 is provided with at least one upper strata weld pad 71.
In addition, this second embodiment bonding wire arranges respectively as follows, lower floor's chip 5, interlayer chip 6, and upper strata chip 7 employings method of the present invention be electrically connected respectively, and lower floor's chip 5 is connected to the metallic contact 12 of substrate 1 again.And the connected mode in first chip 2, second chip 3 as the above-mentioned preferred embodiment originally and be connected to the metallic contact 11 of substrate 1.This second embodiment mainly explains; The IC chip structure that piles up also might pile up the chip of difference in functionality; It between its different stacked chips simple connection one by one fully; And the chip of identical function needs to connect respectively, and it can adopt method of the present invention equally, so the present invention can be suitable for the stacked chips structure of any pattern fully.
The foregoing description only is to explain for ease and give an example, and the interest field that the present invention advocated is from should being as the criterion so that claim is said, but not only limits to the foregoing description.

Claims (8)

1. the manufacturing approach of a stacked chip package structure is characterized in that may further comprise the steps:
(A) substrate is provided, the upper surface of this substrate is provided with at least one metallic contact;
(B) set one first chip, and one second chip in this substrate top but expose this at least one metallic contact; Wherein, the upper surface of this first chip is provided with at least one first weld pad, and this at least one first weld pad includes the first area that abuts one another, an and second area; This second chip is stacked at this first chip top but exposes this at least one first weld pad, and the upper surface of this second chip is provided with at least one second weld pad; And
(C) connect one first be wired in this second chip this at least one second weld pad, and this first area of this at least one first weld pad of this first chip between; And, connect one second be wired in this at least one first weld pad of this first chip this second area, and this at least one metallic contact of this substrate between.
2. the manufacturing approach of stacked chip package structure as claimed in claim 1 is characterized in that, in this step (B) more set at least one lower floor chip is arranged between this substrate and this first chip, but expose this at least one metallic contact.
3. the manufacturing approach of stacked chip package structure as claimed in claim 1 is characterized in that, in this step (B) more set at least one interlayer chip is arranged between this first chip and this second chip, but expose this at least one first weld pad.
4. the manufacturing approach of stacked chip package structure as claimed in claim 1 is characterized in that, going back set in this step (B) has at least one upper strata chip in this second chip top, but exposes this at least one second weld pad.
5. the manufacturing approach of stacked chip package structure as claimed in claim 1; It is characterized in that; First solder joint of this first bonding wire of this step (C) is electrically connected to this second weld pad of this second chip, and second solder joint of this first bonding wire is electrically connected to this first area of this first weld pad.
6. the manufacturing approach of stacked chip package structure as claimed in claim 1; It is characterized in that; First solder joint of this second bonding wire of this step (C) is electrically connected to this second area of this first weld pad, and second solder joint of this second bonding wire is electrically connected to this metallic contact of this substrate.
7. the manufacturing approach of stacked chip package structure as claimed in claim 1 is characterized in that, after step (C), also includes a step:
(D) encapsulation coats this first chip, this second chip, this first bonding wire, this second bonding wire and this substrate at least a portion in an adhesive body.
8. the manufacturing approach of stacked chip package structure as claimed in claim 1 is characterized in that, this first weld pad, and this second weld pad be respectively an aluminium pad.
CN2008102109624A 2008-08-15 2008-08-15 Manufacturing method of stacked chip package structure Expired - Fee Related CN101651106B (en)

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EP0642164A2 (en) * 1993-09-03 1995-03-08 International Business Machines Corporation Stackable vertical thin package/plastic molded lead-on-chip memory cube
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EP0642164A2 (en) * 1993-09-03 1995-03-08 International Business Machines Corporation Stackable vertical thin package/plastic molded lead-on-chip memory cube
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