CN101625893B - Strap-contact scheme for compact array of memory cells - Google Patents
Strap-contact scheme for compact array of memory cells Download PDFInfo
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- CN101625893B CN101625893B CN2009100004247A CN200910000424A CN101625893B CN 101625893 B CN101625893 B CN 101625893B CN 2009100004247 A CN2009100004247 A CN 2009100004247A CN 200910000424 A CN200910000424 A CN 200910000424A CN 101625893 B CN101625893 B CN 101625893B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000011799 hole material Substances 0.000 description 116
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 22
- 229920005591 polysilicon Polymers 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 230000008901 benefit Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
A semiconductor device with multiple strap-contact configurations for a memory cell array. An array with memory cells interconnected with bit-lines, control-gate lines, erase gate lines, common-source lines, and word-lines is provided. In one aspect of an illustrative embodiment, a strap-contact corridor is spaced at n bit-line intervals (n>1) across the array. The strap-contact corridor comprises strap-contact cells, which provide electrical interconnection between control-gate lines, erase gate lines, common-source lines, and word-lines and their respective straps.
Description
Technical field
Relate generally to semiconductor devices of the present invention, the banded contact hole that relates in particular to memory cell array disposes.
Background technology
Various semiconductor storage units are developed, and these semiconductor storage units constantly are used in the application new and that extend, these integrated circuit that application need capacity is big and cost is low.Therefore, the demand to cheap semiconductor devices with high storage capacity, small size chip continues to exist.Many semiconductor devices comprise polytype circuit, for example memory circuit and logical circuit.Flash memory cell is usually together with other circuit (non-memory circuit), for example kernel circuitry together, as the embedded flash storer.Flash memory cell can be included in SOC(system on a chip), and (system on a chip is SOC) in the device.
In recent years, the flash memory increased popularity that becomes.Typical flash memory comprises storage array, and this storage array has the storage unit that much is arranged in piece.Each flash memory cell is manufactured to the field effect transistor with control gate and floating boom.Floating boom can keep electric charge, and separates with the drain region with source electrode in being included in substrate through thin oxide layer.This storage unit can be carried out various operations, comprises programming, reads, writes and wipes etc.For example, electronics is passed oxide layer be injected on the floating boom from the drain region, storage unit is electrically charged.In erase operation, utilize existing method that electronics is passed oxide layer and be tunneling to grid, thereby electric charge is removed from floating boom.Thus, the data in the storage unit are by whether there being the electric charge decision on the floating boom.
Amorphous state polysilicon (poly) line or buried regions line (for example the doped silicon of composition) can be with the mode of array with the component interconnect of storage unit to together.Between polysilicon lines or buried regions line and interconnection structure (being generally metal), be provided with and contact.Along with array is increasing, possibly there is voltage drop along polysilicon lines or buried regions line.This voltage drop can determine the function and the speed of array.A method that overcomes this problem is can use metal wire but not polysilicon lines or buried regions line, the parts of the storage unit that interconnects.But, possibly need bigger storage unit to provide and connect contact and the required space of each storage unit component.
Summary of the invention
The banded contact hole configuration that is used for memory cell array through the present invention can overcome above-mentioned and other problem, and the advantage of acquisition of technology.
A kind of semiconductor devices comprises a plurality of storage unit by arrayed, and said array comprises: a plurality of bit lines, each bit line form row in said array; A plurality of control gate line, each control gate line form control gate row in said array; A plurality of erase gate polar curves, each erase gate polar curve form erase gate row in said array; A plurality of common source line, each common source line form common source line row in said array; And a plurality of word lines, each word line forms word line row in said array.
In addition, said array comprises a plurality of bands, and each is charged to be connected to one or more in control gate line, erase gate polar curve, common source line and the word line.In addition, each band is electrically connected to one or more in control gate line, erase gate polar curve, common source line or the word line through the banded contact hole in the banded contact hole unit.
First storage unit is electrically connected to first bit line, first control gate line, shared erase gate polar curve, common source line and first word line.Second storage unit is electrically connected to first bit line, second control gate line, shared erase gate polar curve, common source line and second word line.First storage unit and second storage unit form a unit group.A plurality of banded contact holes unit is provided, and wherein each banded contact hole unit has the length identical substantially with said unit group and has about 1 to the 3 times width of said unit group.
In this semiconductor devices, each banded contact hole passage is the banded contact hole passage of common source, and the banded contact hole width of channel of wherein said common source is approximately 2 times of said unit group width.
In this semiconductor devices, each banded contact hole passage is the banded contact hole passage of word line, and the banded contact hole width of channel of wherein said word line is approximately 1.5 times of width of said unit group.
In this semiconductor devices, each banded contact hole passage is the how banded contact hole passage of word line/common source, and the how banded contact hole width of channel of wherein said word line/common source is approximately 2 times of said unit group width.
In this semiconductor devices, each banded contact hole passage is a word line/wipe the how banded contact hole passage of grid, and wherein said word line/wipe the how banded contact hole width of channel of grid is approximately 1.5 times of said unit group width.
The advantage of the embodiment of the invention has been to provide a kind of band bypass configuration with efficient masks, and need not increase complicated processing step.
In order to understand the detailed description of the present invention of hereinafter better, preceding text general description the characteristic and the technological merit of the embodiment of the invention.During the supplementary features of the embodiment of claim theme and advantage will be described below according to the present invention.Those of ordinary skill in the art should be appreciated that notion disclosed by the invention and specific embodiment can easily be utilized as the basis of revising or design other structures or technology to realize the identical purpose of the present invention.Those of ordinary skill in the art it is to be further appreciated that such equivalent structure does not break away from spirit and the scope like the embodiment that illustrates in the accessory claim of the present invention.
Description of drawings
In order more fully to understand the embodiment of the invention and advantage thereof, will combine accompanying drawing that hereinafter is described now and make reference, wherein:
Fig. 1 is the planimetric map according to the partial memory cell array of the embodiment of the invention;
Fig. 2 is the cross section view of unit group (unit set);
Fig. 3 has shown the cross section view and the corresponding vertical view thereof of the banded contact hole of EG unit;
Fig. 4 has shown the cross section view and the corresponding vertical view thereof of the banded contact hole of CS unit;
Fig. 5 A has shown the how banded contact hole of the CS/CG of first embodiment of the invention unit,
Fig. 5 B has shown the vertical view of the how banded contact hole of this CS/CG unit, and
Fig. 5 C has shown the how banded contact hole of the CS/CG of second embodiment of the invention unit; And
Fig. 6 has shown EG/WL how banded contact hole unit and vertical view thereof.
Only if point out in addition, corresponding numbers and symbol are often referred to corresponding elements in the different accompanying drawings.The accompanying drawing of describing is the related fields that are used for clearly illustrating preferred embodiment, and does not need proportionally to describe.
Embodiment
To describe the semiconductor devices of the preferred embodiment of the present invention below in detail, still, should be appreciated that illustrated embodiment provides many inventive concept used that can be embodied under the various specific environments.The specific embodiment of these discussion is an ad hoc fashion of explaining realization of the present invention and use only, and can not be used to limit the present invention.
To promptly divide grid flash storage (SGF) array that the present invention is made description to illustrated embodiment in concrete context below.But the present invention can also be applied to other flash memory array and other comprise the semiconductor devices of flash memory array.
Now, with reference to figure 1, the figure illustrates planimetric map according to the partial memory cell of the embodiment of the invention.Array 100 comprises a plurality of storage unit that are provided with by row and column.Plurality of units 106 in a plurality of storage unit of forming array is represented by the cross part of bit line (BL) row 102 and word line (WL) row 104.Bit line is a lead, can comprise metal, metal level, polysilicon etc.According to the aspect of embodiment, bit line comprises first metal interconnecting layer, ground floor metal (metall), and it can be Al, Cu, other Metal and Alloys, polysilicon and other conductive materials.In the present embodiment, bit line is that copper is inlayed (Cu damascene) structure.Word line is polysilicon lines normally, but also can comprise other conductive materials.
In example embodiment, banded contact hole path 10 8 can be parallel to BL row 102.Banded contact hole path 10 8 is arranged with row in array 100, and being used for provides banded contact hole for band (straps).The band (not shown) is the lead as polysilicon lines or buried regions line bypass (shunt).For example, along identical length, metal wire can have lower voltage drop than polysilicon or buried regions line.Therefore, utilizing metal or other leads to come the advantage of bypass polysilicon lines is to each storage unit more consistent voltage to be provided.Yet because banded contact hole needs array area, therefore the increase of band possibly increase the area of array significantly.Therefore, in example embodiment, not banded contact hole all to be provided to each storage unit.But cross array polysilicon lines or the buried regions line with banded contact hole is set periodically.Therefore, when need not expanding each storage unit and holding the required exceptional space of the banded contact hole of each unit node, illustrated embodiment also has the consistent advantage of voltage of metal wire.In addition, when according to embodiment design stores array, consider dirigibility, the banded contact hole of varying number can be set different storage unit lines.For example, per 128 bits of control gate line can be set have a banded contact hole, have a banded contact hole and per 32 bits of common source line common source can be set.
Banded contact hole path 10 8 can comprise the control gate contact hole that connects control gate (CG) line, connects its source electrode contact hole of common source (CS) line, the erase gate contact hole of connection erase gate (EG) line and the word line contact hole that connects word line (WL).Banded contact hole comprises conductive material, for example tungsten (W), polysilicon, metal, metal alloy, other conductive materials etc.Preferably, for example, the contact hole material can be a tungsten.Usually, through in that patterning of materials and etching in the layer between the lead of interconnection are formed banded contact hole, provide contact hole thus with the conducting contact material.Usually the size of setting the platform (landing) that is used for the banded contact hole on polysilicon or the silicon is even as big as allowing the variation of some technologies.The platform size that is used to contact possibly change according to some factors, like the quantity and the type of material in the necessary etched middle layer.Banded contact hole platform possibly increase the size of array significantly.But, if with on the contact hole that provides considerably less, then polysilicon lines and buried regions line possibly have too high impedance, and array can not be optimised.In whole description, term " unit group (unitset) " is used for representing to share two storage unit of a common source.
Fig. 2 has shown the sectional elevation according to the unit group of the embodiment of the invention.Unit group 200 comprises the flash memory cell 210 and 220 of two common sources, and wherein storage unit 210 and 220 is formed on the Semiconductor substrate 230.Storage unit 210 comprises floating boom FG
1252, control grid CG
1206, word line WL
1204 and bit line node BL
1254.Bit line node BL
1254 can share with another unit group (not shown).Bit line node BL
1Contact hole 256 is with bit line node BL
1254 are connected to (not shown) on the bit line.Storage unit 220 comprises floating boom FG
2253, control grid CG
2207, word line WL
2205 and bit line node BL
2255.And, bit line node BL
2255 can share with another unit group (not shown). Storage unit 210 and 220 is shared common source CS 208 and is wiped grid EG 209, bit line node BL
1254 with bit line node BL
2255 through the interconnection of bit line (not shown).
Can notice, wipe the top that grid 209 is positioned at common source 208.Therefore, according to illustrated embodiment, wipe grid together the banded contact hole of source electrode can not appear in the same banded contact hole unit group.
In the illustrated embodiment, control grid CG
1206 with control grid CG
2207 do not connect mutually, therefore control grid CG
1206 with control grid CG
2207 can be connected to different voltages with different.For example, in the process that storage unit 210 is programmed, at word line Node B L
1254 and common source CS 208 between apply voltage, for example the voltage on the bit line is approximately 0.4V, for example the voltage on the common source is approximately 4V.In order to make the turn in the Semiconductor substrate 230, can be at word line WL
1Apply the for example voltage of about 1.5V on 204.Therefore, electric current is at common source CS 208 and bit line node BL
1Flow between 254.Can be at control grid CG
1Therefore apply high control gate pole tension on 206, for example, this high control gate pole tension is about 10V, and under high electric field effects, electronics is programmed into floating boom FG
1In 252.Control grid CG in storage unit 220
2207 when for example being connected on the low-voltage of about 0V, and can programme to storage unit 220 writes.
Single (Mono) banded contact hole unit is those banded contact hole unit that utilize one type of banded contact hole, and for example CG (comprises CG
1And CG
2), CS, WL (comprise WL
1And WL
2) and EG.The type of the banded contact hole of list that adopts according to single banded contact hole unit, the banded contact hole of different lists unit can be of different sizes.
Fig. 3 has shown the sectional elevation 375 and the vertical view 376 thereof of the banded contact hole of EG unit 300.The banded contact hole of EG unit 300 is single banded contact hole, representes only to comprise in this unit one type banded contact hole.Therefore, the banded contact hole of list unit can comprise the banded contact hole of CS, the banded contact hole of EG, CG
1And CG
2Banded contact hole, perhaps WL
1And WL
2Banded contact hole.Sectional elevation 375 shows that the banded contact hole of EG unit 300 adopts the banded contact hole 359 of EG to contact EG 309.Corresponding vertical view 376 has shown the polysilicon EG belt 390 that is positioned at EG contact hole 359 belows.Referring again to Fig. 2 can know, EG polysilicon 209 is positioned at the top in CS zone 208.
Fig. 4 has shown the sectional elevation 475 and the vertical view 476 thereof of the banded contact hole 400 of CS.The banded contact hole of CS unit 400 adopts the banded contact hole 458 of CS to contact CS 408.Notice that group 400 removes (the unit group 200 of comparing Fig. 2) to EG 209 from the unit, make the banded contact hole 458 of CS can touch the common source CS 408 in the substrate thus.Therefore, according to an aspect of illustrated embodiment, there is not the how banded contact hole unit that can comprise banded contact hole of EG and the banded contact hole of CS simultaneously.There is not polysilicon EG layer (comparing the polysilicon EG layer 390 of vertical view 376 demonstrations of Fig. 3) in the below that the vertical view 476 of the banded contact hole of CS unit 400 is presented at the banded contact hole 458 of CS.
In one embodiment, how banded contact hole unit can adopt the banded contact hole more than a type in the unit group, and this unit group is the unit group 200 among Fig. 2 for example.For example, so how banded contact hole unit can be the banded contact hole of EG/WL, CG/CS, WL/CS or CG/EG unit.For the area that optimum signal is transmitted and minimized storage array, multiple list banded contact hole unit and how banded contact hole unit can be applied in this storage array.The Fig. 5 that comprises Fig. 5 A and Fig. 5 B has shown the embodiment of the banded contact hole of CG/CS unit.Fig. 6 has shown the embodiment of the how banded contact hole of EG/WL unit.
Fig. 5 A has shown an embodiment of the how banded contact hole of CG/CS unit, and Fig. 5 B has shown corresponding vertical view.How banded CG/CS contact hole unit 550 be as shown in the figure, the banded contact hole 552 contact CS 554 of CS.CG
1Banded contact hole 557 and CG
2Banded contact hole 558 contact CG
1555 and CG
2556.In another embodiment, CG
1 Banded contact hole 557 and CG
2Banded contact hole 558 can have the platform configuration of expansion, thereby allows the technique change in the contact hole technology.Compare the control grid CG line in the unit group, can revise banded contact hole unit group and hold bigger control grid CG contact hole platform.
Fig. 5 C has shown the how banded contact hole of the CS/CG of another embodiment unit.In the banded contact hole of CG unit group, the WL polysilicon can be discontinuous, and the banded contact hole platform of CG can be arranged on the WL position in the banded contact hole of the CG unit group.How banded CG/CS contact hole unit 560 be as shown in the figure.The banded contact hole 562 contact common source CS 564 of CS, CG
1Banded contact hole 567 and CG
2Banded contact hole 568 is touch controls grid CG respectively
1565 with control grid CG
2566.CG
1Banded contact hole 567 and CG
2Banded contact hole 568 can have the platform structure of expansion, to allow the technique change in the contact hole technology.
In other embodiments, can expand the CG polysilicon and to the WL polysilicon, (between two-layer, have insulation course).Under other situation, the WL polysilicon can not be arranged in the banded contact hole of same unit group.Though CG
1565 and CG
2566 are arranged in the how banded contact hole unit with the banded contact hole 562 of CS, but the metal connecting line (not shown) that connects these contact holes does not together shorten.Connect these contact holes to different metal layers, these metal levels are formed among the subsequent technique of semiconductor devices.
Fig. 6 has shown the how banded contact hole of EG/WL unit, and the how banded contact hole of EG/WL unit 600 comprises and word line WL
1The WL of 604 connections
1Banded contact hole 654, with word line WL
2The WL of 605 connections
2Banded contact hole 655 and with wipe the EG contact hole 659 that grid EG 609 is connected.
Range of application of the present invention is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the instructions.From disclosure of the present invention; To easily understand as those of ordinary skill in the art; For the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present; Wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.Therefore.Accompanying claims of the present invention is intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection domain.
Claims (15)
1. semiconductor devices comprises:
A plurality of storage unit according to arrayed;
A plurality of bit lines, each bit line form row in said array;
A plurality of control gate line, each control gate line form control grid row in said array;
A plurality of erase gate polar curves, each erase gate polar curve form in said array wipes grid row;
A plurality of common source line, each common source line form common source row in said array;
A plurality of word lines, each word line forms word line row in said array;
A plurality of bands; Each the band with said control gate line, said erase gate polar curve, said common source line and said word line at least one be electrically connected, each of wherein said band all is electrically connected to each in said control gate line, said erase gate polar curve, said common source line and the said word line through the banded contact hole in the banded contact hole unit;
First storage unit, it is electrically connected with first bit line, first control gate line, shared erase gate polar curve, common source line and first word line;
Second storage unit, it is electrically connected with said first bit line, second control gate line, said shared erase gate polar curve, said common source line and second word line, and wherein said first storage unit and said second storage unit form the unit group;
A plurality of banded contact holes unit, wherein each banded contact hole unit has with the essentially identical length of said unit group and has about 1 to the 3 times width of said unit group; And
A plurality of banded contact hole passages; Each banded contact hole passage forms the son row in said array; Wherein each banded contact hole passage comprises at least one banded contact hole unit, and wherein each banded contact hole width of channel is the width of each banded contact hole unit basically.
2. semiconductor devices as claimed in claim 1, wherein, each banded contact hole passage is the banded contact hole passage of control grid, and the banded contact hole width of channel of wherein said control grid is approximately 3 times of width of said unit group.
3. semiconductor devices as claimed in claim 1, wherein, each banded contact hole passage is for wiping the banded contact hole passage of grid, and the wherein said width of wiping banded contact hole width of channel of grid and said unit group is basic identical.
4. semiconductor devices as claimed in claim 1, wherein, each banded contact hole passage is the banded contact hole passage of common source, and the banded contact hole width of channel of wherein said common source is approximately 2 times of said unit group width.
5. semiconductor devices as claimed in claim 1, wherein, each banded contact hole passage is the banded contact hole passage of word line, and the banded contact hole width of channel of wherein said word line is approximately 1.5 times of width of said unit group.
6. semiconductor devices as claimed in claim 1; Wherein, Each banded contact hole passage is the how banded contact hole passage of control grid/common source, and the how banded contact hole width of channel of wherein said control grid/common source is approximately 3 times of said unit group width.
7. semiconductor devices as claimed in claim 1; Wherein, Each banded contact hole passage is control grid/wipe the how banded contact hole passage of grid, and wherein said control grid/wipe the how banded contact hole width of channel of grid is approximately 3 times of said unit group width.
8. semiconductor devices as claimed in claim 1, wherein, each banded contact hole passage is the how banded contact hole passage of word line/common source, and the how banded contact hole width of channel of wherein said word line/common source is approximately 2 times of said unit group width.
9. semiconductor devices as claimed in claim 1; Wherein, Each banded contact hole passage is a word line/wipe the how banded contact hole passage of grid, and wherein said word line/wipe the how banded contact hole width of channel of grid is approximately 1.5 times of said unit group width.
10. semiconductor devices as claimed in claim 1, wherein, said a plurality of banded contact hole passages are separated by n bit line, and wherein n is more than or equal to 1.
11. semiconductor devices as claimed in claim 1 also comprises:
The banded contact hole of a plurality of control grids, it has j bit line between the banded contact hole of each control grid in said control grid row;
A plurality of banded contact holes of grid of wiping, it has said wipes that each wipes k bit line between the banded contact hole of grid in the grid row;
The banded contact hole of a plurality of common sources, it has m bit line between the banded contact hole of each common source in said common source row; And
The banded contact hole of a plurality of word lines, it has p bit line between the banded contact hole of each word line in said word line row;
Wherein j, k, m and p can be the arbitrary integers more than or equal to 1.
12. semiconductor devices as claimed in claim 11, wherein j ≠ k, j ≠ m and j ≠ p.
13. semiconductor devices as claimed in claim 11, wherein k=m.
14. semiconductor devices as claimed in claim 13, wherein k ≠ p.
15. semiconductor devices as claimed in claim 1 also comprises a banded contact hole of control grid that is used for sub b the bit line of going of said control grid, wherein b equals the quantity of said array neutrality line.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/170,186 US7701767B2 (en) | 2008-07-09 | 2008-07-09 | Strap-contact scheme for compact array of memory cells |
| US12/170,186 | 2008-07-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101625893A CN101625893A (en) | 2010-01-13 |
| CN101625893B true CN101625893B (en) | 2012-04-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100004247A Expired - Fee Related CN101625893B (en) | 2008-07-09 | 2009-01-08 | Strap-contact scheme for compact array of memory cells |
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| Country | Link |
|---|---|
| US (1) | US7701767B2 (en) |
| CN (1) | CN101625893B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8780628B2 (en) * | 2011-09-23 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit including a voltage divider and methods of operating the same |
| US8513728B2 (en) * | 2011-11-17 | 2013-08-20 | Silicon Storage Technology, Inc. | Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates |
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| CN101625893A (en) | 2010-01-13 |
| US20100008141A1 (en) | 2010-01-14 |
| US7701767B2 (en) | 2010-04-20 |
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