CN101577271B - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
CN101577271B
CN101577271B CN2009101475149A CN200910147514A CN101577271B CN 101577271 B CN101577271 B CN 101577271B CN 2009101475149 A CN2009101475149 A CN 2009101475149A CN 200910147514 A CN200910147514 A CN 200910147514A CN 101577271 B CN101577271 B CN 101577271B
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substrate
semiconductor element
semiconductor
semiconductor device
film
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CN2009101475149A
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CN101577271A (en
Inventor
桑原秀明
高山彻
后藤裕吾
丸山纯矢
大野由美子
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

The invention provides a semiconductor device and its manufacturing method. The invention aims to provide a technology for manufacturing a semiconductor device which is low in cost, is less in volume, and is highly integrated. The technology is to manufacture a semiconductor device by transferring a semiconductor element, which is formed by using a semiconductor film, on a semiconductor element, which is formed by using a semiconductor substrate, by a transfer technology. Compared with a prior manufacturing method, a semiconductor device which is highly integrated can be mass-produced at a low cost and in high throughput, and the production cost per a semiconductor device can be controlled.

Description

Semiconductor device with and preparation method thereof
Application of the present invention be applicant of the present invention on December 26th, 2003 submit to, application number is 200310123567.X, denomination of invention is divided an application for the invention application of " semiconductor device with and preparation method thereof ".
Technical field
The present invention relates to highly integrated semiconductor device with and preparation method thereof.Exactly, the present invention relates to semiconductor device that a kind of semiconductor element that is integrated through its circuit of range upon range of stack (IC chip) obtains with and preparation method thereof.
Background technology
With mobile phone and electronic memo serves as typical portablely to be asked to have the various transmitting-receivings that comprise Email with electronic apparatus, and audio frequency identification is included image by minicam, utilizes functions such as the Internet.So, portable with electronic apparatus demand circuit scale and the bigger semiconductor device (encapsulation) of memory space.
On the other hand, portable with electronic apparatus from angle easy to carry, to the miniaturization of electronic apparatus volume, light and handyization, and the demand of cheapization of price has been goed deep into a step more.So just equal semiconductor device (encapsulation); The passive components of resistance etc.; Loading has proposed the requirement of miniaturization and cheapization with substrate etc.; And, accomplish almost and the semiconductor device (encapsulation) of bare chip same size that promptly wafer-level package CSP (Chip Size Package) also has been developed.(patent document 1)
So, just having had and improved the integrated multicore sheet encapsulation MCP (Multi ChipPackage) of semiconductor, this MCP will carry an encapsulation by integrated integrated circuit (IC chip) on a plurality of Semiconductor substrate.(patent document 2)
Patent document 1
The open Hei No.9-121002 of patent (P8-P10, Fig. 1)
Patent document 2
The open Hei No.5-90486 of patent (P2-P3, Fig. 1)
Multicore sheet encapsulation MCP comprises the integrated circuit (IC chip) that uses a plurality of Semiconductor substrate to form thereby transversely arrangedly improves integrated MCP.Yet transversely arranged a plurality of IC chips have caused the package area increase, have so just hindered to load dwindling with substrate.
In addition, the semiconductor device (encapsulation) that proposes in the patent document 2 is with a plurality of range upon range of and obtain with the integrated circuit (IC chip) of silicon chip (Semiconductor substrate) formation.The thickness of the IC chip that forms with silicon chip is thicker relatively, and as with these chip laminates stacks, though the area of encapsulation can reduce, the volume of encapsulation can increase, and consequently, has hindered light and handyization of the electronic apparatus that uses this encapsulation.
Therefore, in multicore sheet encapsulation MCP,, adopted and to have ground thin technology (grinding back surface (back grind)) with the I C chip that silicon chip forms for the volume that reduces to encapsulate.But,, and become the reason that the mechanical strength that causes semiconductor element reduces because the grinding technics of this grinding back surface can stay the grinding vestige of dark tens nm in silicon chip back.Its result, the problem that the grinding technics of this semiconductor element has caused rate of finished products to reduce.
And silicon chip is higher than the price of glass substrate, so range upon range of multilayer uses the semiconductor element of silicon chip to also have the problem of the cost up of every encapsulation unit.
Summary of the invention
To the problems referred to above, the purpose of this invention is to provide low cost, small size, and highly integrated semiconductor device.
The present invention provide a kind of on the insulating properties substrate range upon range of in order wiring portion, first semiconductor element, the manufacture method of the semiconductor device of second semiconductor element, it may further comprise the steps:
Form the integrated circuit of said first semiconductor element with Semiconductor substrate;
Bonding said first semiconductor element on said insulating properties substrate, the said wiring portion of the two therebetween;
Laminated metal film in order on the surface of first substrate, metal oxide film, dielectric film, semiconductive thin film;
Carry out heat treatment and come said metal oxide film of crystallization and said semiconductive thin film;
The semiconductive thin film of using this crystallization to cross forms the integrated circuit of said second semiconductor element;
With first adhesive bonding second substrate on said second semiconductor element, and this second substrate and said first substrate are faced one another;
Between the metal oxide film that said metal film and said crystallization are crossed, between the metal oxide film and said dielectric film that said crystallization is crossed, or in the metal oxide film that said crystallization is crossed, carry out and peel off with physical method;
Bonding said second semiconductor element on said first semiconductor element;
Remove said first adhesive;
Peel off said second substrate from said second semiconductor element;
Be electrically connected said first semiconductor element and said wiring portion, be electrically connected said second semiconductor element and said wiring portion then.
In addition, the present invention provide a kind of on the insulating properties substrate range upon range of in order wiring portion, first semiconductor element, the manufacture method of the semiconductor device of second semiconductor element, it may further comprise the steps:
Form the integrated circuit of said first semiconductor element with Semiconductor substrate;
Be connected electrically in the said wiring portion and said first semiconductor element that form on the said insulating properties substrate;
Laminated metal film in order on the surface of first substrate, metal oxide film, dielectric film, semiconductive thin film;
Carry out heat treatment and come said metal oxide film of crystallization and said semiconductive thin film;
The semiconductive thin film of using this crystallization to cross forms the integrated circuit of said second semiconductor element;
With first adhesive bonding second substrate on said second semiconductor element, and this second substrate and said first substrate are faced one another;
Between the metal oxide film that said metal film and said crystallization are crossed, between the metal oxide film and said dielectric film that said crystallization is crossed, or in the metal oxide film that said crystallization is crossed, carry out and peel off with physical method;
Bonding said second semiconductor element on said first semiconductor element;
Remove said first adhesive;
Peel off said second substrate from said second semiconductor element;
Be electrically connected said second semiconductor element and said wiring portion.
In addition, the present invention provide a kind of on the insulating properties substrate range upon range of in order first wiring portion, first semiconductor element, second wiring portion, the manufacture method of the semiconductor device of second semiconductor element, it may further comprise the steps:
Form the integrated circuit of said first semiconductor element with Semiconductor substrate;
Be connected electrically in said first wiring portion and said first semiconductor element that form on the said insulating properties substrate, then, on said first semiconductor element, form second wiring portion, the two therebetween dielectric film;
Laminated metal film in order on the surface of first substrate, metal oxide film, dielectric film, semiconductive thin film;
Carry out heat treatment and come said metal oxide film of crystallization and said semiconductive thin film;
The semiconductive thin film of using this crystallization to cross forms the integrated circuit of said second semiconductor element;
With first adhesive bonding second substrate on said second semiconductor element, and this second substrate and said first substrate are faced one another;
Between the metal oxide film that said metal film and said crystallization are crossed, between the metal oxide film and said dielectric film that said crystallization is crossed, or in the metal oxide film that said crystallization is crossed, carry out and peel off with physical method;
Bonding the 3rd substrate on said second semiconductor element, and the 3rd substrate and said second substrate are faced one another,
Remove said first adhesive;
Peel off said second substrate from said second semiconductor element;
Be electrically connected said second semiconductor element and said second wiring portion.
In addition, the present invention provide a kind of on the insulating properties substrate range upon range of in order wiring portion, second semiconductor element, the manufacture method of the semiconductor device of first semiconductor element, it may further comprise the steps:
Form the integrated circuit of said first semiconductor element with Semiconductor substrate;
Laminated metal film in order on the surface of first substrate, metal oxide film, dielectric film, semiconductive thin film;
Carry out heat treatment and come said metal oxide film of crystallization and said semiconductive thin film;
The semiconductive thin film of using this crystallization to cross forms the integrated circuit of said second semiconductor element;
With first adhesive bonding second substrate on said second semiconductor element, and this second substrate and said first substrate are faced one another;
Between the metal oxide film that said metal film and said crystallization are crossed, between the metal oxide film and said dielectric film that said crystallization is crossed, or in the metal oxide film that said crystallization is crossed, carry out and peel off with physical method;
Bonding said second semiconductor element on said first semiconductor element;
Remove said first adhesive;
Peel off second substrate from said second semiconductor element;
Bonding said second semiconductor element on said insulating properties substrate, the said wiring portion of the two therebetween;
Be electrically connected said second semiconductor element and said wiring portion, be electrically connected said first semiconductor element and said wiring portion then.
In addition, the present invention provide a kind of on the insulating properties substrate range upon range of in order wiring portion, second semiconductor element, the manufacture method of the semiconductor device of first semiconductor element, it may further comprise the steps:
Form the integrated circuit of said first semiconductor element with Semiconductor substrate;
Laminated metal film in order on the surface of first substrate, metal oxide film, dielectric film, semiconductive thin film;
Carry out heat treatment and come said metal oxide film of crystallization and said semiconductive thin film;
The semiconductive thin film of using this crystallization to cross forms the integrated circuit of said second semiconductor element;
With first adhesive bonding second substrate on said second semiconductor element, and this second substrate and said first substrate are faced one another;
Between the metal oxide film that said metal film and said crystallization are crossed, between the metal oxide film and said dielectric film that said crystallization is crossed, or in the metal oxide film that said crystallization is crossed, carry out and peel off with physical method;
Bonding said second semiconductor element on said first semiconductor element;
Remove said first adhesive;
Peel off said second substrate from said second semiconductor element;
Be connected electrically in the said wiring portion and said second semiconductor element that form on the said insulating properties substrate;
Be electrically connected said first semiconductor element and said wiring portion.
In addition, the present invention provide a kind of on the insulating properties substrate range upon range of in order first wiring portion, second semiconductor element, second wiring portion, the manufacture method of the semiconductor device of first semiconductor element, it may further comprise the steps:
Form the integrated circuit of said first semiconductor element with Semiconductor substrate;
Laminated metal film in order on the surface of first substrate, metal oxide film, dielectric film, semiconductive thin film;
Carry out heat treatment and come said metal oxide film of crystallization and said semiconductive thin film;
The semiconductive thin film of using this crystallization to cross forms the integrated circuit of said second semiconductor element;
With first adhesive bonding second substrate on said second semiconductor element, and this second substrate and said first substrate are faced one another;
Between the metal oxide film that said metal film and said crystallization are crossed, between the metal oxide film and said dielectric film that said crystallization is crossed, or in the metal oxide film that said crystallization is crossed, carry out and peel off with physical method;
Bonding the 3rd substrate on said second semiconductor element, and the 3rd substrate and said second substrate are faced one another;
Remove said first adhesive;
Peel off said second substrate from said second semiconductor element;
Be connected electrically in said first wiring portion and said second semiconductor element that form on the said insulating properties substrate, then, on said second semiconductor element, form second wiring portion, said the 3rd substrate of the two therebetween;
Be electrically connected said first semiconductor element and said second wiring portion.
Notice that above-mentioned Semiconductor substrate is monocrystalline substrate or compound semiconductor substrate, be typically to be selected from N type or p type single crystal silicon substrate, GaAs substrate, InP substrate, GaN substrate, SiC substrate, ZnSe substrate, GaP substrate, or a kind of in the InSb substrate.
In addition, above-mentioned semiconductive thin film comprises silicon.
Said first semiconductor element among the present invention comprises power circuit at least, transceiver circuit, memory, or a kind of in the amplifier of audio frequency treatment circuit.And said second semiconductor element among the present invention comprises the scan line drive circuit of pixel portion at least, signal-line driving circuit, controller, CPU, or a kind of in the converter of audio frequency treatment circuit.
In addition, said first adhesive of the present invention is the adhesive that can peel off.
Notice that above-mentioned insulating properties substrate comprises and is selected from polyimides, alumina, pottery, the material of glass epoxy resin.
The present invention provides a kind of semiconductor device, and it comprises:
Form first semiconductor element of integrated circuit with Semiconductor substrate;
With second semiconductor element of semiconductive thin film formation integrated circuit, wherein,
On the insulating properties substrate that said first semiconductor element and said second semiconductor element is stacked together, and the two therebetween organic resin or adhesive.
Notice that above-mentioned first semiconductor element is clipped between said second semiconductor element and the said insulating properties substrate.
In addition, said second semiconductor element is clipped between said first semiconductor element and the said insulating properties substrate.
Notice that the thickness of the film of above-mentioned second semiconductor element is equal to or less than 50 μ m, preferably in the scope of 0.1 μ m-1 μ m.
In addition, the semiconductor device processed according to this embodiment pattern can reduce be used for each semiconductor device form the semiconductor element of its integrated circuit by Semiconductor substrate, be typically the quantity of monocrystalline silicon integrated circuit.So, compare with conventional MCP, can use more low-cost, and a large amount of production in higher yield ground semiconductor device, and can reduce the production cost of each semiconductor device.
Through semiconductor device of the present invention is used for electronic apparatus; The bigger semiconductor device of circuit scale or memory capacity is loaded in the limited volume of electronic apparatus more; So not only can realize the multifunction of electronic apparatus; And can realize the small sizeization of electronic apparatus, light and handyization.The particularly portable electronic apparatus of using, because its small sizeization, light and handyization is much accounted of, and is effective so utilize semiconductor device of the present invention.
Semiconductor device of the present invention can be used in the controlling and driving liquid crystal display device; In its each pixel, providing with organic illuminating element is the luminescent device of typical light-emitting component, DMD (DMD, Digital Micromirror Device); PDP (plasma display panel; Plasma Display Panel), the various circuit of the display device of FED (electroluminescent display, FieldEmission Display) etc.
For example, at active-matrix liquid crystal display device, in the situation of luminescent device; Select the scan line drive circuit of each pixel, the signal-line driving circuit that vision signal arrives the time of selected pixel is presented in control, generates the controller of the signal that is fed to scan line drive circuit and signal-line driving circuit; The transducer of audio frequency treatment circuit etc. all forms with TFT, and, these circuit layers are stacked in the circuit that Semiconductor substrate such as handy silicon chip processes (are typically power circuit; Transceiver circuit; Memory, the amplifier of audio frequency treatment circuit) on, thereby the semiconductor device of acquisition stepped construction.
Electronic apparatus of the present invention not only comprises the aforementioned display device part, also comprises video camera, digital camera; Goggles formula display (head mounted display), navigation system, audio frequency replay device (automobile audio; Combined acoustics etc.), personal computer, game machine; Portable data assistance (portable computer, mobile phone, portable game machine; Or e-book etc.), be equipped with the image replay device (specifically DVD replay recording mediums such as (digital universal disc, DigitalVersatile Disc) and can show the device that is equipped with display of its image) of recording medium.Particularly, the present invention is being used to notebook field camera; Portable digital camera; Goggles formula display (head mounted display), portable data assistance (portable computer, mobile phone; Portable game machine, or e-book etc.) effective when being typical portable electronic appliance.
Description of drawings
Fig. 1 is the cross-sectional view of semiconductor device of the present invention;
Fig. 2 is the view of expression wiring portion of the present invention;
Fig. 3 A and 3B are respectively the vertical views of module of using the electronic apparatus of semiconductor device of the present invention, with and block diagram;
Fig. 4 A-4F is the sketch map of embodiment of the present invention pattern 1;
Fig. 5 A-5D is the sketch map of embodiment of the present invention pattern 2;
Fig. 6 A-6G is the sketch map of embodiment of the present invention mode 3;
Fig. 7 A-7E is the sketch map of embodiments of the invention 1;
Fig. 8 A-8D is the sketch map of embodiments of the invention 1;
Fig. 9 is the cross-sectional view of semiconductor device of the present invention.
Selection figure of the present invention is Fig. 1
The specific embodiments pattern
Hereinafter will be described in detail with reference to the attached drawings embodiment of the present invention pattern.The present invention can realize with various different embodiments, if those skilled in the art just is not difficult to find that under the situation that does not break away from aim of the present invention and scope thereof, scheme mode of the present invention and details can be changed into various forms.Therefore, the present invention can not be interpreted as and be defined in the context of describing in embodiment of the present invention pattern.
Embodiment pattern 1
Embodiment pattern 1
This embodiment pattern describes semiconductor device of the present invention with Fig. 1.Fig. 1 illustrates the cross-sectional view of semiconductor device of the present invention.On insulating properties substrate (built-in inserted plate) 101; The adhesive layer 103 of therebetween wiring layer 102 and hot pressing sheet etc.; The semiconductor element 104 of processing its integrated circuit with Semiconductor substrate is provided, and, on this semiconductor element 104; The adhesive layer 105 of therebetween hot pressing sheet etc. provides the semiconductor element 106 of processing its integrated circuit with semiconductive thin film.On the insulating properties substrate, formed contact hole (contact hole) 107, through the exterior terminal 108 of this contact hole connecting wiring layer 102 and solder ball etc.
Can adopt polyimide substrate, the alumina substrate, ceramic substrate, well-known materials such as glass epoxide substrate are as insulating properties substrate 101.In addition, in order to spread the heat that is created in the range upon range of integrated circuit, the material of this insulating properties substrate preferably has the high thermal conductivity about 2-30W/mK.
In addition, on the surface of semiconductor element, form electronic pads 109,110, and the terminal of this electronic pads 109,110 and wiring portion 102 links together through electric wire 111,113 respectively.In addition, electronic pads forms with aluminum or aluminum alloy.
Fig. 2 is the vertical view of expression wiring portion 102.Wiring portion 102 comprises: being used on insulating properties substrate 101 connects the metal gasket 221 of exterior terminal; And the terminal 222 that connects through the electronic pads on electric wire (Fig. 1 111,113) and the semiconductor element (Fig. 1 109,110), and this metal gasket 221 and terminal 222 223 link together through connecting up.In addition, wiring portion is to by copper, gold, and aluminium, the film that nickel or tin are made is implemented etching by desirable figure and is formed.In addition, the terminal of the electronic pads of semiconductor element and wiring portion is realized being connected through the circuit bonding method that uses pressure sintering or ultrasonic wave Method for bonding.Electric wire under this situation is to use by gold, contains the alloy of gold, copper or contain the metal fine that the alloy of copper forms.In addition, exterior terminal is to be used for connecting loading with the wiring of substrate and the wiring portion of semiconductor device, just is used for connecting the terminal that loads with substrate and semiconductor element.
Form the semiconductor element 104 use monocrystalline substrate of its integrated circuit or the FET (Field EffectTransistor) that compound semiconductor substrate forms field-effect transistor, bipolar transistor, memory element with Semiconductor substrate; Diode; Photo-electric conversion element, resistive element, coil (coil); The element of capacity cell and inductor etc., and with this element formation integrated circuit.In addition; Typical monocrystalline substrate comprises N type or p type single crystal silicon substrate (< 100>substrate, < 110>substrate, < 111>substrate etc.); And the exemplary compounds Semiconductor substrate comprises GaAs substrate, InP substrate, is used for the GaN substrate of GaN system extension, SiC substrate, ZnSe substrate, GaP substrate, InSb substrate.The typical semiconductor element that forms its integrated circuit with Semiconductor substrate comprises power circuit, transceiver circuit, memory, the amplifier of audio frequency treatment circuit.
The semiconductor element 106 that forms its integrated circuit with semiconductive thin film is to process integrated circuit with polysilicon film.Specifically, use thin-film transistor (TFT), memory element, diode, photo-electric conversion element, resistive element, coil, capacity cell and inductor etc. constitute integrated circuit.In addition; In the situation of display device; The semiconductor element that forms its integrated circuit with semiconductive thin film comprises the scan line drive circuit of selecting each pixel, and the signal-line driving circuit of vision signal to the timing of selected pixel, controller are presented in control; CPU, the transducer of audio frequency treatment circuit etc.
And; As shown in Figure 9, also can be on insulating properties substrate (built-in inserted plate) 101, the adhesive layer 103 of therebetween wiring layer 102 and hot pressing sheet etc.; The semiconductor element 106 that uses semiconductive thin film to form its integrated circuit is provided; And on this semiconductor element 106, the adhesive layer 105 of therebetween hot pressing sheet etc. provides the semiconductor element 104 that uses Semiconductor substrate to form its integrated circuit.
Note; In this embodiment pattern; The example that range upon range of two-layer semiconductor element forms semiconductor device has been described; But the present invention is not limited to this, uses the semiconductor element 104 that Semiconductor substrate forms and uses the film formed semiconductor element 106 of semiconductor film can be by range upon range of three layers or the structure of multilayer more.
In addition, in Fig. 1, described the example that a plurality of semiconductor elements are connected by electrical wiring to the wiring portion (terminal) that is provided at the insulating properties substrate respectively, but also can each semiconductor element be connected to each other together with electric wire.
Embodiment pattern 2
This embodiment pattern is with the relevant manufacture method at the semiconductor device shown in the embodiment pattern 1 of explanation.All semiconductor elements in the semiconductor device of this embodiment pattern are (face up) types that face up.
At first, with Fig. 4 A the manufacture method of using Semiconductor substrate to form the semiconductor element (first semiconductor element) of its integrated circuit is shown.On insulating properties substrate 411, form wiring portion 412, then the semiconductor element (first semiconductor element) 413 of adhesive layer 414 bonding its integrated circuits of use Semiconductor substrate formation through hot pressing sheet etc.To note, in order realizing being connected of exterior terminal and semiconductor element, on insulating properties substrate 411, to form contact hole (Figure 1A 107).In addition, exterior terminal is to be used to be electrically connected load with the wiring of substrate and the terminal of semiconductor element.With insulating properties substrate 411, wiring portion 412 is expressed as A1 with adhesive 414 fixing semiconductor element 413 grades that are made up of monocrystalline silicon.
Secondly, with Fig. 4 B-4D the manufacture method of using semiconductive thin film to form the semiconductor element (second semiconductor element) of its integrated circuit is shown.At first, such shown in Fig. 4 B, on substrate 401, form metal level 402.Material as metal level 402 can use from W Ti, Ta, Mo, Cr, Nd; Fe, Ni, Co, Zr, Zn, Ru; Rh, Pd, Os, the element of selecting among the Ir, or make the alloy material of main composition or the individual layer that compound-material is processed, the lamination of perhaps above-mentioned element or material with above-mentioned element; Or with above-mentioned nitride, such as titanium nitride, tungsten nitride, the individual layer that tantalum nitride, molybdenum nitride are processed or the lamination of this individual layer.In addition, the condition when the stripping technology of back is according to metal level alloy components in proportions or include in the ratio of the oxygen of metal level or nitrogen component and difference.So,, can make stripping technology be applicable to various processing through regulating the ratio of mentioned component.The thickness of the film of nitride layer or metal level 402 is in the scope of 10nm-200nm, preferably in the scope of 50nm-75nm.
Then, on metal level or nitride layer 402, form oxide skin(coating) 403.At this, between metal film 402 and oxide skin(coating) 403, form amorphous oxidized metal film (oxidation tungsten film) 405 that thickness is about 2nm-5nm.In follow-up stripping technology, in the film of oxidized metal, the contact-making surface of the contact-making surface of oxidized metal film and oxide skin(coating) or oxidized metal film and metal film produces and separates.Oxide skin(coating) 403 adopts silica, oxidized silicon nitride, and the oxidized metal material is made material, and forms with sputtering method.The thickness of the film of oxide skin(coating) 403 is about twice of nitride layer or metal level 402 or thicker preferably.Form the silicon oxide film of thick 150nm-200nm here, through sputtering method with silicon oxide target.
Then, on oxide skin(coating) 403, form the layer that contains hydrogen.Can adopt semiconductor layer or nitride layer as the layer that contains hydrogen.In this embodiment pattern, form first semiconductor layer 404 as the layer that contains hydrogen.Then, implement heat treatment and contain the hydrogen that contains in the material membrane of hydrogen with diffusion.This heat treatment can be carried out with the technology that forms the crystalloid semiconductive thin film respectively, or for save this heating treatment step can with the technology dual-purpose that forms the crystalloid semiconductive thin film.For example, under the amorphous silicon film that contains hydrogen was used as the film that contains hydrogen and is heated with the situation that forms polysilicon film, the heat treatment that is used for crystallization under 500 ℃ or the higher temperature can realize the formation of polysilicon film and the diffusion of hydrogen simultaneously.At this moment, metal oxide layer 405 conducts that are formed between metal level 402 and the oxide skin(coating) 403 have crystalline metal oxide interlayer dielectric film 435.
Then, shown in Fig. 4 C, use well-known method,, constitute by TFT (not expressing among the figure) so that form second semiconductor layer, 434, the second semiconductor layers 434 by desirable shape etch first semiconductor layer 404.At this moment, the thickness of the film of second semiconductor layer 434 is 50 μ m or thinner, preferably in the scope of 0.1 μ m-1 μ m.
Subsequently, with fix second substrate 406 as support of the 2nd semiconductor layer 434 of the adhesive 407 bonding usefulness that can be stripped from.In addition, second substrate 406 preferably adopts its intensity to be higher than the substrate of first substrate 401, preferred typical quartz substrate, metal substrate, ceramic substrate.Material as the adhesive that can be stripped from 407; Can adopt the adhesive of processing by organic material, such as reaction removable adhesive, heat-releasable adhesive; The photospallation type adhesive of UV removable adhesive etc., various removable adhesives such as anaerobism removable adhesive.In addition, adhesive 407 also can use the two-sided material that all has adhesive layer, and this adhesive layer is to form (typically such as two-sided tape, two-sided thin plate) by the adhesive that can be stripped from.
In Fig. 4 C, with first substrate 401 and the metal level 402 that forms above that be called and peel off body 450.And, will be called body 451 to be stripped from oxide skin(coating) 403 to second semiconductor layers 434 (that is, be clipped in metal level 402 and be used for fixing the layer between the adhesive that can be stripped from 407 of second substrate 406).
Secondly, shown in Fig. 4 D, tear with physical method and to peel off body 450 and body 451 to be stripped.In metal oxide layer 435, the contact-making surface of oxide skin(coating) 403 and metal oxide layer 435, perhaps the contact-making surface of metal oxide layer 435 and metal level 402 produces and separates, therefore with smaller power just can with peel off body 450 and body 451 to be stripped tear peel next.
According to above-mentioned technology, can separate body 451 to be stripped from peeling off body 450.At this, second substrate 404 that the adhesive 407 that uses body 451 to be stripped and can strip down from it is fixed is expressed as B1.
Secondly, cut apart second substrate and layer B1 to be stripped fixed thereon, form the layer to be stripped (hereinafter being expressed as C1) of shaped like chips.The layer to be stripped of shaped like chips comprises second semiconductor element.Second semiconductor layer 434 that second semiconductor element 1434 has been cut apart.In addition, go up fixed second half conductor element 1434 with adhesive 1407 at second substrate of having been cut apart (hereinafter being expressed as the 3rd substrate 1406).In addition, the opposition side with being fixed with second semiconductor element of adhesive 1407 is formed with oxide skin(coating) 1403 (oxide skin(coating) of having been cut apart 403).
Then, shown in Fig. 4 E, the fixing C1 shown in Fig. 4 D on the A1 shown in Fig. 4 A.Exactly, be formed on the surface of first semiconductor element 413 on the insulating properties substrate 411, with adhesive 421 bonding bodies 451 to be stripped, the specifically bonding oxide skin(coating) that is formed with second semiconductor element.In addition, between oxide skin(coating) 403 and adhesive 421,, can improve thermal diffusivity like the good material of folder thermal conductivity.
Importantly, be higher than with the adhesiveness of the bonding body to be stripped 451 of adhesive 421 and first semiconductor element 413 and use the second bonding substrate 406 of the adhesive that can peel off processed by organic material 407 and the adhesiveness of body 451 to be stripped.In addition, reaction constrictive type adhesive, the photo-hardening type adhesive of thermmohardening type adhesive, UV cured type etc., various constrictive type adhesives such as anaerobic type adhesive can be used as adhesive 421.In addition, adhesive 421 also can use the two-sided material that all has adhesive layer, and this adhesive layer is to form (typically such as two-sided tape, two-sided thin plate) by the adhesive that can be stripped from.
Then, shown in Fig. 4 F, peel off the 3rd substrate 1406 and the adhesive 1407 that can peel off as support from second semiconductor element 1434.Make the adhesive of processing by organic material that can peel off 1407 because of heat, light, humidity and produce reaction; Or chemical reaction (for example, water, oxygen); Like this, just can the 3rd substrate 1406 and the adhesive 1407 that can peel off be stripped down from second semiconductor element 1434.
Next, connect the electronic pads 422,423 of each semiconductor element and the terminal 424,425 of wiring portion with electric wire 426,427.At first; Electronic pads 423 and the terminal 424 of wiring portion that will be provided on first semiconductor element with the circuit juncture link together; Electronic pads 422 and the terminal 425 of wiring portion that will be provided on second semiconductor element through same technology then, link together.
Then, also can seal semiconductor element and electric wire with vacuum sealing mode or resin-sealed mode.When using vacuum sealing mode, the general pottery that uses, the box of metal or glass etc. seals.When using resin-sealed mode, specifically use shaping resin (moldresin).In this embodiment pattern; Because of second semiconductor element also plays a role as the protective layer of protection first semiconductor element; So not necessarily must sealing semiconductor element and electric wire; But, can increase the mechanical strength of semiconductor element, and stop from electromagnetic noise in abutting connection with circuit through sealing.After this, the terminal and the exterior terminal 429 of the contact hole connecting wiring part 412 through the insulating properties substrate.
According to above-mentioned technology; Can process the semiconductor device of laminated construction; This lamination comprises the semiconductor element that uses Semiconductor substrate to form its integrated circuit; Be typically the semiconductor element that uses monocrystalline substrate to form its integrated circuit, and use semiconductive thin film to form the semiconductor element of its integrated circuit, be typically the semiconductor element that uses polysilicon membrane to form its integrated circuit.
In addition, use identical technology, further range upon range of the 3rd semiconductor element on second semiconductor element, the 4th semiconductor element like this, can be made more highly integrated semiconductor device.In addition, the method for second semiconductor element being transferred to first semiconductor element is not limited to above-mentioned operation, also can use other operations.
The semiconductor device of processing according to this embodiment pattern is the semiconductor device that the range upon range of semiconductor element that is formed by integrated circuit forms; The part of the semiconductor element that the reason integrated circuit forms is to form with semiconductive thin film, so this semiconductor device has the characteristic of highly integrated and small size.
In addition, the semiconductor device processed according to this embodiment pattern can reduce be used for each semiconductor device form the semiconductor element of its integrated circuit by Semiconductor substrate, be typically the quantity of monocrystalline silicon integrated circuit.So, compare with conventional MCP, can use more low-cost, and a large amount of production in higher yield ground semiconductor device, and can reduce the production cost of each semiconductor device.
The embodiment mode 3
The semiconductor device that its structure and embodiment pattern 1 and embodiment pattern 2 are different will be described in this embodiment pattern.First semiconductor element of this embodiment pattern is flip chip structure (flip chip structure is claimed face down structure again), sees that from this point they are different with embodiment pattern 2.
The cross-sectional view of the semiconductor device of this embodiment pattern at first, is shown with Fig. 5 A-5D.Wiring portion 502 on insulating properties substrate 501, the electronic pads 504 of first semiconductor element of being processed by Semiconductor substrate 503 links together with the splicing ear 505 of projection etc.In addition, with the wiring portion 502 that forms on fixing first semiconductor element 503 such as resin and insulating properties substrate 501 and the insulating properties substrate.In addition, be formed with the contact hole (not illustrating) that connects exterior terminal and semiconductor element on the insulating properties substrate 501, link together with exterior terminal in this contact hole place wiring portion 502.In addition, exterior terminal links together with the wiring of loading with substrate.With insulating properties substrate 501, the electronic pads 504 of wiring portion 502, the first semiconductor elements 503, projection 505, resin 506 grades of fixing these are expressed as A2.
Then, carry out the technology identical, with second semiconductor element 1434 shown in the semiconductor film formation Fig. 4 E that is fixed on the 3rd substrate 1406 with embodiment pattern 2.The no more than 50 μ m of the thickness of the film of second semiconductor element 1434 at this moment, preferably 0.1-1 μ m.In addition, with the adhesive that can peel off 1407 fixing the 3rd substrates 1406 with film formed second semiconductor element 1434 of semiconductor.(the 3rd substrate and second semiconductor element that is fixed on the 3rd substrate are expressed as C1) (Fig. 5 B).
Secondly, the C1 with Fig. 5 B is fixed on the A2 of Fig. 5 A with adhesive 511.Specifically, with adhesive 511 bonding oxidation film layer 1403 that is formed with second semiconductor element on the surface that is formed at first semiconductor element 503 on the insulating properties substrate 501.In addition, as at oxide skin(coating) 1403 and the high material of adhesive 511 therebetween thermal conductivitys, can improve thermal diffusivity.After this, carry out the technology identical, peel off as the 3rd substrate 1406 of support and the adhesive 1407 that can peel off from second semiconductor element 1434 with embodiment pattern 1.(Fig. 5 C)
Then, shown in Fig. 5 D, the electronic pads 512 of second semiconductor element 1434 and the terminal 513 of wiring portion 502 are linked together by electric wire 514.Afterwards, also can carry out the technology identical, the integrated circuit 434,503 and the electric wire 514 of insulating properties substrate 501 laminated sealed with embodiment pattern 2.Then, the electronic pads and the exterior terminal 516 of connecting wiring part 502 at the contact hole place of insulating properties substrate 501.
According to above-mentioned technology; Can process the semiconductor device of laminated construction; This lamination comprises the semiconductor element that uses Semiconductor substrate to form its integrated circuit; Be typically the semiconductor element that uses monocrystalline substrate to form its integrated circuit, and use semiconductor film to form the semiconductor element of its integrated circuit, be typically the semiconductor element that uses polysilicon membrane to form its integrated circuit.
The semiconductor device of processing according to this embodiment pattern is the semiconductor device that stacked integrated circuit forms; The part of the semiconductor element that the reason integrated circuit forms is to form with semiconductive thin film, so this semiconductor device has the characteristic of highly integrated and small size.
In addition, the semiconductor device processed according to this embodiment pattern can reduce be used for each semiconductor device form the semiconductor element of its integrated circuit by Semiconductor substrate, be typically the quantity of monocrystalline silicon integrated circuit.So, compare with conventional MCP, can use more low-cost, and a large amount of production in higher yield ground semiconductor device, and can reduce the production cost of each semiconductor device.
Also have,, can be reduced so be used to connect the number of electrical lines of terminal of electronic pads and the wiring portion of integrated circuit, so can make the littler semiconductor device of volume because of the integrated circuit that uses Semiconductor substrate to process is the flip-chip form.
Embodiment pattern 4
The manufacture method of the semiconductor device that its structure is different with embodiment pattern 1 to embodiment mode 3 will be described in this embodiment pattern.All integrated circuits of this embodiment pattern all are the flip-chip forms, see from this point, and they are different with embodiment pattern 2 and embodiment mode 3.
The cross-sectional view of the semiconductor device of this embodiment pattern at first, is shown with Fig. 6 A-6G.First semiconductor element 503 with Semiconductor substrate formation integrated circuit shown in Fig. 6 A has the structure identical with the embodiment mode 3 (A2 among Fig. 5 A); It has insulating properties substrate 501; First wiring portion 502; The electronic pads 504 of first semiconductor element 503, projection 505, and the resin 506 of fixing above-mentioned parts etc.
Secondly, shown in Fig. 6 B, therebetween insulating barrier 601 forms second wiring portion 602 on first semiconductor element.
Then, carry out the technology identical, second semiconductor layer 434 that constitutes by integrated circuit with the semiconductor film formation that is fixed on second substrate 406 with embodiment pattern 2.In addition, form second semiconductor layer 434 that constitutes by integrated circuit with the adhesive that can peel off 407 fixing second substrates 406 with semiconductor film.(second substrate and second semiconductor element that is fixed on second substrate are expressed as B1) (Fig. 6 C).
Secondly, shown in Fig. 6 D, the B1 of Fig. 6 C is fixed on the 4th substrate 603 with adhesive 604.Specifically, with adhesive 604 bonding oxidation film layer 403 that is formed with second semiconductor layer 434 on the 4th substrate 603.The 4th substrate 603 can adopt glass, organic resin, and metal, plastics, or pottery etc. is as backing material.Film through using thin film thickness can reduce the volume of semiconductor device as the 4th substrate.In addition, in order to improve thermal diffusivity, the 4th substrate preferably adopts the DLC (Diamond Like Carbon) such as diamond-like-carbon, copper, the material that thermal conductivitys such as aluminium are high.
Then, peel off second substrate 406 and the adhesive 407 that can peel off from second semiconductor layer 434 as support.After this, preferably clean is carried out on the surface of the electrode wiring that comes out from the surface of second integrated circuit etc. or oxygen plasma treatment cleans its surface.Then, cut apart the 4th substrate, thereby form the semiconductor element of shaped like chips.At this, with the 4th substrate (hereinafter being referred to as the 5th substrate 1604) of shaped like chips, and second semiconductor element of transferring on it 1434 is expressed as C2 (Fig. 6 E).In addition, on second semiconductor element 1434, be bonded in oxidation film layer 1403 and the 5th substrate 1604 that its surface forms with adhesive layer.
Then, shown in Fig. 6 F, the bonding second semiconductor element C2 on the first semiconductor element A3.Specifically, while aim at the position of the electronic pads 605 of second wiring portion 602 and second semiconductor component surfaces and carry out bonding with adhesive.In this embodiment pattern, apply pressure to second wiring portion 602 that forms on the surface of first semiconductor element and the electronic pads 605 of second semiconductor component surfaces with the ACF (Anisotropic Conductive Film) of anisotropic conductive film or anisotropic conductive polymer (Anisotropic Conductive Polymer) 606.
Then, shown in Fig. 6 G, the electronic pads and the exterior terminal 608 of connecting wiring part 502 at the contact hole place of insulating properties substrate 501.
According to above-mentioned technology, can process the semiconductor device of laminated construction, this lamination comprises the semiconductor element that uses Semiconductor substrate to form its integrated circuit, and uses semiconductive thin film to form the semiconductor element of its integrated circuit.
The semiconductor device of processing according to this embodiment pattern is the semiconductor device that stacked integrated circuit forms; The part of the semiconductor element that the reason integrated circuit forms is to form with semiconductive thin film, so this semiconductor device has the characteristic of highly integrated and small size.
In addition, the semiconductor device processed according to this embodiment pattern can reduce be used for each semiconductor device form the semiconductor element of its integrated circuit by Semiconductor substrate, be typically the quantity of monocrystalline silicon integrated circuit.So, compare with conventional MCP, can use more low-cost, and a large amount of production in higher yield ground semiconductor device, and can reduce the production cost of each semiconductor device.
Also have,, do not use the electric wire of the terminal of the electronic pads that connects semiconductor element and wiring portion, so can make the littler semiconductor device of volume because of the semiconductor element of all semiconductor device of processing in this embodiment pattern all is the flip-chip form.The 3rd substrate adopt have insulating properties such as glass, organic resin, or pottery etc. is during as backing material, because of the surface insulation of semiconductor device, so need not use shaping resin to seal.Therefore, can make the littler semiconductor device of volume.
Embodiment
Embodiment 1
The example of the manufacture method of the semiconductor device that present embodiment obtains according to the technology shown in the embodiment pattern 1 with Fig. 7 and Fig. 8 explanation, this semiconductor device are the range upon range of integrated circuit of being made by monocrystalline substrate (first integrated circuit) and the integrated circuit (second integrated circuit) made by polysilicon film and the lamination that constitutes.
Shown in Fig. 7 A; (thickness of film is 10nm-200nm to go up the formation tungsten film with sputtering method in glass substrate (first substrate 700); Preferred 50nm-75nm) as metal film 701; Then, under the situation that is not exposed to atmosphere, formation and stack silicon oxide film (thickness of film is 150nm-200nm) 702 are as oxide-film.Between tungsten film 701 and silicon oxide film 702, form amorphous oxidation tungsten film 703 that thickness is about 2nm-5nm here.Note,, preferably use O because sputtering method can form film at edges of substrate 2Tungsten film and the silicon oxide film that is formed on edges of substrate optionally disposed in ashing etc.In follow-up stripping technology, the contact-making surface of tungsten film and oxidation tungsten film, in the oxidation tungsten film or the generation of the contact-making surface of oxidation tungsten film and silicon oxide film separate.
In addition, metal film 701 also can utilize the alloy that contains tungsten, and for example the W-Mo alloy replaces tungsten film, regulates the component ratio of this alloy and controls the easy degree of peeling off.In addition, also can be with ion implantation technique or ion doping technique, peel off the difficulty that becomes thereby nitrogen-doping made in the oxidation film, thereby or oxygen element is doped to make in the oxidation film to peel off becomes easy.
Then, form oxygen silicon nitride membrane (thickness of film is 100nm, does not express among the figure), form and range upon range of amorphous silicon film 704 (thickness of film is 54nm) and not in being exposed to atmosphere as underlying insulation film with the PCVD method.
Then, can adopt known crystallization technology (for example solid state growth or laser crystallization, and the crystallization method that utilizes metallic catalyst) to form polysilicon film.Then, form polysilicon region, make then with the TFT (p channel-type TFT 705,708 and n channel-type TFT 706,707) of this polysilicon region as the active region thereby implement pattern by desirable shape., suitably form gate insulating film here, form gate electrode, and form source/drain regions to the active region, form interlayer dielectric then, form source electrode or drain electrode, and implement to activate and handle through impurity.
Present embodiment adopts and utilizes the crystallization method of metallic catalyst to obtain polysilicon film.Exactly, doped metallic elements Ni is to amorphous silicon film, and carries out 550 ℃ of following heat treatments of 4 hours.This Technology for Heating Processing has also realized the crystallization of oxidation tungsten film 703 simultaneously.Then, improve the crystallinity of this polysilicon film with continuous oscillation type laser irradiation polysilicon film, and, by desirable shape etch polysilicon film and make the scanning direction of raceway groove length direction and laser beam of TFT consistent.Use such polysilicon film can obtain the high-field effect mobilance as the TFT of active region.In addition, mutual combination p channel-type TFT 705 and n channel-type TFT 706, thereby and p channel-type TFT 708 and n channel-type TFT 707 formation cmos circuits (Fig. 7 B).
Then, form interlayer dielectric 709, form wiring 710,711 that contact hole and formation is connected in TFT then as electronic pads (Fig. 7 C).
Then, shown in Fig. 7 D, the jointing material 721 of water soluble or alcohols is coated in whole surface, and carries out roasting.Anyly in epoxy resin, acrylic resin, the silicones etc. can constitute above-mentioned adhesive.At this, with spin-applied by water-soluble resin (the synthetic system in East Asia: the film of VL-WSHL10) processing (thickness of film is 30 μ m) 721, carry out realizing formal curing after the primary solidification.
Implemented easily for the stripping technology that makes the back, following technology is used for the adhesiveness that part reduces tungsten film 701 and silicon oxide film 702.Being used for part, to reduce fusible processing be laser radiation; Wherein shine tungsten film 701 or silicon oxide film 702 along the peripheral part of wanting stripping area with laser; Or apply local pressure from the outside along the peripheral part of wanting stripping area, with the part in the layer that damages silicon oxide film 702 or the part of interface.Specifically, vertically depress hard pin, and the limit is moved said layer limit and is applied load with diamond pen etc.Preferably use the scriber device and volume under pressure is located at 1mm, exert pressure in limit so that said layer is moved on the limit.By this way before peel off to the part of easy peeling off phenomenon, implement selectivity (partly) and reduce fusible preliminary treatment, it is important promptly causing mechanism, thereby having avoided peeling off fails and has improved rate of finished products.
Then, the bonding medium (two-sided thin plate) that can peel off of use 722 is pasted film 721 to second substrates of being processed by water-soluble resin 723.And the bonding medium that use can be peeled off (two-sided thin plate) 722 is pasted the 3rd substrate to first substrate 700 (not expressing among the figure).The 3rd substrate protective first substrate 700 is injury-free in the technology of back.Second lining the 723rd and the 3rd serves as a contrast the and preferably adopts the higher substrate of strength ratio first substrate 700, such as, quartz substrate etc.
Then, shown in Fig. 7 E, reduce fusible zone from part and begin to peel off, peel off first substrate 700 that provides tungsten film 701 with physical method.Utilize less power with regard to peelable substrate (for example, utilize people's hand, utilize the blow pressure of nozzle blow gas, utilize ultrasonic, or the like).In the present embodiment, the contact-making surface of silicon oxide film and oxidation tungsten film produces and separates.According to above-mentioned steps, the integrated circuit of processing by polysilicon film that can form from separation of oxygenated silicon fiml on first substrate 700 702.In addition, tungsten oxide is as remaining in the surface of silicon oxide film 702, and therefore the bonding force between the silicon oxide film 702 and first integrated circuit might diminish, so, improve bonding force thereby remove this residue fully with methods such as etchings.After this, cut apart second substrate 723, form second integrated circuit.
Then, shown in Fig. 8 A, on insulating properties substrate 730, form wiring portion 731, with adhesive first integrated circuit of being processed by monocrystalline substrate 734 is installed on this insulating properties substrate and wiring portion then.Note,, on insulating properties substrate 730, form contact hole in order to realize exterior terminals such as connecting wiring part 731 and solder ball.
Said wiring portion is according to the alloy formation pattern of photolithographicallpatterned with gold.
And first integrated circuit adopts the FET of known technology formation field-effect transistor, and forms integrated circuit with this FET.Present embodiment forms the also NMOSFET (N-channel metaloxide semiconductor FET) 735 of mutual combination n channel metal oxide semiconductor field effect transistor on monocrystalline substrate 750; 736 with the PMOSFET (P-channel metal oxide semiconductor FET) 737 of P-channel metal-oxide-semiconductor field-effect transistor; 738, thus CMOS (Complementary MOS) circuit of formation complementary type MOS.Note the NMOSFET 735,736 and PMOSFET 737 shown in the present embodiment; The 738th, by source/drain regions 752,753, gate electrode 754 and interlayer dielectric 755; (, being that the typical case illustrates) of 756 formations with NMOSFET735 at this, and; The electronic pads of the wiring that is used for being connected with each FET (Fig. 8 A 739,740) exposes the surface from the interlayer dielectric velum.And the oxidized film 751 of each FET separates.Local Oxidation of Silicon method) or trench isolations method (trench isolation) the formation method of said oxide-film can use the selective oxidation method (to claim the selective oxidation method again, i.e. the LOCOS method:.
Note; On with semi-conductive substrate, form under the situation of NMOSFET and PMOSFET; Conductive region with the conductivity that is different from substrate (trap) just need be provided; Its method comprises the P trap system, wherein on N type substrate, forms the P trap, is forming the N channel transistor on the P trap and on N type substrate, is forming p channel transistor; The N trap system wherein forms the N trap on P type substrate, forming p channel transistor on the N trap and on P type substrate, forming the N channel transistor; And two trap systems, on N type or P type substrate, form N trap and P trap, form p channel transistor on the N trap and on the P trap, forming the N channel transistor.And, though the FET with a channel formation region is shown, be not restricted to this, and FET can have a plurality of raceway grooves.
Then, shown in Fig. 8 B, with jointing material 741 bonding silicon oxide layer 1702 that is formed with second integrated circuit on first integrated circuit of processing with silicon substrate 734.In addition, second integrated circuit is the cmos circuit that on silicon oxide layer 1702, forms, and is formed with electronic pads.Also have, be fixed with second substrate (hereinafter being called the 3rd substrate 1723) that has separated with the bonding medium that can peel off 1722 with water-soluble binder 1721 on this surface.Importantly, be higher than with bonding the 3rd substrate 1723 of water-soluble resin 1721 and the bonding medium that can peel off 1722 and the adhesiveness of second integrated circuit with the adhesiveness of the bonding silicon oxide layer 1702 of jointing material 741 and first integrated circuit 734.Present embodiment uses bonding thin plate as jointing material 741, Yi Bian and the position of aiming at first and second integrated circuits make its not coated electrode pad 739,740, Yi Bian implement bonding.
Then, shown in Fig. 8 C, behind bonding medium (two-sided thin plate) 1722 separation the 3rd substrate 1723 that can peel off, peel off the bonding medium (two-sided thin plate) 1722 that to peel off from water-soluble resin 1721.In addition, also can two-sided thin plate and the two while of the 3rd substrate be peeled off from water-soluble resin together.
Then, water dissolves water-soluble resin 1721 and disposes this water-soluble resin 1721.If water-soluble resin is arranged by residual, can become the reason of substandard products, so preferably through clean or O at this 2Plasma treatment cleans the surface of electronic pads 710,711.
Then, shown in Fig. 8 D, the electronic pads 739 on first integrated circuit; 740 are electrically connected through electric wire 743,744 respectively with the terminal 741,742 of wiring portion; Then, the terminal 745 of electronic pads on second integrated circuit 710,711 and wiring portion; 746 are electrically connected through electric wire 747,748 respectively.
Through above step, can make the range upon range of and semiconductor device that forms of integrated circuit (second integrated circuit) that the integrated circuit (first integrated circuit) processed by monocrystalline substrate and polysilicon film process.
Embodiment 2
Present embodiment is an example with the mobile phone of one of electronic apparatus of the present invention, with the actual situation of being carried electronic apparatus of Fig. 3 A explanation encapsulation.
The module of the mobile phone that Fig. 3 A representes is on printed substrate 816, to carry to be laminated in the CPU 802 (zone 802/811 among Fig. 3 A) on the memory 811; Power circuit 803 is laminated in the controller 801 (field 801/829 among Fig. 3 A) on the audio frequency treatment circuit 829, transceiver circuit 804; And other; Resistance, buffer, elements such as capacity cell.In addition, screen board (panel) 800 adheres to each other through FPC 808 (flexible print circuit, Flexible PrintedCircuit) and printed substrate 816.The pixel cell 805 that light-emitting component is provided at each pixel is installed on the screen board 800, selects the scan line drive circuit 806 of the pixel that this pixel cell 805 has, present the signal-line driving circuit 807 of sound signal to selected pixel.
(interface I/F) 809 is fed to printed substrate 816 for supply voltage and the routine interface used through the printed substrate that is equipped with a plurality of input terminals from the various signals of keyboard input.In addition, be used for and antenna between the antenna port (antenna port) 810 of signal transmitting and receiving letter be provided at printed substrate 816.
In addition, present embodiment is connected to screen board 800 on the printed substrate 816 with FPC 808, yet not necessarily must be this structure.Also can adopt glass film plates to upload the COG of chip (ChipOn Glass) mode, direct piggyback controller 801 on screen board 800, audio frequency treatment circuit 829, memory 811, CPU 802 or power circuit 803.
And, in printed substrate 816, exist and be formed on the resistance that capacitor and wiring itself between each wiring have, can cause the noise of supply voltage and signal thus or the signal transmission is slowed up.Therefore, the various elements such as capacitor or buffer are provided on printed substrate 816, slow up so that prevent the noise of supply voltage and signal or anti-stop signal transmission.
Fig. 3 B is the block diagram of the module shown in Fig. 3 A.
In the present embodiment, memory 811 comprises VRAM 832, and DRAM 825, flash memory (flash memory) 826.VRAM 832 storages are presented at the view data on the screen board, DRAM825 storing image data or audio data, the various programs of flash memory 826 storages.Along with the raising of memory span, the area of loading also enlarges, so the most handy monocrystalline silicon piece is made memory.
Power circuit 803 is given screen board 800, controller 801, and CPU 802, audio frequency treatment circuit 829, memory 811, transceiver circuit 804 provides supply voltage.In addition, according to the specification of screen board, power circuit 803 also can be equipped with power supply.Power circuit has stable control to screen board, controller, the function of supplying electric currents such as CPU.So, can be suitable as this element through the bipolar transistor of a large amount of electric currents, the consequently the most handy silicon chip manufacturing of power circuit.
CPU 802 has control signal generative circuit 820, decoder 821, and register circuit 822, calculation circuit 823, RAM 824, the interface that CPU uses (interface) 835 etc.After the various signals that are input to CPU 802 through interface 835 temporarily are stored in register circuit 822, be imported into calculation circuit 823, decoder 821 etc.Calculation circuit 823 performs calculations according to the signal that input comes, and specifies the place of transmitting various command then.On the other hand, the signal that is input to decoder 821 is fed among the control signal generative circuit 82O after decoder 821 places are decrypted.Control signal generative circuit 820 generates the signal that comprises various instructions according to the signal that input comes; This signal is fed to the place by 823 appointments of calculation circuit, specifically, is fed to memory 811; Transceiver circuit 804, audio frequency treatment circuit 829 and controller 801 or the like.Make CPU through using as the TFT of active region, can make its reduced thickness with polysilicon.
Memory 811, transceiver circuit 804, audio frequency treatment circuit 829 and controller 801 operate according to the instruction that receives separately.Hereinafter is put up with its running and is carried out simple declaration.
Be fed to the CPU 802 of lift-launch on printed substrate 816 from the signal of keyboard 831 inputs through routine interface 809.Control signal generative circuit 820 converts the view data that is stored in VRAM 832 into predetermined format, and is fed to controller 801 according to the signal from keyboard 831 inputs.
Controller 801 cooperates the specification of screen board to carry out data processing to present the signal that comprises view data that comes from CPU 802, and the signal that will handle then is fed to screen board 800.Controller 801 generates the Hsync signal according to from the supply voltage of power circuit 803 inputs or the various signals of importing from CPU, the Vsync signal, and clock signal clk, alternating voltage (AC Cont), and be fed to screen board 800.Controller can use with the TFT of polysilicon as the active region and make.
Transceiver circuit 804 is handled the signal as electric wave that antenna 833 is received and dispatched, and transceiver circuit 804 specifically comprises isolator, band pass filter; VCO (voltage controlled oscillator; VoltageControlled Oscillator), LPF (low pass filter, Low Pass Filter); Coupler, the high-frequency circuit of balanced-to-unblanced transformer (balun) etc.Transceiver circuit 804 with the signal that comprises audio-frequency information in the receiving and transmitting signal, is fed to audio frequency treatment circuit 829 according to the instruction of CPU802.Transceiver circuit is because of comprising high-frequency circuit, so be to process with GaAs Semiconductor substrate or silicon chip.
Be fed the signal that comprises audio-frequency information that comes according to the instruction of CPU802 and in audio frequency treatment circuit 829, be demodulated to sound signal, and be fed to loud speaker 828.In addition, modulated audio frequency treatment circuit 829 from the sound signal that microphone 827 sends, and be sent to transceiver circuit 804 according to the instruction of CPU802.The audio frequency treatment circuit is to be formed by amplifier and transducer.Because of the inhomogeneous meeting of the characteristic of amplifier badly influences from the tonequality of loud speaker output, so amplifier preferably adopts the few silicon chip of its inhomogeneous characteristic.On the other hand, can make transducer, can make its reduced thickness like this with the TFT that polysilicon forms.
The semiconductor device of making according to embodiment 1 can be applied to be layered in the CPU 802 (zone 802/811 among Fig. 3 A) on the memory 811, or is applied to be layered in the controller 801 (zone 801/829 among Fig. 3 A) on the audio frequency treatment circuit 829.Notice that though present embodiment shows the semiconductor device with said structure, the present invention is not limited to this structure.For example, also can adopt following stepped construction, be about to the circuit (controller 801 that the enough TFT of ability form; CPU 802, the transducer of audio frequency treatment circuit 829, the scan line drive circuit 806 of the pixel of selection pixel portion; Present the signal-line driving circuit 807 of sound signal to selected pixel) random layer is stacked in the circuit that Semiconductor substrate such as handy silicon chip processes and (is typically power circuit 803; Transceiver circuit 804, memory 811, the amplifier of audio frequency treatment circuit 829) on.
Semiconductor device constructed in accordance is that the semiconductor element that is formed by integrated circuit is range upon range of and form, because of it forms the part of this semiconductor element with semiconductive thin film, so the characteristic of this semiconductor device is highly integrated and small size.
In addition, the semiconductor device processed according to this embodiment pattern can reduce be used for each semiconductor device form the semiconductor element of its integrated circuit by Semiconductor substrate, be typically the quantity of monocrystalline silicon integrated circuit.So, compare with conventional MCP, can use more low-cost, and a large amount of production in higher yield ground semiconductor device, and can reduce the production cost of each semiconductor device.
And, through being applicable to power circuit, transceiver circuit with the semiconductor element that Semiconductor substrate forms its integrated circuit; The high-frequency circuit of the amplifier of memory or audio frequency treatment circuit etc., high density integrated circuit having or high power capacity circuit, and; Through being applicable to controller with the semiconductor element that semiconductive thin film forms its integrated circuit; CPU, the transducer of audio frequency treatment circuit, select pixel portion pixel scan line drive circuit or present the circuit that sound signal forms to the enough TFT of ability of the signal-line driving circuit of selected pixel etc.; Can make volume littler (just small size adds low clearance); Function is more increased the semiconductor device of (be typically increase memory capacity etc.), so can in the limited volume of electronic apparatus, carry this semiconductor device more, so not only can realize the multifunction of electronic apparatus; And can realize the small sizeization of electronic apparatus, light and handyization.The particularly portable electronic apparatus of using, because of its small sizeization, light and handyization is much accounted of, and is effective so utilize semiconductor device of the present invention.

Claims (6)

1. semiconductor device comprises:
The insulating properties substrate that comprises first wiring portion, a plurality of contact hole and exterior terminal, wherein said first wiring portion and said exterior terminal are connected in a plurality of contact holes of said insulating properties substrate;
First semiconductor element that comprises Semiconductor substrate; Wherein said first semiconductor element is formed on the said insulating properties substrate; And accompany resin in the middle of the two; And said first semiconductor element is electrically connected to said first wiring portion via first electronic pads, between said first electronic pads and said first wiring portion, projection is set;
Be formed on second wiring portion on said first semiconductor element, accompany insulating barrier in the middle of the two; With
Second semiconductor element that comprises a plurality of thin-film transistors and second electronic pads; Wherein said second semiconductor element is formed on the said insulating barrier; And wherein said second electronic pads is connected to said second wiring portion via the anisotropic conductive electrostrictive polymer, and said anisotropic conductive polymer is clipped between said second electronic pads and said second wiring portion.
2. according to the semiconductor device of claim 1, wherein this Semiconductor substrate is one of monocrystalline substrate and compound semiconductor substrate.
3. according to the semiconductor device of claim 1, wherein said first semiconductor element comprises power circuit at least, transceiver circuit, a kind of in the amplifier of memory and audio frequency treatment circuit.
4. according to the semiconductor device of claim 1, wherein said second semiconductor element comprises the scan line drive circuit of pixel portion at least, signal-line driving circuit, controller, CPU, a kind of in the converter of audio frequency treatment circuit.
5. according to the semiconductor device of claim 1, wherein said insulating properties substrate comprises and is selected from polyimides, alumina, pottery, the material of glass epoxy resin.
6. according to the semiconductor device of claim 1, wherein said a plurality of contact holes are full of a plurality of solder balls.
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Families Citing this family (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7442629B2 (en) 2004-09-24 2008-10-28 President & Fellows Of Harvard College Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate
US7057256B2 (en) 2001-05-25 2006-06-06 President & Fellows Of Harvard College Silicon-based visible and near-infrared optoelectric devices
SG121707A1 (en) 2002-03-04 2006-05-26 Micron Technology Inc Method and apparatus for flip-chip packaging providing testing capability
SG111935A1 (en) 2002-03-04 2005-06-29 Micron Technology Inc Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
US7436050B2 (en) 2003-01-22 2008-10-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a flexible printed circuit
JP4526771B2 (en) * 2003-03-14 2010-08-18 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP2005109068A (en) * 2003-09-30 2005-04-21 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
US8048251B2 (en) 2003-10-28 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing optical film
CN100583193C (en) 2003-11-28 2010-01-20 株式会社半导体能源研究所 Manufacturing method of display device
US7130234B2 (en) * 2003-12-12 2006-10-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7405665B2 (en) * 2003-12-19 2008-07-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, RFID tag and label-like object
US7508305B2 (en) * 2003-12-26 2009-03-24 Semiconductor Energy Laboratory Co., Ltd. Packing material, tag, certificate, paper money, and securities
KR100541655B1 (en) * 2004-01-07 2006-01-11 삼성전자주식회사 Package circuit board and package using thereof
WO2005069204A1 (en) * 2004-01-16 2005-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7915723B2 (en) * 2004-01-29 2011-03-29 Casio Computer Co., Ltd. Transistor array, manufacturing method thereof and image processor
WO2005103180A1 (en) * 2004-04-20 2005-11-03 Hitachi Chemical Co., Ltd. Adhesive sheet, semiconductor device and process for producing semiconductor device
US8123896B2 (en) * 2004-06-02 2012-02-28 Semiconductor Energy Laboratory Co., Ltd. Laminating system
US7465654B2 (en) 2004-07-09 2008-12-16 Megica Corporation Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US8022544B2 (en) 2004-07-09 2011-09-20 Megica Corporation Chip structure
US7591863B2 (en) * 2004-07-16 2009-09-22 Semiconductor Energy Laboratory Co., Ltd. Laminating system, IC sheet, roll of IC sheet, and method for manufacturing IC chip
US7452803B2 (en) 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US8288773B2 (en) 2004-08-23 2012-10-16 Semiconductor Energy Laboratory Co., Ltd. Wireless chip and manufacturing method thereof
JP4649198B2 (en) * 2004-12-20 2011-03-09 新光電気工業株式会社 Wiring board manufacturing method
US7307006B2 (en) * 2005-02-28 2007-12-11 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
KR101241066B1 (en) * 2005-05-20 2013-03-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Manufacturing method of semiconductor device
JP2006344824A (en) 2005-06-09 2006-12-21 Nec Electronics Corp Semiconductor device and method for manufacturing semiconductor device
US20060289981A1 (en) * 2005-06-28 2006-12-28 Nickerson Robert M Packaging logic and memory integrated circuits
CN102157494B (en) 2005-07-22 2013-05-01 米辑电子股份有限公司 Wiring assembly
JP2007048958A (en) * 2005-08-10 2007-02-22 Renesas Technology Corp Semiconductor device and manufacturing method thereof
KR101319468B1 (en) * 2005-12-02 2013-10-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Manufacturing method of semiconductor device
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7692295B2 (en) * 2006-03-31 2010-04-06 Intel Corporation Single package wireless communication device
US7785938B2 (en) * 2006-04-28 2010-08-31 Semiconductor Energy Laboratory Co., Ltd Semiconductor integrated circuit, manufacturing method thereof, and semiconductor device using semiconductor integrated circuit
JP5034332B2 (en) * 2006-06-14 2012-09-26 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
JP4302720B2 (en) * 2006-06-28 2009-07-29 株式会社沖データ Semiconductor device, LED head, and image forming apparatus
JP2008053319A (en) * 2006-08-22 2008-03-06 Nec Electronics Corp Semiconductor device
TW201820190A (en) * 2007-03-05 2018-06-01 美商泰拉創新股份有限公司 Semiconductor chip
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7759629B2 (en) * 2007-03-20 2010-07-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US8253526B2 (en) * 2007-05-07 2012-08-28 Texas Instruments Incorporated Termination compensation for differential signals on glass
US9059247B2 (en) * 2007-05-18 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
US8358005B2 (en) * 2007-06-04 2013-01-22 International Rectifier Corporation Packaged gallium nitride material transistors and methods associated with the same
CN101122382B (en) * 2007-08-24 2012-12-05 黎昌兴 LED energy-saving lamp heat radiator
US9271398B2 (en) * 2008-02-18 2016-02-23 Cyntec Co., Ltd. Power supply module
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
JP5518381B2 (en) * 2008-07-10 2014-06-11 株式会社半導体エネルギー研究所 Color sensor and electronic apparatus including the color sensor
KR101739709B1 (en) 2008-07-16 2017-05-24 텔라 이노베이션스, 인코포레이티드 Methods for cell phasing and placement in dynamic array architecture and implementation of the same
JP5581106B2 (en) * 2009-04-27 2014-08-27 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US9911781B2 (en) 2009-09-17 2018-03-06 Sionyx, Llc Photosensitive imaging devices and associated methods
US9673243B2 (en) 2009-09-17 2017-06-06 Sionyx, Llc Photosensitive imaging devices and associated methods
DE112011101135B4 (en) * 2010-03-29 2021-02-11 X-Celeprint Limited Electrically connected fields of active components in transfer printing technology
US9161448B2 (en) 2010-03-29 2015-10-13 Semprius, Inc. Laser assisted transfer welding process
US8692198B2 (en) 2010-04-21 2014-04-08 Sionyx, Inc. Photosensitive imaging devices and associated methods
US20120146172A1 (en) 2010-06-18 2012-06-14 Sionyx, Inc. High Speed Photosensitive Devices and Associated Methods
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9496308B2 (en) 2011-06-09 2016-11-15 Sionyx, Llc Process module for increasing the response of backside illuminated photosensitive imagers and associated methods
EP2732402A2 (en) 2011-07-13 2014-05-21 Sionyx, Inc. Biometric imaging devices and associated methods
US20130168792A1 (en) * 2011-09-16 2013-07-04 Sionyx, Inc. Three Dimensional Architecture Semiconductor Devices and Associated Methods
US9412727B2 (en) 2011-09-20 2016-08-09 Semprius, Inc. Printing transferable components using microstructured elastomeric surfaces with pressure modulated reversible adhesion
US9064764B2 (en) 2012-03-22 2015-06-23 Sionyx, Inc. Pixel isolation elements, devices, and associated methods
KR102091687B1 (en) 2012-07-05 2020-03-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Light-emitting device and method for fabricating the same
KR102173801B1 (en) 2012-07-12 2020-11-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Display device and method for manufacturing display device
US11074025B2 (en) 2012-09-03 2021-07-27 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
WO2014127376A2 (en) 2013-02-15 2014-08-21 Sionyx, Inc. High dynamic range cmos image sensor having anti-blooming properties and associated methods
US9939251B2 (en) 2013-03-15 2018-04-10 Sionyx, Llc Three dimensional imaging utilizing stacked imager devices and associated methods
WO2014209421A1 (en) 2013-06-29 2014-12-31 Sionyx, Inc. Shallow trench textured regions and associated methods
JP6545976B2 (en) 2014-03-07 2019-07-17 株式会社半導体エネルギー研究所 Semiconductor device
US11472171B2 (en) 2014-07-20 2022-10-18 X Display Company Technology Limited Apparatus and methods for micro-transfer-printing
CN105528598B (en) * 2014-09-29 2019-03-29 上海箩箕技术有限公司 Optical fingerprint sensor
US9704821B2 (en) 2015-08-11 2017-07-11 X-Celeprint Limited Stamp with structured posts
JP6917700B2 (en) 2015-12-02 2021-08-11 株式会社半導体エネルギー研究所 Semiconductor device
US10748793B1 (en) 2019-02-13 2020-08-18 X Display Company Technology Limited Printing component arrays with different orientations

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1169593A (en) * 1995-11-29 1998-01-07 株式会社日立制作所 Semiconductor device and electronic device using same
CN1276090A (en) * 1997-10-30 2000-12-06 株式会社日产制作所 Semiconductor device and method for manufacturing the same
CN1344026A (en) * 2000-09-21 2002-04-10 三洋电机株式会社 Multi-chip assembly
US6376904B1 (en) * 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5948950A (en) 1982-09-13 1984-03-21 Agency Of Ind Science & Technol Manufacture of three-dimensional integrated circuit structure
JPH0344067A (en) * 1989-07-11 1991-02-25 Nec Corp Laminating method of semiconductor substrate
JP3043484B2 (en) 1991-09-30 2000-05-22 ローム株式会社 Semiconductor device
US5614766A (en) * 1991-09-30 1997-03-25 Rohm Co., Ltd. Semiconductor device with stacked alternate-facing chips
US5643804A (en) * 1993-05-21 1997-07-01 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a hybrid integrated circuit component having a laminated body
US6107213A (en) 1996-02-01 2000-08-22 Sony Corporation Method for making thin film semiconductor
JP3364081B2 (en) * 1995-02-16 2003-01-08 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP3406727B2 (en) * 1995-03-10 2003-05-12 株式会社半導体エネルギー研究所 Display device
US5757456A (en) 1995-03-10 1998-05-26 Semiconductor Energy Laboratory Co., Ltd. Display device and method of fabricating involving peeling circuits from one substrate and mounting on other
JP3176542B2 (en) 1995-10-25 2001-06-18 シャープ株式会社 Semiconductor device and manufacturing method thereof
WO1997038444A1 (en) * 1996-04-08 1997-10-16 Hitachi, Ltd. Semiconductor integrated circuit device
EP1758169A3 (en) * 1996-08-27 2007-05-23 Seiko Epson Corporation Exfoliating method, transferring method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device produced by the same
KR100447035B1 (en) * 1996-11-21 2004-09-07 가부시키가이샤 히타치세이사쿠쇼 Manufacturing process of semiconductor device
JP3809733B2 (en) * 1998-02-25 2006-08-16 セイコーエプソン株式会社 Thin film transistor peeling method
JP2001102523A (en) * 1999-09-28 2001-04-13 Sony Corp Thin-film device and manufacturing method therefor
JP2001196529A (en) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp Semiconductor device and wiring method therefor
JP2001257307A (en) * 2000-03-09 2001-09-21 Sharp Corp Semiconductor device
EP2988331B1 (en) * 2000-08-14 2019-01-09 SanDisk Technologies LLC Semiconductor memory device
US6599818B2 (en) * 2000-10-10 2003-07-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device manufacturing method, heat treatment apparatus, and heat treatment method
JP4061846B2 (en) * 2001-01-23 2008-03-19 セイコーエプソン株式会社 Laminated body manufacturing method and semiconductor device manufacturing method
JP2002299587A (en) * 2001-03-30 2002-10-11 Mitsubishi Electric Corp Semiconductor integrated circuit device and method of manufacturing the same
JP3839323B2 (en) * 2001-04-06 2006-11-01 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
JP4449258B2 (en) * 2001-06-15 2010-04-14 ソニー株式会社 Electronic circuit device and manufacturing method thereof
US7030488B2 (en) * 2001-10-30 2006-04-18 Intel Corporation Packaged combination memory for electronic devices
US6833287B1 (en) * 2003-06-16 2004-12-21 St Assembly Test Services Inc. System for semiconductor package with stacked dies

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1169593A (en) * 1995-11-29 1998-01-07 株式会社日立制作所 Semiconductor device and electronic device using same
CN1276090A (en) * 1997-10-30 2000-12-06 株式会社日产制作所 Semiconductor device and method for manufacturing the same
US6376904B1 (en) * 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
CN1344026A (en) * 2000-09-21 2002-04-10 三洋电机株式会社 Multi-chip assembly

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开平11-3969A 1999.01.06

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US7037752B2 (en) 2006-05-02

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