CN101576864B - Computer system and data signal processing method of memory interface thereof - Google Patents
Computer system and data signal processing method of memory interface thereof Download PDFInfo
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- CN101576864B CN101576864B CN2008100952930A CN200810095293A CN101576864B CN 101576864 B CN101576864 B CN 101576864B CN 2008100952930 A CN2008100952930 A CN 2008100952930A CN 200810095293 A CN200810095293 A CN 200810095293A CN 101576864 B CN101576864 B CN 101576864B
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Abstract
The invention relates to a computer system and a data signal processing method of a memory interface thereof, wherein the computer system comprises a memory module, a memory controller and a digital signal processor; the memory controller stores data which is temporarily stored in the memory module through a data bus; and the digital signal processor processes variant data generated on the data bus according to a group of option codes and reduces the data.
Description
Technical field
The present invention relates to a kind of data signal processing method of memory interface, particularly relate to the data signal processing method of a kind of computer system and memory interface thereof.
Background technology
In recent years, along with progressing greatly of semi-conductive technology, (centralprocessing unit, manufacturing CPU) also evolves to nanometer (nano-meter) technology by deep-sub-micrometer (deep sub-micron) technology to central processing unit.Therefore, the function scale of central processing unit not only can increase thereupon, and its frequency of operation also must be tending towards speeding, and so will help to promote the work efficiency of computer system integral body.In order to want successfully to promote the task performance of computer system integral body, generally can utilize memory modules (memory module) to assist central processing unit, using provides its temporary required data.
Yet, because memory modules and the Memory Controller Hub (memorycontroller that controls its access action, be built in the north bridge chips in general) between the two the mode of Data transmission be directly by printed circuit board (PCB) (printable circuit board mostly, PCB) data bus (data bus) that the Copper Foil lead (coppertrace) on is constituted transmits, so be limited by the ghost effect (stray inductance for example of these Copper Foil leads, stray capacitance ... etc.) influence, carry out at central processing unit under the situation of high speed data delivery, the data of being transmitted on the data bus will produce serious decay (decay) and phase deviation variations such as (phase shift).
And above-mentioned phenomenon not only can cause Memory Controller Hub can't interpretation from the correctness of the stored data of memory modules, moreover also have the data that also can cause Memory Controller Hub to desire to write to memory modules to make a mistake.Therefore, for irrational variation takes place in the data of wanting to suppress on the data bus effectively and being transmitted, a reasonable value exactly will be in reasonable range be obtained with the frequency of operation of central processing unit in unavoidable ground, the situation that morphs of data just can ease up by this, but so the practice also can cause the overclocking of Memory Controller Hub range limited many, and then has suppressed the amplitude of computer system overall work enhancing efficiency.
Summary of the invention
In view of this, the invention provides the data signal processing method of a kind of computer system and memory interface thereof, to improve the disappearance of prior art.
The present invention proposes a kind of computer system, comprises memory modules, Memory Controller Hub, South Bridge chip and digital signal processor.Above-mentioned digital signal processor couples memory modules, Memory Controller Hub and South Bridge chip respectively.Digital signal processor and on the data transfer path between Memory Controller Hub and the memory modules is to come the signal of being exported by Memory Controller Hub is carried out signal Processing according to the pairing mode of operation of an option code.Above-mentioned option code is what set according to the frequency of operation of central processing unit.
From another viewpoint, the present invention proposes a kind of data signal processing method of memory interface, and this data signal processing method is applicable between Memory Controller Hub and the memory modules.Above-mentioned data signal processing method comprises: receive the data-signal of a decay, and the data-signal of decay is to be formed by first data-signal decay that Memory Controller Hub is exported; Come the data-signal of decay is carried out signal Processing according to the pairing mode of operation of an option code, to obtain second data-signal; And transmitting second data-signal to this memory modules, wherein above-mentioned option code is relevant with the frequency of operation of central processing unit.
Beneficial effect of the present invention.The embodiment of the invention is serially connected with the transmission road of internal memory control module and Memory Controller Hub data bus between the two through last with digital signal processor, use the data that morph that compensate on data bus to be transmitted, and make it return to state originally, so the amplitude that computer system that the embodiment of the invention provides can make the overclocking scope computer system overall efficiency applied with it of Memory Controller Hub promote is neither limited again.
For above-mentioned feature and advantage of the present invention can be become apparent, several embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1 shows that the calcspar of the computer system of first embodiment of the invention.
Figure 2 shows that the calcspar of the computer system of second embodiment of the invention.
Fig. 3 shows the process flow diagram of data signal processing method of the memory interface of preferred embodiment of the present invention.
Embodiment
One of technology effect that preferred embodiment of the present invention is desired to reach mainly is for the ghost effect of the Copper Foil lead of the motherboard that will the solve computer system influence to data transfer; Another then is for the overclocking scope that will promote Memory Controller Hub computer system overall efficiency applied with it.And following content will encyclopaedize at the technical characterictic of preferred embodiment of the present invention, considers and examines to offer those skilled in the art.
Figure 1 shows that the calcspar of the computer system of first embodiment of the invention.Please refer to Fig. 1, the computer system 1 that present embodiment provided comprises motherboard 10, north bridge chips 110, digital signal processor (DSP) 120, memory modules 130, South Bridge chip 140, Basic Input or Output System (BIOS) 150, reaches central processing unit (CPU) 160.
In the present embodiment, north bridge chips 110 built-in Memory Controller Hub 111.In other embodiments, Memory Controller Hub 111 can be incorporated in the central processing unit 160 of computer system 1.In other embodiments, north bridge chips 110 also can be incorporated in the central processing unit 160 of computer system 1, and Memory Controller Hub 111 also is incorporated into central processing unit 160.
Above-mentioned north bridge chips 110 couples digital signal processor 120, South Bridge chip 140 respectively, reaches central processing unit 160.Memory Controller Hub 111 in north bridge chips 110 also couples digital signal processor 120 and memory modules 130.Above-mentioned digital signal processor 120 also couples memory modules 130 and South Bridge chip 140 respectively.South Bridge chip 140 also couples Basic Input or Output System (BIOS) 150.
Above-mentioned Basic Input or Output System (BIOS) 150 is a Nonvolatile memory, and it stores Basic Input or Output System (BIOS) (BIOS) program code of computer system 1.The bios program code of the Basic Input or Output System (BIOS) 150 that this enforcement provided can be adjusted the frequency of operation of central processing unit 160, this action that is " overclocking " that be commonly called as.In addition, above-mentioned Basic Input or Output System (BIOS) 150 can write down the frequency of operation of controlled central processing unit 160.
Above-mentioned South Bridge chip 140 can read the frequency of operation of the central processing unit 160 that is stored in the Basic Input or Output System (BIOS) 150.South Bridge chip 140 also produces an option code SEL according to frequency of operation that it read, and (general purpose input outputsystem GPIO) is transferred to digital signal processor 120 by general input-output system then.
In the present embodiment, above-mentioned South Bridge chip 140 can utilize look-up table to produce option code SEL.For example: when the frequency of operation that South Bridge chip 140 reads central processing unit 160 is 1GHz, then South Bridge chip 140 can utilize a built-in form (this form can be stored in the Basic Input or Output System (BIOS) 150) to inquire about and the corresponding option code SEL of 1GHz frequency of operation, for example: " 000 ".If when the frequency of operation of central processing unit 160 was 1.5GHz, option code SEL was " 001 ".By this, South Bridge chip 140 just can produce option code SEL according to the frequency of operation of the central processing unit 160 that is read, and again this option code SEL is sent to digital signal processor 120 then.
Above-mentioned digital signal processor 120 has a compensating module, and this compensating module can utilize hardware means to implement or software approach is implemented.In the present embodiment, compensating module is to utilize software approach to implement, it has a plurality of mode of operations, each mode of operation is corresponding with a kind of option code SEL, that is digital signal processor 120 is when receiving different option code SEL, just can change the mode of operation of compensating module according to the option code SEL that is received, and utilize the mode of operation relevant to carry out signal Processing with the option code SEL that is received.
In the present embodiment, above-mentioned option code SEL comprises 3 bits (bit), and in other embodiments, above-mentioned option code SEL also can be 1 bit or 2 bits, and its figure place is relevant with a plurality of mode of operations of compensating module.
Figure 2 shows that the calcspar of the computer system of second embodiment of the invention.The computer system 1 that present embodiment provided comprises motherboard 10, north bridge chips 110, digital signal processor (DSP) 120, memory modules 130, South Bridge chip 140, Basic Input or Output System (BIOS) 150, central processing unit (CPU) 160, reaches super I/O chip 210.
Each element that present embodiment provided and function square are all similar with first embodiment.But present embodiment also provides super I/O chip 210, and it couples South Bridge chip 140 and digital signal processor 120 respectively.In first embodiment, the mode of operation of the compensating module of digital signal processor 120 is controlled by South Bridge chip 140, and in a second embodiment, the mode of operation of the compensating module of digital signal processor 120 then is by super I/O chip 210 controls.
Fig. 3 shows the process flow diagram of data signal processing method of the memory interface of preferred embodiment of the present invention.The explanation of relevant present embodiment please be in the lump with reference to Fig. 1 and Fig. 3.In computer system 1, Memory Controller Hub 111 one of the most important component devices on motherboard 10 or the whole computer system 1 of can saying so.What the function of Memory Controller Hub 111 was supervision and control data from memory modules 130 is written into/exports (input ﹠amp; Output).In addition, in certain embodiments, Memory Controller Hub 111 also can detect (Data integration verification) to the integrality of data.
In this embodiment, memory interface comprises Memory Controller Hub 111 and memory modules 130, and the data signal processing method that present embodiment provided can carry out signal Processing to the data-signal between Memory Controller Hub 111 and the memory modules 130.
Memory Controller Hub 111 transmission of data signals are to memory modules 130, or Memory Controller Hub 111 is during by memory modules 130 reading of data, by memory modules 130 transfer to Memory Controller Hub 111 data-signal may (for example: relation Copper Foil) produces signal attenuation because of the data bus on the motherboard 10.Present embodiment is to be example with Memory Controller Hub 111 transmission of data signals to memory modules 130, with the restoring data signal, to transfer to memory modules 130.
In step S305, Memory Controller Hub 111 transmission first data-signal is to memory modules 130.Can signal attenuation when the data bus of this first data-signal on motherboard 10 transmits.Therefore, the digital signal processor 120 on the data transfer path between Memory Controller Hub 111 and the memory modules 130 can receive the data-signal of a decay.The data-signal of this decay is to be formed by first data-signal decay that Memory Controller Hub 111 is exported.
In step S305, digital signal processor 120 can be selected the mode of operation of its compensating module according to South Bridge chip 140 or super I/O chip (other embodiment) the option code SEL that is exported.For example: when the frequency of operation of central processing unit 160 was 1.5GHz at present, then option code SEL was " 001 ".Digital signal processor 120 just can be selected the corresponding mode of operation of compensating module for " 001 " according to option code SEL.
Then, after digital signal processor 120 receives the data-signal of decay, just can come the data-signal of decay is carried out signal Processing according to the pairing mode of operation of option code SEL (" 001 "), for example: the signal reduction be handled, to obtain one second data-signal.In the present embodiment, the waveform of second data-signal, frequency, and phase place etc. equal first data-signal that Memory Controller Hub 111 is exported in fact.
In the present embodiment, the signal processing mode of above-mentioned digital signal processor 120 following state bright.At first, digital signal processor 120 receives after the data-signal of decay, can utilize the data-signal of itself included analogy digital quantizer sampling decay earlier, and with its digitizing.Then, 120 digital data conversion that are sampled to of digital signal processor are to frequency domain.And utilize option code to select appropriate operating mode and reduce the variation of the data that it received.At last, digital signal processor 120 is changed these data again to time domain, and is sent to memory modules 130.
In step S315, digital signal processor 120 transmits second data-signal to memory modules 130.
In addition, if when the frequency of operation of central processing unit 160 changes (that is central processing unit 160 is by overclocking), can store the frequency of operation of change in the Basic Input or Output System (BIOS) 150.Described as above-mentioned explanation, South Bridge chip 140 can read new frequency of operation by basic input-output unit 150, and produces new option code SEL and be transferred to digital signal processor 120.That is to say that even if the frequency of operation of central processing unit 160 is dynamically adjusted, also corresponding its mode of operation of adjusting of the digital signal processor 120 of data variation by way of compensation is to finish the effect of compensation.
In sum, the present invention utilizes digital signal processor to compensate and reduces the data of data bus between memory modules and Memory Controller Hub.Digital signal processor wherein and can cooperate the frequency of operation of central processing unit dynamically, adjust pairing built-in compensation program, make computer system and motherboard can be under multiple different frequency of operation operate as normal, and then promote its task performance.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with the claim of this area.
Claims (5)
1. a computer system is characterized in that, comprising:
Memory modules;
Memory Controller Hub;
South Bridge chip couples above-mentioned Memory Controller Hub, sets option code with the frequency of operation of foundation central processing unit; And
Digital signal processor, couple above-mentioned memory modules, above-mentioned Memory Controller Hub and above-mentioned South Bridge chip respectively, and on the data transfer path between above-mentioned Memory Controller Hub and the above-mentioned memory modules, handle to come that according to the pairing mode of operation of above-mentioned option code the signal of being exported by above-mentioned Memory Controller Hub is carried out recovering signal.
2. computer system according to claim 1 is characterized in that, the data-signal of wherein above-mentioned digital signal processor receiving attenuation, the data-signal of above-mentioned decay are to be formed by the data-signal decay that above-mentioned Memory Controller Hub is exported.
3. computer system according to claim 2 is characterized in that, wherein above-mentioned digital signal processor reduces to the data-signal of above-mentioned decay, is resent to above-mentioned memory modules.
4. computer system according to claim 1 is characterized in that, also comprises Basic Input or Output System (BIOS), couples above-mentioned South Bridge chip, in order to set and to store the frequency of operation of above-mentioned central processing unit.
5. the data signal processing method of a memory interface is executed between Memory Controller Hub and the memory modules, it is characterized in that, above-mentioned data signal processing method comprises:
The data-signal of receiving attenuation, and the data-signal of above-mentioned decay is to be formed by first data-signal decay that above-mentioned Memory Controller Hub is exported;
Come the data-signal of above-mentioned decay is carried out the recovering signal processing according to the pairing mode of operation of option code, to obtain second data-signal; And
Transmit above-mentioned second data-signal to above-mentioned memory modules,
Wherein above-mentioned option code is relevant with the frequency of operation of central processing unit.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1707384A (en) * | 2004-06-04 | 2005-12-14 | 华硕电脑股份有限公司 | Main machine board and control method thereof |
| US7039755B1 (en) * | 2000-05-31 | 2006-05-02 | Advanced Micro Devices, Inc. | Method and apparatus for powering down the CPU/memory controller complex while preserving the self refresh state of memory in the system |
| CN1828478A (en) * | 2005-03-05 | 2006-09-06 | 鸿富锦精密工业（深圳）有限公司 | Main board double data rate power supply circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7039755B1 (en) * | 2000-05-31 | 2006-05-02 | Advanced Micro Devices, Inc. | Method and apparatus for powering down the CPU/memory controller complex while preserving the self refresh state of memory in the system |
| CN1707384A (en) * | 2004-06-04 | 2005-12-14 | 华硕电脑股份有限公司 | Main machine board and control method thereof |
| CN1828478A (en) * | 2005-03-05 | 2006-09-06 | 鸿富锦精密工业（深圳）有限公司 | Main board double data rate power supply circuit |
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