CN101540306B - Semiconductor wafer encapsulation body and encapsulation method thereof - Google Patents
Semiconductor wafer encapsulation body and encapsulation method thereof Download PDFInfo
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- CN101540306B CN101540306B CN2008100830435A CN200810083043A CN101540306B CN 101540306 B CN101540306 B CN 101540306B CN 2008100830435 A CN2008100830435 A CN 2008100830435A CN 200810083043 A CN200810083043 A CN 200810083043A CN 101540306 B CN101540306 B CN 101540306B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 191
- 238000000034 method Methods 0.000 title claims description 45
- 238000005538 encapsulation Methods 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 239000004020 conductor Substances 0.000 claims abstract description 24
- 239000010410 layer Substances 0.000 claims description 113
- 239000002184 metal Substances 0.000 claims description 85
- 229910052751 metal Inorganic materials 0.000 claims description 85
- 230000004888 barrier function Effects 0.000 claims description 82
- 238000009434 installation Methods 0.000 claims description 69
- 239000013078 crystal Substances 0.000 claims description 59
- 239000011241 protective layer Substances 0.000 claims description 49
- 239000003292 glue Substances 0.000 claims description 43
- 238000012856 packing Methods 0.000 claims description 28
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 24
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 230000002520 cambial effect Effects 0.000 claims description 6
- 239000011247 coating layer Substances 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 claims description 5
- 238000003466 welding Methods 0.000 abstract 6
- 238000004519 manufacturing process Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Packaging Frangible Articles (AREA)
Abstract
The invention relates to a semiconductor wafer encapsulation body, which comprises a semiconductor substrate, an insulating layer, a plurality of conductors, an upper covering layer, a lower covering layer, and a plurality of external circuit connecting points, wherein the semiconductor substrate is provided with a welding pad mounting surface provided with a welding pad, a back surface opposite to the mounting surface, and a plurality of semicircular holes formed on two lateral surfaces of the substrate; the insulating layer is formed on the welding pad mounting surface of the substrate, and the insulating layer is provided with a plurality of through holes for exposing the corresponding welding pad of the substrate, and semicircular holes aligned to the semicircular holes on the two lateral surfaces of the substrate; the plurality of conductors are respectively extended to a predetermined position of the back surface of the substrate from a corresponding welding pad through a corresponding semicircular hole; the upper covering layer is formed on the welding pad mounting surface of the substrate, and the upper covering layer is provided with a plurality of exposing holes for exposing partial corresponding conductors; the lower covering layer is formed on the back surface of the substrate, and the lower covering layer is provided with a plurality of exposing holes for exposing partial corresponding conductors; and the plurality of external circuit connecting points are respectively formed in a corresponding exposing hole on the upper covering layer.
Description
Invention field
The present invention is about a kind of semiconductor chip package and method for packing thereof, more particularly, and about a kind of semiconductor chip package that is suitable for being stacked and method for packing thereof.
Background technology
Microminiaturization is that electronic installation continues the trend of carrying out, and to employed semiconductor memory body in electronic installation, stacked structures is wherein a kind of microminiaturized mode that promotes.Yet being electrically connected because of meeting between thickness after the integral stacked and layer and the layer influences whole height and electrical characteristic respectively so is the key of stacked structures superiority and inferiority.
Summary of the invention
The objective of the invention is for a kind of semiconductor chip package and method for packing thereof are provided.
According to a characteristic of the present invention; A kind of semiconductor chip package is to be provided; It comprises: a semiconductor substrate, its have a pad installation surface, back surface relative with this upper surface, several be formed at weld pad on this upper surface, and several be formed on the roughly semi-circular hole on both side surface of this semiconductor substrate; Insulating barrier on pad installation surface that is formed at this semiconductor substrate, this insulating barrier are to be formed with the through hole of several corresponding pad that are used to expose to the open air this semiconductor substrate and the roughly semi-circular hole of aiming at the roughly semi-circular hole on the both side surface of this semiconductor substrate; Several respectively extend to the conductor in precalculated position on the back surface of this semiconductor substrate via the semi-circular hole of correspondence from a corresponding pad; Upper caldding layer on pad installation surface that is formed on this semiconductor substrate, this upper caldding layer are to be formed with the exposing hole that several are used to expose to the open air the part of corresponding conductor; A back lip-deep lower caldding layer that is formed on this semiconductor substrate, this lower caldding layer are to be formed with the exposing hole that several are used to expose to the open air the part of corresponding conductor; And several respectively are formed on the interior external circuit connecting points of exposing hole of a correspondence of this upper caldding layer.
According to another characteristic of the invention, a kind of semiconductor chip package is to be provided, and it comprises: a semiconductor substrate, and it has a pad installation surface and several are formed at the weld pad on this upper surface; Insulating barrier on pad installation surface that is formed at this semiconductor substrate, this insulating barrier are to be formed with the through hole that several are used to expose to the open air the corresponding pad of this semiconductor substrate, and have oblique edge surface so that it has a trapezoidal cross-section; A lead cambium layer that is formed on this insulating barrier; This lead cambium layer is to be formed with the perforation that several each through holes corresponding with one of this insulating barrier are communicated with and expose to the open air the part of this insulating barrier, and this lead cambium layer also has oblique edge surface in order to do forming continuous edge surface with the corresponding edge surface of this insulating barrier; Be filled in the through hole and the interior conducting metal glue of the cambial perforation of this lead of this insulating barrier of connection; One covers the cambial insulating protective layer of this lead, and this insulating protective layer is the exposing hole that is formed with a part that is used to expose to the open air corresponding conducting metal glue; And several respectively are formed on the interior external circuit connecting points of exposing hole of a correspondence of this protective layer.
According to another feature again of the present invention, a kind of semiconductor chip package is to be provided, and it comprises: a semiconductor substrate, its have a pad installation surface, back surface relative with this upper surface, and several be formed at the weld pad on this upper surface; Pad installation surface that is formed at this semiconductor substrate, the lip-deep insulating coating of side surface and back, this insulating coating are to be formed with the through hole that several are used to expose to the open air the corresponding pad of this semiconductor substrate; Several respectively extend to the conductor in precalculated position on the back surface of this semiconductor substrate from a corresponding pad; One be formed on this insulating coating at the coating layer on the pad installation surface of semiconductor substrate part upper caldding layer in order to do the conductor part on the pad installation surface that can cover this semiconductor substrate, this upper caldding layer is to be formed with the exposing hole that several are used to expose to the open air the part of corresponding conductor; One be formed on this insulating coating the back lip-deep coating layer part of semiconductor substrate in order to do the conductor part on the back surface that can cover this semiconductor substrate lower caldding layer, this lower caldding layer is to be formed with the exposing hole that several are used to expose to the open air the part of corresponding conductor; And several respectively are formed on the interior external circuit connecting points of exposing hole of a correspondence of insulating barrier on this.
According to another feature more of the present invention; A kind of method for packing of semiconductor chip package is to be provided; It comprises following step: a semiconductor crystal wafer is provided; This semiconductor crystal wafer has several semiconductor die panel region, and each semiconductor die panel region comprises a semiconductor substrate, each semiconductor substrate have a pad installation surface, back surface relative with this pad installation surface, and several be installed on the weld pad on this pad installation surface; The pad installation surface of these semiconductor substrates forms the pad installation surface of this semiconductor crystal wafer jointly, and the back surface of these semiconductor substrates forms the back surface of this semiconductor crystal wafer jointly; On the pad installation surface of this semiconductor crystal wafer, form an insulating barrier in order to do can covering these weld pads, this insulating barrier be by exposure with develop that to be formed with several through holes that are used to expose to the open air corresponding pad be the perforation of aiming at line of cut with several along arrangement of wafer line of cut and middle body; On this insulating barrier, form a lead cambium layer in order to do can covering these weld pads, this lead cambium layer is to be formed with several respectively and corresponding through hole and the perforation that is communicated with corresponding perforation by exposure with developing; The perforation that on the matrix of this wafer, forms several each perforations connections corresponding with one of insulating barrier is so that the perforation of the aligning of the matrix of wafer and insulating barrier is to form through hole jointly; With these through holes of conducting metal glue filling, these perforation and by the formed through hole of aiming at of perforation; On the back surface of this semiconductor crystal wafer, form a back side insulating barrier, this back side insulating barrier is to be formed with the through hole that several each perforations corresponding with one are communicated with by exposure and development; Through hole with this back side insulating barrier of conducting metal glue filling; On this back side insulating barrier and this lead cambium layer, form a following insulating protective layer and one respectively and go up insulating protective layer, these protective layers are by exposure and develop and be formed with the exposing hole of a part that is used to expose to the open air corresponding conducting metal glue; And in each exposing hole of last insulating protective layer, form an external circuit connecting points, and along this semiconductor crystal wafer of line of cut cutting.
According to another feature again more of the present invention; A kind of method for packing of semiconductor chip package is to be provided; It comprises following step: a semiconductor crystal wafer is provided; This semiconductor crystal wafer has several semiconductor die panel region, and each semiconductor die panel region comprises a semiconductor substrate, each semiconductor substrate have a pad installation surface, back surface relative with this pad installation surface, and several be installed on the weld pad on this pad installation surface; The pad installation surface of these semiconductor substrates forms the pad installation surface of this semiconductor crystal wafer jointly, and the back surface of these semiconductor substrates forms the back surface of this semiconductor crystal wafer jointly; Each bar line of cut along this semiconductor crystal wafer forms a groove; On the pad installation surface of this semiconductor crystal wafer, form an insulating barrier in order to do can covering these weld pads, this insulating barrier is by exposure and develops and be formed with several through holes that are used to expose to the open air corresponding pad and arrange and middle body is the perforation of aiming at line of cut along the wafer line of cut with several; On this insulating barrier, form a lead cambium layer in order to do can covering these weld pads, this lead cambium layer is by exposure and develops and be formed with several each and corresponding through hole and the perforation that is communicated with corresponding perforation; With these through holes of conducting metal glue filling, perforation and perforation; On the back surface of this semiconductor crystal wafer, form a groove along each bar line of cut; On the back surface of this semiconductor crystal wafer, form a back side insulating barrier, this back side insulating barrier is to be formed with the through hole that several each perforations corresponding with one are communicated with through exposure and development; On this back side insulating barrier, form a back side lead cambium layer, this back side lead cambium layer is by exposure and develops and be formed with several each perforation of being communicated with corresponding through hole; With these perforation of conducting metal glue filling and through hole; On this back side lead cambium layer and this lead cambium layer, be formed with a following insulating protective layer and one respectively and go up insulating protective layer, these insulating protective layers are to borrow exposure and developing to come the exposing hole that is formed with a part that is used to expose to the open air corresponding conducting metal glue at preposition; And on this, be formed with an external circuit connecting points in each exposing hole of insulating protective layer, and along this semiconductor crystal wafer of line of cut cutting.
According to another characteristic of the invention; A kind of method for packing of semiconductor chip package is to be provided; It comprises following step: a semiconductor crystal wafer is provided; This semiconductor crystal wafer has several semiconductor die panel region; Each semiconductor die panel region comprises a semiconductor substrate, and each semiconductor substrate has a pad installation surface and several are installed on the weld pad on this pad installation surface, and the pad installation surface of these semiconductor substrates forms the pad installation surface of this semiconductor crystal wafer jointly; On the pad installation surface of this semiconductor crystal wafer, form an insulating barrier, this insulating barrier is by exposure and develops and be formed with several through holes and several that are used to expose to the open air corresponding pad each extends and expose the exposing hole on the surface of this wafer to the open air along a wafer line of cut; On this insulating barrier, form a lead cambium layer in order to do can covering these weld pads, this insulating barrier is by exposure and develops and be formed with several each each exposing hole that is communicated with a corresponding exposing hole of perforation and several of being communicated with corresponding through hole; With these through holes of conducting metal glue filling; On this lead cambium layer, form an insulating protective layer, this insulating protective layer is through exposure and to develop to come at preposition be the exposing hole that is formed with a part that is used to expose to the open air corresponding conducting metal glue; In each exposing hole of insulating protective layer, form an external circuit connecting points, and along this semiconductor crystal wafer of line of cut cutting.
Description of drawings
Fig. 1 to 8 is the exemplary flow cutaway views for the method for packing of the semiconductor chip package that shows first preferred embodiment of the present invention;
Fig. 9 is to be the schematic sectional view of the aspect that is stacked of a packaging body that shows two first embodiment of the present invention;
Figure 10 to 16 is the exemplary flow cutaway views for the method for packing of the semiconductor chip package that shows second preferred embodiment of the present invention; And;
Figure 17 to 21 is the exemplary flow cutaway views for the method for packing of the semiconductor chip package that shows the 3rd preferred embodiment of the present invention.
Embodiment
In the detailed description of preferred embodiment of the present invention at the back, identical or similar elements is to be indicated by identical label, and their detailed description will be omitted.In addition, for clear announcement characteristic of the present invention, the element in figure is not to describe by actual ratio.
Fig. 1 to 8 is the exemplary flow cutaway views for the method for packing of the semiconductor chip package that shows first preferred embodiment of the present invention.
See also shown in Figure 1ly, the semiconductor crystal wafer 1 that a slice has several semiconductor wafer region D at first is provided.Should be noted that in the drawings for the sake of brevity, only wherein two semiconductor wafer region D are intactly shown.Each semiconductor wafer region D comprises a semiconductor substrate 10.Each semiconductor substrate 10 have a pad installation surface 100, one and this pad installation surface 100 relative back surperficial 101, and several be installed on the weld pad 102 on this pad installation surface 100.Should be noted that the pad installation surface 100 common pad installation surface that form this semiconductor crystal wafer 1 of these semiconductor substrates 10, and the back surperficial 101 common back surfaces that form this semiconductor crystal wafer 1 of these semiconductor substrates 10.
Then, insulating barrier 2 is to be formed on the pad installation surface 100 of this semiconductor crystal wafer 1 in order to do covering these weld pads 102.In the present embodiment, this insulating barrier 2 is to be coated with polyimides with the spin coating mode to form.Yet this insulating barrier 2 also can be formed by other materials that is fit to.
Then, by carrying out exposure and developing manufacture process, this insulating barrier 2 is to be formed with several through holes 20 that are used to expose to the open air corresponding pad 102 to arrange and middle body is the perforation of aiming at line of cut CL 21 along wafer line of cut CL with several.Then, be the conductive metal layer 3 that is formed with an effect such as conductor on the surface of each weld pad 102.
After forming conductive metal layer 3, lead cambium layer 4 is to be formed on this insulating barrier 2 in order to do covering these conductive metal layers 3, and is as it be shown in fig. 2.
Then, through exposure and developing manufacture process, this lead cambium layer 4 is to be formed with several each and corresponding through hole 20 and the perforation 40 that is communicated with corresponding perforation 21.
Subsequently, through suitable processing procedure, similarly be as the Laser drill, several each be formed on the matrix of this wafer 1 so that the perforation of aiming at 21,11st forms through hole jointly with perforation 11 that corresponding perforation 21 is communicated with.
See also shown in Figure 3ly, conducting metal glue 5 then is these through holes 20 of filling by rights, these perforation 40 and by perforation 11, the 21 formed through holes of aiming at.After the filling of conducting metal glue 5, the rear surface of this semiconductor crystal wafer 1 can experience milled processed and then a back side insulating barrier 6 be to be formed on the rear surface of this semiconductor crystal wafer 1, as shown in FIG. 4.
Subsequently, see also shown in Figure 5ly, through exposure and developing manufacture process, this back side insulating barrier 6 is the through holes 60 that are formed with several each perforations 11 connections corresponding with one.Then, conducting metal glue 5 also is these through holes 60 of filling by rights.
After conducting metal glue 5 is filled in the through hole 60 of back side insulating barrier 6, on the surface of all conducting metal glue 5, form a metal level 7.This metal level 7 can comprise a nickel dam and a gold layer.
Then, as shown in figure 6, be to be formed with a following insulating protective layer 81 and a last insulating protective layer 80 respectively on this back side insulating barrier 6 and this lead cambium layer 4.In the present embodiment, this lead cambium layer 4 worked like a upper caldding layer with going up insulating protective layer 80 1, and this back side insulating barrier and this time insulating protective layer 81 1 work like a lower caldding layer.
Through exposure and developing manufacture process, these protective layers 80 are the exposing hole 82 that is formed with the part of the conducting metal glue 5 that is used to expose to the open air correspondence with 81 at preposition.At last, in each exposing hole 82 of last insulating protective layer 80, be to be formed with an external circuit connecting points 820.
After above-described processing procedure is all accomplished, as long as can obtain as at the semiconductor chip package of the present invention shown in Fig. 7 along this semiconductor crystal wafer 1 of line of cut CL cutting.
Should be noted that by the perforation of aiming at 21, the 11 common through holes that form and after the semiconductor crystal wafer cutting step, will become the roughly semi-circular hole of filling up conducting metal glue 5 on the both side surface of each semiconductor chip package.
See also shown in Figure 9ly, show two as the aspects that are stacked at the semiconductor chip package shown in Fig. 7 among the figure.Visible from figure; The external circuit connecting points 820 of the semiconductor chip package of lower floor is to extend in the exposing hole 82 of following insulating protective layer 81 of semiconductor chip package on upper strata in order to do being electrically connected with the conducting metal glue 5 that is exposed to the open air by this exposing hole 82, so that the corresponding pad 102 of two semiconductor chip packages is to be electrically connected.
Figure 10 to 16 is the exemplary flow cutaway views for the method for packing of the semiconductor chip package that shows second preferred embodiment of the present invention.
See also shown in Figure 10ly, identical with first embodiment, the semiconductor crystal wafer 1 that a slice has several semiconductor wafer region D at first is provided (in the drawings only one of them semiconductor wafer region D by complete demonstration).Different with first embodiment, this semiconductor crystal wafer 1 at first is to utilize cutter (not shown) or any suitable mode to be formed with a groove 103 along each bar line of cut CL.
Identical with first embodiment, insulating barrier 2 is to be formed on the pad installation surface 100 of this semiconductor crystal wafer 1 in order to do covering these weld pads 102, and is as illustrated in fig. 11.
Then, by carrying out exposure and developing manufacture process, this insulating barrier 2 be formed with several through holes 20 that are used to expose to the open air corresponding pad 102 with several along wafer line of cut CL arrange and middle body be the perforation 21 aimed at line of cut CL '.Then, be to be formed with a conductive metal layer 3 on the surface of each weld pad 102.
After forming conductive metal layer 3, a lead cambium layer 4 is to be formed on this insulating barrier 2 in order to do covering these conductive metal layers 3.
Then, through exposure and developing manufacture process, this lead cambium layer 4 be formed with several each with corresponding through hole 20 and with the perforation 40 of corresponding perforation 21 ' be communicated with ', as shown in Figure 12.
Subsequently, the effect as the conducting metal glue 5 of conductor then are these through holes 20 of filling by rights, these bore a hole 40 ' and these perforations 21 '.
After the filling of conducting metal glue 5, this semiconductor crystal wafer 1 be then utilize cutter (not shown) or any suitable mode on the surface, back along each bar line of cut CL cutting being formed with a groove 105, as shown in Figure 13.A back side insulating barrier 6 is to be formed on the back surface of this semiconductor crystal wafer 1 then.In the present embodiment, this insulating barrier 2 works like a coating layer with this back side insulating barrier 6 one.
Subsequently, through exposure and developing manufacture process, this back side insulating barrier 6 be the through hole 60 that is formed with several each perforation 21 ' connections corresponding with one '.Then, a back side lead cambium layer 9 is to be formed on this back side insulating barrier 6.Through exposure and developing manufacture process, this back side lead cambium layer 9 be formed with several each with the perforation 90 of corresponding through hole 60 ' connection, as shown in Figure 14.Conducting metal glue 5 also be filling by rights these the perforation 90 with through hole 60 '.
Be filled in the through hole 60 of back side insulating barrier 6 ' afterwards, on the surface of all conducting metal glue 5, form a metal level 7, as shown in FIG. 15 at conducting metal glue 5.This metal level 7 can comprise a nickel dam and a gold layer.
Then, be to be formed with a following insulating protective layer 81 and a last insulating protective layer 80 respectively on this back side lead cambium layer 9 and this lead cambium layer 4.In the present embodiment, this back side lead cambium layer 9 works like a lower caldding layer with this time insulating protective layer 81 1, and insulating protective layer 80 1 works like a upper caldding layer and this lead cambium layer 4 is with being somebody's turn to do upward.
Through exposure and developing manufacture process, these protective layers 80 are the exposing hole 82 that is formed with the part of the conducting metal glue 5 that is used to expose to the open air correspondence with 81 at preposition.At last, in each exposing hole 82 of last insulating protective layer 80, be to be formed with an external circuit connecting points 820.
After above-described processing procedure is all accomplished, as long as can obtain like semiconductor chip package in the second embodiment of the present invention shown in Figure 16 along this semiconductor crystal wafer 1 of line of cut CL cutting.
Figure 17 to 21 is the exemplary flow cutaway views for the method for packing of the semiconductor chip package that shows the 3rd preferred embodiment of the present invention.
See also shown in Figure 17ly, identical with first embodiment, the semiconductor crystal wafer 1 that a slice has several semiconductor wafer region D at first is provided (in the drawings only wherein two semiconductor wafer region D by complete demonstration).
Then, insulating barrier 2 is to be formed on the pad installation surface 100 of this semiconductor crystal wafer 1 in order to do covering these weld pads 102.
Then, by carrying out exposure and developing manufacture process, this insulating barrier 2 is to be formed with several through holes 20 and several that are used to expose to the open air corresponding pad 102 each extends and expose the roughly v-depression 22 on the surface 100 of this wafer 1 to the open air along a wafer line of cut CL.The edge that should be noted that the insulating barrier 2 in each semiconductor wafer region D has an oblique edge surface owing to the formation of v-depression 22 roughly.Then, be to be formed with a conductive metal layer 3 on the surface of each weld pad 102.
As shown in Fig. 18, after forming conductive metal layer 3, a lead cambium layer 4 is to be formed on this insulating barrier 2 in order to do covering these conductive metal layers 3.Then, through exposure and developing manufacture process, this lead cambium layer 4 is to be formed with several each perforation 40 " each roughly v-depression 41 that are communicated with a corresponding groove 22 with several of being communicated with corresponding through hole 20.The edge that should be noted that the lead cambium layer 4 in each semiconductor wafer region D forms the oblique edge surface of continuous edge surface owing to the formation of v-depression 41 roughly has one with the corresponding edge surface of this insulating barrier 2.
Subsequently, as shown in Figure 19, conducting metal glue 5 then is these through holes 20 of filling by rights.
After the filling of conducting metal glue 5, on the surface of all conducting metal glue 5, form a metal level 7.This metal level 7 can comprise a nickel dam and a gold layer.
Then, be to be formed with an insulating protective layer 80 on this lead cambium layer 4.Through exposure and developing manufacture process, this protective layer 80 is the exposing hole 82 that is formed with a part that is used to expose to the open air corresponding conducting metal glue 5 at preposition.At last, in each exposing hole 82 of insulating protective layer 80, be to be formed with an external circuit connecting points 820.
After above-described processing procedure is all accomplished, as long as can obtain like semiconductor chip package in the third embodiment of the present invention shown in Figure 21 along this semiconductor crystal wafer 1 of line of cut CL cutting.
Claims (27)
1. a semiconductor chip package is characterized in that, comprises:
A semiconductor substrate, its have a pad installation surface, back surface relative with this pad installation surface, several be formed at weld pad on this pad installation surface, and several be formed on the roughly semi-circular hole on both side surface of this semiconductor substrate;
Insulating barrier on pad installation surface that is formed at this semiconductor substrate, this insulating barrier are to be formed with the through hole of several corresponding pad that are used to expose to the open air this semiconductor substrate and the roughly semi-circular hole of aiming at the roughly semi-circular hole on the both side surface of this semiconductor substrate;
At least one extends to the conductor in precalculated position on the back surface of this semiconductor substrate via at least one semi-circular hole from one of them weld pad;
Upper caldding layer on pad installation surface that is formed on this semiconductor substrate, this upper caldding layer are the exposing hole that is formed with the part of several conductors that are used to expose to the open air the correspondence on this pad installation surface;
A back lip-deep lower caldding layer that is formed on this semiconductor substrate, this lower caldding layer are to be formed with several to be used to expose to the open air the exposing hole in the part of the conductor of this lip-deep correspondence in back; And
Several respectively are formed on the interior external circuit connecting points of exposing hole of a correspondence of this upper caldding layer.
2. semiconductor chip package as claimed in claim 1, its characteristic more are, comprise the conductive metal layer that is formed on each weld pad.
3. semiconductor chip package as claimed in claim 1, its characteristic more be, comprise several be formed at corresponding conductors on the pad installation surface of semiconductor substrate with the surface, back on conductor part on conductive metal layer.
4. semiconductor chip package as claimed in claim 3 is characterized in that, each in these conductive metal layers can comprise stacked a nickel dam and a gold layer.
5. a semiconductor chip package is characterized in that, comprises:
A semiconductor substrate, it has a pad installation surface and several are formed at the weld pad on this pad installation surface;
Insulating barrier on pad installation surface that is formed at this semiconductor substrate, this insulating barrier are to be formed with the through hole that several are used to expose to the open air the corresponding pad of this semiconductor substrate, and have oblique edge surface so that it has a trapezoidal cross-section;
A lead cambium layer that is formed on this insulating barrier; This lead cambium layer is to be formed with at least one to be communicated with and to expose to the open air the perforation of the part of this insulating barrier with one of them through hole of this insulating barrier, can form continuous edge surface with the corresponding edge surface of this insulating barrier thereby this lead cambium layer also has oblique edge surface;
Be filled in the through hole and the interior conducting metal glue of the cambial perforation of this lead of this insulating barrier of connection;
One covers the cambial insulating protective layer of this lead, and this insulating protective layer is the exposing hole that is formed with a part that is used to expose to the open air corresponding conducting metal glue; And
Several respectively are formed on the interior external circuit connecting points of exposing hole of a correspondence of this protective layer.
6. semiconductor chip package as claimed in claim 5 is characterized in that, more comprises the conductive metal layer on each weld pad that is formed at this semiconductor substrate.
7. semiconductor chip package as claimed in claim 5 is characterized in that, more comprises the lip-deep conductive metal layer that is formed at the conducting metal glue in cambial each perforation of lead.
8. semiconductor chip package as claimed in claim 7 is characterized in that, each in these conductive metal layers can comprise stacked a nickel dam and a gold layer.
9. a semiconductor chip package is characterized in that, comprises:
A semiconductor substrate, its have a pad installation surface, back surface relative with this pad installation surface, and several be formed at the weld pad on this pad installation surface;
Pad installation surface that is formed at this semiconductor substrate, the lip-deep insulating coating of side surface and back, this insulating coating are to be formed with the through hole that at least one is used to expose to the open air one of them weld pad of this semiconductor substrate;
At least one extends to the conductor in precalculated position on the back surface of this semiconductor substrate from this one of them weld pad;
Thereby one be formed on this insulating coating can cover the upper caldding layer of the conductor part on the pad installation surface of this semiconductor substrate in the coating layer on the pad installation surface of semiconductor substrate part, this upper caldding layer is to be formed with the exposing hole that several are used to expose to the open air the part of corresponding conductor part;
Thereby back lip-deep coating layer part that is formed on this insulating coating at semiconductor substrate can cover conductor part on the back surface of this semiconductor substrate lower caldding layer, this lower caldding layer is to be formed with the exposing hole that several are used to expose to the open air the part of corresponding conductor part; And
Several respectively are formed on the interior external circuit connecting points of exposing hole of a correspondence of insulating barrier on this.
10. semiconductor chip package as claimed in claim 9 is characterized in that, more comprises the conductive metal layer on each weld pad that is formed at this semiconductor substrate.
11. semiconductor chip package as claimed in claim 9 is characterized in that, more comprises the lip-deep conductive metal layer that is formed at the conducting metal glue in cambial each perforation of lead.
12. semiconductor chip package as claimed in claim 11 is characterized in that,
In these conductive metal layers each can comprise stacked a nickel dam and a gold layer.
13. the method for packing of a semiconductor chip package is characterized in that, comprises following step:
A semiconductor crystal wafer is provided; This semiconductor crystal wafer has several semiconductor die panel region; Each semiconductor die panel region comprises a semiconductor substrate; Each semiconductor substrate have a pad installation surface, back surface relative with this pad installation surface, and several be installed on the weld pad on this pad installation surface; The pad installation surface of these semiconductor substrates forms the pad installation surface of this semiconductor crystal wafer jointly, and the back surface of these semiconductor substrates forms the back surface of this semiconductor crystal wafer jointly;
Thereby on the pad installation surface of this semiconductor crystal wafer, form an insulating barrier and can cover these weld pads, this insulating barrier be by exposure with develop that to be formed with at least one through hole that is used to expose to the open air one of them weld pad be the perforation of aiming at line of cut with at least one along arrangement of wafer line of cut and middle body;
Thereby on this insulating barrier, form a lead cambium layer and can cover these weld pads, this lead cambium layer is to be formed with several respectively and corresponding through hole and the perforation that is communicated with corresponding perforation by exposure with developing;
The perforation that on the matrix of this wafer, forms several each perforations connections corresponding with one of insulating barrier is so that the perforation of the connection of the matrix of wafer and insulating barrier is to form through hole jointly;
With these through holes of conducting metal glue filling, these perforation and by the formed through hole of perforation that is communicated with;
On the back surface of this semiconductor crystal wafer, form a back side insulating barrier, this back side insulating barrier is to be formed with the through hole that several each perforations corresponding with one are communicated with by exposure and development;
Through hole with this back side insulating barrier of conducting metal glue filling;
On this back side insulating barrier and this lead cambium layer, form a following insulating protective layer and one respectively and go up insulating protective layer, these protective layers are by exposure and develop and be formed with the exposing hole of a part that is used to expose to the open air corresponding conducting metal glue; And
In each exposing hole of last insulating protective layer, form an external circuit connecting points, and along this semiconductor crystal wafer of line of cut cutting.
14. like claim 13 a described method for packing, it is characterized in that, before forming the lead cambium layer, more comprise a step that on the surface of each weld pad, forms a conductive metal layer.
15., it is characterized in that in the step that forms conductive metal layer, each in these metal levels can comprise stacked a nickel dam and a gold layer like claim 14 a described method for packing.
16. method for packing as claimed in claim 13 is characterized in that, on forming, before insulating protective layer and the following insulating protective layer, more comprises a step that on the surface of all conducting metal glue, forms a conductive metal layer.
17. method for packing as claimed in claim 16 is characterized in that, in the step that forms conductive metal layer, each in these metal levels can comprise stacked a nickel dam and a gold layer.
18. the method for packing of a semiconductor chip package is characterized in that, comprises following step:
A semiconductor crystal wafer is provided; This semiconductor crystal wafer has several semiconductor die panel region; Each semiconductor die panel region comprises a semiconductor substrate; Each semiconductor substrate have a pad installation surface, back surface relative with this pad installation surface, and several be installed on the weld pad on this pad installation surface; The pad installation surface of these semiconductor substrates forms the pad installation surface of this semiconductor crystal wafer jointly, and the back surface of these semiconductor substrates forms the back surface of this semiconductor crystal wafer jointly;
Each bar line of cut along this semiconductor crystal wafer forms a groove;
Thereby on the pad installation surface of this semiconductor crystal wafer, form an insulating barrier and can cover these weld pads, this insulating barrier is by exposure and develops and be formed with at least one through hole that is used to expose to the open air one of them weld pad and arrange and middle body is the perforation of aiming at line of cut along the wafer line of cut with at least one;
Thereby on this insulating barrier, form a lead cambium layer and can cover these weld pads, this lead cambium layer is by the perforation that makes public and develop and be formed with at least one through hole of at least one and this and be communicated with this at least one perforation;
With these through holes of conducting metal glue filling, perforation and perforation;
On the back surface of this semiconductor crystal wafer, form a groove along each bar line of cut;
On the back surface of this semiconductor crystal wafer, form a back side insulating barrier, this back side insulating barrier is to be formed with the through hole that several each perforations corresponding with one are communicated with through exposure and development;
On this back side insulating barrier, form a back side lead cambium layer, this back side lead cambium layer is by exposure and develops and be formed with several each perforation of being communicated with corresponding through hole;
With these perforation of conducting metal glue filling and through hole;
On this back side lead cambium layer and this lead cambium layer, be formed with a following insulating protective layer and one respectively and go up insulating protective layer, these insulating protective layers are through exposure and develop to come the exposing hole that is formed with a part that is used to expose to the open air corresponding conducting metal glue at preposition;
On this, be formed with an external circuit connecting points in each exposing hole of insulating protective layer, and along this semiconductor crystal wafer of line of cut cutting.
19. method for packing as claimed in claim 18 is characterized in that, before forming the lead cambium layer, more comprises a step that on the surface of each weld pad, forms a conductive metal layer.
20. method for packing as claimed in claim 19 is characterized in that, in the step that forms conductive metal layer, each in these metal levels can comprise stacked a nickel dam and a gold layer.
21. method for packing as claimed in claim 19 is characterized in that, on forming, before insulating protective layer and the following insulating protective layer, more comprises a step that on the surface of all conducting metal glue, forms a conductive metal layer.
22. method for packing as claimed in claim 21 is characterized in that, in the step that forms conductive metal layer, each in these metal levels can comprise stacked a nickel dam and a gold layer.
23. the method for packing of a semiconductor chip package is characterized in that, comprises following step:
A semiconductor crystal wafer is provided; This semiconductor crystal wafer has several semiconductor die panel region; Each semiconductor die panel region comprises a semiconductor substrate; Each semiconductor substrate has a pad installation surface and several are installed on the weld pad on this pad installation surface, and the pad installation surface of these semiconductor substrates forms the pad installation surface of this semiconductor crystal wafer jointly;
On the pad installation surface of this semiconductor crystal wafer, form an insulating barrier, this insulating barrier is by exposure and develops and be formed with several through holes and several that are used to expose to the open air corresponding pad each extends and expose the exposing hole on the surface of this wafer to the open air along a wafer line of cut;
Thereby on this insulating barrier, form a lead cambium layer and can cover these weld pads, this insulating barrier is by exposure and develops and be formed with several each each exposing hole that is communicated with a corresponding exposing hole of perforation and several of being communicated with corresponding through hole;
With these through holes of conducting metal glue filling;
On this lead cambium layer, form an insulating protective layer, this insulating protective layer is through exposure and to develop to come at preposition be the exposing hole that is formed with a part that is used to expose to the open air corresponding conducting metal glue;
In each exposing hole of insulating protective layer, form an external circuit connecting points, and along this semiconductor crystal wafer of line of cut cutting.
24. method for packing as claimed in claim 23 is characterized in that, before forming the lead cambium layer, more comprises a step that on the surface of each weld pad, forms a conductive metal layer.
25. method for packing as claimed in claim 24 is characterized in that, in the step that forms conductive metal layer, each in these metal levels can comprise stacked a nickel dam and a gold layer.
26. method for packing as claimed in claim 23 is characterized in that, before forming insulating protective layer, more comprises a step that on the surface of all conducting metal glue, forms a conductive metal layer.
27. method for packing as claimed in claim 26 is characterized in that, in the step that forms conductive metal layer, each in these metal levels can comprise stacked a nickel dam and a gold layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100830435A CN101540306B (en) | 2008-03-18 | 2008-03-18 | Semiconductor wafer encapsulation body and encapsulation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100830435A CN101540306B (en) | 2008-03-18 | 2008-03-18 | Semiconductor wafer encapsulation body and encapsulation method thereof |
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| CN101540306A CN101540306A (en) | 2009-09-23 |
| CN101540306B true CN101540306B (en) | 2012-07-04 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6660626B1 (en) * | 2000-08-22 | 2003-12-09 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint |
| US6701614B2 (en) * | 2002-02-15 | 2004-03-09 | Advanced Semiconductor Engineering Inc. | Method for making a build-up package of a semiconductor |
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2008
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6660626B1 (en) * | 2000-08-22 | 2003-12-09 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint |
| US6701614B2 (en) * | 2002-02-15 | 2004-03-09 | Advanced Semiconductor Engineering Inc. | Method for making a build-up package of a semiconductor |
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| CN101540306A (en) | 2009-09-23 |
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