CN101533853A - 半导体结构 - Google Patents

半导体结构 Download PDF

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CN101533853A
CN101533853A CN200810215842A CN200810215842A CN101533853A CN 101533853 A CN101533853 A CN 101533853A CN 200810215842 A CN200810215842 A CN 200810215842A CN 200810215842 A CN200810215842 A CN 200810215842A CN 101533853 A CN101533853 A CN 101533853A
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stress
layer
strain bar
semiconductor structure
active area
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CN101533853B (zh
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王彦森
林仲德
曹敏
杨胜杰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer

Abstract

本发明公开一种半导体结构，包括：一有源区(active region)、位于有源区上方的一栅极带层、以及一金属－氧化物－半导体(MOS)装置。一部份的栅极带层构成MOS装置的栅极。一部份的有源区构成MOS装置的源极/漏极(source/drain)区。半导体结构还包括：位于MOS装置上方的一应激(stressor)区以及位于应激区内部且位于有源区上方外侧的一无应激(stressor－free)区。通过本发明的半导体结构可以改善施加于MOS装置的应力，进而改善MOS装置的效能。

Description

半导体结构
技术领域
本发明涉及一种半导体装置，尤其涉及一种金属-氧化物-半导体(metal-oxide-semiconductor，MOS)装置，尤其更涉及MOS装置中应力的改善。
背景技术
在半导体装置中，例如MOS装置，尺寸及原有特征(inherent feature)的缩小，能够持续改善过去数年来集成电路的速度、效能、密度以及每单位运作的成本。根据MOS装置的设计及其中一原有特征，调整栅极下方位于MOS装置的源极与漏极之间的通道区(channel region)长度，改变通道区的阻值，进而影响MOS装置的效能。更特别的是假设MOS装置其他参数相对维持不变，缩短通道区的长度而降低MOS装置中源极至漏极的阻值，可在MOS装置的栅极施加适当的电压时，增加源极与漏极之间的电流。
为了进一步提升MOS装置的效能，在MOS装置的通道区导入应力，以改善其载流子迁移率(carrier mobility)。一般而言，会在N型MOS装置(NMOS)的通道区的源极至漏极的方向(通道区长度方向)导入一伸张应力，而在P型MOS装置(PMOS)的通道区的通道区长度方向导入一压缩应力。
一种常用的方法用于施加压缩应力于MOS装置的通道区为形成受应力的接触孔蚀刻终止层(contact etch stop layer，CESL)，其施加应力于MOS装置下方。由于CESL为MOS装置现有的部件，故很少采用受应力的CESL，若有的话，也会额外增加制造成本。对于NMOS装置而言，上方的CESL需具备原有的伸张应力并施加伸张应力至通道区。对于PMOS装置而言，上方的CESL需具备原有的压缩应力并施加压缩应力至通道区。
CESL在所有方向都施加一相同的应力(伸张或压缩其中一者)至MOS装置下方。然而，MOS装置较倾向不同方向有不同类型的应力。举例而言，PMOS装置倾向在通道长度方向为压缩应力，而在通道宽度方向为伸张应力。因此，在PMOS装置的通道宽度方向施加压缩应力，实际上是会降低PMOS装置的效能。本发明提供一种新的结构可解决MOS装置特定应力需求的问题。
发明内容
根据本发明的一型态，一种半导体结构包括：一有源区、位于有源区上方的一栅极带层、以及一金属-氧化物-半导体(MOS)装置。一部份的栅极带层构成MOS装置的栅极。一部份的有源区构成MOS装置的源极/漏极区。半导体结构还包括：位于MOS装置上方的一应激区以及位于应激区内部且位于有源区上方外侧的一无应激区。
根据本发明的另一型态，一种半导体结构包括：一半导体基底、位于半导体基底内的一有源区、位于半导体基底内且与有源区相邻的一隔离区，以及一MOS装置。MOS装置包括：位于有源区上方的一栅极电极以及位于栅极电极的相对侧的一源极区及一漏极区，其中源极区及漏极区与部份的有源区重叠。半导体结构还包括：位于有源区及隔离区上方一应激层、被应激层所围绕且位于隔离区正上方的一无应激区、以及位于无应激区的一应变条层。
根据本发明的另一型态，一种半导体结构包括：一半导体基底、位于半导体基底内的一有源区、位于半导体基底内且与有源区相邻的一浅沟槽隔离(shallow trench isolation，STI)区，以及一MOS装置。MOS装置包括：位于有源区上方的一栅极电极以及位于栅极电极的相对侧的一源极区及一漏极区，其中源极区及漏极区与部份的有源区重叠。半导体结构还包括：位于有源区及STI区上方一接触孔蚀刻终止层(CESL)、位于STI区上方且被CESL所围绕的一无应激区、填入无应激区的一应变条层、位于CESL上方的一层间介电(inter-layer dielectric，ILD)层、以及位于ILD层内，且与源极区及漏极区其中的一接触的一接触插塞。
根据本发明的另一型态，一种半导体结构制造方法包括：提供一半导体基底，其内包括一有源区；提供一隔离区，其位于半导体基底内且与有源区相邻的；以及形成一MOS装置。形成MOS装置的步骤包括：在有源区上方形成一栅极电极；以及在栅极电极的相对侧形成一源极区及一漏极区。上述方法还包括：在有源区及隔离区上方形成一应激层；以及在隔离区上方形成一应变条层，其中应变条层被应激层所围绕。
根据本发明的另一型态，一种半导体结构制造方法包括：提供一半导体基底，其内包括一有源区；提供一STI区，其位于半导体基底内且与有源区相邻；以及形成一MOS装置。形成MOS装置的步骤包括：在有源区上方形成一栅极电极；以及在栅极电极的相对侧形成一源极区及一漏极区。上述方法还包括：在有源区及STI区上方形成一CESL；在CESL内且位于STI区正上方形成一开口；以及填充开口以形成一应变条层。
本发明的优点包括改善施加于MOS装置的应力，进而改善MOS装置的效能。
附图说明
图1示出了应变条层形成于PMOS装置上方压缩应激层内的平面示意图；
图2示出了应变条层形成于PMOS装置上方伸张应激层内的平面示意图；
图3A和图3B示出了应变条层形成于NMOS装置上方压缩应激层内的平面示意图；
图4示出了没有应变条层形成于NMOS装置上方伸张应激层内的平面示意图；
图5示出了单一应激层平面示意图，其中一相同的伸张应激层形成于PMOS装置与NMOS装置上方；
图6示出了单一应激层平面示意图，其中一相同的压缩应激层形成于PMOS装置与NMOS装置上方；
图7示出了具有不规则外型的应变条层平面示意图；
图8和图9示出了形成图2结构的中间步骤剖面示意图，其中应变条层由层间介电层所构成；
图10示出了图1结构的剖面示意图；
图11至图13示出了形成图2结构的中间步骤剖面示意图，其中应变条层由相同于接触插塞的材料所构成；
图14至图17示出了形成图2结构的中间步骤剖面示意图，其中应变条层由与应激层具有相反应力类型的介电材料所构成；
图18示出了用于进行实验的一样品结构平面示意图；及
图19和图20示出了应激层的尺寸影响的实验结果。
其中，附图标记说明如下：
10～半导体基底；
30～接触插塞；
30’～接触开口；
31～辅助接触插塞；
31’～辅助接触开口；
100～PMOS装置；
110、210～有源区；
112、212～多晶硅带层(栅极带层)；
114、214、314、CESL1、CESL2～应激层；
116、216～应变条层；
118、218～层间介电层；
200～NMOS装置；216’～应变条层开口；
Dx、Dy、Enx、Eny～距离；
L1、L2～长度；STI～浅沟槽隔离区；
W1、W2～宽度。
具体实施方式
以下详细说明本发明实施例的制造与使用。然而，必须了解的是本发明提供许多适当的发明概念，可实施于不同的特定背景。述及的特定实施例仅仅用于说明以特定方法来制造及使用本发明，并非用以限定本发明范围。
以下说明一种新的应激层，其用来施加应力于MOS装置。接着说明较佳实施例的制造方法。而在本发明实施例中，所有相同的部件使用相同的标号。
图1示出了本发明一实施例的PMOS装置100及围绕区的平面示意图。PMOS装置100包括有源区110以及延伸跨越有源区110的多晶硅带层(栅极带层)112。在以下的说明，“多晶硅带层”一词表示由多晶硅或其他导电材料所构成的导电带层，例如金属、金属硅化物、或金属氮化物等等。有源区110被绝缘区所围绕，例如浅沟槽隔离区(STI，参见图10)。应激层114形成于多晶硅带层112及有源区110上方。应激层114可为一接触孔蚀刻终止层(CESL)或形成于PMOS装置100上方的其他介电层。
由公知技术可知，PMOS装置较佳为受到压缩应力。在本实施例中，应激层114具有原有(inherent)压缩应力。因此，压缩应力自X方向及Y方向施加于PMOS装置100。X方向(通道长度的方向)的压缩应力(应激层114的原有应力以及施加于PMOS装置100的应力)有助于改善PMOS装置100的驱动电流，因而最好将其保留。而Y方向(通道宽度的方向)的压缩应力则不利于PMOS装置100的驱动电流，因而最好将其排除。在较佳的实施例中，二应变条层116形成于浅沟槽隔离(STI)区(有源区110外侧)上方，且位于应激层114内。通过蚀刻应激层114而形成开口并于开口内填入不同于应激层114的材料便可形成应变条层116。因此，应变条层116所在区域也是无应激区。在一实施例中，应变条层116填入层间介电材料。在其他实施例中，应变条层116填入相同于接触插塞(contact plug)的材料。又另一实施例中，应变条层116填入具有中性应力(无应力)或具有与应激层114相反应力类型的材料。又另一实施例中，应变条层116甚至可填入具有相同应力类型的材料，但是其应力小于应激层114的应力。本文稍后将进一步说明应变条层116的材料以及制造方法。有源区110的作侧及右侧并无形成应变条层。
应变条层116有助于阻断Y方向的应变途径，进而降低Y方向中有害原有压缩应力。因此，施加于PMOS装置100的有害原有压缩应力便可降低。位于应变条层116与有源区100所对应的边缘之间的距离Eny最好是短的。在较佳的实施例中，上述距离Eny小于1微米(μm)且最好小于0.3μm。当距离Eny增加时，应激层114仍具有降低Y方向应力的效果。然而，降低的量将会减少。较大的应变条层116宽度W2有助于降低Y方向的压缩应力。较佳的宽度W2约为1.0μm。应变条层116的长度L2最好是大于施加于MOS装置的通道的有害应力途径。在一实施例中，应变条层116的长度L2大于栅极带层112的宽度且较佳为大于长度L1。再者，应变条层116的左端及右端最好是延伸超越有源区110所对应的左端及右端。
PMOS装置100可被具有原有伸张应力的应激层所覆盖，如图2所示。伸张应激层214自X方向及Y方向施加伸张应力于PMOS装置100。由于通道宽度W1方向(Y方向)的伸张应力有助于PMOS装置100的效能，故无应变条层形成于Y方向的原有应力的途径。另一方面，由于通道长度L1方向(X方向)的伸张应力不利于PMOS装置100的效能，故形成应变条层216平行于多晶硅带层112，且与有源区110所对应的左边缘及右边缘相邻。类似地，应变条层216的由不同于应激层214的材料所构成。应变条层216有助于降低施加于PMOS装置100的通道长度方向的伸张应力。位于应变条层216与栅极带层112所对应的侧壁之间的距离Enx较佳为小于1微米(μm)且最好小于0.3μm，使得降低有害应力的效果能增加到最大限度。
图3A至图4示出了如何形成应变条层来改善NMOS装置的效能。请参见图3A，NMOS装置200包括有源区210以及位于有源区210上方的多晶硅带层212，其中一部分的多晶硅带层212作为NMOS装置200的栅极。压缩应激层114形成于NMOS装置200上方。由于通道长度方向与通道宽度方向的压缩应力不利于NMOS装置200的效能，故应变条层116形成于应激层114内以降低应激层114内X方向及Y方向的原有应力。在图3A中，应变条层116为分离条层而彼此完全分开。然而，一或一个以上相邻的应变条层116可连接在一起。如图3B所示，应变条层116连接在一起而形成一应变圈层。类似于图1，应变条层116可填入内层介电(ILD)材料、接触插塞材料、或具有伸张或中性应力的介电材料。
可以理解的是受到表面型态(geographical)的限制，并非皆可形成所有列举应变条层。举例而言，另一MOS装置占据了一应变条层的位置。然而，尽管在尺寸缩小的情形下，只有形成部分的应变条层仍可改善所对应的MOS装置的效能。举例而言，可在图1和图2所示的结构中仅形成一应变条层，也可在图3A中形成一个、二个、或三个应变条层。
请参见图4，NMOS装置200被具有伸张应力的应激层214所覆盖。由于NMOS装置200较佳为通道长度方向与通道宽度方向受到伸张应力，故不形成应变条层。
在上述实施例中，在没有形成应变条层的方向，应激层最好作深远的延伸，以加强所需应力。举例而言，距离Dx及Dy(请参见图1、图2和图4)较佳为大于5μm。换句话说，在应激层施加有利应力于MOS装置的通道的方向上，各自方向的距离Dx及Dy并没有上限值。
图5和图6示出了形成于单一应激层的应变条层平面示意图。图5示出了一相同的伸张应激层214覆盖PMOS装置100及NMOS装置200。该实施例实质上是图2及图4实施例的结合。图6示出了一单一压缩应激层114形成于PMOS装置100及NMOS装置200上方。该实施例实质上是图1及图3A实施例的结合。
在双重应激结构中，较佳为一压缩应激层形成于PMOS装置上方，而一伸张应激层形成于NMOS装置上方。因此，各自的实施利可通过结合图1及图4实施例而得。
可以理解的是虽然图1至图6所示的应变条层为矩形条层，但是其可为任何外型，只要其形成于应激层内不要的原有应力途径上。图7示出了不规则外型的应变条层116形成于应激层114内。在此情形中，相邻的MOS装置的应变条层连接在一起。再者，原本形成于MOS装置两侧的应变条层可仅形成于MOS装置的一侧，如图7所示。
图8至图17示出了本发明实施例的剖面示意图并用于解释前述实施例形成过程。图8和图9示出了沿图2的A-A’线形成该结构的中间步骤剖面示意图。请参见图8，形成PMOS装置100，其有源区110由浅沟槽隔离区STI所定义而成。有源区110包括一半导体基底10表面。形成应激层214以覆盖整个PMOS装置100。于应激层214内形成应变条层开口216’，例如该应变条层开口216’可以通过蚀刻而形成。为了形成应变条层开口216’，需要一额外的掩模(mask)。请参见图9，形成一层间介电(ILD)层218，且在应变条层开口216’内填入层间介电层218。接着，形成接触开口以贯穿ILD层218及应激层214，其中应激层214可作为CESL。接着在接触开口内形成接触插塞30。在本实施例中，以ILD层218的底部作为应变条层216。因此，应变条层216(及应变条层116)的形成方法可包括：次常压化学气相沉积(sub-atmospheric pressure chemical vapor deposition，SACVD)、高密度等离子体(high density plasma，HDP)、及旋转涂覆(spin-on)等等。应变条层216/116可包括一般所使用的ILD材料，例如含碳低介电材料、未掺杂硅玻璃(un-doped silicate glass，USG)、或是其他介电材料。图10示出了沿图1的B-B’线的结构剖面示意图。类似于图8和图9所示的实施例，应变条层116由塡入ILD层118而成。形成接触插塞30以贯穿ILD层118及应激层114。
图11至图13示出了另一实施例沿图2的A-A’线形成该结构的剖面示意图。请参见图11，形成PMOS装置100，接着形成应激层214及ILD层218。请参见图12，同时形成接触开口30’及辅助接触开口31’以贯穿ILD层218及应激层214。如图13所示，辅助接触开口31’形成于应变条层216所在位置，且位于浅沟槽隔离区STI上方。请参见图13，形成接触插塞30及辅助接触插塞31。辅助接触插塞31较佳为浮置(floating)的。应激层214内的辅助接触插塞31作为应变条层216。因此，应变条层216(及其他实施例的应变条层116)可包括钨、铝、铜、钽、钛、其氮化物、其组合及其构成的多层结构等等。形成应变条层216的适当方法包括物理气相沉积(physicalvapor deposition，PVD)、原子层沉积(atomic layer deposition，ALD)、溅镀(sputtering)、及电镀(plating)等等。在本实施例中，好处在于无需额外的掩模及额外的制造工艺步骤来形成应变条层216。
图14至图17示出了又另一实施例，其中应变条层具有与应激层相反的应力类型。再次以图2中沿A-A’线的剖面示意图作为范例说明。请参见图14，首先在PMOS装置100上方形成压缩应激层314。接着，请参见图15，将应激层314图案化且留下一部分而形成应变条层216，其位于浅沟槽隔离区STI上方。请参见图16，伸张应激层214全面性覆盖PMOS装置100及应变条层216。再一次实施图案化以去除位于应变条层216正上方的应激层214，以形成图17所示的结构。在该结构中，应变条层216具有与应激层314相反的应力类型且对于降低有害应力非常有效。然而，本实施例需要二个额外的掩模，一个用于应激层314图案化，而另一个则用于应激层214图案化。
虽然图8至图17仅示出了本发明若干实施例的制造工艺步骤，任何本领域普通技术人员可知本发明其他实施例可运用上述的技术并配合选择适当的材料及图案。
应变条层116及216可使用逻辑操作进行设计，其包括掩模的图形数据系统(graphic data system，GDS)文件的布局调整(layout modification)。举例而言，在逻辑操作中，首先找出MOS装置及其上方CESL的掩模，并确定CESL所施加的有害应力的方向，之后决定出应变条层的适当位置及尺寸并将应变条层的图案加入至掩模。另外，应变条层也可手动加入。应变条层较佳为形成于STI区或场氧化物(field oxide)区正上方，而不是有源区正上方。在其他实施例中，应变条层也可形成于有源区正上方。
图19和图20示出了应激层尺寸对于装置效能改善的影响的实验结果。图18示出了使用于上述实验的样品，其包括PMOS装置100(包括多晶带层112即有源区110)及形成于PMOS装置100上方的压缩应激层CESL1。应激层CESL2围绕应激层CESL1且具有伸张应力。图19示出了驱动电流ΔIdsat(％)的增量与距离Dy之间函数关系图，该距离示出了于图18。不同的样品实验结果以不同外型类别进行区分。由图19可知在有害应力的施加方向，距离Dy的缩减能增进更多驱动电流直至某一距离(在这些样品中约为0.1μm)为止，驱动电流的增进达到饱和。因此，应变条层较佳为形成于靠近有源区的地方。
图20示出了驱动电流ΔIdsat(％)的降低量与距离Dx之间函数关系图，该距离也示出了于图18。由图20可知在有利应力的施加方向，距离Dx的增加有较少的驱动电流降低量(换句话说，驱动电流的增加与距离Dx呈一函数关系)直至某一距离(在这些样品中约为3.0μm)为止，驱动电流的降低量达到饱和。因此，没有应变条层形成于施加有利应力的方向。
利用本发明的实施例，应激层所施加的有害应力可达到最小程度，同时由相同应激层所施加的有利应力则得以维持，因而改善MOS装置的效能。本发明实施例所需的额外步骤及掩模最少，故制造成本实质上并未增加。
虽然本发明已以较佳实施例公开如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作更动与润饰，因此本发明的保护范围当以随附的权利要求所界定的范围为准。

Claims (20)

1.一种半导体结构，包括：
一有源区；
一栅极带层，位于该有源区上方；
一金属-氧化物-半导体装置，其中一部份的该栅极带层构成该金属-氧化物-半导体装置的一栅极；
一部份的该有源区构成该金属-氧化物-半导体装置的一源极/漏极区；
一应激区，位于该金属-氧化物-半导体装置上方；以及
一无应激区，位于该应激区内部与其外部的该有源区上方。
2.如权利要求1所述的半导体结构，其中该无应激区与该有源区的一边缘相邻，且具有一长度大于有害应力施加于该金属-氧化物-半导体装置的通道的途径。
3.如权利要求1所述的半导体结构，其中该无应激区位于该应激区内一有害原有应力的途径，且其中位于该应激区内一有利原有应力的途径没有应变条层形成于内。
4.如权利要求3所述的半导体结构，其中该金属-氧化物-半导体装置为P型金属-氧化物-半导体装置，该应激区具有一压缩应力，且其中该无应激区位于该金属-氧化物-半导体装置的栅极宽度方向的一原有应力途径。
5.如权利要求3所述的半导体结构，其中该金属-氧化物-半导体装置为P型金属-氧化物-半导体装置，该应激区具有一伸张应力，且其中该无应激区位于该金属-氧化物-半导体装置的栅极长度方向的一原有应力途径。
6.如权利要求3所述的半导体结构，其中该金属-氧化物-半导体装置为N型金属-氧化物-半导体装置，该应激区具有一压缩应力，且其中该无应激区位于该金属-氧化物-半导体装置的栅极宽度方向的一原有应力途径。
7.如权利要求6所述的半导体结构，还包括一额外的无应激区，位于该金属-氧化物-半导体装置的栅极长度方向的该原有应力途径。
8.如权利要求1所述的半导体结构，还包括一层间介电层，位于该应激区上方，其中该层间介电层延伸至该无应激区内。
9.如权利要求1所述的半导体结构，还包括：
一层间介电层，位于该应激区上方；
一辅助接触插塞，延伸至该层间介电层内以及该无应激区内。
10.如权利要求1所述的半导体结构，其中该无应激区包括一介电材料，其具有与该应激区相反类型的原有应力。
11.一种半导体结构，包括：
一半导体基底；
一有源区，位于该半导体基底内；
一隔离区，位于该半导体基底内且与该有源区相邻；
一金属-氧化物-半导体装置，包括：
一栅极电极，位于该有源区上方；以及
一源极区及一漏极区位于该栅极电极的相对侧，其中该源极区及该漏极区与部份的该有源区重叠；
一应激层，位于该有源区及该隔离区上方；
一无应激区，被该应激层所围绕且位于该隔离区正上方；以及
一第一应变条层，位于该无应激区。
12.如权利要求11所述的半导体结构，其中该第一应变条层与该有源区一最靠近的边界之间的距离小于0.3微米。
13.如权利要求11所述的半导体结构，其中该第一应变条层具有一应力类型相反于该应激层的应力类型。
14.如权利要求11所述的半导体结构，其中该第一应变条层大体平行于该有源区一最靠近的边缘，其中该第一应变条层具有一长度大于有害应力施加于该金属-氧化物-半导体装置的通道的途径。
15.如权利要求11所述的半导体结构，还包括一第二应变条层，位于与该第一应变条层相对侧的该有源区内，其中该第二应变条层被该应激层所围绕且位于一第二隔离区正上方。
16.如权利要求15所述的半导体结构，还包括一第三应变条层，大体垂直该第一及该第二应变条层，其中该第三应变条层被该应激层所围绕且位于一第三隔离区正上方。
17.如权利要求15所述的半导体结构，其中该第一及该第二应变条层与多个额外应变条层形成一封闭圈，且其中所述多个额外应变条层被该应激层所围绕且位于具有该第一及该第二隔离区的一连续隔离区上方。
18.一种半导体结构，包括：
一半导体基底；
一有源区，位于该半导体基底内；
一浅沟槽隔离区，位于该半导体基底内且与该有源区相邻；
一金属-氧化物-半导体装置，包括：
一栅极电极，位于该有源区上方；以及
一源极区及一漏极区位于该栅极电极的相对侧，其中该源极区及该漏极区与部份的该有源区重叠；
一接触孔蚀刻终止层，位于该有源区及该浅沟槽隔离区上方；
一无应激区，位于该浅沟槽隔离区上方且被该接触孔蚀刻终止层所围绕；
一应变条层，填入该无应激区；
一层间介电层，位于该接触孔蚀刻终止层上方；以及
一接触插塞，位于该层间介电层内，且与该源极区及该漏极区其中的一接触。
19.如权利要求18所述的半导体结构，其中该层间介电层延伸至该无应激区内以形成该应变条层。
20.如权利要求18所述的半导体结构，还包括一辅助接触插塞，位于该层间介电层内，其中该辅助接触插塞延伸至该无应激区内以形成该应变条层。
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CN103855077B (zh) * 2012-12-05 2018-07-10 联华电子股份有限公司 具有接触插栓的半导体结构与其形成方法
US10049929B2 (en) 2012-12-05 2018-08-14 United Microelectronics Corp. Method of making semiconductor structure having contact plug

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US20110195554A1 (en) 2011-08-11

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