CN101529586B - 封装半导体器件和预制连接器的方法 - Google Patents
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Abstract
一种封装第一器件(12,102)的方法,该第一器件具有第一主表面和第二主表面,该方法包括:在第一器件的第二主表面上和第一器件的侧面周围形成第一层(14,104),并且把第一器件的第一主表面暴露,其中第一层是从由封装物和聚合物组成的群组中选出来的;在第一器件的第一主表面上形成第一电介质层(52,152,170);在第一电介质层中形成过孔(30,32,128);在过孔内和在第一电介质层的一部分上形成种籽层(38,40,136);将连接器物理地耦合到种籽层(82,116);以及在种籽层上镀敷导电材料以在第一过孔内和在第一电介质层的一部分上形成第一互连(90,92,144,164)。
Description
技术领域
本发明一般涉及半导体器件,更具体地,涉及封装预制连接器和半导体器件。
背景技术
典型地,为了在工作期间的保护而封装器件。这些封装的器件和其它的器件一起被置于印制电路板(PCB)上。带有上述器件的PCB用在诸如计算机或蜂窝电话的产品中。由于希望减小诸如计算机和蜂窝电话的产品的尺寸,因此需要在不牺牲功能的情况下减小PCB和封装的器件的尺寸。在很多情况下,期望有附加的功能,同时还提供连接的便利。例如,可以期望提供要求最少制造的(如果有的话)到半导体器件的连接。因此,需要有一种可以提供便利的连接、同时具有至少一些其它半导体封装的益处的封装方法。
附图说明
本发明是利用举例来说明的,而不局限于附图,其中同样的附图标记指示类似的元件。本领域技术人员应当理解,图中的元件是为了简单和清楚而示出,不一定按比例绘制。
图1是根据一个实施例、具有半导体器件的加工件在处理阶段的截面图;
图2是图1的加工件在随后的处理阶段的截面图;
图3是图2的加工件在随后的处理阶段的截面图;
图4是图3的加工件在随后的处理阶段的截面图;
图5是图4的加工件在随后的处理阶段的截面图;
图6是图5的加工件在随后的处理阶段的截面图;
图7是图6的加工件在随后的处理阶段的截面图;
图8是图7的加工件在随后的处理阶段的截面图;
图9是图8的加工件在随后的处理阶段的截面图;
图10是图9的加工件在随后的处理阶段的截面图;
图11是图10的加工件在随后的处理阶段的截面图;
图12是图11的加工件在随后的处理阶段的截面图;
图13是图12的加工件在随后的处理阶段的截面图;
图14是根据另一实施例的具有半导体器件的加工件在处理阶段的截面图;
图15是图14的加工件在随后的处理阶段的截面图;
图16是图15的加工件在随后的处理阶段的截面图;
图17是图16的加工件在随后的处理阶段的截面图;
图18是图17的加工件在随后的处理阶段的截面图;
图19是图18的加工件在随后的处理阶段的截面图;
图20是图19的加工件在随后的处理阶段的截面图;
图21是图20的加工件在随后的处理阶段的截面图;
图22是图21的加工件在随后的处理阶段的截面图;以及
图23是图15的加工件在随后的处理阶段的截面图。
具体实施方式
在一个方面,半导体器件和预制连接器一起形成在单个封装中。预制连接器的管脚被置于种籽层附近,并且随后的镀敷(plating)步骤使镀层与管脚物理接触并且电接触。镀层还与半导体器件电接触,以便在管脚和半导体器件之间制造电接触。随后的绝缘层的沉积为将连接器和半导体器件保持在一起提供了物理支持。
图1示出了加工件10,包括除了顶部之外全部被绝缘层14包围的半导体器件12。还由虚线16示出了定义切单区域(singulation area)的切单边界(singulation boundary)。这示出了加工件10在哪里将与其它加工件分离,该其它加工件可以与加工件10相同或不同。图10的整体结构是用于从位于包装物(container)中的多个切单的管芯建立封装的处理。具有接触的侧面被带子绑起(tape)以保护接触。在下接触配置中,材料在多个管芯上方流过。在固化所述材料之后,由所述材料维系在一起作为一个单元的多个管芯被从包装物中移除,并且移除带子。随后的沉积绝缘层和导电层的步骤形成了封装集成电路。在图1的例子中,流动以形成绝缘层14的材料优选的是聚合物,但也可以使用其它材料,例如环氧化物。在这种情况下聚合物是优选的,因为将形成通过该聚合物的过孔。如果过孔不被形成为通过所述聚合物,则环氧化物可能是优选的,因为环氧化物很可能更加成本有效。关于这类封装,对于具有过孔的绝缘层来说聚合物是通常优选的,而对于不具有过孔的绝缘层来说环氧化物是通常优选的。具有过孔的层典型地是大约20微米。厚度也可以大于或小于该数值,尤其可以如所期望的那样使其显著地大于该数值。半导体器件12具有在一个主表面(顶面)上暴露的接触18、20、22和24。另一个主表面(底面)具有覆盖其的绝缘层14。绝缘层14包围其它侧面。
图2示出了在半导体器件12顶面上方沉积绝缘层26以及形成通过绝缘层以分别暴露接触18、20、22和24的过孔28、30、32和34之后的加工件10。
图3示出了在绝缘层26上方形成分别位于过孔28、30、32和34中并且分别与接触18、20、22和24接触的种籽层36、38、40和42之后的加工件10。通过沉积薄金属层以传统的种籽层方式形成种籽层36、38、40和42,接着利用传统的掩模和蚀刻技术有选择地蚀刻薄金属层。过孔可以是大约100微米,但是它们也可以显著地不同于100微米。
图4示出了在通过镀敷进行金属沉积以使得在种籽层36、38、40和42存在的位置分别形成导电层44、46、48和50之后的加工件10。
图5示出了在优选通过沉积在半导体器件12顶面上方形成绝缘层52之后的加工件10。绝缘层52遍布整个切单区域、绝缘层26和导电层44、46、48和50。在沉积绝缘层52之后,如朝着半导体器件12的底面看去所观察到的,翻转加工件10,并且过孔54和56被分别形成穿过绝缘层14和16以暴露导电层44和50。
图6示出了形成在绝缘层14上、分别位于过孔54和56中并且分别与导电层44和50接触的种籽层58和60之后的加工件10。
图7示出了在种籽层58和60存在的位置形成导电层62和64,在绝缘层14和导电层62和64上的整个切单区域中形成绝缘层66,并且形成通过绝缘层66以分别暴露导电层62和64的过孔68和70之后的加工件10。过孔68和70的形成可以被推迟到在稍后的处理中。
图8示出了在将带子72加到绝缘层66以及过孔68和70上之后的加工件10,带子72在随后的处理期间保护导电层62和64。接着翻转加工件10用于在半导体器件12的顶面上进行处理。
图9示出了在形成过孔74和76以分别暴露导电层46和48,以及形成在绝缘层52上、分别位于过孔74和76中并且分别与导电层46和48接触的种籽层78和80之后的加工件10。
图10示出了具有预制连接器82的加工件10,所述预制连接器82具有分别与种籽层78和80接触地设置的管脚84和86。在这个例子中,种籽层78和80从过孔74和76充分地延伸,以便管脚84和86确实能被设置在导电层84和86上。如果管脚84和86可以被确保具有足够的位置确定性,则一个选择是使过孔74和76足够大到可容纳管脚84和86。预制连接器在上下文中意指能够在连接器的两侧之间提供电连接的单元,其中至少一侧能够通过摩擦、压力或一些其它容易与另一连接器相反的装置提供物理支持以维持电接触。由此,不需要例如焊接技术(例如利用焊锡)来维持连接器到连接器接触。如图10所示,保护盖88覆盖连接器82的电接触的区域,连接器82也具有维持电接触的物理支持。
图11示出了在进行如下步骤之后的加工件10,所述步骤是具有在种籽层78和80以及管脚84和86上沉积金属的效果以分别在种籽层78和80上以及分别在管脚84和86周围形成导电层90和92的镀敷步骤。作为替代,与连接器82的主体部分邻接的管脚84和86的一部分可以覆有隔离体,从而镀层不会延伸到连接器的主体。取决于连接器,因为可靠性原因而将镀层与连接器的主体隔开可能是有利的。
图12示出了在绝缘层52及导电层90和92之上的整个切单区域中以及沿着连接器82的侧面沉积绝缘层94之后的加工件10。这保护了导电层90和92并且提供物理支持以便使连接器82保持在适当的位置。
图13示出了在移除带子72,形成分别与导电层62和64接触的焊球96和98,执行切单并且移除保护盖88之后的加工件10。由此,加工件10准备好安装到电子产品中。保护盖可以留在连接器82上。在镀敷处理中,对于种子和镀层来说优选的金属是铜。在形成焊球的情况下,可以有益地在形成诸如焊球96和98的焊球之前在铜上提供诸如镍-金(NiAu)的插入层或牺牲保护覆层。
图14示出了加工件100,包括除了顶部之外全部被绝缘层104包围的半导体器件102以及在绝缘层104的位于半导体器件102和切单线114之间的一部分之上的连接器116。连接器116由带子黏附地固定到绝缘层104。此外,虚线114示出了定义切单区域的切单边界。半导体器件具有暴露在顶面上的接触106、108、110和110。连接器116具有管脚118和120,管脚118和120在绝缘层104上方从连接器116的主体横向延伸。与管脚118相比,管脚120距绝缘层104的顶面更高。保护盖122覆盖连接器116的具有物理支持以维持电接触的一侧上的电接触。
图15示出了在半导体器件102顶面上、在绝缘层104上以及连接器124周围沉积绝缘层124之后的加工件100。绝缘层124为连接器116提供物理支持。绝缘层124大约与管脚118位于绝缘层104上方的一样厚。在沉积过程中,绝缘层124的薄层很可能在管脚118之上。在这一点上,可以有益地在没有掩模的情况下进行各向同性的蚀刻以移除管脚118上的绝缘层部分。这将降低绝缘层124的厚度,但是可以选择绝缘层124的初始厚度来将回蚀刻考虑在内。
图16示出了在形成通过绝缘层124以暴露接触106、108、110和112的过孔128、130、132和134之后的加工件100。此外,在过孔形成期间,管脚118的侧面被暴露以保证从这些侧面移除绝缘层124,从而可以制造到管脚118的电接触。在这个例子中,管脚120与管脚118对齐,从而使得在管脚118上除去绝缘层124变得困难。纵向偏移管脚的连接器将允许从管脚124的顶部方便地除去绝缘层124。为保证管脚124的侧面被暴露,进行到绝缘层124中的某些蚀刻,使得孔126与管脚118的侧面邻接。这个孔可以延伸到绝缘层104,但仅仅到达绝缘层104。
图17示出了形成位于绝缘层124上、分别位于过孔128、130、132和134中并且分别与接触106、108、110和112接触的种籽层136、138、140和142之后的加工件100。种籽层136延伸到包括其侧面的管脚118。
图18示出了在种籽层136、138、140和142存在的位置分别镀敷形成导电层144、146、148和150之后的加工件100。这示出导电层144与管脚118的接触。
图19示出了在导电层144、146、148和150上、在绝缘层124上以及在连接器116周围形成绝缘层152之后的加工件100。绝缘层152为连接器116提供了支持。
图20示出了在形成分别与导电层146、148和150接触的导电层154、156和158之后的加工件。这是通过之前描述的在镀敷之后形成过孔以及种籽层来实现的。在这个例子中,在对用于选择性移除部分种籽层的掩模进行曝光的光刻期间,由于管脚120的遮蔽,也有可能在管脚120下面形成导电层160。导电层160被绝缘材料包围,将不会对电性能有不利影响。图20还示出了在绝缘层152上、在导电层154、156和158上以及在连接器116周围形成绝缘层162之后的加工件100。绝缘层162为连接器162提供物理支持。其也示出了管脚120之上的绝缘层162的一部分。对于管脚118,这部分绝缘层162可以通过各向同性的蚀刻移除。
图21示出了在形成与管脚120接触的导电层164之后的加工件100,该形成过程类似于形成与管脚118接触的导电层144。还示出了分别与导电层156和158接触的导电层166和168。
图22示出了在导电层164、166和168上、在绝缘层162上以及在连接器116周围形成绝缘层170之后的加工件100。还示出了暴露导电层166和168的过孔开口。
图23示出了形成分别与导电层166和168接触的焊球172和174,按线114进行切单,以及除去保护盖122之后的加工件100。在这种情况下,导电层166和168具有可以被认为是可焊的接触并位于与连接器相同的侧面上的暴露部分。可以用和图1-13所示的一样的方法形成导电层,从而可焊的接触与连接器一起被嵌入产生的封装集成电路中作为连接器116,该可焊的接触可以位于该连接器的相对侧上。类似的,在与用图14-23所示的方式形成的连接器的相同侧面上,图13的加工件10可以具有可焊的接触。此外,连接器和可焊的接触可以与示出的情形反向。由此,连接器116或82可以在管芯的底部上而不是所示的顶部上。
由此,示出了预制连接器可以被嵌入到所获得的封装集成电路中,其中,连接器电连接到半导体器件,并且可焊的接触(在加工件的外部可用的可焊的接触)也连接到半导体器件。
在前面的说明书中,已经参考具体实施例描述本发明。然而,本领域技术人员应当理解可以进行各种修改和变化,而不偏离由下面的权利要求所阐明的本发明的范围。例如,连接器被示出为具有直的边缘,但连接器可以具有锯齿状的边缘,或另外的,连接器可以具有通过绝缘层提供附加固定物(anchoring)的横向延伸。作为另一例子,连接器可以是预先制造的多触点的聚合物连接器。因此,说明书和图将被认为是说明性的而不是限制的意义,并且所有这样的修改将被包括在本发明的范围之内。
益处、优势、问题的解决方案以及可能使任何益处、优势或解决方案出现或变得更加显著的任何元素不理解为任何或全部的权利要求的关键的、要求的或必需的特征或元素。本文中使用的术语“一”定义为一个或多于一个,即使其它元素被清楚地声明为是权利要求书或说明书中的一个或多个。本文使用的术语“多个”定义为两个或多于两个。本文使用的术语“另外的”定义为至少第二或更多。本文使用的术语“耦合”定义为连接的,不过不必直接地连接,也不必机械地连接。此外,在说明书和权利要求中的术语“前”、“后”、“顶”、“底”、“上”、“下”、“侧”等等(如果有的话)是用于描述的目的而不必描述永久的相对位置。应当理解,如是使用的术语在适当的环境下是可互换的,从而本文描述的本发明的实施例例如能够在除了示出的这些方向之外的方向上工作,或相反,在本文描述的方向上工作。
Claims (20)
1.一种封装第一器件的方法,该第一器件具有第一主表面和第二主表面,该方法包括:
在所述第一器件的所述第二主表面上方和所述第一器件的侧面周围形成第一层,并且使所述第一器件的所述第一主表面暴露,其中所述第一层是封装物;
在所述第一器件的所述第一主表面上方形成第一电介质层;
在所述第一电介质层中形成过孔;
在所述过孔内和在所述第一电介质层的一部分上方形成种籽层;
获得预制连接器;
将具有接触部分的所述预制连接器物理地耦合到所述种籽层;以及
在所述种籽层上方镀敷导电材料以在所述过孔内和在所述第一电介质层的一部分上方以及在所述预制连接器的所述接触部分的一部分周围形成第一互连。
2.一种封装第一器件的方法,该第一器件具有第一主表面和第二主表面,该方法包括:
在所述第一器件的所述第二主表面上方和所述第一器件的侧面周围形成第一层,并且使所述第一器件的所述第一主表面暴露,其中所述第一层是聚合物;
在所述第一器件的所述第一主表面上方形成第一电介质层;
在所述第一电介质层中形成过孔;
在所述过孔内和在所述第一电介质层的一部分上方形成种籽层;
获得预制连接器;
将具有接触部分的所述预制连接器物理地耦合到所述种籽层;以及
在所述种籽层上方镀敷导电材料以在所述过孔内和在所述第一电介质层的一部分上方以及在所述预制连接器的所述接触部分的一部分周围形成第一互连。
3.根据权利要求1或2的方法,还包括
在形成所述第一电介质层之前在所述第一器件上方形成第二电介质层;
在所述第二介质层中形成第二互连,其中所述第二互连耦合到所述第一互连;以及
在所述第二电介质层中形成第三互连,其中所述第三互连耦合到外部连接器。
4.根据权利要求3的方法,其中外部连接器包括焊球。
5.根据权利要求3的方法,其中所述外部连接器被形成在所述第一器件的所述第一主表面上方,并且所述预制连接器被形成在所述第一器件的所述第一主表面上方。
6.根据权利要求3的方法,其中所述外部连接器位于所述第一器件的所述第二主表面上方,并且所述预制连接器被形成在所述第一器件的所述第一主表面上方。
7.根据权利要求3的方法,其中将所述预制连接器物理地耦合到所述种籽层包括将所述预制连接器设置在所述第一器件的所述第一主表面上方,其中所述第一器件的所述第一主表面包括接触。
8.根据权利要求1或2的方法,其中将所述预制连接器物理地耦合到所述种籽层包括将所述预制连接器设置在所述第一器件的所述第二主表面上方,其中所述第一器件的所述第一主表面包括接触。
9.根据权利要求1或2的方法,其中将所述预制连接器物理地耦合到所述种籽层包括:
将所述预制连接器设置在所述第一层上方,其中:
所述第一层包括邻近第二部分的第一部分;
所述第一器件被形成在所述第一层的所述第一部分中;
所述预制连接器被设置在所述第一层的所述第二部分上方;
所述预制连接器包括侧面接触;并且
所述侧面接触耦合到所述种籽层。
10.根据权利要求9的方法,其中所述侧面接触是从由插座连接器和插头连接器组成的组中选出的。
11.一种封装第一器件的方法,该第一器件具有第一主表面和第二主表面,该方法包括:
在所述第一器件的所述第一主表面上方形成电介质层;
在所述电介质层中形成第一过孔;
在所述电介质层中形成第二过孔;
在所述第一过孔中形成第一种籽层;
在所述第二过孔中形成第二种籽层;
获得预制连接器;
将预制连接器的至少一部分设置在所述电介质层上方,其中形成所述第一种籽层以及设置所述预制连接器的至少一部分将所述预制连接器物理地耦合到所述第一器件;
镀敷所述第一种籽层以形成第一互连;
镀敷所述第二种籽层以形成第二互连;以及
将所述第二互连耦合到第二外部连接器。
12.根据权利要求11的方法,其中所述预制连接器和所述第二外部连接器是不同类型的连接器。
13.根据权利要求12的方法,其中所述第二外部连接器包括焊球。
14.根据权利要求13的方法,其中所述预制连接器和所述第二外部连接器被形成在所述第一器件的所述第一主表面上方,其中所述第一主表面包括接触。
15.根据权利要求11的方法,其中,在设置所述预制连接器的至少一部分的步骤之后形成所述第一种籽层。
16.根据权利要求11的方法,其中,在设置所述预制连接器的至少一部分的步骤之前形成所述第一种籽层。
17.一种封装第一器件的方法,该第一器件具有第一主表面和第二主表面,该方法包括:
在所述第一器件的第二主表面上方以及所述第一器件的侧面周围形成第一层,并且使所述第一器件的所述第一主表面暴露,其中所述第一层是封装物;
在所述第一器件的所述第一主表面上方形成第一电介质层;
使预制连接器嵌入到至少所述第一电介质层中,包括:
在所述第一电介质层中形成过孔;
在所述过孔内和在所述第一电介质层的一部分上方形成种籽层;
将所述预制连接器物理地耦合到所述种籽层;以及
在所述种籽层上方镀敷导电材料;
其中所述预制连接器包括管脚;以及
形成从所述第一器件的所述第一主表面到所述预制连接器的管脚的互连。
18.根据权利要求17的方法,还包括切割所述封装物以切单所述第一器件和所述预制连接器。
19.一种封装第一器件的方法,该第一器件具有第一主表面和第二主表面,该方法包括:
在所述第一器件的第二主表面上方以及所述第一器件的侧面周围形成第一层,并且使所述第一器件的所述第一主表面暴露,其中所述第一层是聚合物;
在所述第一器件的所述第一主表面上方形成第一电介质层;
使预制连接器嵌入到至少所述第一电介质层中,包括:
在所述第一电介质层中形成过孔;
在所述过孔内和在所述第一电介质层的一部分上方形成种籽层;
将所述预制连接器物理地耦合到所述种籽层;以及
在所述种籽层上方镀敷导电材料;
其中所述预制连接器包括管脚;以及
形成从所述第一器件的所述第一主表面到所述预制连接器的管脚的互连。
20.根据权利要求19的方法,还包括切割所述聚合物以切单所述第一器件和所述预制连接器。
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Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8217511B2 (en) * | 2007-07-31 | 2012-07-10 | Freescale Semiconductor, Inc. | Redistributed chip packaging with thermal contact to device backside |
TWI360207B (en) | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
US8035216B2 (en) * | 2008-02-22 | 2011-10-11 | Intel Corporation | Integrated circuit package and method of manufacturing same |
US8410584B2 (en) | 2008-08-08 | 2013-04-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
FR2938976A1 (fr) * | 2008-11-24 | 2010-05-28 | St Microelectronics Grenoble | Dispositif semi-conducteur a composants empiles |
TWI456715B (zh) * | 2009-06-19 | 2014-10-11 | Advanced Semiconductor Eng | 晶片封裝結構及其製造方法 |
TWI466259B (zh) * | 2009-07-21 | 2014-12-21 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法 |
TWI405306B (zh) | 2009-07-23 | 2013-08-11 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體 |
TWI528514B (zh) * | 2009-08-20 | 2016-04-01 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
US20110084372A1 (en) | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US20110108999A1 (en) * | 2009-11-06 | 2011-05-12 | Nalla Ravi K | Microelectronic package and method of manufacturing same |
US8378466B2 (en) | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
US8327532B2 (en) * | 2009-11-23 | 2012-12-11 | Freescale Semiconductor, Inc. | Method for releasing a microelectronic assembly from a carrier substrate |
TWI497679B (zh) * | 2009-11-27 | 2015-08-21 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8937381B1 (en) * | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US8742561B2 (en) | 2009-12-29 | 2014-06-03 | Intel Corporation | Recessed and embedded die coreless package |
US8901724B2 (en) | 2009-12-29 | 2014-12-02 | Intel Corporation | Semiconductor package with embedded die and its methods of fabrication |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8372689B2 (en) | 2010-01-21 | 2013-02-12 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof |
US8320134B2 (en) | 2010-02-05 | 2012-11-27 | Advanced Semiconductor Engineering, Inc. | Embedded component substrate and manufacturing methods thereof |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8535989B2 (en) | 2010-04-02 | 2013-09-17 | Intel Corporation | Embedded semiconductive chips in reconstituted wafers, and systems containing same |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8319318B2 (en) | 2010-04-06 | 2012-11-27 | Intel Corporation | Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages |
US8618652B2 (en) | 2010-04-16 | 2013-12-31 | Intel Corporation | Forming functionalized carrier structures with coreless packages |
US9847308B2 (en) | 2010-04-28 | 2017-12-19 | Intel Corporation | Magnetic intermetallic compound interconnect |
US8939347B2 (en) | 2010-04-28 | 2015-01-27 | Intel Corporation | Magnetic intermetallic compound interconnect |
US8313958B2 (en) | 2010-05-12 | 2012-11-20 | Intel Corporation | Magnetic microelectronic device attachment |
US8434668B2 (en) | 2010-05-12 | 2013-05-07 | Intel Corporation | Magnetic attachment structure |
US8609532B2 (en) | 2010-05-26 | 2013-12-17 | Intel Corporation | Magnetically sintered conductive via |
US20120001339A1 (en) | 2010-06-30 | 2012-01-05 | Pramod Malatkar | Bumpless build-up layer package design with an interposer |
US8372666B2 (en) | 2010-07-06 | 2013-02-12 | Intel Corporation | Misalignment correction for embedded microelectronic die applications |
US8216918B2 (en) | 2010-07-23 | 2012-07-10 | Freescale Semiconductor, Inc. | Method of forming a packaged semiconductor device |
US8238113B2 (en) * | 2010-07-23 | 2012-08-07 | Imbera Electronics Oy | Electronic module with vertical connector between conductor patterns |
US8754516B2 (en) | 2010-08-26 | 2014-06-17 | Intel Corporation | Bumpless build-up layer package with pre-stacked microelectronic devices |
US8304913B2 (en) | 2010-09-24 | 2012-11-06 | Intel Corporation | Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
US8937382B2 (en) | 2011-06-27 | 2015-01-20 | Intel Corporation | Secondary device integration into coreless microelectronic device packages |
US8848380B2 (en) | 2011-06-30 | 2014-09-30 | Intel Corporation | Bumpless build-up layer package warpage reduction |
US9224674B2 (en) * | 2011-12-15 | 2015-12-29 | Intel Corporation | Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages |
US9257368B2 (en) | 2012-05-14 | 2016-02-09 | Intel Corporation | Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias |
KR101947722B1 (ko) * | 2012-06-07 | 2019-04-25 | 삼성전자주식회사 | 적층 반도체 패키지 및 이의 제조방법 |
CN104321864B (zh) | 2012-06-08 | 2017-06-20 | 英特尔公司 | 具有非共面的、包封的微电子器件和无焊内建层的微电子封装 |
US9806048B2 (en) * | 2016-03-16 | 2017-10-31 | Qualcomm Incorporated | Planar fan-out wafer level packaging |
WO2018009671A1 (en) | 2016-07-07 | 2018-01-11 | Stern Mark S | Spinous laminar clamp assembly |
US10515921B2 (en) * | 2017-07-27 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of fabricating semiconductor package |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1333560A (zh) * | 2000-07-07 | 2002-01-30 | 索尼公司 | 半导体封装及其制造方法 |
US6797145B2 (en) * | 1999-08-27 | 2004-09-28 | Lex Kosowsky | Current carrying structure using voltage switchable dielectric material |
Family Cites Families (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4088546A (en) | 1977-03-01 | 1978-05-09 | Westinghouse Electric Corp. | Method of electroplating interconnections |
US5829128A (en) * | 1993-11-16 | 1998-11-03 | Formfactor, Inc. | Method of mounting resilient contact structures to semiconductor devices |
US4866501A (en) | 1985-12-16 | 1989-09-12 | American Telephone And Telegraph Company At&T Bell Laboratories | Wafer scale integration |
US5354695A (en) * | 1992-04-08 | 1994-10-11 | Leedy Glenn J | Membrane dielectric isolation IC fabrication |
US5948533A (en) * | 1990-02-09 | 1999-09-07 | Ormet Corporation | Vertically interconnected electronic assemblies and compositions useful therefor |
US5250843A (en) | 1991-03-27 | 1993-10-05 | Integrated System Assemblies Corp. | Multichip integrated circuit modules |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US6400573B1 (en) * | 1993-02-09 | 2002-06-04 | Texas Instruments Incorporated | Multi-chip integrated circuit module |
US5438877A (en) * | 1994-06-13 | 1995-08-08 | Motorola, Inc. | Pressure sensor package for reducing stress-induced measurement error |
US6254815B1 (en) * | 1994-07-29 | 2001-07-03 | Motorola, Inc. | Molded packaging method for a sensing die having a pressure sensing diaphragm |
US6148673A (en) * | 1994-10-07 | 2000-11-21 | Motorola, Inc. | Differential pressure sensor and method thereof |
US5967844A (en) * | 1995-04-04 | 1999-10-19 | Berg Technology, Inc. | Electrically enhanced modular connector for printed wiring board |
US5746307A (en) * | 1997-04-07 | 1998-05-05 | Motorola, Inc. | Switch assembly for a portable radio |
US5977826A (en) * | 1998-03-13 | 1999-11-02 | Behan; Scott T. | Cascaded error correction in a feed forward amplifier |
US6153929A (en) * | 1998-08-21 | 2000-11-28 | Micron Technology, Inc. | Low profile multi-IC package connector |
GB9818840D0 (en) * | 1998-08-29 | 1998-10-21 | Koninkl Philips Electronics Nv | Personal communications apparatus |
KR100300527B1 (ko) * | 1998-09-03 | 2001-10-27 | 윤덕용 | 밀봉형무선압력측정소자및그제조방법 |
US6346742B1 (en) * | 1998-11-12 | 2002-02-12 | Maxim Integrated Products, Inc. | Chip-scale packaged pressure sensor |
US6869870B2 (en) * | 1998-12-21 | 2005-03-22 | Megic Corporation | High performance system-on-chip discrete components using post passivation process |
KR20010002843A (ko) * | 1999-06-18 | 2001-01-15 | 김영환 | 몰드형 웨이퍼 레벨 패키지 |
JP2001024312A (ja) * | 1999-07-13 | 2001-01-26 | Taiyo Yuden Co Ltd | 電子装置の製造方法及び電子装置並びに樹脂充填方法 |
US6316287B1 (en) * | 1999-09-13 | 2001-11-13 | Vishay Intertechnology, Inc. | Chip scale surface mount packages for semiconductor device and process of fabricating the same |
KR100462980B1 (ko) * | 1999-09-13 | 2004-12-23 | 비쉐이 메저먼츠 그룹, 인코포레이티드 | 반도체장치용 칩 스케일 표면 장착 패키지 및 그 제조공정 |
US6271060B1 (en) * | 1999-09-13 | 2001-08-07 | Vishay Intertechnology, Inc. | Process of fabricating a chip scale surface mount package for semiconductor device |
US6254515B1 (en) * | 1999-10-20 | 2001-07-03 | Cybex International, Inc. | Apparatus for stabilizing a treadmill |
US6350623B1 (en) * | 1999-10-29 | 2002-02-26 | California Institute Of Technology | Method of forming intermediate structures in porous substrates in which electrical and optical microdevices are fabricated and intermediate structures formed by the same |
US6307282B1 (en) * | 1999-12-06 | 2001-10-23 | Motorola, Inc. | Smart switch |
NL1014082C2 (nl) * | 2000-01-17 | 2001-07-18 | Franciscus Antonius Maria Van | Systeem voor het verbinden van elementen. |
US6401545B1 (en) * | 2000-01-25 | 2002-06-11 | Motorola, Inc. | Micro electro-mechanical system sensor with selective encapsulation and method therefor |
US6392257B1 (en) * | 2000-02-10 | 2002-05-21 | Motorola Inc. | Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same |
US6586836B1 (en) * | 2000-03-01 | 2003-07-01 | Intel Corporation | Process for forming microelectronic packages and intermediate structures formed therewith |
US6407929B1 (en) * | 2000-06-29 | 2002-06-18 | Intel Corporation | Electronic package having embedded capacitors and method of fabrication therefor |
KR20030060898A (ko) * | 2000-09-25 | 2003-07-16 | 이비덴 가부시키가이샤 | 반도체소자,반도체소자의 제조방법,다층프린트배선판 및다층프린트배선판의 제조방법 |
US6890829B2 (en) * | 2000-10-24 | 2005-05-10 | Intel Corporation | Fabrication of on-package and on-chip structure using build-up layer process |
US6441753B1 (en) * | 2000-10-25 | 2002-08-27 | Motorola, Inc. | Multi-function key assembly for an electronic device |
GB2371436B (en) * | 2001-01-22 | 2004-09-08 | Nokia Mobile Phones Ltd | Portable telephone |
US7498196B2 (en) * | 2001-03-30 | 2009-03-03 | Megica Corporation | Structure and manufacturing method of chip scale package |
US6825552B2 (en) * | 2001-05-09 | 2004-11-30 | Tessera, Inc. | Connection components with anisotropic conductive material interconnection |
GB0115793D0 (en) * | 2001-06-28 | 2001-08-22 | Univ Cranfield | A novel mediator for electrochemical detection |
JP2004039897A (ja) * | 2002-07-04 | 2004-02-05 | Toshiba Corp | 電子デバイスの接続方法 |
WO2004034759A1 (ja) * | 2002-10-08 | 2004-04-22 | Dai Nippon Printing Co., Ltd. | 部品内蔵配線板、部品内蔵配線板の製造方法 |
US6921860B2 (en) * | 2003-03-18 | 2005-07-26 | Micron Technology, Inc. | Microelectronic component assemblies having exposed contacts |
US6764748B1 (en) * | 2003-03-18 | 2004-07-20 | International Business Machines Corporation | Z-interconnections with liquid crystal polymer dielectric films |
US6838776B2 (en) * | 2003-04-18 | 2005-01-04 | Freescale Semiconductor, Inc. | Circuit device with at least partial packaging and method for forming |
US6921975B2 (en) * | 2003-04-18 | 2005-07-26 | Freescale Semiconductor, Inc. | Circuit device with at least partial packaging, exposed active surface and a voltage reference plane |
US7053799B2 (en) * | 2003-08-28 | 2006-05-30 | Motorola, Inc. | Keypad with illumination structure |
TWI251920B (en) * | 2003-10-17 | 2006-03-21 | Phoenix Prec Technology Corp | Circuit barrier structure of semiconductor package substrate and method for fabricating the same |
US7335972B2 (en) * | 2003-11-13 | 2008-02-26 | Sandia Corporation | Heterogeneously integrated microsystem-on-a-chip |
US7015075B2 (en) * | 2004-02-09 | 2006-03-21 | Freescale Semiconuctor, Inc. | Die encapsulation using a porous carrier |
US7345359B2 (en) * | 2004-03-05 | 2008-03-18 | Intel Corporation | Integrated circuit package with chip-side signal connections |
US20050242425A1 (en) * | 2004-04-30 | 2005-11-03 | Leal George R | Semiconductor device with a protected active die region and method therefor |
US20060146027A1 (en) * | 2004-12-31 | 2006-07-06 | Tracy James L | Keypad and button mechanism having enhanced tactility |
JP2006332094A (ja) * | 2005-05-23 | 2006-12-07 | Seiko Epson Corp | 電子基板の製造方法及び半導体装置の製造方法並びに電子機器の製造方法 |
US7503799B2 (en) * | 2006-08-28 | 2009-03-17 | Commscope Inc. | Communications plug with reverse cordage and anti-snag configuration |
US20080085572A1 (en) | 2006-10-05 | 2008-04-10 | Advanced Chip Engineering Technology Inc. | Semiconductor packaging method by using large panel size |
US20080119004A1 (en) | 2006-11-17 | 2008-05-22 | Burch Kenneth R | Method of packaging a device having a keypad switch point |
-
2006
- 2006-11-17 US US11/561,063 patent/US7588951B2/en not_active Expired - Fee Related
-
2007
- 2007-09-27 KR KR1020097009943A patent/KR101484494B1/ko not_active IP Right Cessation
- 2007-09-27 EP EP07853658A patent/EP2084743A2/en not_active Withdrawn
- 2007-09-27 WO PCT/US2007/079714 patent/WO2008063742A2/en active Application Filing
- 2007-09-27 CN CN2007800393403A patent/CN101529586B/zh not_active Expired - Fee Related
- 2007-09-27 JP JP2009537252A patent/JP2010510663A/ja not_active Withdrawn
- 2007-10-12 TW TW096138316A patent/TW200834767A/zh unknown
-
2009
- 2009-07-28 US US12/510,369 patent/US7655502B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6797145B2 (en) * | 1999-08-27 | 2004-09-28 | Lex Kosowsky | Current carrying structure using voltage switchable dielectric material |
CN1333560A (zh) * | 2000-07-07 | 2002-01-30 | 索尼公司 | 半导体封装及其制造方法 |
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WO2008063742A3 (en) | 2008-07-17 |
CN101529586A (zh) | 2009-09-09 |
US7588951B2 (en) | 2009-09-15 |
US7655502B2 (en) | 2010-02-02 |
US20080119015A1 (en) | 2008-05-22 |
WO2008063742A2 (en) | 2008-05-29 |
KR20090080527A (ko) | 2009-07-24 |
KR101484494B1 (ko) | 2015-01-20 |
TW200834767A (en) | 2008-08-16 |
EP2084743A2 (en) | 2009-08-05 |
JP2010510663A (ja) | 2010-04-02 |
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