CN101501859B - 高功率绝缘栅双极晶体管 - Google Patents
高功率绝缘栅双极晶体管 Download PDFInfo
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Abstract
一种绝缘栅双极晶体管(IGBT)包括具有第一导电类型的衬底(12),具有与第一导电类型相反的第二导电类型的漂移层(16),以及在漂移层中并具有第一导电类型的阱区(18)。外延沟道调节层(40)在漂移层上并且具有第二导电类型。发射极区域(22)从外延沟道调节层的表面延伸通过外延沟道调节层并进入阱区。发射极区域具有第二导电类型并且至少部分定义了阱区中相邻于发射极区域的沟道区。栅极氧化物层(26)在沟道区域上,并且栅极(28)在栅极氧化物层上。相关的方法也被公开。
Description
美国政府利益的陈述
本发明是在ONR/DARPA授予的合同号为N00014-05-C-0202的政府支持下完成的。政府对本发明具有一定的权利。
对相关申请的交叉引用以及要求优先权
本申请要求以2006年8月17日提交的,美国临时专利申请号为60/838,249,发明名称是“高功率绝缘栅双极晶体管”的申请为优先权并请求其利益,该公开的全部内容引入本文作为参考。
背景技术
本发明涉及电子器件。更确切地说,本发明涉及高功率绝缘栅双极晶体管。
由于SiC的高临界场和宽带隙,相对于那些硅上的功率器件,由碳化硅(SiC)制成的功率器件被预期在高速、高功率和/或高温的应用上展现出巨大的优势。对于可以阻断高压的器件,例如超过大约5kV的电压,可能希望具备双极操作以通过从注入的少数载流子获得的电导率调制降低漂移层阻抗。然而,碳化硅双极器件的一个技术难题是随时间的正向电压退化,或许是由于在碳化硅的单晶中基面差排(BPD)的存在。因此,例如SiC肖特基二极管和MOSFET的单极器件典型地运用在高功率应用中。
已经制造出具有10kV阻断能力的SiC DMOSFET,具有大约100mΩ×cm2的比导通电阻。例如,由于它们的多数载流子本性,DMOSFET器件可以展现出例如比100ns还小的非常快的切换速度。然而,随着期望的器件阻断电压增加,例如高达15kV或更高,由于漂移层厚度中对应的增加,MOSFET器件的导通电阻可能显著地增加。由于体迁移率的降低在高温下这种问题可能恶化,其可导致过多的功耗。
随着SiC晶体材料生长的进步,已经发展了一些减少BPD相关问题的途径。例如,来看B.Hull,M.Das,J.Sumakeris,J.Richmond,和S.Krishinaswami,“无漂移10-kv,20-A4H-SiC PiN二极管”,电学材料杂志,2005年第34卷第4号。这些进步可以增强例如半导体闸流管、GTO等的SiC双极器件的开发和/或潜在的应用。即使半导体闸流管和/或GTO可以提供低正向电压降,它们将需要庞大的用于栅极驱动和保护的整流电路。因此,期望具有栅极关断能力的SiC双极器件。由于它们良好的导通态特性,合理的切换速度,和/或极好的安全操作区(SOA),4H-SiC绝缘栅极双极晶体管(IGBT)变得更加适合于功率切换应用。
发明内容
根据一些实施例的基于碳化硅的绝缘栅双极晶体管(IGBT)包括具有第一导电类型的碳化硅衬底,具有与第一导电类型相反的第二导电类型的碳化硅漂移层和位于该漂移层中的阱区,该阱区具有第一导电类型。碳化硅外延沟道调节层在该漂移层上并且具有第二导电类型。发射极区域自外延沟道调节层的表面延伸通过外延沟道调节层并进入该阱区。该发射极区域具有第二导电类型并且至少部分定义了阱区中相邻于发射极区域的沟道区。栅极氧化物层位于沟道区上,栅极位于栅极氧化物层上。
碳化硅漂移层可以包括相邻于阱区的JFET区。发射极区域可以与JFET区隔开并可定义在发射极区域和JFET区之间的沟道区。
在一些实施例中,第一导电类型可以是n型并且第二导电类型可以是p型。
晶体管可以进一步包括:具有第一导电类型的连接器区,从沟道调节层的表面延伸进入阱区;在连接器区上的第一欧姆接触;在发射极区域上并包括不同于第一欧姆接触的材料的第二欧姆接触;以及电连接第一欧姆接触和第二欧姆接触的金属重迭层。
第一欧姆接触可以包括基于镍的导电材料并且第二欧姆接触可以包括基于铝的导电材料。
沟道调节层可以具有大约是0.25μm或更厚的厚度。而且,从发射极区域的底部到阱区的底部大约是0.45μm或更长的距离。沟道调节层可以具有大约0.1μm到大约0.5μm的厚度,并具有大约1×1016cm-3到大约5×1018cm-3的净掺杂浓度。
本发明的一些实施例提供了在碳化硅中形成绝缘栅双极晶体管(IGBT)器件的方法。这些方法包括在n型碳化硅衬底上形成p型碳化硅漂移层,在p型碳化硅漂移层中形成n型阱,并在p型碳化硅漂移层上和n型阱上外延生长p型沟道调节层。可以注入p型掺杂离子以形成延伸通过沟道层进入碳化硅层的表面的n型阱的p型发射极区域。P型发射极区域至少部分定义了n型阱中相邻于p型发射极区域的沟道区域。这些方法进一步包括注入n型掺杂离子以形成n型连接器区,其延伸通过沟道层进入碳化硅层的表面的n型阱中。对注入离子退火。在沟道区上形成栅极氧化物层,并且在栅极氧化物层上形成栅极。
这些方法可进一步包括为注入激活形成石墨覆盖层并且在对注入离子退火后移除石墨覆盖层。对注入离子退火可包括对碳化硅层和石墨覆盖层退火。这些方法可进一步包括在对注入离子退火前晶体化石墨覆盖层。
对注入离子的退火可包括在高于1700℃的温度下对注入离子退火,在一些实施例中高于1800℃。形成栅极氧化物层可以包括在干O2中形成栅极氧化物层,这些方法可进一步包括在湿O2中对栅极氧化物层退火。特别是,形成栅极氧化物层可以包括在干O2中在低于或等于约1200℃的温度下形成栅极氧化物层。
这些方法可进一步包括在形成栅极氧化物层之后且在湿O2中对栅极氧化物层退火之前,在惰性气氛中在低于或等于大约1200℃的温度下对栅极氧化物层退火。
在湿氧中对栅极氧化物层退火可包括在湿O2中在低于或等于大约950℃的温度下对栅极氧化物层退火至少一个小时。
在湿O2中对氧化物层退火可包括在热室内生成高热蒸汽,将高热蒸汽提供给退火室,并在退火室里对氧化物层退火。生成高热蒸汽可以包括对热室加热,给热室提供氢气和氧气,并且燃烧氢气和氧气以形成高热蒸汽,提供给热室的氢气和氧气的氢对氧的分子比大约是1.8或更高。
这些方法可以进一步包括对漂移层注入p型掺杂离子以形成相邻于n型阱的JFET区。p型发射极区域可与JFET区隔开并且可以定义在p型发射极区域和JFET区之间的沟道区。
沟道调节层可以具有大约0.1μm到大约0.5μm的厚度,并且净受主浓度是大约1×1016cm-3到大约5×1018cm-3。
附图说明
所包括的附图有助于对本发明进一步的理解并且构成本申请的一部分,说明了本发明的特定实施例。在附图中:
图1是根据根据本发明的一些实施例的碳化硅绝缘栅双极晶体管(IGBT)器件的截面图。
图2A到2D是展示了根据本发明的一些实施例的IGBT器件的形成中的中间结构的截面图。
图3是说明了根据本发明的一些实施例可能使用的热室和退火室的示意图。
图4-5是根据本发明的一些实施例的IGBT器件的导通状态I-V特性的图。
图6是根据本发明的一些实施例的IGBT器件的漏电流密度相对于阻断电压的曲线图。
图7是根据本发明的一些实施例的用于测试器件的切换特性的钳位电感性切换测试电路拓扑结构的图。
图8是根据本发明的一些实施例的器件的电感性切换波形的图。
具体实施方式
在下文中参照展示本发明的实施例的附图,将更加充分地描述本发明的实施例。然而,本发明可以具体化为很多不同的形式并且不应将其解释为局限于在此提到的实施例中。更合适地,提供这些实施例以使直接并完整地描述公开的发明,并且向本领域技术人员充分传达本发明的范围。相同的数字始终对应相同或相似的部件。
在这里即使称谓第一、第二等用于描述不同的部件,可以理解这些部件不应局限于这些称谓。这些称谓仅仅是用于把一个部件和另一个部件区分开。例如,在并不脱离本发明的范围下,第一部件可以叫做第二部件,并且,类似地,第二部件可以叫做第一部件。在此使用的称谓“和/或”包括相关的列出的一个或多个项目的任意和所有组合。
在此使用的术语目的仅是描述特定的实施例并不是限制本发明。在此采用单数形式“一”和“该”目的是也包括复数形式,除非上下文另外清晰指出。可以进一步理解当在此使用称谓“包括”、“包含”、和/或“含”,明确说明所述的特征、整体、步骤、操作、部件、和/或组件的存在,但是不排除一个或多个其他的特征、整体、步骤、操作、部件、组件,和/或其组合的存在或增加。
除非另外定义,在此采用的所有的称谓(包括技术和科学术语)具有与本发明所属领域的技术人员一般理解相同的意思。可以进一步理解在此使用的称谓应当认为是具有与它们在说明书上下文和相关领域中所一致的意思,并且不能以理想的或过于字面的意思来解释,除非在此被清楚地定义。
可以理解当部件,例如一个层、区或衬底被称为“在”另一个部件“之上”或延伸到另一个部件“之上”时,其可以直接地在另一个部件之上或延伸到直接在另一个部件之上,或也可存在居间的部件。相反地,当部件被称为“直接地在”另一部件“之上”或延伸到“直接在”另一个部件“之上”时,将没有居间部件存在。也可以理解为当部件被称为“连接”或“耦接”到另一部件时,它可以直接地连接或耦接到该另一部件或可以存在居间部件。相反地,当部件被称为“直接连接”或“直接耦接”到另一个部件时,将不存在居间部件。
在此可使用相对性术语例如“在..之下”或“在..之上”或“上部”或“下部”或“水平”或“横向”或“垂直”以描述在图中所示的一个部件、层或区与另一个部件、层、或区的关系。可以理解为这些术语目的是包含器件除了图中所示的方向以外的不同的方向。
在此参考截面图描述的本发明的实施例是本发明的理想化的实施例(和中间结构)的示意图。为了清楚起见图中的层和区的厚度被放大。另外,可以预期到例如,由于制造工艺和/或误差容限而产生从示例的形状的变化。因此,本发明的实施例不应被认为局限于在此所示的特定区域形状,而应该包括例如由于制造而产生的变形。例如,典型地,被示为矩形的注入区域会具有圆形或弯曲的特征和/或在其边缘的注入浓度存在梯度而不是从注入区域到非注入区域的不连续变化。同样地,注入形成的掩埋区可以导致在掩埋区和注入通过其发生的表面之间的区域中的一些注入。因此,图中所示的区域实质上是示意性的并且它们的形状不能代表器件区域的真实形状并且并不意在限制本发明的范围。
本发明一些实施例的描述参考特征化为具有例如n型或p型的导电类型的半导体层和/或区,n型或p型指的是层和/或区中的多数载流子浓度。因此,n型材料具有负电荷电子的多数平衡浓度,同时p型材料具有正电荷空穴的多数平衡浓度。一些材料可以被分配“+”或“-”(如n+,n-,p+,p-,n ++,n--,p++,p--,等),以指示相对于另一层或区的多数载流子的相对大(“+”)或小(“-”)的浓度。然而,这种符号并不意味着在一个层或区中多数或少数载流子的特定浓度的存在。
本发明的一些实施例提供了适用于高功率和/或高温应用的绝缘栅双极晶体管(IGBT)。本发明的一些实施例提供了高压平面IGBT。虽然在此描述的本发明的一些实施例包括碳化硅衬底和外延层,采用其他材料,例如硅、锗、砷化镓、和氮化镓及其合金制成的器件采用在此所述的原理和结构可能是有利的。
首次报道,于2005年,在n型衬底上构造的平面栅5.8kV的SiC中的IGBT。参见2006年ISPSD Proceeding,Q.Zhang,C.Jonas,S.Ryu,A.AgaRwal和J.Palmour的“4H-SiC上的高压IGBT的设计和制造”。由于缺少n沟道IGBT需要的高质量低电阻率p-SiC衬底,选择了p沟道IGBT。该器件在25℃下栅偏压为-30V时展示大约为570mΩ×cm2的微分导通电阻(Rdiff,导通),并且在200℃下衰减到约118mΩ×cm2。高导通电阻主要是由于低的体载流子寿命,以及低的空穴沟道迁移率。
根据本发明的一些实施例的IGBT结构如图1所示。平面器件结构,例如图1的器件10的结构,可以提供工艺简单化和/或增强器件可靠性。然而,可有利地采用其他的器件结构。
图1的器件10包括在n型衬底12上的p型缓冲层14和p漂移外延层16。衬底12可以包括n+型离轴8度的4H-SiC衬底。P漂移层16可以具有大约为110μm的厚度并可以用p型掺杂物以选择为提供期望的阻断电压的掺杂浓度掺杂。例如,为了得到10kV的阻断能力,p漂移层16可以用p型掺杂物掺杂到大约2×1014cm-3到大约6×1014cm-3的掺杂浓度。p型缓冲层14可以具有大约1μm到大约2μm的厚度并且可以用p型掺杂物掺杂到掺杂浓度约1×1017cm-3。提供p型缓冲层14作为沟道停止层以阻碍穿通现象。
在p型漂移层16的表面形成N+阱区18。该n+阱区18可由离子注入形成,可以延伸进入漂移层16大约0.5μm的距离。
在漂移层16上是一外延p型沟道调节层40。该沟道调节层40可具有大约0.1μm到大约0.5μm的厚度,并且可以掺杂p型掺杂物以具有大约1×1016cm-3到大约5×1018cm-3的净受主浓度。特别地,外延p型沟道调节层40可以具有大约0.25μm的厚度并且可以用受主离子例如铝离子以大约为1×1017cm-3的掺杂浓度掺杂。p型沟道调节层40的存在可以调整阈电压和/或提高器件10的反型沟道迁移率。
器件10进一步包括n+型连接器区24和p+型发射极区域22,其可以分别通过例如氮和铝的选择注入来形成。n+连接器区24和p+型发射极区域22延伸通过p型沟道调节层40进入n+阱区18。在一些实施例中,p+发射极区域22的底部和n+阱区18的底部之间的距离d可以是约0.45μm或更多。增加的距离d可以提供n+阱区18更低的电阻,其可导致器件10的改进的导通状态电阻。
可以在器件外围提供基于保护环的边缘终止(未示出)。可以采用其他类型的边缘终止。
器件10包括在相邻的n+阱区18之间的漂移层16中的JFET区20。可以用p型掺杂物注入JFET区20以减少来自相邻的n+阱区18的JFET电阻。在一些实施例中,通过外延生长工艺形成JFET区20。
例如,在栅极绝缘层26上形成多晶硅的栅极28。层间介电层33在器件10的表面上并且电隔离栅极28。
对n+连接器区24形成n型欧姆接触35,并对p+发射极区域22形成p型欧姆接触37。n型欧姆接触35可以包括基于镍的导电层,例如Ni和/或NiSi。p型欧姆接触37可以包括基于铝的导电层,例如Al和/或AlSi。金属重迭层39在层间介电层33上形成并通过n型连接器区24和p型发射极区域22各自的欧姆接触35、37电连接n型连接器区24和p型发射极区域22。在衬底12上形成n型欧姆金属集电极接触32。
图2A到2D展示了可执行的一些操作和可在器件10的形成过程中形成的中间结构10A到10D。参考图2A,在n+型离轴8度的4H-SiC衬底12上通过外延生长形成p型SiC缓冲层14和p-SiC漂移层16。P型缓冲层14可以具有约1μm到约2μm的厚度并以约1×1017cm-3的掺杂浓度用p型掺杂物掺杂。在p型漂移层16形成后,例如,通过施主离子,例如氮,注入在漂移层16中形成n+阱区18。希望注入n+阱区18越深越好。可用的注入能量会限制n+阱区18的深度。
然后在大约1600℃或更高的温度下对结构退火以激活注入离子。特别是,可以在本领域公知的标准SiC激活退火条件下对该结构退火以激活n型掺杂物。
例如,通过在相邻的n+阱区18之间的漂移层16中注入铝形成JFET区20。可以用p型掺杂物注入JFET区20以降低来自相邻n+阱区18的JFET电阻。特别地,可以选择JFET注入量以在将注入损伤保持在可接受的水平的同时降低JFET电阻。在一些实施例中,以足够的量执行JFET注入以在JFET区20中提供约1×1016cm-3的掺杂浓度。在一些实施例中,通过外延生长工艺形成JFET区。
参考图2B,在漂移层16上形成外延沟道调节层40,例如采用公知的SiC外延再生长技术。可以约1×1017cm-3掺杂浓度用受主离子对沟道调节层40掺杂。
该外延沟道调节层40可以调节阈电压和/或提高器件的反型沟道迁移率。而且,该沟道调节层40也可以允许相对于n型阱区18更浅的p型源极区22的形成。通过将p型发射极注入22提升到再生长沟道调节层40的表面来提供更深的n型阱区18,可以减少或防止器件中的闩锁效应。由于p型发射极区域22的底部和n+阱18的底部之间的间距d的增加,深n+阱18可以导致更低的N阱电阻。更低的n阱电阻可以增加器件闩锁效应电流和/或提供更好的导通状态电阻。
参考图2C,例如,分别通过施主和受主离子的选择注入进入或通过外延沟道调节层40形成n型连接器区24和p型发射极区域22。
将理解图2C所示的距离d是n型阱区18垂直范围和p型发射极区域22的垂直范围的函数。一般的,期望使得在p型发射极区域22的底部和n+阱区18的底部之间的间距d越大越好。而且,如上所述,可以在形成p型外延沟道调节层40后形成p型发射极区域22。因此,用于制造器件的系统的最大注入能量决定阱区18的厚度(深度)。然而,p+发射极区域22进入n型阱区18的穿透深度可能会被可大约为0.25μm的外延沟道调节层40的厚度减小。
仍然参考图2C,可以通过硅过压(silicon over pressure)和/或用例如石墨膜的密封层覆盖该结构的情况下,对该结构在大约1600℃或更高的温度下退火,来激活注入掺杂物。在一些实施例中,可以通过采用石墨密封层的在高于1700℃的温度下的退火来激活注入杂质。
高温激活退火(例如1700℃或者更高)可以提高阈电压调节离子的活性,以及对沟道区40中的缺陷退火。然而,该高温退火可能损伤碳化硅漂移层16的表面。
参考图2C,为了减少高温退火导致的损伤,石墨覆盖层50可以优先于形成栅极氧化物26、栅极接触28和发射极接触30而形成在结构10C的表面上。也就是,可优先于为激活注入离子而对结构10C的退火,在结构10C的顶/正面施加石墨覆盖层50,以便在退火中保护该结构的表面。可以通过常规的光致抗蚀剂涂覆方法来施加石墨覆盖层50,并且其可以具有足够在高温退火中保护下面的SiC层的厚度。例如,石墨覆盖层50可以具有约1μm的厚度。可以加热石墨覆盖层50以在沟道调节层40上形成晶体覆盖层。例如,可以通过可以在约1700℃或更高的温度下在惰性气体中执行的热退火激活注入离子。特别地,可以在约1850℃的温度下在氩气中执行热退火5分钟。在高温退火中石墨覆盖层50可以有助于保护外延沟道调节层40和/或漂移层16的表面。
例如,可以通过灰化和热氧化将石墨覆盖层50移除。
注入退火之后,例如,可以沉积具有约1μm厚度的二氧化硅构成的场氧化物(未示出),并对其图案化以暴露器件的有源区。
可以在移除石墨覆盖层50之后在漂移层16的暴露表面上生长栅极绝缘层26。栅极绝缘层26可以包括通过干-湿氧化工艺生长的氧化物层,所述干-湿氧化工艺包括在干氧气中生长体氧化物接着在湿氧气中对体氧化物退火,例如,如美国专利5972801中所述,在此引入其全部公开作为参考。如在此所用的,氧化物在湿氧气中的退火指的是在包含氧气和水蒸气两者的环境中对氧化物的退火。可以在干氧化物生长和湿氧化物生长之间执行退火。例如,在石英炉管中在高达大约为1200℃温度下在干氧中执行干氧氧化物生长至少约2.5个小时的时间。执行干氧化物生长以生长体氧化物层至期望的厚度。干氧化物生长的温度将影响氧化物生长率。例如,更高的工艺温度可以导致更高的氧化物生长率。生长温度的最大值取决于采用的系统。例如,通过采用碳化硅炉替代石英管,干氧生长可以达到更高的温度。然而,更高的温度可能不会改善氧化物的质量。
在一些实施例中,可以在约1175℃的温度下在干氧中执行干氧化物生长约3.5个小时。可以在高达约1200℃的温度下在惰性气氛中对这样生成的氧化物层退火。特别是,得到的氧化物层可以在约1175℃的温度下在Ar中退火大约1小时。
可以在大约950℃或更低的温度下执行湿氧氧化物退火至少约1小时的时间。可限制湿氧退火的温度以阻止SiC/SiO2界面上进一步的热氧化物生长,其可以引入额外的界面态。特别地,可以在大约950℃的温度下在湿氧中执行湿氧退火大约3个小时。由此得到的栅极绝缘层26可以具有大约为500的厚度。
在一些实施例中,可以采用高热工艺生成在湿氧退火步骤中采用的蒸汽,因而得到的湿氧退火可以称为“高热氧化”。参考图3,在高热氧化中,将氧(O2)气和氢(H2)气流进热室210内,热室210与退火室220分离,并且热室210加热到例如约为800℃的高温。在热室210中氢气和氧气燃烧并形成水蒸汽(H2O)和氧气(O2)的混合物,将其供应给退火室220。
在一些情况下,希望调节氢气和氧气进入热室210的流速以使得氢和氧的分子比接近但不超过2∶1的比率。也就是说,希望提供给退火室220的混合物在合理的安全限制内尽可能地湿。在一些情况下,可以采用1.8∶1或1.9∶1的氢/氧比。
再次参考图2D,栅极绝缘层26形成之后,沉积并例如用硼掺杂多晶硅栅极28,随后进行金属化工艺以减小栅极电阻。例如由二氧化硅构成的层间介电层33形成于结构10D上并且覆盖栅极28和结构10D的暴露部分。在层间介电层33中形成通路孔,并且对p型发射极区域22和n型连接器区24形成欧姆接触。可以沉积基于铝的导电材料,例如Al和/或AlSi作为p型欧姆金属发射极接触37,并且沉积例如Ni和/或NiSi的基于Ni的导电层作为n型欧姆金属接触35。可以在快速热退火装置中对所有接触烧结。如图1所示,金属重迭层39,例如厚的Ti/Au层,可以沉积在层间介电层上以电连接p型发射极区域22和n型连接器区24。形成n型连接器接触32作为器件10上的背面接触。
制造如上所述并且具有0.4mm2的面积的有源区的平面IGBT,并在栅极和集电极具有负电势下描绘导通状态和阻断特性。室温下的0.4mm2IGBT的导通态特性如图4所示,其具有约-20V的最大栅极偏压。膝处电压大约为-3V,其显示发射极和集电极良好的欧姆接触。微分导通电阻是88mΩ×cm2,其是高压IGBT的最小值。将这种器件的功耗设置在300W/cm2,集电极电流密度大约为50A/cm2。在该电流密度水平下,集电极电压降大约是-8.65V,其对应的比导通电阻大约是173mΩ×cm2。
在导通状态下,根据本发明实施例的IGBT可以显示正温度系数。对同一个器件图5示出了在200℃下的I-V特性。膝处电压相对保持恒定在-3V。微分导通电阻在栅极偏压为-20V下进一步减小到大约25mΩ×cm2。在集电极电流密度为50A/cm2时,集电极电压降降低到约-5.30V,其对应的比导通电阻约为106mΩ×cm2。高温下的导通电阻减小可能反映了目前采用的SiC材料中的载流子寿命是与IGBT导通状态电流传导能力相关的主要因素。相对于10kV级的SiCDMOSFET,根据本发明一些实施例的IGBT大概是由于不充分的电阻率调制,在室温下仍然显示了较高的电压降。然而,在高温下电压降变得比DMOSFET的值低。
图6展示了在室温下的相同器件的电压阻断特性。特别是,如上所述的IGBT器件在栅电极与发射极接地并浸泡在氟油(Fluorinert)中以防止空气中的电弧的条件下测试。如图6所示,具有比约为0.1mA/cm2还小的漏电流密度的9kV的阻断电压在0V的栅极偏压下已经达到。在器件终止外围中发生了击穿,这可能说明利用更好的边缘终止设计来接近漂移层厚度决定的阻断电压还有余地。
与IGBT结合制造的横向4H-SiC p-MOSFET的空穴迁移率和MOS阈电压的测量显示了MOSFET器件在室温下具有约6.5cm2/V-s的峰值沟道迁移率和约-7.5V的阈电压。当阈电压随着温度降低时,沟道迁移率在100℃下达到约为8.2cm2/V-s的最大值。
在根据本发明的实施例的IGBT器件上执行切换测试。切换测试采用图7所示的钳位电感性切换测试电路拓扑结构。在切换测试中测试的IGBT器件10具有4mm2面积的有源区以达到高导通电流,但是在其他方面测试器件具有和以上所述类似的设计。在该测试电路中,IGBT 10耦接到1.1mH的由续流二极管D1钳位的电感性负载L1。该二极管D1包括两个串联的具有零反向恢复的CreeCSD10120SiC肖特基二极管。一个CSD10120二极管额定为1200V和10A,串联起来的两个可以提供2400V的阻断能力。电容器C1具有2μF的电容并且可以处理高达4kV的电压。电源Vin的从0到-20V的负脉冲用于开启IGBT。电源电压Vss是-500V。
图8显示了25℃下的集电极电压为-500V的切换波形。在图8中,水平轴以500nsec/div测量时间,同时垂直轴以200V/div测量电压和以1A/div测量电流。定义下降时间tfall为关断时集电极电流从峰值2A的90%降落到5%的时间。上升时间trise为开启时集电极电流从2A电流峰值的5%上升到90%的时间。开启延迟时间在施加-20栅极偏压和集电极电流上升到2A峰值之间的时间。关断延迟时间是在栅极偏压的移除和集电极电流降落到0之间的时间。
表格1展示了对不同温度的切换时间。切换时间在室温下总共是约350ns并且在200℃增加到约460ns。该IGBT特征是快速切换能力,其可以在高频下在宽温度范围内工作。关断延迟时间是总的切换时间的主要部分,其主要由输入电容器决定。
表格1-切换时间
温度(℃) | tfall(ns) | trise(ns) | Tdelay(on)(ns) | Tdelay(off)(ns) | ttotal(ns) |
25 | 64 | 14 | 40 | 220 | 338 |
50 | 81 | 16 | 20 | 220 | 337 |
100 | 51 | 10 | 18 | 220 | 299 |
150 | 75 | 14 | 18 | 320 | 427 |
200 | 77 | 7 | 36 | 340 | 460 |
根据本发明的一些实施例的SiC IGBT适合于高功率和/或高温操作。本发明的一些实施例提供了在n型4H-SiC衬底上的高压平面IGBT。在一些实施例中,在25℃约-20V的栅极偏压下达到约88mΩ×cm2的微分导通电阻,并且在200℃降低到约24.8mΩ×cm2。根据本发明的实施例的器件可以展现具有约0.1mA/cm2或更小的漏电流密度的约9kV的阻断电压。在室温下阈电压为-6.5V时达到约6.5cm2/V-s的空穴沟道迁移率,导致增强的导电能力。电感性切换测试显示了根据本发明的一些实施例的IGBT可以在室温和提高的温度下都展现快的切换能力。
根据本发明的一些实施例的IGBT器件可展现出低导通状态电阻。特别是,通过采用掩埋沟道注入/再生长、热氧化、高温注入激活和/或注入激活中的石墨密封中之一或更多,可以达到高沟道迁移率。本发明的一些实施例可以提供优化的单元设计,其具有在高沟道密度和低JFET电阻间更好的平衡。而且,本发明的一些实施例可以提供场停止层,其被配置以在保持期望的阻断能力的同时提高载流子注入效率。通过外延沟道再生长和/或采用高温退火和/或石墨密封的阈值调节/掩埋沟道注入离子的激活可以获得高沟道迁移率。可以通过为获得高空穴载流子浓度的p型外延生长获得来自p型发射极的高多数载流子注入。而且,本发明的一些实施例可以提供降低的n和p型材料上的欧姆接触电阻。
在附图和说明书中,已经揭示了发明的典型实施例并且,虽然采用了专门的术语,但它们仅仅用于普通的和叙述性的意思并且其目的并非在于限制,在接下来的权利要求中将阐述本发明的范围。
Claims (22)
1.一种绝缘栅双极晶体管,包括:
具有第一导电类型的衬底;
具有与第一导电类型相反的第二导电类型的漂移层;
在漂移层中并具有第一导电类型的阱区;
在漂移层上并具有第二导电类型的外延沟道调节层;
从外延沟道调节层的表面延伸通过外延沟道调节层并进入阱区的发射极区域,发射极区域具有第二导电类型并且至少部分定义了阱区中相邻于发射极区域的沟道区;
在沟道区上的栅极氧化物层;
在栅极氧化物层上的栅极;
从沟道调节层的表面延伸进入阱区的具有第一导电类型的连接器区;
在连接器区上的第一欧姆接触;
在发射极区域上并且包含不同于第一欧姆接触的材料的第二欧姆接触;以及
电连接第一欧姆接触和第二欧姆接触的金属重迭层。
2.如权利要求1所述的晶体管,其中漂移层包括相邻于阱区的JFET区,并且其中发射极区域与JFET区隔开并且定义在发射极区域和JFET区之间的沟道区。
3.如权利要求1所述的晶体管,其中第一导电类型是n型并且第二导电类型是p型。
4.如权利要求1所述的晶体管,其中第一欧姆接触包括基于镍的导电材料并且其中第二欧姆接触包含基于铝的导电材料。
5.如权利要求1所述的晶体管,其中发射极区域的底部和阱区的底部之间的距离为0.45μm或更大。
6.如权利要求1所述的晶体q管,其中沟道调节层具有0.1μm到0.5μm的厚度并且具有1×1016cm-3到5×1018cm-3的净掺杂浓度。
7.如权利要求1所述的晶体管,其中衬底包括碳化硅衬底并且其中漂移层包括衬底上的碳化硅外延层。
8.一种晶体管,包括:
n型衬底;
p型漂移层;
在漂移层中的n型阱;
在漂移层上的p型沟道调节层;
延伸通过沟道调节层并进入n型阱的p型发射极区域,p型发射极区域至少部分定义了n型阱中相邻于p型发射极区域的沟道区;
延伸通过沟道调节层并进入n型阱的n型连接器区;
在p型发射极区域上的包括铝的第一欧姆接触;
在n型连接器区上的包括不同于第一欧姆接触的金属的第二欧姆接触,第二欧姆接触包括镍;
在沟道区上的栅极氧化物层;
在栅极氧化物层上的栅极;
棚极上的层间介电层,该层间介电层包括暴露第一欧姆接触的第一开口和暴露第二欧姆接触的第二开口;以及
在层间介电层上并且电连接第一欧姆接触和第二欧姆接触的金属重迭层。
9.一种形成绝缘栅双极晶体管(IGBT)器件的方法,包括:
在n型衬底上形成p型漂移层;
在p型漂移层中形成n型阱;
在p型漂移层和n型阱上外延生长p型沟道调节层;
注入p型掺杂物离子以形成延伸通过沟道调节层并进入漂移层表面的n型阱的p型发射极区域,p型发射极区域至少部分定义了n型阱中相邻于p型发射极区域的沟道区;
注入n型掺杂物离子以形成延伸通过沟道层并进入漂移层表面的n型阱的n型连接器区;
在沟道调节层上形成石墨覆盖层;
对注入离子和石墨覆盖层退火;
在对注入离子退火之后移除石墨覆盖层;
在沟道区上形成栅极氧化物层;以及
在栅极氧化物层上形成栅极。
10.如权利要求9所述的方法,进一步包括在对注入离子退火之前晶体化石墨覆盖层。
11.如权利要求9所述的方法,其中对注入离子的退火包括在高于1700℃的温度下对注入离子退火。
12.如权利要求9所述的方法,其中对注入离子的退火包括在高于1800℃的温度下对注入离子退火。
13.如权利要求9所述的方法,其中形成栅极氧化物层包括在干O2中形成栅极氧化物层,该方法进一步包括在湿O2中对栅极氧化物层退火。
14.如权利要求13所述的方法,其中形成栅极氧化物层包括在低于或等于1200℃的温度下在干O2中形成栅极氧化物层。
15.如权利要求13所述的方法,进一步包括在形成栅极氧化物层之后且在湿O2中对栅极氧化物层退火之前,在低于或等于1200℃的温度下在惰性气氛里对栅极氧化物层退火。
16.如权利要求13所述的方法,其中在湿O2中对栅极氧化物层退火包括在低于或等于950℃的温度下在湿O2中对栅极氧化物层退火。
17.如权利要求16所述的方法,其中在湿O2中对栅极氧化物层退火包括在湿O2中对栅极氧化物层退火至少一小时。
18.如权利要求13所述的方法,其中在湿O2中对氧化物层退火包括在热室中生成高热蒸汽,给退火室提供高热蒸汽,以及在退火室中对氧化物层退火。
19.如权利要求18所述的方法,其中生成高热蒸汽包括对热室加热,给热室提供氢气和氧气,以及燃烧氢气和氧气以形成高热蒸汽,其中以1.8或更高的氢与氧的分子比将氢气和氧气提供给热室。
20.如权利要求9所述的方法,进一步包括注入p型掺杂物离子到漂移层中以形成相邻于n型阱的JFET区,并且其中p型发射极区域与JFET区隔开并且定义p型发射极区域和JFET区之间的沟道区。
21.如权利要求9所述的方法,其中沟道调节层形成为具有0.1μm到0.5μm的厚度,并且其中沟道调节层具有1×1016cm-3到5×1018cm-3的净受主浓度。
22.如权利要求9所述的方法,其中衬底包括碳化硅,并且其中漂移层包括外延碳化硅层。
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CN101501859A (zh) | 2009-08-05 |
KR20090052878A (ko) | 2009-05-26 |
EP2631951B1 (en) | 2017-10-11 |
US20150287805A1 (en) | 2015-10-08 |
WO2008020911A2 (en) | 2008-02-21 |
EP2052414B1 (en) | 2016-03-30 |
US9548374B2 (en) | 2017-01-17 |
EP2631951A3 (en) | 2013-09-04 |
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US20080105949A1 (en) | 2008-05-08 |
EP2631951A2 (en) | 2013-08-28 |
JP5645404B2 (ja) | 2014-12-24 |
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US8710510B2 (en) | 2014-04-29 |
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