CN101442319B - Encoder based on dual-diagonal quasi cyclic shift LDPC code check matrix - Google Patents
Encoder based on dual-diagonal quasi cyclic shift LDPC code check matrix Download PDFInfo
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Abstract
The invention discloses a coder for a double-opposite angle quasi-cyclic shift LDPC code based check matrix. The coder comprises a z frequency divider and an output register, wherein two channels of data storage and pre-coding devices, check bit generators and one-of-two selectors are connected between the z frequency divider and the output register; the data storage and pre-coding devices are used to generate pre-coding bit; the check bit generators are used to generate check bit of the LDPC code; and the one-of-two selectors are used for the selection output of the information bit and the check bit. Each data storage and pre-coding device and each check bit generator are both provided with two working states of storage and operation, the information bit outputted by the two data storage and pre-coding devices and the check bit outputted by the two check bit generators are both inputted to the output register through the one-of-two selectors, and the output register combines the inputted information bit and check bit into coding bit for output. The coder has the advantages of simple structure and high coding efficiency, and can be used for the quick coding of the LDPC code.
Description
Technical field
The invention belongs to the communications field, relate to coding techniques, specifically a kind of FPGA coder structure of realizing fast coding.
Background technology
In modern digital communication systems, for guarantee various data can be reliably, transmission effectively, often to utilize error correction coding.In recent years, along with the development of radio digital communication and the appearance of various high speed data transmission service, study and utilize error correction coding just to seem more and more important.
Theoretical research shows: the performance of low-density checksum LDPC long code surpasses Turbo code, near shannon limit, has linear decoding complexity simultaneously, is applicable to high speed data transfer.The LDPC sign indicating number steps into the evolution of practical application gradually from theoretical research, and the encoder complexity of LDPC sign indicating number and the coding time delay that causes thereof become the key factor that restriction LDPC sign indicating number is used in high-speed data service.
In the encoder design process of existing LDPC sign indicating number, if the method that directly adopts information bit and generator matrix to multiply each other, then encoder complexity is o (n
2), this complexity can cause very big coding time delay when middle long code.Two kinds of solutions are arranged at present usually, and a kind of is to adopt to have the sparse check matrix direct coding of lower triangular structure, and its complexity is o (n); Another kind is to adopt the LDPC sign indicating number with accurate cycle characteristics, be that its check matrix is made of 0 gust of cyclic shift matrices with unit matrix, the Algebraic Structure characteristic of the generator matrix of such LDPC sign indicating number and check matrix helps adopting large scale integrated circuit to realize coder, thereby improves code efficiency.
LDPC sign indicating number in the IEEE.802.16e standard has just been selected the structure with accurate cycle characteristics for use, and has provided three kinds of coding methods: serial code, parallel encoding and the minor matrix coding that multiplies each other.Wherein, fairly simple based on the coder structure of serial code conceptual design, but code efficiency is lower, is difficult to be applied to high speed data transmission system; Encoder based on full parallel encoding conceptual design can effectively improve coding rate, but the hardware complexity height, and it is big to take memory space, realizes relatively difficulty; Based on the multiply each other encoder of encoding scheme design of minor matrix, can effectively improve coding rate, when the matrix-block that decomposes was smaller, implementation complexity was lower, but its encoder complexity still is exponential increase with the increase of matrix exponent number, and minute block size and code length are all had certain restriction.
To sum up, all there is the complexity height in existing encoder, and code efficiency is low, the big deficiency of coding time delay.
Summary of the invention
The purpose of this invention is to provide a kind of encoder based on biconjugate angle quasi cyclic shift LDPC code check matrix, to solve above-mentioned encoder complexity height, code efficiency is low, and the big problem of coding time delay realizes fast coding.
For achieving the above object, the invention provides the technical scheme of two kinds of encoders:
Above-mentioned encoder, wherein the output port of z frequency divider selects input port to link to each other with precoder, second storage with the state of precoder and the first check digit maker, the second check digit maker with first storage respectively, and described two data storages link to each other with output register by two alternative selectors respectively with the output of precoder and two check digit makers.
Above-mentioned encoder, wherein the z frequency divider is exported four road clock division signals, first via clock division signal is directly inputted to the state of first storage and precoder and selects port, the second road clock division signal is selected port by the state that inverter is input to second storage and precoder, Third Road clock division signal is selected port by the state that the inverter and first d type flip flop are input to the first check digit maker, and the four road clock division signal is input to state selection port and two alternative selectors of the second check digit maker respectively by second d type flip flop and 3d flip-flop.
Above-mentioned encoder, wherein first storage all links to each other with information source with the data-in port of precoder with second storage with precoder, receives the data of information source output; First storage links to each other with the information bit input port of output register by first alternative selector with the information bit output port of precoder with second storage with precoder; First storage links to each other with the check digit input port of output register with the second check digit maker and second alternative selector by the first check digit maker respectively with the precoding output port of precoder with second storage with precoder.
Above-mentioned encoder, wherein first storage links to each other with the data-in port of the first check digit maker and the second check digit maker respectively with the precoding output port of precoder with second storage with precoder, and the check digit output port of the first check digit maker and the second check digit maker links to each other with the check digit input port of output register by second alternative selector.
Above-mentioned encoder, wherein the output port of z frequency divider is exported two-way clock division signal, one road clock division signal outputs to the state of storage and precoder and selects input port, and another road clock division signal is selected input port by the state that inverter and d type flip flop output to the check digit maker.
Above-mentioned encoder, wherein storage and precoder are exported the two-way bit signal, one road bit signal is directly exported to the information bit input of output register, another road bit signal is input to the data input pin of check digit maker, outputs to the check digit input of output register by the check digit maker.
Encoder operation principle in the described technical scheme 1 is:
Described two data storages and precoder and two check digit makers are equipped with storage and two operating states of computing, select output signal to control the operating state of each storage and precoder and each check digit maker by the state of z frequency divider.Under the control of state selection signal, the storage of two data is operated in different conditions with precoder, and promptly one when being operated in store status, another is operated in compute mode, alternately produces precoding bit and output information position.This information bit is input to output register by first alternative selector.Under the control of state selection signal, two check digit makers are operated in different conditions, and promptly one when being operated in store status, another is operated in compute mode, two check digit makers alternately produce check digit, and this check digit is input to output register by second alternative selector.Be combined into coded-bit and export by the information bit and the check digit of output register input.
Encoder operation principle in the described technical scheme 2 is:
Described storage and precoder and check digit maker are equipped with storage and two operating states of computing, the operating state that the state selection output signal by the z frequency divider is come control data storage and precoder and check digit maker.Under the control of state selection signal, storage and precoder produce precoding bit and output information position, and this information bit is directly inputted to output register.Under the control of state selection signal, the check digit maker produces check digit, and this check digit is directly inputted to output register.Be combined into coded-bit and export by the information bit and the check digit of output register input.
The present invention is respectively applied for to produce precoding bit and check digit bit owing to the encoder with the LDPC sign indicating number resolves into storage and precoder and two modules of check digit maker, has reduced the coding time delay; Compare simultaneously because the present invention has adopted the bifurcation shift register in storage and precoder and check digit maker, thereby with the barrel shift register that conventional codec adopts, have lower encoder complexity; In addition, owing in the check digit maker, adopted from top to bottom between bifurcation shift register and the modulo 2 adder and two-way recursion annexation from the bottom to top, thereby can further improve the throughput of encoder.
Description of drawings
Fig. 1 is a two-way LDPC encoder theory structure schematic diagram of the present invention;
Fig. 2 is a single channel LDPC encoder theory structure schematic diagram of the present invention.
Embodiment
With reference to Fig. 1, two-way LDPC code coder of the present invention comprises:
The z frequency divider: the clock of mainly finishing input carries out the z frequency division, and this module has an input end of clock mouth and a state to select output port, and state selection output port is used for exporting the clock through behind the z frequency division.
Two data are stored and precoder: are mainly used in precoding processing, promptly produce precoding bit data message, and output information position bit.Each storage and precoder all have two input ports and two output ports, and promptly state is selected input port, data-in port, information bit output port and precoding output port.
Two check digit makers:, generate the check digit of LDPC sign indicating number mainly according to the precoding bit of storage and precoder output.Each check digit maker has two input ports and an output port, and promptly state is selected input port, data-in port and check digit output port.
Output register: be used for k that storage and precoder are sent
bThe m that individual information bit and check digit maker are sent
bIndividual check digit is combined, and forms k
b+ m
b=n
bIndividual final coded data.This output register comprises two input ports and an output port, i.e. information bit input port, check digit input port and coding output port.
Alternative selector: be used for selection output to information bit and check digit bit.
The annexation of these parts is:
The output port of z frequency divider 1 is connected with precoder with storage with the check digit maker respectively, control the clock cycle of its work, first lead-in wire that is z frequency divider 1 output port selects input port directly to link to each other with first storage with the state of precoder 2, second lead-in wire selects input port to link to each other with second storage with the state of precoder 3 by inverter 7, the 3rd lead-in wire selects port to link to each other with first d type flip flop 8 with the state of the first check digit maker 4 by inverter 7, and the 4th lead-in wire selects port with two alternative selectors 11 with 12 to link to each other with 3d flip-flop 10 with the state of the second check digit maker 5 by second d type flip flop 9 respectively.The input port of z frequency divider 1 links to each other with external timing signal.
First storage all links to each other with information source with the data-in port of precoder 3 with second storage with precoder 2, receives the data of information source output; First storage links to each other with the information bit input port of output register 6 by first alternative selector 11 with the information bit output port of precoder 2; The precoding output port links to each other with the data-in port of the first check digit maker 4; Second storage links to each other with the information bit input port of output register 6 by first alternative selector 11 with the information bit output port of precoder 3; The precoding output port links to each other with the data-in port of the second check digit maker 5.
The check digit output port of the first check digit maker 4 and the second check digit maker 5 all links to each other with the check digit input port of output register 6 by second alternative selector 12, and the coding output port of this output register is exported the coded-bit that produces.
Described encoder operation principle is:
Described two data storages and precoder and two check digit makers are equipped with storage and two operating states of computing, select output signal to control the operating state of each storage and precoder and each check digit maker by the state of z frequency divider.Under the control of state selection signal, two data storages are operated in different conditions with precoder, promptly one when being operated in store status, another is operated in compute mode, alternately produce precoding bit and output information position, this information bit is input to output register by first alternative selector.Under the control of state selection signal, two check digit makers are operated in different conditions, and promptly one when being operated in store status, another is operated in compute mode, two check digit makers alternately produce check digit, and this check digit is input to output register by second alternative selector.Be combined into coded-bit and export by the information bit and the check digit of output register input.
Described two data storage with the operation principle of precoder is:
Each storage and precoder are equipped with storage and two operating states of computing, and two operating states alternately occur.When storage and precoder are started working, at first be in store status, promptly will be the k of precoding
bThe bit data move into successively, and are the k of precoding the last time
bThe bit initial data shifts out.Behind z clock, just stored k in storage and the precoder
b* z bit data, and with the k of last time
b* z bit data all shift out.All will carry out the k of precoding
bAfter * z bit data all moved into, storage and precoder just became compute mode, the data of storage are pursued the bit cyclic shift, and carry out precoding.Through z clock, storage and precoder are got back to initial condition, produce z * m simultaneously
bIndividual precoding bit.
Two data storages in the encoder of the present invention select the input signal of port reverse with the state of precoder, make two data storages be operated in different states with precoding, promptly when first storage and precoder 2 are store status, second storage and precoder 3 are compute mode, first alternative selector 11 is selected the information bit of second storage and encoder 3 outputs, and this information bit is exported to the information bit input of output register 6; When second storage and precoder 3 are store status, when first storage and precoder 2 are compute mode, first alternative selector 11 is selected the information bit of first storage and encoder 2 outputs, and this information bit is exported to the information bit input of output register 6.
The operation principle of described two check digit makers is:
Each check digit maker is equipped with storage and two operating states of computing, and two operating states alternately occur.When the check digit maker is started working, at first be in store status, the m that storage and precoder are obtained
bThe bit pre-code data moves into successively.Behind z clock, just stored m in the bifurcation shift register in the check digit maker
b* z data.All m
bAfter * z precoding bit all moved in the check digit maker, the check digit maker transferred compute mode to, and the bifurcation shift register is in the cyclic shift state, and the pre-code data of storage is carried out the check digit that computing produces the LDPC sign indicating number.Through z clock cycle, the bifurcation shift register in the check digit maker is got back to initial condition, has produced all m simultaneously
b* z check bit.The state of two check digit makers of the present invention's design selects the input signal of port reverse, makes two check digit makers be operated in different states.Promptly when the first check digit maker 4 is store status, the second check digit maker 5 is a compute mode, second alternative selector 12 selected the check digit of the second check digit maker, 5 outputs, and this check digit exported to the check digit input of output register 6; When the second check digit maker 5 is a store status, when the first check digit maker 4 was compute mode, second alternative selector 12 selected the check digit of the first check digit maker, 4 outputs, and this check digit exported to the check digit input of output register 6.Output register is with the k of input
bIndividual information bit and m
bIndividual check digit is combined, and forms k
b+ m
b=n
bIndividual final coded data, and this coded data exported.
With reference to Fig. 2, LDPC code coder of the present invention comprises:
The z frequency divider: the clock of mainly finishing input carries out the z frequency division, and this module has an input end of clock mouth and a state to select output port, and state selection output port is used for exporting the clock through behind the z frequency division.
Storage and precoder: be mainly used in precoding processing, promptly produce precoding bit data message, and output information position bit.Storage and precoder have two input ports and two output ports, and promptly state is selected input port, data-in port, information bit output port and precoding output port.
Check digit maker:, generate the check digit of LDPC sign indicating number mainly according to the precoding bit of storage and precoder output.The check digit maker has two input ports and an output port, and promptly state is selected input port, data-in port and check digit output port.
Output register: be used for k that storage and precoder are sent
bThe m that individual information bit and check digit maker are sent
bIndividual check digit is combined, and forms k
b+ m
b=n
bIndividual final coded data.This output register comprises two input ports and an output port, i.e. information bit input port, check digit input port and coding output port.
The annexation of these parts is: the output port of z frequency divider 1 is connected with precoder with storage with the check digit maker respectively, control the clock cycle of its work, first lead-in wire that is z frequency divider 1 output port selects input port directly to link to each other with storage with the state of precoder 2, and second lead-in wire selects port to link to each other with first d type flip flop 8 with the state of check digit maker 4 by inverter 7.The input port of z frequency divider 1 links to each other with external timing signal.
Storage links to each other with information source with the data-in port of precoder 2, receives the data of information source output; Storage links to each other with the information bit input port of output register 6 with the information bit output port of precoder 2; The precoding output port links to each other with the data-in port of check digit maker 4.The check digit output port of check digit maker 4 links to each other with the check digit input port of output register 6, and the coding output port of this output register is exported the coded-bit that produces.
Described encoder operation principle is:
Described storage and precoder and check digit maker are equipped with storage and two operating states of computing, the operating state that the state selection output signal by the z frequency divider is come control data storage and precoder and check digit maker.Under the control of state selection signal, storage and precoder produce precoding bit and output information position, and this information bit is directly inputted to output register.Under the control of state selection signal, the check digit maker produces check digit, and this check digit is directly inputted to output register.Be combined into coded-bit and export by the information bit and the check digit of output register input.
The operation principle of described storage and precoder:
Storage and precoder have two operating states, i.e. store status and compute mode, and two operating states alternately occur.When storage and precoder are started working, at first be in store status, promptly will be the k of precoding
bThe bit data move into successively, and are the k of precoding the last time
bThe bit initial data shifts out.Behind z clock, just stored k in storage and the precoder
b* z bit data, and with the k of last time
b* z bit data all shift out.All will carry out the k of precoding
bAfter * z bit data all moved into, storage and precoder just became compute mode, the data of storage are pursued the bit cyclic shift, and carry out precoding.Through z clock, storage and precoder are got back to initial condition, produce z * m simultaneously
bIndividual precoding bit.
The operation principle of described check digit maker is:
The check digit maker has two operating states, i.e. store status and compute mode, and two states alternately occur.When the check digit maker is started working, at first be in store status, the m that storage and precoder are obtained
bThe bit pre-code data moves into successively.Behind z clock, just stored m in the bifurcation shift register in the check digit maker
b* z data.All m
bAfter * z precoding bit all moved in the check digit maker, the check digit maker transferred compute mode to, and the bifurcation shift register is in the cyclic shift state, and the pre-code data of storage is carried out the check digit that computing produces the LDPC sign indicating number.Through z clock cycle, the bifurcation shift register in the check digit maker is got back to initial condition, has produced all m simultaneously
b* z check bit.
The overall structure of above-mentioned encoder uses the Verilog hardware description language according to the IEEE.802.16e standard, realizes its code length n=2304, code check r=0.5 on the XC3S1000 of Xilinx company chip.
Of the present invention can further specifying by following simulation result.
Simulated conditions: use the clock constraint of 83.3M, on ISE, carry out comprehensive and wiring, and adopt Modelsim software to carry out post-simulation.
The wiring result of simulation result: ISE shows that this encoder has used 65964 equivalent gates altogether, and after the time delay of encoding first, the parallel input of each clock of encoder k
bIndividual data to be encoded can be synchronously and line output k
b+ m
bData behind the individual coding, so the final code rate of encoder can reach (k
b+ m
b) * 50=1200Mb/s.2z the required clock of store status that the coding time delay of designed encoder equals storage and precoder and check digit maker added the flowing water time-delay of two clocks between three modules, amounts to 2z+2=194 clock, and be as shown in table 1.
The accurate parallel encoder performance of table 1.
| Encoding platform | Code rate | The coding time delay | The encoder area |
| The accurate parallel encoder of the LDPC of code length n=2304, code check r=0.5 | 50*24Mb/s?＝1200Mb/s | 194clk/1.94us | 65964 school gates such as grade |
As seen from Table 1, it is few that encoder provided by the invention has a hardware resource of taking, the low and high advantage of code efficiency of implementation complexity.
Claims (3)
1. encoder based on biconjugate angle quasi cyclic shift LDPC code check matrix, comprise z frequency divider and output register, it is characterized in that: be connected with two paths of data storage and precoder, check digit maker and alternative selector between z frequency divider and the output register, this storage and precoder are used to produce precoding bit, and output information position bit, this check digit maker is used to produce the check bit of LDPC sign indicating number, and this alternative selector is used for the selection output to information bit and check digit bit;
Described z frequency divider is exported four road clock division signals, first via clock division signal is directly inputted to the state of first storage and precoder and selects port, the second road clock division signal is selected port by the state that inverter is input to second storage and precoder, Third Road clock division signal is selected port by the state that the inverter and first d type flip flop are input to the first check digit maker, and the four road clock division signal is input to state selection port and two alternative selectors of the second check digit maker respectively by second d type flip flop (9) and 3d flip-flop;
Described first storage links to each other with the data-in port of the first check digit maker and the second check digit maker respectively with the precoding output port of precoder with second storage with precoder, and the check digit output port of the first check digit maker and the second check digit maker links to each other with the check digit input port of output register by second alternative selector;
Described first alternative selector with link to each other with the check digit input with the information bit input of output register respectively with the output of second alternative selector.
2. encoder according to claim 1 is characterized in that: first storage all links to each other with information source with the data-in port of precoder with second storage with precoder, receives the data of information source output.
3. encoder based on biconjugate angle quasi cyclic shift LDPC code check matrix, comprise: z frequency divider and output register, it is characterized in that: be connected with a data storage and precoder and a check digit maker between z frequency divider and the output register, this storage and precoder are used to produce precoding bit, and output information position bit, this check digit maker is used to produce the check bit of LDPC sign indicating number;
The output port output two-way clock division signal of described z frequency divider, one road clock division signal outputs to the state of storage and precoder and selects input port, and another road clock division signal is selected input port by the state that inverter and d type flip flop output to the check digit maker;
Described storage and precoder output two-way bit signal, one road bit signal is directly exported to the information bit input of output register, another road bit signal is input to the data input pin of check digit maker, outputs to the check digit input of output register by the check digit maker.
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| US5751744A (en) * | 1993-02-01 | 1998-05-12 | Advanced Micro Devices, Inc. | Error detection and correction circuit |
| US6543029B1 (en) * | 1999-09-29 | 2003-04-01 | Emc Corporation | Error corrector |
| CN101114834A (en) * | 2007-07-31 | 2008-01-30 | 北京航空航天大学 | Encoder device and encoding method for LDPC code |
| CN101141132A (en) * | 2007-10-22 | 2008-03-12 | 清华大学 | Quasi-circulation low density parity code encoder and check bit generating method |
| CN101192833A (en) * | 2006-11-28 | 2008-06-04 | 华为技术有限公司 | A device and method for low-density checksum LDPC parallel coding |
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| US4077028A (en) * | 1976-06-14 | 1978-02-28 | Ncr Corporation | Error checking and correcting device |
| US5751744A (en) * | 1993-02-01 | 1998-05-12 | Advanced Micro Devices, Inc. | Error detection and correction circuit |
| US6543029B1 (en) * | 1999-09-29 | 2003-04-01 | Emc Corporation | Error corrector |
| CN101192833A (en) * | 2006-11-28 | 2008-06-04 | 华为技术有限公司 | A device and method for low-density checksum LDPC parallel coding |
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