CN101431327B - Bolt lock device - Google Patents
Bolt lock device Download PDFInfo
- Publication number
- CN101431327B CN101431327B CN2007101850681A CN200710185068A CN101431327B CN 101431327 B CN101431327 B CN 101431327B CN 2007101850681 A CN2007101850681 A CN 2007101850681A CN 200710185068 A CN200710185068 A CN 200710185068A CN 101431327 B CN101431327 B CN 101431327B
- Authority
- CN
- China
- Prior art keywords
- current
- circuit
- transistor
- signal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
A latching device comprises an amplification circuit, a latching unit and a bias circuit. The amplification circuit is used for receiving a first bias current in a first state, so as to amplify an input signal and produce an amplified signal; the latching unit is used for latching the amplified signal and receiving a second bias current in a second state, so as to output the amplified signal; the bias circuit is used for supplying the first bias current to the amplification circuit, and supplying the second bias current to the latching unit; and the bias circuit comprises a first bias module used for supplying a third bias current to the amplification circuit in the first state, and a second bias module used for supplying a fourth bias current to the amplification circuit in the first state, wherein, the first bias current equals to the sum of the third bias current and the fourth bias current.
Description
Technical field
The present invention relates to a kind of bolt lock device, but the bolt lock device of particularly a kind of high frequency running.
Background technology
Among integrated circuit, often need use clock signals of different frequencies, to carry out different operations; Therefore, phase-locked loop (phase locked loop)/frequency synthesizer (synthesizer) is used by industry widely, to produce clock signals of different frequencies.
Have now as industry, phase-locked loop/frequency synthesizer has a frequency divider (divider), with signal that the voltage-controlled oscillator (VCO) that it is inner was produced frequency division in addition, so just can make the output of phase-locked loop can produce the signal of institute's palpus frequency by the feedback mechanism of frequency divider.
In general, frequency divider normally utilizes D flip-flop (D-type flip flop) to realize.See also Fig. 1 at this, Fig. 1 is the schematic diagram of 2 frequency divider 100 for existing divisor.As shown in Figure 1, frequency divider 100 realizes that with a D flip-flop 200 wherein, the inverse output terminal Q ' of D flip-flop 200 and input D couple mutually; Thus, the clock signal C K that signal that output Q is exported and input end of clock are imported just can be as shown in Figure 1, has a multiple each other and be 2 relation.Because the principle of D flip-flop is had now by industry with running, so do not give unnecessary details in this in addition.
In addition, because frequency divider often must be operated at high frequency, therefore on real the work, D flip-flop often adopts CML (current mode logic, CML) circuit is realized, it is to be made up of two bolt lock devices, and its relative theory and available circuit structure please refer among the works RFMicroelectronics (I SBN:0-13-887571-5) of Behzad Razavi the 290th page explanation, so just do not give unnecessary details in addition at this.
Yet, if will reach the function of aforementioned frequency divider 100, only the input/output terminal of two bolt lock devices of aforementioned D flip-flop inside must be connected in series mutually, to constitute as shown in Figure 1, feed back to the feedback loop of input D by output Q.As previously mentioned, compared with general standard package, though the D flip-flop of aforementioned currents pattern more is applicable on the high-frequency operation but still its restriction is arranged.
For instance, when circuit designers must design one when removing 4 frequency divider, the simplest way is two-stage to be removed 2 frequency divider (that is serial connection two-stage D flip-flop) be serially connected.
But if a frequency divider except that 4 will be operated in high frequency, common settling mode diminishes D flip-flop internal load (may be resistance or driving component) exactly, so just can make whole RC constant littler.But, also must provide bigger bias current simultaneously, so just can provide enough signal amplitudes, for the D flip-flop use of next stage serial connection.
And the operation that strengthens bias current can suffer from several problems:
At first, first kind of way is that electrorheological is big, but do not adjust the transistorized length-width ratio of bias voltage inside modules (W/L ratio), but such way can make the grid leak pole tension V in bias current source (being generally current mirroring circuit)
DSLittler, even may cause the bias current source to enter triode region (triode region), to such an extent as to electric current can't increase again, and also make frequency of operation to increase again.
And second kind of way is that electrorheological is big, and adjusts the length-width ratio of internal transistor thereupon; Yet the parasitic capacitance that such way can make transistor gate internally extremely see into becomes big; For the D flip-flop of next stage serial connection, the parasitic capacitance that it increased will be the load of prime D flip-flop.In other words, the parasitic capacitance that the next stage D flip-flop is increased can cause the RC of prime D flip-flop to postpone to increase, and then limit the highest frequency of operation of integrated circuit.
Summary of the invention
Therefore one of main purpose of the present invention is to provide a kind of bolt lock device that can the high frequency running, to solve the problems of the prior art.
According to one embodiment of the invention, a kind of bolt lock device (latch) is provided, it includes: an amplifying circuit is used for receiving one first bias current at one first state, to amplify an input signal and to produce an amplifying signal; One bolt-lock unit is coupled to this amplifying circuit, is used for this amplifying signal of bolt-lock, and receives one second bias current at one second state, to export this amplifying signal; An and bias circuit, be coupled to this amplifying circuit and this bolt-lock unit, be used for providing this first bias current to this amplifying circuit at this first state, and provide this second bias current to this bolt-lock unit at this second state, this bias circuit includes: one first bias voltage module, be coupled to this amplifying circuit, be used for when this first state, providing one the 3rd bias current to this amplifying circuit; And one second bias voltage module, be coupled to this amplifying circuit, be used for providing one the 4th bias current to this amplifying circuit at this first state; Wherein, this first bias current equates with the 4th bias current sum with the 3rd bias current.
Bolt lock device of the present invention need not be poor by adjusting transistorized length-width ratio or increasing transistorized gate-source voltage, increases its bias current; Therefore, bolt lock device of the present invention can be avoided existing parasitic capacitance problems, with so that operate in the environment of high frequency more.
Description of drawings
Fig. 1 is the schematic diagram of 2 frequency divider for existing divisor.
Fig. 2 is the schematic diagram of first embodiment of bolt lock device of the present invention.
Fig. 3 is control clock CK and the schematic diagram of oppositely controlling clock CKN.
Fig. 4 is the schematic diagram of second embodiment of bolt lock device of the present invention.
Fig. 5 is the schematic diagram of the 3rd embodiment of bolt lock device of the present invention.
Fig. 6 is the schematic diagram of the 4th embodiment of bolt lock device of the present invention.
Reference numeral explanation numbering
100 frequency dividers
400,500,600,700 bolt lock devices
410,510,610,710 pre-amplification circuits
420,520,620,720 bolt-lock unit
430,530,630,730 bias circuits
431,432,531,532,631,632 bias current sources
640,650,740,750 ac-coupled circuits
731,732 variable current sources.
Embodiment
Below with reference to graphic detailed description the present invention.
See also Fig. 2 at this, Fig. 2 is the schematic diagram of first embodiment of bolt lock device 400 of the present invention.As shown in Figure 2, bolt lock device 400 includes a pre-amplification circuit (preamplifier) 410, one bolt-lock unit 420, and a bias circuit 430.Note that at this pre-amplification circuit 410 and bolt-lock unit 420 have identical functions and operation with aforesaid pre-amplification circuit (pre-amplifier) 211 and bolt-lock unit 212 respectively, so do not give unnecessary details its detailed operation in addition at this.
For instance, bolt-lock unit 420 is to be made up of two staggered transistor M5, M6 that couple (cross-coupled); Because the grid of transistor M5, M6 is coupled to drain electrode each other respectively, therefore reverse signal Von, Vop just can be used to the conducting state of oxide-semiconductor control transistors M5, M6, and then is maintained the voltage level of itself.
Different at this bias circuit 430 that note that bolt lock device 400 of the present invention with existing bias circuit.In the present embodiment, bias circuit 430 includes four transistor M1-M4; Wherein, the grid of transistor M2, M 3 system is coupled to a common-mode voltage V
CM, and the grid of transistor M1, M4 is coupled to control clock CK respectively and oppositely controls clock CKN.See also Fig. 3 at this, Fig. 3 is control clock CK and the schematic diagram of oppositely controlling clock CKN.。
In addition, transistor M1, M2 can be considered a differential circuit (or can be considered a sub-bias voltage module), and its source electrode all is connected to a bias current source 431, and the drain electrode of transistor M1 is coupled to pre-amplification circuit 410, and the drain electrode of transistor M2 then is coupled to external voltage source V
DD
On the other hand, transistor M3, M4 can be considered another differential circuit (or can be considered another sub-bias voltage module), its source electrode all is connected to a bias current source 432, and the drain electrode of transistor M3 is coupled to pre-amplification circuit 410, and the drain electrode of transistor M4 then is coupled to bolt-lock unit 420.
In addition, correct in order to make circuit running, control clock CK, oppositely control clock CKN, with common-mode voltage V
CMMagnitude of voltage must carry out suitable setting; In the present embodiment, when control clock CK is in high logic level when edge (for example positive), its magnitude of voltage is than common-mode voltage V
CMBe height; In addition, when control clock CK is in low logic level (when for example bearing edge), its magnitude of voltage is than common-mode voltage V
CMFor low.For instance, the high logic level of control clock CK can corresponding actual voltage value 3.5V, common-mode voltage V
CMCurrent potential 0 accordingly, and the low logic level of control clock CL can corresponding actual voltage value-3.5V.Yet, aforesaid magnitude of voltage 3.5V, 0V ,-3.5V only illustrates with convenient as an example, but not restriction of the present invention.
And the integrated operation of bolt lock device 400 is just as described below:
At first, when control clock CK was in positive edge (high logic level), the differential circuit of being formed for transistor M1, M2 was owing to control the pairing voltage level of clock CK much larger than common-mode voltage V this moment
CM, therefore, the electric current I 3 that bias current source 431 is provided almost can be passed to pre-amplification circuit 410 by transistor M1 all.On the other hand, the differential circuit of being formed for transistor M3, M4 since this moment common-mode voltage V
CMMuch larger than the pairing voltage level of reverse control clock CKN, therefore, the electric current I 4 that bias current source 432 is provided almost can be passed to pre-amplification circuit 410 by transistor M3 all.
In the present embodiment, pre-amplification circuit 410 includes a transistor to (transistorpair) M7, M8, and two corresponding load, and after the transistor of electric current I 3+I4 input pre-amplification circuit 410 is to (transistor pair) M7, M8, transistor M7, M8 just can come into operation, with the cooperation load input signal Vin, Vip are carried out an amplifieroperation, and the signal after will amplifying inputs to bolt-lock unit 420.
Then, when controlling clock CK by the time and being in negative edge (low logic level), this moment, oppositely control clock CKN was in positive edge (high logic level), for the differential circuit that transistor M3, M4 are formed, oppositely controlled the pairing voltage level of clock CKN much larger than common-mode voltage V
CM, therefore, the electric current I 4 that bias current source 432 is provided almost can be passed to bolt-lock unit 420 by transistor M4 all.Therefore, bolt-lock unit 420 just can come into operation, with signal that pre-amplification circuit 410 is passed over bolt-lock in addition, and with the signal output of bolt-lock.
By the exposure of front as can be known, the total bias current that inputs to pre-amplification circuit 410 is the summation of two bias current I3, I4; Therefore as seen, if electric current I 3 identical with I4 (all equaling I), bias circuit 430 so of the present invention just can provide the electric current of 2I to pre-amplification circuit 410; Thus, the effect of current doubles (as increasing the transistor length-width ratio in the prior art) is arranged in the equivalence not only, and because the grid system of transistor M 3 is coupled to common-mode voltage V
CMTherefore, the parasitic capacitance of seeing into from the gate terminal of transistor M1 can't be subjected to the influence of transistor M2 and increase, and therefore also can not increase the load of previous stage and limits whole bolt lock device 400 operable highest frequencies.
In other words, if frequency that will operating in of bolt lock device 400 is higher and when needing bigger bias current, the current design that the present invention can increase needs is for being provided (bias current I3 can remain unchanged) by bias current I4, so just need not increase the length-width ratio of transistor M1 and increase parasitic capacitance; Hence one can see that, and the present invention can reach the purpose that promotes total bias current under the prerequisite that does not increase parasitic capacitance.Therefore, bolt lock device 400 of the present invention may operate in higher frequency.
Please note at this, in the present embodiment, because the drain electrode of transistor M2 is coupled to external voltage source, therefore when control clock CK is in negative edge (when bolt-lock unit 420 operates), only have only bias current I4 can be passed to bolt-lock unit 420, use for bolt-lock unit 420.
Please note at this, the present invention is length-width ratio and bias current source 431,432 size of current that provided of limit transistor M1-M4 not, circuit designers can be provided by length-width ratio and each bias current source 431,432 size of current that provided that its demand (such as frequency of desire operation) is adjusted transistor M1-M4, so that whole bolt lock device 400 reaches preferable usefulness.For instance, among bolt lock device 400 operates in environment than low frequency, bolt-lock unit 420 just needed long time of signal bolt-lock so, hence one can see that, the electric current of 420 palpuses in bolt-lock unit is also bigger, therefore, circuit designers just can be designed to bigger numerical value with electric current I 4 accordingly.
Disclose so far, this field has knows that usually the knowledgeable should understand the operation and the function of bolt lock device 400, so do not give unnecessary details in addition.In addition, the dealer should be applied to bolt lock device 400 among D flip-flop, frequency divider or the phase-locked loop easily; For instance, as previously mentioned, only need two bolt lock devices, 400 serial connections just can be obtained D flip-flop; In addition, the output Q ' of D flip-flop need only be fed back to input D, just can obtain one and remove 2 frequency divider; Certainly, with several frequency divider serial connections of removing 2, just can obtain the frequency divider of bigger divisor; Owing to state in front the exposure of these ways, so do not give unnecessary details in this in addition.
See also Fig. 4 at this, Fig. 4 is the schematic diagram of first embodiment of bolt lock device 500 of the present invention.As shown in Figure 4, in the present embodiment, bolt lock device 500 and aforesaid bolt lock device 400 are roughly the same, and its both differences are: in bias circuit 530, the drain electrode of transistor M2 is coupled to bolt-lock unit 520, but not external voltage source V
DD
Therefore, in the present embodiment, when reverse control clock CKN is in high logic level (control clock CK is in low logic level simultaneously), for the differential circuit that transistor M1, M2 are formed, common-mode voltage V
CMMuch larger than the pairing voltage level of control clock CK, therefore, the electric current I 3 that bias current source 531 is provided almost can be passed to bolt-lock unit 520 by transistor M2 all; The differential circuit of being formed for transistor M3, M4 is oppositely controlled the pairing voltage level of clock CKN much larger than common-mode voltage V on the other hand
CM, therefore, the electric current I 4 that bias current source 532 is provided almost can be passed to bolt-lock unit 520 by transistor M4 all; Therefore, bolt-lock unit 520 just can come into operation, with the signal output of bolt-lock just now.
As described above as can be known, when bolt-lock unit 520 running, the electric current by transistor M2 also imports among the bolt-lock unit 520, uses for bolt-lock unit 520.In other words, in the present embodiment, the total bias current that flows into pre-amplification circuit 510 or bolt-lock unit 520 is all the summation of electric current I 3 and electric current I 4.
In the same manner, the present invention is length-width ratio and bias current source 531,532 size of current that provided of limit transistor M1-M4 not, circuit designers can be provided by length-width ratio and each bias current source 531,532 size of current that provided that its demand (such as frequency of desire operation) is adjusted transistor M1-M4, so that whole bolt lock device 500 reaches preferable usefulness.
See also Fig. 5 at this, Fig. 5 is the schematic diagram of the 3rd embodiment of bolt lock device 600 of the present invention.As shown in Figure 5, bolt lock device 600 has added two ac-coupled circuits (AC couple circuit) 640,650 in addition; Ac-coupled circuit 640 is coupled between control clock CK and the pre-amplification circuit 610, and ac-coupled circuit 650 is coupled between reverse control clock CKN and the bolt-lock unit 620.Wherein, each ac-coupled circuit 640 all includes resistance electric capacity in parallel with one, and its connected mode as shown in Figure 5.In the present embodiment, ac-coupled circuit 640,650 is to be used for integrated circuit is operated in the optimal bias point, owing to its function and running are had now by industry, so do not give unnecessary details in this in addition.
See also Fig. 6 at this, Fig. 6 is the schematic diagram of the 4th embodiment of bolt lock device 700 of the present invention.As shown in Figure 6, in the bias circuit 730 of bolt lock device 700, the current source that is adopted not is the fixed current source as front embodiment, and changes variable current source 731,732 into; Thus, circuit designers can change 731,732 current ratios that electric current is provided of variable current source more easily, with according to different frequency of operation, reaches the best efficiency in the circuit running.
Compared to prior art, bolt lock device of the present invention need not be poor by adjusting transistorized length-width ratio or increasing transistorized gate-source voltage, increases its bias current; Therefore, bolt lock device of the present invention can be avoided existing parasitic capacitance problems, with so that operate in the environment of high frequency more.
Though more than with embodiment the present invention is described, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, the sector person can carry out various distortion or change.
Claims (10)
1. bolt lock device, it includes:
One input circuit is used for receiving an input signal, and produces an output signal according to this input signal and an input reference current;
One output circuit couples this input circuit, is used for receiving this output signal, and exports this output signal according to an output reference current; And
One current generating circuit is coupled to this input circuit and this output circuit, is used for according to a clock signal producing this input reference current to this input circuit, and produces this output reference current to this output circuit, and this current generating circuit comprises:
One first current generating unit, being used for value in this clock signal provides one first electric current to this input circuit during for one first logic level, this first electric current is the part of this input reference current, and this first current generating unit provides this first electric current to this output circuit in this clock signal during for one second logic level, and this first electric current is part of this output reference current; And
One second current generating unit, being used for value when this clock signal provides one second electric current to this input circuit during for this first logic level, this second electric current is the part of this input reference current, and this second current generating unit provides this second electric current to this output circuit in this clock signal during for this second logic level, and this second electric current is all or part of of this output reference current.
2. as claim 1 a described bolt lock device, wherein, this input circuit comprises:
One transistor is right, is used for receiving this input signal; And
A plurality of load units, it is right to couple this transistor, is used for determining this output signal with this input reference current;
Wherein, this input signal is a differential wave.
3. bolt lock device as claimed in claim 1, wherein, this output circuit comprises:
The one staggered transistor that couples is right, couple this input circuit and this second current generating unit, the transistor that should staggered couple is to receiving this input signal, and be used for this output signal of bolt-lock, and export this output signal according to this output reference current during for this second logic level when this clock signal.
4. bolt lock device as claimed in claim 1, wherein, this first current generating unit comprises:
One the first transistor is right, couples this input circuit and this output circuit, is used for receiving this clock signal and a reference signal respectively; And
One first current source, it is right to couple this first transistor, is used to provide this first electric current;
Wherein, this the first transistor forms one first guiding path when being this first logic level for this clock signal, this first current source provides this first electric current to this input circuit via this first guiding path, and this first transistor forms one second guiding path when being this second logic level for this clock signal, and this first current source provides this first electric current to this output circuit via this second guiding path.
5. bolt lock device as claimed in claim 4, wherein, the value of this reference signal is less than this first logic level, and greater than this second logic level.
6. bolt lock device as claimed in claim 1, wherein, this second current generating unit comprises:
One transistor seconds is right, couples this input circuit and this output circuit, is used for receiving an inversion signal and a reference signal of this clock signal respectively; And
One second current source, it is right to couple this transistor seconds, is used to provide this second electric current;
Wherein, this transistor seconds forms one the 3rd guiding path when being this first logic level for this clock signal, this second current source provides this second electric current to this input circuit via the 3rd guiding path, and this transistor seconds forms one the 4th guiding path when being this second logic level for this clock signal, and this second current source provides this second electric current to this output circuit via the 4th guiding path.
7. bolt lock device as claimed in claim 6, wherein, the value of this reference signal is less than this first logic level, and greater than this second logic level.
8. bolt lock device as claimed in claim 1, wherein, this first current generating unit and this second current generating unit one of them comprises a variable current source at least.
9. bolt lock device as claimed in claim 1, wherein, the value of this first electric current is different from the value of this second electric current.
10. bolt lock device as claimed in claim 1, it includes in addition:
One ac-coupled circuit is coupled to this current generating circuit, and this clock signal system is coupled to this current generating circuit via this ac-coupled circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101850681A CN101431327B (en) | 2007-11-06 | 2007-11-06 | Bolt lock device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101850681A CN101431327B (en) | 2007-11-06 | 2007-11-06 | Bolt lock device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101431327A CN101431327A (en) | 2009-05-13 |
| CN101431327B true CN101431327B (en) | 2011-01-19 |
Family
ID=40646525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101850681A Active CN101431327B (en) | 2007-11-06 | 2007-11-06 | Bolt lock device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101431327B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105391426B (en) * | 2015-12-15 | 2018-05-11 | 成都振芯科技股份有限公司 | The high-speed latches of millivolt level signal can be received |
| CN113746437A (en) * | 2020-05-27 | 2021-12-03 | 瑞昱半导体股份有限公司 | Operational amplifier and DC voltage level control method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5510734A (en) * | 1994-06-14 | 1996-04-23 | Nec Corporation | High speed comparator having two differential amplifier stages and latch stage |
| US5892382A (en) * | 1997-03-25 | 1999-04-06 | Mitsubishi Denki Kabushiki Kaisha | Current mode logic circuit, source follower circuit and flip flop circuit |
| US6501314B1 (en) * | 2002-03-06 | 2002-12-31 | Teradyne, Inc. | Programmable differential D flip-flop |
| US6774721B1 (en) * | 2003-03-07 | 2004-08-10 | Quake Technologies, Inc. | High speed logic circuits |
-
2007
- 2007-11-06 CN CN2007101850681A patent/CN101431327B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5510734A (en) * | 1994-06-14 | 1996-04-23 | Nec Corporation | High speed comparator having two differential amplifier stages and latch stage |
| US5892382A (en) * | 1997-03-25 | 1999-04-06 | Mitsubishi Denki Kabushiki Kaisha | Current mode logic circuit, source follower circuit and flip flop circuit |
| US6501314B1 (en) * | 2002-03-06 | 2002-12-31 | Teradyne, Inc. | Programmable differential D flip-flop |
| US6774721B1 (en) * | 2003-03-07 | 2004-08-10 | Quake Technologies, Inc. | High speed logic circuits |
Non-Patent Citations (1)
| Title |
|---|
| 同上. |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101431327A (en) | 2009-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7400183B1 (en) | Voltage controlled oscillator delay cell and method | |
| US5635877A (en) | Low voltage high frequency ring oscillator for controling phase-shifted outputs | |
| US8513997B2 (en) | RF duty cycle correction circuit | |
| CN102356547B (en) | Injection-locked frequency divider and pll circuit | |
| US5191301A (en) | Integrated differential voltage controlled ring oscillator | |
| US7737795B2 (en) | Voltage controlled oscillator | |
| KR19990025790A (en) | Multiple Feedback Loop Ring Oscillator and its Delay Cells | |
| US5469116A (en) | Clock generator circuit with low current frequency divider | |
| JPS639409B2 (en) | ||
| US7724101B2 (en) | Crystal oscillator circuit with amplitude control | |
| US10998896B2 (en) | Clock doublers with duty cycle correction | |
| JP4756135B2 (en) | Frequency divider | |
| CN104426523A (en) | Waveform transformation circuit with reduced jitter | |
| CN106209086A (en) | Voltage-controlled oscillator | |
| JP2005500781A (en) | Differential ring oscillator stage | |
| CN101431327B (en) | Bolt lock device | |
| US5136263A (en) | Harmonic oscillator | |
| CN101425803A (en) | Voltage controlled oscillator for loop circuit | |
| WO2020105182A1 (en) | Voltage-controlled oscillator and pll circuit in which same is used | |
| US20050046496A1 (en) | Widely tunable ring oscillator utilizing active negative capacitance | |
| CN108847843B (en) | Orthogonal ring oscillator based on resistance enhanced feedforward | |
| US7511584B2 (en) | Voltage controlled oscillator capable of operating in a wide frequency range | |
| US7642867B2 (en) | Simple technique for reduction of gain in a voltage controlled oscillator | |
| Demartinos et al. | Delay elements suitable for CMOS ring oscillators | |
| US7701258B2 (en) | Latch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |