CN101426316B

CN101426316B - Irregular LED array displaying message frame sending controller and method

Info

Publication number: CN101426316B
Application number: CN2008102196942A
Authority: CN
Inventors: 贺前华; 陈荣研; 肖建明; 李韬
Original assignee: South China University of Technology SCUT
Current assignee: South China University of Technology SCUT
Priority date: 2008-12-05
Filing date: 2008-12-05
Publication date: 2012-10-31
Anticipated expiration: 2028-12-05
Also published as: CN101426316A

Abstract

The present invention provides an irregular LED array display information frame transmission controller which comprises a DVI/USB data receiving circuit board and a FPGA control circuit board. The DVI/USB data receiving circuit board which is used as a target device is connected with the FPGA control circuit board that is used as a master control device. The transmission controller is connected with a computer terminal respectively through the DVI cable and USB cable. The transmission controller is also connected with a data distributor group through UTP-five categories, and then is sequentially connected with a data buffer and an LED lamp for forming an LED lamp decoration control system, wherein the data distributor group is formed by the series connecting of a plurality of data distributors. Any information played on the computer can be displayed in the LED array with a real-time mode through the video processing system according to the invention. The video processing system according to the invention has the advantages of plug and play, high speed of data transmission, high stability, strong expandability, and strong system robustness. The video processing system can satisfy the requirement of any planning array and different scale of LED array.

Description

Irregular LED array displaying message frame sending controller and method

Technical field

The present invention relates to the LED display control technology in the semiconductor lighting, specifically be meant irregular LED array displaying message frame sending controller and method.

Background technology

Traditional Landscape Lighting uses static neon bulb as curtain wall decoration; Only there are light and simple colored to change; Can not the double as amusement, multiple use such as advertisement, information propagation; Can not satisfy building, like the individualized feature demand on significant building, bridge and square, and power consumption is relatively large.LED is a kind of novel high efficiency light source; For neon bulb, daylight lamp; Except that have no mercury, economize material, to the advantages such as environment no electromagnetic pollution, no harm ray; The more important thing is to have advantages such as energy-conservation, that the life-span is long, the LED technical development has become the important component part of national energy strategy.In Landscape Lighting, because adopting low-voltage power supply, its expense that is used to insulate to compare with neon bulb, LED wants much little, reliability is higher, so LED light become the main development trend of landscape light in city from now on, has also obtained fast development in recent years.

The application of LED landscape lamp decoration system is increasing; Provide the producer of light fixture many; But the unit of research control system is few, and that sees on the market has two kinds: a kind of control system of the DMX512 of being based on agreement, another kind are based on the LED lamp decoration control system of Ethernet.But these systems all only are applicable to regular LED cell array (the LED pixel is arranged by the mode of ranks, and has unified line-spacing and unified row distance).Another defective of these systems is often to require the picture element of computing machine indication range and LED picture element to have relation one to one, makes it to lack the dirigibility of playing scope definition.

In practical engineering application, irregular LED cell array layout has very big demand, and such as the existence of skin window, even the specification of the window on the same face wall all can have variety classes.The exterior wall surface of part building also is not necessarily with a kind of specification, and some building can adopt different styles for outstanding individual character in different floor sections.For this type buildings, just have certain difficulty by unified line-spacing and row apart from layout L ED light fixture, even feasible reluctantly, the image quality that its engineering cost also can be higher, show is not high yet.On the other hand; If hope that (this is the major function with LED lamp decoration system of real-time play function for profile with the less bigger picture of LED cell array demonstration; The integrality of picture is one of main performance index; The sophistication of picture takes second place), adopt above-mentioned mapping relations one to one also to be difficult to realize.

Summary of the invention

The object of the invention is to overcome the deficiency of prior art; A kind of irregular LED array displaying message frame sending controller is provided; Transmit control device of the present invention can satisfy the large LED lamp decoration control system that is applied to irregular LED cell array layout, and layout is flexible, engineering cost is lower, image quality is high, realization is simple.

Another object of the present invention is to provide irregular LED array displaying message frame sending controller to realize that irregular LED array displaying message frame sends the method for control.

The object of the invention is realized through following technical proposals: irregular LED array displaying message frame sending controller comprises the FPGA control circuit board as main control equipment that is connected, as the DVI/USB data receiver circuit plate of target device;

Wherein, said FPGA control circuit board comprises image buffer storage SRAM, configuration information buffer memory SRAM, network interface circuit, the power circuit that FPGA main control chip and said FPGA main control chip connect respectively;

Said DVI/USB data receiver circuit plate comprises DVI data-interface, usb data interface, and said DVI data-interface, usb data interface are connected with the FPGA main control chip of said FPGA control circuit board respectively.

Said FPGA main control chip comprises DVI data reception module, SPI data reception module, PLL frequency multiplication module, view data and configuration information processing module, internal RAM module, network interface sending module; Wherein, Said DVI data reception module, SPI data reception module also respectively with image buffer storage SRAM, the corresponding connection of configuration information buffer memory SRAM; Said view data is connected with DVI data reception module, SPI data reception module, PLL frequency multiplication module, internal RAM module, network interface sending module and above-mentioned image buffer storage SRAM, configuration information buffer memory SRAM respectively with the configuration information processing module; PLL frequency multiplication module is connected with DVI data reception module, SPI data reception module simultaneously; The internal RAM module is connected with the network interface sending module simultaneously, and the network interface sending module is connected with network interface circuit.

Said SPI data reception module comprises the SPI string that is connected and modular converter, SPI data memory module.

Said DVI data-interface comprises the DVI decoding circuit, and the DVI decoding circuit comprises DVI decoding chip and peripheral circuits thereof, and peripheral circuits comprises EEPROM and some exclusions of power circuit, storage EDID data.

Said USB receiving interface comprises the chip and the peripheral circuits thereof of ARM7 (can be replaced by other serial ARM chips, like ARM9) kernel, and peripheral circuits comprises power circuit, program download circuit, feeds dog circuit etc.

Said DVI data reception module is provided with clock port, image synchronization control port, the effective port of image, view data input port, external SRAM control signal port, external SRAM data/address port; Said SPI data reception module is provided with SPI clock port, SPI FPDP, external SRAM control signal port, external SRAM data/address port, USB ready signal port, and said view data and configuration information processing module are provided with clock port, external SRAM data/address read write port is arranged, internal RAM data write port, frame data are prepared port, control signal port.Above DVI data reception module, SPI data reception module, view data and configuration information processing module are connected according to following form; The clock port of said DVI data reception module, view data and configuration information processing module is connected with the 65MHz clock of process PLL frequency multiplication module respectively; The SPI clock port of said SPI data reception module connects the 25MHz clock through PLL frequency multiplication module, and the write data enable port (WE) of the SRAM of DVI data reception module, SPI data reception module and output enable port (OE) are controlled image buffer storage SRAM, configuration information buffer memory SRAM through the alternative multiway analog switch (MUX) of view data and configuration information processing module respectively.The SRAM data-signal port (data) of DVI data reception module, SPI data reception module and address signal port (address) are also controlled image buffer storage SRAM, configuration information buffer memory SRAM through this alternative multiway analog switch (MUX) respectively.

Adopt the irregular LED array lamp decoration control system of above-mentioned irregular LED array displaying message frame sending controller; Comprise irregular LED array displaying message frame sending controller, computer terminal, data distributor group, data buffer, LED light fixture; DVI data-interface, the usb data interface of the DVI/USB data receiver circuit plate of said irregular LED array displaying message frame sending controller are connected with the computer terminal through DVI cable, USB cable respectively; The network interface circuit of the FPGA control circuit board of said irregular LED array displaying message frame sending controller is connected with the data distributor group through ultra Category-5 twisted pair; Be connected successively with data buffer, LED light fixture again; Wherein, said data distributor group is formed by a plurality of data distributors are connected in series.

Said computer terminal comprises and is used to generate the topology file generation module of topology file and the information sending module that is used to send layout information, sectional drawing frame information and user's input information.

The information of said user's input comprises X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly.

The irregular LED array lamp decoration control method of above-mentioned irregular LED array lamp decoration control system may further comprise the steps:

(1) the topology file generation module of computer terminal generates the led array layout according to any irregular layout situation of actual light fixture, thereby and X, the Y coordinate figure of each picture element of storage led array obtain the topology file of suffix lmp by name;

(2) information sending module of computer terminal generates the layout information Frame that comprises each LED picture element X, Y coordinate figure according to topology file, and information sending module sends to the layout information Frame through the USB interface of computer terminal the usb data interface of DVI/USB data receiver circuit plate then;

(3) information sending module of computer terminal generates sectional drawing frame information configuration frame according to the position and the user's input information of sectional drawing frame; This user's input information comprises X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly, through the USB interface of computer terminal sectional drawing frame information configuration frame is sent to the usb data interface of DVI/USB data receiver circuit plate then;

(4) computer terminal sends to computer desktop color of image data the DVI data-interface of DVI/USB data receiver circuit plate through the DVI interface by the DVI standard;

(5) the DVI data reception module of FPGA main control chip receives computer desktop color of image data and stores into the image buffer storage SRAM from the DVI data-interface of DVI/USB data receiver circuit plate;

(6) the usb data receiver module of FPGA main control chip receives layout information Frame, sectional drawing frame information configuration frame and stores into the configuration information buffer memory SRAM from the usb data interface of DVI/USB data receiver circuit plate;

(7) view data of FPGA main control chip and configuration information processing module are handled said layout information Frame, sectional drawing frame information configuration frame, obtain the LED picture element that actual needs shows coordinate figure (x, y);

(8) coordinate figure (x of the LED picture element that shows according to actual needs of the view data of FPGA main control chip and configuration information processing module; Y); From image buffer storage SRAM, extract corresponding computer desktop color of image data; Judge then whether frame data run through,, then combine corresponding layout information to be assembled into ethernet data frame and store in the internal RAM if run through; If do not run through, repeating step (7) then;

(9) said network interface sending module is read ethernet data frame and is sent to data distributor through network interface circuit among the RAM internally, judges that then sectional drawing frame configuration information has no change, if change, then repeating step (3) is to step (9); If do not change, then repeating step (6) is to step (9);

(10) data distributor constantly repeats to receive ethernet data frame, and information extraction produces pwm control signal driving LED light fixture from ethernet data frame.

In the said method, the said computer desktop color of image of step (1) data comprise R, G, the trichromatic pixel data of B.

In the said method; The said computer desktop color of image of step (4) data are continual, real-time operations through the operation that the DVI interface sends to the DVI data-interface of DVI/USB data receiver circuit plate; Walk abreast with other each steps, do not receive the influence of other each procedure.In the said method, adopt ping-pong operation performing step (4) and the parallel of other each steps to carry out.

In the said method; The view data of the said FPGA main control chip of step (7) and configuration information processing module are handled said layout information Frame, sectional drawing frame information configuration frame; Obtain the LED picture element that actual needs shows coordinate figure (x, y), specific as follows:

The view data of said FPGA main control chip and configuration information processing module in order from configuration information buffer memory SRAM extract a certain LED picture element the layout information Frame coordinate figure (x1, y1), (x1 y1) is multiplied by X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly respectively with this coordinate figure then; Obtain coordinate figure (x2, y2), x2=x1 * Lx wherein; Y2=y1 * Ly adds the coordinate figure in the sectional drawing frame upper left corner in the sectional drawing frame information configuration frame, promptly corresponding to the initial point (0 of LED layout; 0) (x0 y0), thereby obtains the coordinate figure (x of the LED picture element that actual needs shows to coordinate figure; Y), x=x0+x1 * Lx wherein, y=y0+y1 * Ly.

In the said method, the said network interface sending module of step (9) is read ethernet data frame and is sent to data distributor through network interface circuit among the RAM internally, and the transmission speed of its ethernet data frame is with 100M/S, so that higher transmission rate to be provided.

Said FPGA main control chip program module is described through the hardware description language (VHDL, Very High Speed Integrated Circuit Hardware Description Language) of very high speed integrated circuit.

The present invention has following advantage and effect with respect to prior art:

(1) irregular LED array displaying message frame sending controller of the present invention can be realized the extraction of the display message of LED layout under actual any irregular conditions; And can realize that the user passes through the processing of the X of computer terminal input, the different magnification ratio coefficients of Y coordinate, can satisfy the large LED lamp decoration control system that is applied to irregular LED cell array layout;

(2) implementation method of the present invention can send to USB interface to sectional drawing frame information configuration frame in real time according to the variation of the real-time sectional drawing frame position information sending module with the different of X, Y coordinate amplification coefficient and through the computer terminal; And finally store among the configuration information buffer memory SRAM; After the FPGA main control chip is handled; Can realize that any information real-time ground of playing on the computing machine shows, satisfies the demand of different designs scheme in led array;

(3) native system adopts the video interface DVI of total digitalization; Be the conversion between the digital signal in the whole signals transmission, related just coding, decoding algorithm ensure the extremely low bit error rate; Digital-to-analog conversion, expensive ADC have been got around; Not only improved picture quality, and further reduced the complexity of circuit, engineering cost is lower.

Description of drawings

Fig. 1 is the structural representation of the LED lamp decoration control system that is made up of irregular LED array displaying message frame sending controller of the present invention;

Fig. 2 is the structural representation of irregular LED array displaying message frame sending controller of the present invention;

Fig. 3 is the structural representation of FPGA main control chip;

Fig. 4 is the schematic flow sheet by irregular LED array displaying message frame sending control method of the present invention.

Embodiment

Below in conjunction with embodiment and accompanying drawing the present invention is described in further detail, but embodiment of the present invention is not limited thereto.

Embodiment 1

Concrete structure for the irregular LED array lamp decoration control system that constitutes by irregular LED array displaying message frame sending controller of the present invention shown in Figure 1; Comprise irregular LED array displaying message frame sending controller, computer terminal, data distributor group, data buffer (differential receiver), LED light fixture; DVI data-interface, the usb data interface of the DVI/USB data receiver circuit plate of said irregular LED array displaying message frame sending controller are connected with the computer terminal through DVI cable, USB cable respectively; The network interface circuit of the FPGA control circuit board of said irregular LED array displaying message frame sending controller is connected with the data distributor group through ultra Category-5 twisted pair; Be connected successively with data buffer, LED light fixture again; Wherein, said data distributor group is formed by a plurality of data distributors are connected in series.

Said computer terminal comprises the information sending module that is used to generate the topology file generation module of topology file and is used to send layout information, sectional drawing frame information and user's input information information such as (comprising X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly).

The circuit structure of irregular LED array displaying message frame sending controller of the present invention comprises the FPGA control circuit board as main control equipment that is connected, as the DVI/USB data receiver circuit plate of target device;

As shown in Figure 2; Said FPGA control circuit board comprises PPGA main control chip (EP1C6Q240C8), image buffer storage SRAM, configuration information buffer memory SRAM, network interface circuit, power circuit, and said FPGA main control chip is connected with image buffer storage SRAM, configuration information buffer memory SRAM, network interface circuit, power circuit respectively.The screen resolution of the LED lamp decoration control system that irregular LED array displaying message frame sending controller of the present invention constitutes is 1024 * 768; Screen refresh rate is 60Hz; The pixel figure place is 24; For guaranteeing the read-write correctly, at a high speed and stably of view data; The FPGA main control chip is peripheral to adopt 4 high speed storing SRAM, comprises SRAM image buffer storage A (512k * 16), SRAM image buffer storage C (512k * 16), SRAM image buffer storage B (512k * 8), SRAM image buffer storage D (512k * 8).

Wherein, DVI/USB data receiver circuit plate comprises DVI data-interface, usb data interface.Wherein, the DVI interface of computer terminal is connected with the DVI data-interface of DVI/USB data receiver circuit plate; The USB interface of computer terminal is connected with the usb data interface of DVI/USB data receiver circuit plate.Simultaneously, the DVI network interface card of computer terminal, DVI interface interconnect.

Shown in Figure 3 is the concrete structure of PPGA main control chip, and the FPGA main control chip comprises DVI data reception module, SPI data reception module, PLL frequency multiplication module, view data and configuration information processing module, internal RAM module, network interface sending module.Wherein, said DVI data reception module, SPI data reception module also respectively with the above-mentioned corresponding connection of image buffer storage SRAM, configuration information buffer memory SRAM.Simultaneously; Said view data is connected with DVI data reception module, SPI data reception module, PLL frequency multiplication module, internal RAM module, network interface sending module and above-mentioned image buffer storage SRAM, configuration information buffer memory SRAM respectively with the configuration information processing module; PLL frequency multiplication module is connected with DVI data reception module, SPI data reception module simultaneously; The internal RAM module is connected with the network interface sending module simultaneously, and the network interface sending module is connected the back and is connected with the data distributor group with network interface circuit.

Simultaneously, said SPI data reception module comprises the SPI string that is connected and modular converter, SPI data memory module.

The DVI data-interface of said DVI/USB data receiver circuit plate, usb data interface are connected with the FPGA main control chip simultaneously.Specifically, the DVI data-interface of DVI/USB data receiver circuit plate, usb data interface are gone here and there and the corresponding connection of modular converter with DVI data reception module, the SPI of FPGA main control chip respectively.

Above-mentioned irregular LED array displaying message frame sending controller realizes that irregular LED array displaying message frame sends the method for control, and is as shown in Figure 4, may further comprise the steps:

(7) view data of FPGA main control chip and configuration information processing module in order from configuration information buffer memory SRAM extract a certain LED picture element the layout information Frame coordinate figure (x1, y1), then with this coordinate figure (x1; Y1) be multiplied by respectively X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly obtain coordinate figure (x2, y2), x2=x1 * Lx wherein; Y2=y1 * Ly, the coordinate figure of adding the sectional drawing frame upper left corner in the sectional drawing frame information configuration frame is (promptly corresponding to the coordinate figure (x0 of the initial point (0,0) of LED layout; Y0)), obtain the LED picture element that actual needs shows coordinate figure (x, y); X=x0+x1 * Lx wherein, y=y0+y1 * Ly;

(8) coordinate figure (x of the LED picture element that shows according to actual needs of the view data of FPGA main control chip and configuration information processing module; Y); From image buffer storage SRAM, extract corresponding computer desktop color of image data; Judge then whether a frame Ethernet data runs through,, then combine corresponding layout information to be assembled into ethernet data frame and store in the internal RAM if run through; If do not run through, repeating step (7) then;

In the said method, the clock that DVI Data Receiving plate offers FPGA is 65MHz, and the clock of PLL frequency multiplication module generation 130MHz provides operating clock for each functional module of FPGA, with storage and the processing operation that makes things convenient for view data.

Among the present invention, it is the on-site programmable gate array FPGA (Field Programmable Gate Array) of EP1C6Q240 that the FPGA main control chip adopts the model of the Cyclone series of a slice altera corp.This a FPGA power supply is 3.3V and 1.5V, nearly 185 in available I/O mouth.Data-carrier store (SRAM) is IS61LV51216, IS61LV5128, the IS61LV10248 of ISSI company.Network interface chip adopts the RTL8021CL chip of Realtek company, and Realtek RTL8201CL is the physical layer transceiver of a single port, has realized whole 10/100M ethernet physical layer functions.The DVI decoding chip adopts a kind of TMDS signal receiving chip TFP101A in the TI PaneIBus of the company flat panel display product series, supports XGA (1024x76880Hz), and pixel clock is up to 86MHz; Support 24 RGBs, have the characteristic of low noise and low-power consumption.Adopt the LPC214x high performance chips of PHILIPS company based on the chip of ARM7 kernel, its greatest feature has been built-in USB2.0 is controller at full speed.

The program implement of said FPGA main control chip is following:

1, with Hardware Description Language VHDL circuit system is described;

2, the IC design integrated software QuartusII with altera corp carries out comprehensively the hardware circuit that VHDL describes, and obtaining with the model of altera corp is the corresponding net meter file of FPGA of EP1C6Q240;

3, carry out placement-and-routing and extraction delayed data;

4, carry out sequential emulation;

5, download to hardware configuration information on the above-mentioned FPGA (model EP1C6Q240) with QuartusII.

As stated, just can realize the present invention preferably.

Claims

1. irregular LED array displaying message frame sending controller comprises the FPGA control circuit board as main control equipment that is connected, as the DVI/USB data receiver circuit plate of target device;

Said DVI/USB data receiver circuit plate comprises DVI data-interface, usb data interface, and said DVI data-interface, usb data interface are connected with the FPGA main control chip of said FPGA control circuit board respectively;

It is characterized in that: said FPGA main control chip comprises DVI data reception module, SPI data reception module, PLL frequency multiplication module, view data and configuration information processing module, internal RAM module, network interface sending module; Wherein, Said DVI data reception module, SPI data reception module also respectively with image buffer storage SRAM, the corresponding connection of configuration information buffer memory SRAM; Said view data is connected with DVI data reception module, SPI data reception module, PLL frequency multiplication module, internal RAM module, network interface sending module and above-mentioned image buffer storage SRAM, configuration information buffer memory SRAM respectively with the configuration information processing module; PLL frequency multiplication module also is connected with DVI data reception module and SPI data reception module simultaneously; The internal RAM module is connected with the network interface sending module simultaneously, and the network interface sending module is connected with network interface circuit.

2. according to the said irregular LED array displaying message frame sending controller of claim 1, it is characterized in that: said SPI data reception module comprises the SPI string that is connected and modular converter, SPI data memory module.

3. adopt the irregular LED array lamp decoration control system of the said irregular LED array displaying message frame sending controller of claim 2; It is characterized in that: comprise irregular LED array displaying message frame sending controller, computer terminal, data distributor group, data buffer, LED light fixture; DVI data-interface, the usb data interface of the DVI/USB data receiver circuit plate of said irregular LED array displaying message frame sending controller are connected with the computer terminal through DVI cable, USB cable respectively; The network interface circuit of the FPGA control circuit board of said irregular LED array displaying message frame sending controller is connected with the data distributor group through ultra Category-5 twisted pair; Be connected successively with data buffer, LED light fixture again; Wherein, said data distributor group is formed by a plurality of data distributors are connected in series.

4. according to the said irregular LED array lamp decoration of claim 3 control system, it is characterized in that: said computer terminal comprises and is used to generate the topology file generation module of topology file and the information sending module that is used to send layout information, sectional drawing frame information and user's input information.

5. according to the said irregular LED array lamp decoration of claim 4 control system, it is characterized in that: the information of said user's input comprises X coordinate amplification coefficient Lx and Y coordinate amplification coefficient Ly; Said X coordinate refers to the lateral coordinates value of each picture element of led array, and said Y coordinate refers to the along slope coordinate of each picture element of led array.

6. utilize the irregular LED array lamp decoration control method of each said irregular LED array lamp decoration control system of claim 3 to 5, it is characterized in that may further comprise the steps:

(6) the usb data receiver module of FPGA main control chip receives layout information Frame, sectional drawing frame information configuration frame from the usb data interface of DVI/USB data receiver circuit plate, and stores among the configuration information buffer memory SRAM;

7. irregular LED array displaying message frame sending control method according to claim 6 is characterized in that: the said computer desktop color of image of step (1) data comprise R, G, the trichromatic pixel data of B.

8. irregular LED array displaying message frame sending control method according to claim 6; It is characterized in that: the view data of the said FPGA main control chip of step (7) and configuration information processing module are handled said layout information Frame, sectional drawing frame information configuration frame; Obtain the coordinate figure (x of the LED picture element of actual needs demonstration; Y), specific as follows: