CN101419963B - Wafer-wafer encapsulation body and manufacturing process therefor - Google Patents

Wafer-wafer encapsulation body and manufacturing process therefor Download PDF

Info

Publication number
CN101419963B
CN101419963B CN2008101755291A CN200810175529A CN101419963B CN 101419963 B CN101419963 B CN 101419963B CN 2008101755291 A CN2008101755291 A CN 2008101755291A CN 200810175529 A CN200810175529 A CN 200810175529A CN 101419963 B CN101419963 B CN 101419963B
Authority
CN
China
Prior art keywords
wafer
bonding film
active surface
carrier
glue
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2008101755291A
Other languages
Chinese (zh)
Other versions
CN101419963A (en
Inventor
沈更新
林俊宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
Original Assignee
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BERMUDA CHIPMOS TECHNOLOGIES Co Ltd, Chipmos Technologies Inc filed Critical BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Priority to CN2008101755291A priority Critical patent/CN101419963B/en
Publication of CN101419963A publication Critical patent/CN101419963A/en
Application granted granted Critical
Publication of CN101419963B publication Critical patent/CN101419963B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The invention provides a wafer-wafer package body which comprises a carrier, a first wafer, a first adhesive film, a second wafer, a second adhesive film, a plurality of solder bumps, a plurality of connecting wires and a package colloid. The first wafer is equipped on the carrier and has a first active surface; the first adhesive film is equipped between the carrier and the first wafer; the second wafer has a second active surface towards the first active surface; the second adhesive film is equipped between the first active surface of the first wafer and the second active surface of the second wafer, and has a B-level characteristic; a plurality of the solder bumps are arranged in the second adhesive film and are electrically connected between the first active surface of the first waferand the second active surface of the second wafer; a plurality of the connecting wires electrically connect the carrier and a first wafer, and the second adhesive film covers part of the connecting wires; and the package colloid is equipped on the carrier to cover the first wafer and the second wafer.

Description

Wafer-wafer encapsulation body and manufacture method thereof
The application is an original applying number 200610083380.5, and on June 6 2006 applying date, denomination of invention is divided an application for " wafer encapsulation body and the wafer processing method that has the wafer of glue-line in order to manufacturing ".
Technical field
The invention relates to a kind of chip architecture, and particularly relevant for a kind of wafer-wafer encapsulation body and manufacture method thereof with wafer (adhesive chip) of glue-line.
Background technology
After semiconductor crystal wafer (semiconductor wafer) is gone up the manufacturing integrated circuit, the cutting semiconductor wafer is to form a plurality of wafers, and these wafers adhere on the suitable IC substrate according to multiple packaged type, and perhaps a wafer adheres on another wafer, pile up to form the polycrystalline sheet.For example, wafer adheres on the printed circuit board (PCB), to form ball-shaped grid array (BGA) packaging body.Perhaps, wafer adheres on the interior pin of wafer pad or lead frame (lead frame), to form thin-type small-size encapsulation (TSOP) body.In addition, the existing known glue-line of wafer of being used to adhere is generally the liquefied mixture or the solid polyimide adhesive tape of thermosetting silver, and in the manufacture method of adhesion wafer, this existing known glue-line is applied on the carrier, and carrier for example is substrate, lead frame or lower wafer.
The method of the assembling polycrystalline sheet module that United States Patent (USP) is disclosed for No. 2001/0005935 will adhere on the substrate than wafer for using wafer adhesion machine, under the situation of not using wafer adhesion machine less wafer is fixed on the bigger wafer then.In existing known techniques, adhesion is liquid thermosetting glue-line or solid polyimide band than the glue-line of wafer and less wafer.Yet this patent fails to disclose the program of coating glue-line, just before wafer adhesion and lead splice program, at first is being coated with glue-line on the less wafer or on than wafer.On the one hand, when the liquid thermosetting glue-line is used for not with lead engages wafer, the liquid thermosetting glue-line is difficult to pre-coating on less wafer (going up wafer), and owing to flowing of liquid thermosetting glue-line, so the liquid thermosetting glue-line is easy to pollute the connection pad (bonding pad) than wafer (lower wafer).On the other hand, when after lead engages, being coated with liquid glue-line since Printing screen can't be seated in have wiring than on the wafer (or substrate), so glue-line must be on being applied to than wafer before the lead joint.Therefore, the restriction of this kind polycrystalline sheet encapsulation process is quite a lot of, thereby causes being not easy to encapsulation.In addition, solid-state adhesive tape also can be used for the wafer adhesion, but the cost height of adhesive tape and adhesive tape are necessary for the joint that layers of two-sided just can be used for wafer-to wafer (chip-chip), wafer-substrate (chip-substrate) or wafer-lead frame (chip-lead frame).In existing known techniques, at first adhesive tape adheres on the substrate (lead frame or than wafer) with predetermined pattern, then wafer is bonded on the adhesive tape.Wafer that cutting crystal wafer forms does not just have glue-line.
Summary of the invention
Therefore, the present invention proposes a kind of wafer-wafer encapsulation body and manufacture method thereof, and it disposes glue-line between two wafers, therefore will be easy to produce the wafer-wafer encapsulation body structure.
The manufacture method of wafer-wafer encapsulation body of the present invention, comprise the following steps: at first, one carrier, one first wafer and one second wafer are provided, first wafer configuration is on carrier, first wafer has one first active surface, and second wafer has one second active surface, and second active surface is provided with a bonding film with B rank characteristic.Then, the bonding film by having B rank characteristic is first active surface of second wafer configuration in first wafer, and first wafer and second wafer are electrically connected to each other by a plurality of solder projections.Form a packing colloid on carrier, to cover first wafer and second wafer.
According to one embodiment of the invention, a plurality of wiring electrically connect between the carriers and first wafer, and the bonding film with B rank characteristic covers the part of described wiring.According to one embodiment of the invention, described solder projection is disposed at first active surface of first wafer.Have a plurality of connection pads and a plurality of solder pads on first active surface of first wafer, and described solder projection is disposed on the described solder pads.
According to one embodiment of the invention, described solder projection is disposed at second active surface of second wafer, and the bonding film with B rank characteristic covers described solder projection.
The present invention proposes a kind of wafer-wafer encapsulation body, comprising: carrier, first wafer, first bonding film, second wafer, second wafer, second bonding film, a plurality of solder projection, a plurality of wiring and packing colloid.First wafer configuration and has one first active surface on this carrier.First bonding film is disposed between the carrier and first wafer.Second wafer has second active surface towards first active surface.Second bonding film is disposed between second active surface of first active surface of first wafer and second wafer, and has B rank characteristic.A plurality of solder projections are in second bonding film and be electrically connected between second active surface of first active surface of first wafer and second wafer.A plurality of wiring electrically connect the carrier and first wafer, and second bonding film covers the part of described wiring.Packing colloid is disposed on the carrier, to cover first wafer and second wafer.
According to one embodiment of the invention, carrier is base plate for packaging or lead frame.
According to one embodiment of the invention, first bonding film has B rank characteristic.
Generally speaking, the present invention is disposed at glue-line (for example bonding film or bonding film with B rank characteristic) on wafer or the carrier, even therefore in the step of piling up of wafer-to wafer, when bonding film or when having the non-active surface of the complete cover wafers of bonding film of B rank characteristic, this bonding film or the bonding film with B rank characteristic will can not damage wiring or the connection pad in wafer-substrate (chip-to-substrate) or wafer-leaded package body structure.Therefore, can under the situation of not considering already present wiring or connection pad, use glue-line so that make easily or effectively that wafer-to wafer piles up, wafer-substrate or wafer-leaded package body structure.
In addition, wafer can be fixed to substrate, another wafer, printed circuit board (PCB), ceramic circuit board or not have the lead frame of extra glue-line by glue-line, therefore glue-line can reduce cost, and effectively and be widely used for that wafer-to wafer piles up or wafer-substrate piles up etc. in the multiple packaging body.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the flow chart according to the wafer processing method of the wafer that has glue-line in order to manufacturing of the present invention.
Fig. 2 is the front view according to the wafer that wafer processing method provided of the wafer that has glue-line in order to manufacturing of the present invention.
Fig. 3 A to Fig. 3 D is the profile according to the wafer in the wafer-process process of the first embodiment of the present invention.
Fig. 3 E to Fig. 3 G is the profile that the wafer-to wafer of the wafer with glue-line of first embodiment piles up.
Fig. 3 H will be for will be applied to the profile of ball-shaped grid array packaging body according to the wafer-wafer encapsulation body of the first embodiment of the present invention.
Fig. 4 A to Fig. 4 D is the profile of the wafer in according to a second embodiment of the present invention the wafer-process process.
Fig. 4 E to Fig. 4 F is the profile of the wafer-substrate package body of the wafer with glue-line of second embodiment.
Fig. 5 is the profile of explanation a third embodiment in accordance with the invention, and the non-active surface of its explanation wafer adheres to a positioning belt in order to cutting, has the wafer of glue-line with manufacturing.
Fig. 6 and Fig. 7 are the profile of the wafer-leaded package body of the wafer with glue-line of the 3rd embodiment.
Fig. 8 A to Fig. 8 D is the profile of the wafer in the wafer-process process of a fourth embodiment in accordance with the invention.
Fig. 8 E to Fig. 8 F is the profile of the wafer-substrate package body of the wafer with glue-line of the 4th embodiment.
Fig. 8 G is applied to the profile of ball-shaped grid array packaging body for the wafer-substrate package body structure with a fourth embodiment in accordance with the invention.
Fig. 9 A to Fig. 9 C is the profile in the wafer-wafer encapsulation body of the wafer with glue-line of the 4th embodiment.
Fig. 9 D is if the wafer-wafer encapsulation body of a fourth embodiment in accordance with the invention is applied to the profile of ball-shaped grid array packaging body.
Figure 10 A to Figure 10 B is the profile of the wafer-leaded package body of the wafer with glue-line of the 4th embodiment.
Figure 11 A to Figure 11 B is the profile of two wafer that piles up-leaded package bodies of the wafer with glue-line of the 4th embodiment.
Figure 12 A is the profile of wafer-wafer encapsulation body of the wafer with glue-line of the 5th embodiment.
Figure 12 B is for being applied to wafer-wafer encapsulation body according to a fifth embodiment of the invention the profile of ball-shaped grid array packaging body.
Figure 12 C is the profile of two wafer that piles up-leaded package bodies of the wafer with glue-line of the 5th embodiment.
Figure 13 is the profile of Figure 12 A, and it illustrates that first wafer electrically connects via most solder projections and carrier.
Figure 14 A to Figure 14 C is the profile of wafer-wafer encapsulation body of the wafer with glue-line of the 6th embodiment.
Figure 15 is another embodiment of the solder projection 30 shown in the allocation plan 14A.
20: soldered ball 30: solder projection
40: primer 100: wafer-substrate package body structure
101: ball-shaped grid array type wafer encapsulation body 102: wafer-wafer encapsulation body
103: ball-shaped grid array type wafer encapsulation body 104: wafer-leaded package body structure
105: two wafer that piles up-leaded package bodies
106: ball-shaped grid array type wafer encapsulation body
107: two wafer that piles up-leaded package body structures
108: wafer-wafer encapsulation body
110: wafer 111: non-active surface
111a: non-active surface 112: active surface
113: wafer 113a: wafer
114: cutting path 115: connection pad
115a: connection pad 117: solder pads
117a: solder pads 121: web plate
121a: web plate 122: scraping
130: liquid glue-line 130a: liquid glue-line
131: bonding film 131a: bonding film
131b: bonding film 140: positioning belt
150: cutting machine 160: wafer
161: connection pad 162: wiring
170: substrate 172: connection pad
174: surface 175: wafer pad
175a: pin 176: connection pad
180: wiring 180a: wiring
182: packing colloid 190: packing colloid
190a: packing colloid 190b: packing colloid
210: wafer 211: active surface
212: non-active surface 212a: non-active surface
213: wafer 213a: wafer
214: cutting path 215: connection pad
215a: solder pads 221: web plate
222: scraping 230: liquid glue-line
231: bonding film 231a: bonding film
240: positioning belt 250: cutting machine
260: carrier 260a: slit
260b: surface 261: soldered ball
262: wiring 262a: wiring
263: packing colloid 265: pin
271: interior pin 272: carrier
273: packing colloid 274: wiring
331a: bonding film 331b: bonding film
Embodiment
Hereinafter disclose a plurality of specific embodiment of the present invention, and then the example of a plurality of possible embodiments of notion of the present invention is described.Purpose for explanation General Principle of the present invention is carried out following description and should do not understood following description in a limiting sense.Judge category of the present invention best with reference to the claim of enclosing.
Hereinafter will the present invention be described with reference to alterations and by means of embodiment.
See also shown in Figure 1, have the wafer processing method of the wafer of glue-line according to of the present invention in order to manufacturing, it comprises following key step: " wafer is provided " 11, " coating has the liquid glue-line of two rank characteristics " 12, " precuring wafer " 13, " location wafer " 14 and " cutting crystal wafer has the wafer of bonding film with formation " 15.
See also Fig. 2 and Fig. 3 A is illustrated, at first, in the step 11 of " wafer is provided ", provide wafer 110.Wafer 110 has an active surface 112, and it has been formed with integrated circuit and connection pad 115, and a non-active surface 111, and it is corresponding to active surface 112, so that a majority wafer 113 is combined.Connection pad 115 is positioned on each wafer 113.Be positioned at the straight cuts path 114 at the periphery place of wafer 113, it is in order to define wafer 113.According to predetermined packaging body or pile up manufacture method, needing the surface of bonding wafer 110 can be active surface 112 or non-active surface 111.In first embodiment, the non-active surface 111 of wafer 110 is predefined for cohesible, and non-active surface 111 should face up.Then, shown in Fig. 3 B, carry out the step 12 of " coating has the liquid glue-line of two rank characteristics ".By screen printing, mould printing (stencil printing) or rotary coating the non-active surface 111 of wafer 110 partly or entirely on coating have the liquid glue-line 130 at least two rank characteristics (A rank, B rank, C rank).Preferably, web plate 121 is seated on the non-active surface 111 of wafer 110, then the liquid glue-line 130 that will have an adequate liquidity by scraping 122 is printed on the non-active surface 111.In this embodiment, because web plate 121 covers on the cutting path 114 of wafer 110, partly be printed on the non-active surface 111 of wafer 110 so that will have the glue-line 130 of two rank characteristics, and glue-line 13 will not cover cutting path 114.Because formed wafer 113 is used for wafer-to wafer and piles up in this embodiment, the thickness that therefore has the glue-line 130 of two rank characteristics is about 3 to 6 mils (mil), and this thickness view plate 121 and deciding.In addition, the solvent that glue-line 130 with two rank characteristics comprises thermosetting resin or polymer (for example: polyimides, poly-quinine (polyquinolin) or benzocyclobutene (benzocyclobutene)) and can dissolve above-mentioned thermosetting resin (for example: butyrolactone (butyrolactone) and cyclopentanone (cyclopentanone) or 1,3,5-trimethylbenzene (1,3, the 5-mesitylene) mixed solvent of Denging).Wherein, for the glue-line 130 with two rank characteristics, solvent is not for essential.When coating, have A rank characteristic owing to have the liquid glue-line 130 of two rank characteristics, therefore liquid glue-line 130 has enough flowabilities, so that printing.
Then, see also the step 13 of carrying out " precuring wafer " shown in Fig. 3 C, wherein pre-cure step can be reached by heating or ultraviolet ray.If adopt heating steps, then wafer 110 can be placed in the baking oven, and heat about 1 hour down at proper temperature (90 to 150 degree Celsius approximately).After the precuring manufacture method, printed liquid glue-line 130 is converted to bonding film 131.Perhaps, pre-cure step 13 also can be reached by vacuumize.Be used for bonding film 131 that wafer-to wafer piles up for solid-state, and between thickness of bonding film 131 about 3 and 8 mils, be preferably between about 5 and 6 mils.In addition, when operating temperature during greater than the glass transition temperature (Tg) of bonding film 131, bonding film 131 will become and have viscosity, meaning promptly, bonding film 131 has B rank characteristic, and also has thermosetting.In addition, the glass transition temperature is for example between Celsius-40 and 175 degree.
Then, see also shown in Fig. 3 D the step 14 of carrying out " location wafer ", upset wafer 110 and adheres to wafer 110 on the positioning belt 140 so that non-active surface 111 faces down.Positioning belt 140 for example is the wafer positioning belt, and its material for example is polyvinyl chloride (polyvinyl chloride), and positioning belt 140 has viscosity, and adheres in the metal framework with circular open, and metal framework is used for the wafer cutting process.In first embodiment, bonding film 131 adheres on the positioning belt 140 by the viscosity of positioning belt 140.After the step 14 of finishing " location wafer ", carry out the step 15 of " cutting crystal wafer has the wafer of bonding film with formation ", its cutting machine 150 (laser or diamond cut instrument) that passes through to use dicing saws is along cutting path 114 cutting crystal wafers 110, thereby formation has most wafers 113 of bonding film 131.Therefore, not only can be low-cost and the wafer 113 with glue-line is provided apace, also can use it for that wafer-to wafer piles up or other multiple packaging bodies.
See also shown in Fig. 3 E, at first, another wafer 160 is fixed to for example carrier of substrate 170, and the connection pad 161 of wafer 160 for example electrically connects by wiring 162 and substrate 170, and wherein substrate 170 can be winding substrate or ceramic substrate.Then, hold wafer 113, and wafer 113 is fixed on the wafer 160 with bonding film 131 by wafer adhesion machine.When apply the hot pressing temperature of about 120 degree Celsius for wafer 113, so that bonding film 131 when becoming toughness (shown in Fig. 3 F), was finished wafer-to wafer stacked structure (even less than a second) in a little several seconds to about 175 degree.Yet preferable hot pressing temperature and time is not make bonding film 131 finish thermosetting reaction after the wafer-to wafer adhesion.
After this, for example, wiring 180 engages (wire-bonded) so that electrically connect between the connection pad 115 and substrate 170 of wafer 113 through lead.Yet the wafer processing method that has the wafer of glue-line in order to manufacturing of the present invention also not only can be applicable to wafer-to wafer and piles up, and also can be applicable to be used for wafer-substrate and wafer-multiple packaging bodies such as lead frame adhesion.Perhaps, in the step 12 of " coating has the liquid glue-line of two rank characteristics ", on the part of the non-active surface 111 of wafer 110, be coated with liquid glue-line 130 fully by rotary coating or printing process with two rank characteristics, then via pre-cure step 13, positioning step 14 and cutting step 15, and then on non-active surface, form most wafers 113, so that be used for the wafer-to wafer adhesion with bonding film 131.Bonding film 131 has higher viscosity and is easier to than existing known liquid elargol to be handled, and makes the contact mat of substrate can more approach to have the wafer 113 of glue-line, so that encapsulate in order to make wafer size (chip scalepackage, CSP).
See also Fig. 3 G, after this, on substrate 170, form packing colloid 182,, and then protect its damage of avoiding the exterior object of dust for example or moisture, and then finish the manufacture method of wafer-wafer encapsulation body with cover wafers 113,160 and wiring 162,180.In another embodiment, in wafer-wafer encapsulation body, bonding film 131 can be glue-line.In addition, the area of bonding film 131 and be not more than the area (Fig. 3 G illustrates the area of the area of bonding film 131 less than wafer 113) of wafer 113.
Seeing also Fig. 3 H is if will be applied to the profile of ball-shaped grid array packaging body according to the wafer-substrate package body structure of the first embodiment of the present invention.With reference to figure 3H, on the surface 174 of substrate 170, dispose most soldered balls 20, and then finish the manufacturing of ball-shaped grid array type wafer encapsulation body.Wherein ball-shaped grid array type wafer encapsulation body for example electrically connects printed circuit board (PCB) (PCB) (not shown) via these soldered balls 20.
In order to understand the surface that the present invention is not limited to print wafer, provide second embodiment.Shown in Fig. 4 A, at first, provide wafer 210.Wafer 210 has an active surface 211, and it has most connection pads 215 (or projection), and a non-active surface 212, and it is corresponding to active surface 211, so that integrate most wafers 213.For example, connection pad 215 is positioned at the center of each wafer 213, and active surface 211 faces up.After this, shown in Fig. 4 B, for example on active surface 211, form liquid glue-line 230 with two rank characteristics by screen printing or mould printing method.More specifically, on the active surface 211 of wafer 210, put web plate 221, then on active surface 211, print liquid glue-line 230 with two rank characteristics by scraping 222.In a second embodiment, because web plate 221 covers the connection pad 215 of wafers 210, therefore the liquid glue-line 230 that will have two rank characteristics is in the predetermined pattern mode, and partly is printed on the active surface 211 of wafer 210, and its thickness is about 1 to 3 mil.
Then, see also shown in Fig. 4 C,,, make that the liquid glue-line 230 with two rank characteristics on the active surface 211 that is positioned at wafer 210 is converted to bonding film 231 with precuring wafer 210 for example by heating or ultraviolet ray.Bonding film 231 has B rank characteristic, and has for example glass transition temperature (Tg) between Celsius-40 and 175 degree.Anticipate promptly, glass transition temperature (Tg) can be higher than 40 degree Celsius, makes bonding film 231 not have viscosity under normal room temperature, so that carry, move and store, and be maintained thermal bonding glue material (thermal-bonding adhesive).
Then, shown in Fig. 4 D, upset wafer 210 so that active surface 211 faces down, and is positioned active surface 211 on the positioning belt 240.After the wafer 210 of location, along cutting path 214 cutting crystal wafers, have most wafers 213 of bonding film 231 with formation on active surface 211 by cutting machine 250.Therefore, not only can be at low cost and the wafer 213 with glue-line is provided apace, and also can be used in the multiple packaging body.For example, shown in Fig. 4 E, hold wafer 213 with bonding film 231 by wafer adhesion machine, and wafer 213 is fixed to the carrier (carrier is printed circuit board (PCB), winding substrate or ceramic circuit board for example) of similar base plate for packaging 260, wherein base plate for packaging 260 has a slit 260a.
For example under the thermal bonding temperature of about 120 degree Celsius about 175 degree extremely Celsius, wafer 213 quick (even in a little several seconds) is adhered on the substrate 260.Under the thermal bonding temperature, pass through bonding film 231, so that the bond strength between substrate 260 and the wafer 213 to be provided.After wafer 213 is fixed on the substrate 260, the slit 260a of substrate 260 will expose the part of wafer 213, so wiring 262 is for example via slit 260a and base plate for packaging 260 and wafer 213 electric connections.Then, configuration packages colloid 263 on substrate 260 with covering wiring 262 and wafer 213, and protects wiring 262 and wafer 213 to avoid the damage of outside moisture or external force.In addition, shown in Fig. 4 F, substrate 260 away from the surface of wafer 213 on form the step of soldered ball 261 after, just can produce the BGA packaging body.
In addition, in the third embodiment of the present invention, the manufacture method step is identical with the explanation among second embodiment shown in Fig. 4 A to Fig. 4 C.See also shown in Figure 5ly, the non-active surface 212 of wafer 210 directly is positioned on the positioning belt 240.After precuring wafer 210,, and wafer 210 is cut out most wafers 213 with the active surface 211 of wafer 210 up by cutting machine 250.As shown in Figure 6, the wafer 213 with bonding film 231 is stacked on the carrier 272, and then the interior pin 271 with the LOC lead frame adheres to downwards on the active surface 211 of wafer 213.By thermal bonding, bonding film 231 becomes and has viscosity, so that between the interior pin 271 of adhering wafers 213 and lead frame.As shown in Figure 7, form wiring 274, packing colloid 273, to make the packaging body of TSOP (thin-type small-size encapsulation) or QFP (flat-four-side encapsulation).Therefore, have the wafer processing method of the wafer of glue-line in order to manufacturing according to of the present invention, can be low-cost and produce wafer 213 on a large scale with bonding film 231, so that be used for wafer-leaded package body.
See also the profile of the wafer in the wafer-process process that Fig. 8 A to Fig. 8 D is an a fourth embodiment in accordance with the invention.With reference to figure 8A, at first, provide wafer 110, wherein wafer 110 has a non-active surface 111, an active surface 112, most cutting paths 114 and most connection pads 115.For example, connection pad 115 for example is configured on the active surface 112.With reference to figure 8B, then, for example on the whole non-active surface 111 of wafer 110, be coated with liquid glue-line 130a with at least two rank characteristics (A rank, B rank, C rank) by screen printing, mould printing or rotary coating.Preferably, put web plate 121a on the non-active surface 111 of wafer 110, wherein the netting twine of web plate 121a is thinner than the netting twine of the web plate 121 described in first embodiment.Then, on non-active surface 111, print liquid glue-line 130a by scraping 122 with adequate liquidity, the glue-line 130a that wherein has two rank characteristics comprises thermosetting resin or polymer (for example polyimides, poly-quinine (polyquinolin) or benzocyclobutene (benzocyclobutene)) and can dissolve the solvent of thermosetting resin mentioned above (for example butyrolactone and cyclopentanone or 1,3, the mixed solvent of 5-trimethylbenzene etc.).It should be noted that solvent is not for essential in the glue-line 130a with two rank characteristics.
See also Fig. 8 C, then, proper temperature (Celsius about 90 and about 150 degree between) following heating wafer 130 for example a hour, and liquid glue-line 130a is converted to the bonding film 131a with B rank characteristic, and the bonding film 131a that wherein has a B rank characteristic for example has the glass transition temperature (Tg) between Celsius-40 and 175 degree.With reference to figure 8D and 8E, by positioning belt 140 and cutting machine 150 wafer 110 is cut into most the wafers 113 of the bonding film 131a with B rank characteristic, wherein have B rank characteristic bonding film 131a area and be not more than the area (area that Fig. 8 E illustrates the bonding film 131a with B rank characteristic equals the area of wafer 113) of the wafer 113 under it.About bonding film 131a, bonding film 131a also can be glue-line, but bonding film 131a is not limited to have the bonding film of B rank characteristic.
Graphic (shown in Fig. 3 A to Fig. 3 D) shown in first embodiment compared with the fourth embodiment of the present invention, and the main difference of the 4th embodiment is the big liquid glue-line 130a with at least two rank characteristics (A rank, B rank, C rank) that is coated with on the whole non-active surface 111 of wafer 110.Then, for example by heating or the liquid glue-line 130a of ultraviolet precuring, so that liquid glue-line 130a is converted to the bonding film 131a with B rank characteristic.Wherein, bonding film 131a also can be glue-line, but bonding film 131a is not limited to have the bonding film of B rank characteristic.About other elements among the 4th embodiment, the feature of the feature of material or film thickness and position thereof in the first embodiment of the present invention for example.
See also the profile of the wafer that Fig. 8 E to Fig. 8 F is the wafer with glue-line of the 4th embodiment-substrate package body.With reference to figure 8E, at first, configuration has the wafer 113 of the bonding film 131a of B rank characteristic on the carrier of for example substrate 170, and by bonding film 131a wafer 113 is fixed on the substrate 170 area of bonding film 131a and be not more than the area (area that Fig. 8 E illustrates bonding film 131a equals the area of wafer 113) of wafer 113 wherein with B rank characteristic.Then, most connection pads 115 of wafer 113 electrically connect by most the connection pads 172 of most wiring 180 with substrate 170.With reference to figure 8F, after this, on substrate 170, form packing colloid 190, with cover wafers 113 and wiring 180, wherein packing colloid 190 can prevent that wafer 113 and wiring 180 from avoiding the damage of the exterior object of dust for example or moisture, and then finishes the manufacturing of wafer-substrate package body structure 100.
See also Fig. 8 G and be applied to the profile of ball-shaped grid array packaging body for wafer-substrate package body structure with a fourth embodiment in accordance with the invention.With reference to figure 8G, on the surface 174 of substrate 170, dispose most soldered balls 20, and then finish the manufacturing of ball-shaped grid array type wafer encapsulation body 101.Wherein ball-shaped grid array type wafer encapsulation body 101 for example electrically connects via these soldered balls 20 and printed circuit board (PCB) (not shown).
See also Fig. 9 A to Fig. 9 C and be the profile of wafer-wafer encapsulation body of the wafer of the 4th embodiment with glue-line.With reference to figure 8E and Fig. 9 A, after the step shown in Fig. 8 E, when covering wiring 180 and connection pad 115, can't damage wiring 180 and connection pad 115 because have the bonding film 131b of B rank characteristic, therefore another wafer 113a with bonding film 131b of B rank characteristic directly can be disposed on the wafer 113, and adhere on the wafer 113 by bonding film 131b with B rank characteristic.Then, the bonding film 131b that configuration has B rank characteristic between the active surface 112 of the non-active surface 111a of wafer 113a and wafer 113.With reference to figure 9B, then, the most bar wiring 180a of configuration on most connection pads 176 of individual connection pad 115a of the majority of wafer 113a and substrate 170 are so that wafer 113a is via wiring 180a and substrate 170 electric connections.
See also Fig. 9 C; after this, on substrate 170, form packing colloid 190a, with cover wafers 113a, 113 and wiring 180,180a; and protect its damage of avoiding the exterior object of dust for example or moisture, and then finish the manufacture method of wafer-wafer encapsulation body 102.In another embodiment, in wafer-wafer encapsulation body 102, bonding film 131b can be glue-line, but bonding film 131b is not limited to have the bonding film of B rank characteristic, wherein the area of bonding film 131b and be not more than the area (area that Fig. 9 C illustrates bonding film 131b equals the area of wafer 113a) of wafer 113a.About bonding film 131a, bonding film 131a also can be glue-line, but bonding film 131a is not limited to have the bonding film of B rank characteristic.
See also Fig. 9 D for the wafer-wafer encapsulation body of a fourth embodiment in accordance with the invention being applied to the profile of ball-shaped grid array packaging body.With reference to figure 9D, after the step shown in Fig. 9 C, on the surface 174 of substrate 170, dispose most soldered balls 20, and then finish the manufacturing of ball-shaped grid array type wafer encapsulation body 103.Wherein ball-shaped grid array type wafer encapsulation body 103 for example electrically connects via these soldered balls 20 and printed circuit board (PCB) (not shown).
See also the profile of the wafer that Figure 10 A to Figure 10 B is the wafer with glue-line of the 4th embodiment-leaded package body.With reference to figure 10A and Fig. 8 D, after the step shown in Fig. 8 D, can on the carrier of for example lead frame, dispose the wafer 113 of the bonding film 131a with B rank characteristic.Lead frame comprises wafer pad 175 and most pin 175a.Wafer 113 with bonding film 131a of B rank characteristic is disposed on the wafer pad 175 by the bonding film 131a with B rank characteristic.Then, the most bar wiring 180 of configuration on individual connection pad 115 of the majority of wafer 113 and pin 175a are so that wafer 113 for example electrically connects with pin 175a by wiring 180.
See also Figure 10 B, subsequently, on wafer pad 175 and pin 175a, form packing colloid 190a,, and then finish the manufacture method of wafer-leaded package body structure 104 with cover wafers 113, wiring 180 and wafer pad 175.In addition, pin 175a can be the shape that is bent into " J " shape, so that be used for the surface adhering on the printed circuit board (PCB) and electrically connect with printed circuit board (PCB).Undoubtedly, be fixed on the lead frame the wafer number can greater than one (meaning promptly, two, three, four ...), following examples illustrate two wafer that piles up-leaded package bodies as an example.
See also Figure 11 A to Figure 11 B and be the profile of two wafer that piles up-leaded package bodies of the wafer of the 4th embodiment with glue-line.With reference to figure 11A and Figure 10 A, after the step shown in Figure 10 A, it should be noted, do not damage wiring 180 and connection pad 115 owing to have the bonding film 131b of B rank characteristic when covering wiring 180 and connection pad 115, another wafer 113a that therefore has bonding film 131b can directly be disposed on the wafer 113 by the bonding film 131b with B rank characteristic.Then, can on individual connection pad 115a of the majority of wafer 113a and pin 175a, dispose most bar wiring 180a, so that wafer 113a electrically connects by wiring 180a and pin 175a.
See also Figure 11 B; after this; on wafer pad 175 and pin 175a, form packing colloid 190b; with cover wafers 113a and 113, wiring 180 and 180a and wafer pad 175; and then protect wafer 113a and 113 to avoid for example damage of external force such as dust, moisture, and then finish the manufacturing of two wafer that piles up-leaded package body structures 105.Then, pin 175a for example is bent into " J " shape, so that be used for the surface adhering of printed circuit board (PCB) and electrically connect with printed circuit board (PCB).It should be noted, in two wafer that piles up-leaded package bodies 105, bonding film 131b can be glue-line, but bonding film 131b is not limited to have the bonding film of B rank characteristic, wherein the area of bonding film 131b and be not more than the area (area that Figure 11 B illustrates bonding film 131b equals the area of wafer 113a) of wafer 113a.About bonding film 131a, bonding film 131a also can be glue-line, but bonding film 131a is not limited to have the bonding film of B rank characteristic.
See also Figure 12 A and be the profile of wafer-wafer encapsulation body of the wafer of the 5th embodiment with glue-line.With reference to figure 4E and 12A, in the 5th embodiment, after the wafer 213 of the bonding film 231 with B rank characteristic is fixed to carrier 260, another wafer 213a with bonding film 231a of B rank characteristic can be fixed to wafer 213, meaning promptly, the bonding film 231a that configuration has B rank characteristic between the non-active surface 212a of the non-active surface 212 of wafer 213 and wafer 213a, the wafer 213a of another bonding film 231a that wherein has B rank characteristic is for example made by the manufacture method described in the fourth embodiment of the present invention shown in Fig. 8 A to Fig. 8 D.About other elements among the 5th embodiment, for example the feature class of material or film thickness and allocation position thereof like or be same as feature described in the second embodiment of the present invention.
See also Figure 12 A, in another embodiment, bonding film 231a can be glue-line, but bonding film 231a is not limited to have the bonding film of B rank characteristic.In addition, the area of bonding film 231a and be not more than the area (area that Figure 12 A illustrates bonding film 231a equals the area of wafer 213a) of wafer 213a.In addition, bonding film 231 also can be glue-line, but bonding film 231 is not limited to have the bonding film of B rank characteristic.In addition, the area of bonding film 231 and be not more than the area (Figure 12 A illustrates the area of the area of bonding film 231 less than wafer 213) of wafer 213.
See also Figure 12 B for wafer-wafer encapsulation body according to a fifth embodiment of the invention being applied to the profile of ball-shaped grid array packaging body.Carrier 260 not only can be substrate, and also can be lead frame.With reference to figure 12A and 12B, if carrier 260 is the substrate (being used for for example ball-shaped grid array packaging body) of for example winding substrate or ceramic substrate, then can on the surperficial 260b of carrier 260, dispose most soldered balls 261, and on carrier 260, form packing colloid 263, with cover wafers 213a, 213 and wiring 262,262a, and then finish the manufacturing of ball-shaped grid array type wafer encapsulation body 106.
Seeing also Figure 12 C is the profile of the wafer-leaded package body of the wafer with glue-line of the 5th embodiment.With reference to figure 12A and Figure 12 C, if carrier 260 be lead frame, then configuration has after the wafer 213a of bonding film 231a of B rank characteristic on wafer 213, and formation packing colloid 263 on carrier 260 is with cover wafers 213a, 213 and wiring 262,262a.Then, finish the manufacturing of two wafer that piles up-leaded package body structures 107, wherein pin 265 for example is bent into " J " shape, so that be used for the surface adhering of printed circuit board (PCB) and electrically connect with printed circuit board (PCB).
Seeing also Figure 13 is the profile of first wafer of Figure 12 A via most solder projections and carrier electric connection.With reference to figure 12A and Figure 13, except wiring 262, can reach the electric connection between carrier 260 and the wafer 213 by most solder projections 30 (meaning is promptly covered brilliant the connection), and most solder pads 215a of solder projection 30 configurations.Therefore, in an embodiment, carrier 260 does not have the through hole (not shown) that wiring of allowing 262 is passed.Primer 40 is configured between carrier 260 and the wafer 213, with covering solder projection 30, and the stress between reduction carrier 260, wafer 213 and the solder projection 30, and then reduce the possibility that solder projection 30 ruptures.
See also Figure 14 A to Figure 14 C and be the profile of wafer-wafer encapsulation body of the wafer of the 6th embodiment with glue-line.With reference to figure 14A, compare with the step shown in Fig. 9 A, bonding film 331a or 331b with B rank characteristic are thinner than bonding film 131a or 131b with B rank characteristic.In addition, the bonding film 331b with B rank characteristic is configured between the active surface 112 of the active surface of wafer 113a and wafer 113.Wafer 113 has most connection pads 115 and most solder pads 117 on its active surface 112, wherein solder projection 30 is disposed on the solder pads 117.With reference to figure 14B, when covering wiring 180, solder projection 30 and connection pad 115, can't damage wiring 180, solder projection 30 and connection pad 115 owing to have the bonding film 331b of B rank characteristic, therefore another wafer 113a with bonding film 331b of B rank characteristic directly can be disposed on the wafer 113 by the bonding film 331b with B rank characteristic, and wafer 113 and 113a for example are electrically connected to each other via solder projection 30.It should be noted, on the active surface 112 of wafer 113 for example by reprovision line layer (redistribution layer, RDL) technology and change the position of solder pads 117.
See also Figure 14 C, after this, on substrate 170, form packing colloid 190a,, and protect its damage of avoiding the exterior object of dust for example or moisture, and then finish the manufacture method of wafer-wafer encapsulation body 108 with cover wafers 113a, 113 and wiring 180.In another embodiment, in wafer-wafer encapsulation body 108, bonding film 331b can be glue-line, but bonding film 331b is not limited to have the bonding film of B rank characteristic, wherein the area of bonding film 331b and be not more than the area (area that Figure 14 C illustrates bonding film 331b equals the area of wafer 113a) of wafer 113a.About bonding film 331a, bonding film 331a also can be glue-line, but bonding film 331a is not limited to have the bonding film of B rank characteristic.In addition, be similar to the step shown in Fig. 9 D, can on the surface 174 of substrate 170, dispose most soldered balls (not shown) to finish the manufacturing of ball-shaped grid array type wafer encapsulation body.
See also Figure 15 and be another embodiment in order to the solder projection 30 shown in the allocation plan 14A.With reference to figure 14A and Figure 15, wafer 113a has most solder pads 117a on its active surface.Compare with the configuration of the solder projection 30 shown in Figure 14 A, can on solder pads 117a, dispose solder projection 30, and have the bonding film 331b covering solder projection 30 of B rank characteristic.Then, can implement the step shown in Figure 14 B and Figure 14 C, and then finish the manufacturing of ball-shaped grid array type wafer encapsulation body.
It should be noted, Fig. 9 C, Figure 11 A, Figure 12 A, Figure 13, Figure 14 C and wafer-to wafer stacked structure shown in Figure 15 are not limited to the stacked structure of two wafers, if manufacture method is feasible, then the structure among the present invention can comprise further that (meaning is plural wafer, three, four ... wafer) stacked structure.In addition, in all embodiment of the present invention, the bonding film with B rank characteristic can be glue-line.In addition, in the present invention, be not limited to lead in carrier and electric connection between the wafer and be connected; And also comprise and cover brilliant the connection.
Generally speaking, the bonding film of utilization of the present invention with B rank characteristic has the wafer of glue-line with manufacturing and the wafer processing method of wafer encapsulation body has the following advantages.
(1) compare with the existing prior art method of the use liquid thermosetting glue-line of the connection pad that more easily pollutes lower wafer, the bonding film of the B of having of the present invention rank characteristic can not damage wiring or the connection pad that has been present in wafer-substrate or the wafer-leaded package body structure.Therefore, even when the non-active surface of the complete cover wafers of wafer stage thermal bonding bonding film with B rank characteristic, the wafer with bonding film of B rank characteristic can easily be stacked under the situation of not considering wiring or connection pad on already present wafer-substrate or wafer-leaded package body structure.
(2) have expensive solid polyimide band and make wafer or the existing prior art method of wafer encapsulation body is compared with using with glue-line, utilization of the present invention has the bonding film of B rank characteristic, and wafer-to wafer piles up to produce cheaply, wafer-substrate or wafer-leaded package body structure.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking aforesaid being as the criterion that claim defines.

Claims (7)

1. the manufacture method of a wafer-wafer encapsulation body is characterized in that it comprises:
One carrier, one first wafer and one second wafer are provided, this first wafer configuration is on this carrier, this first wafer has one first active surface, and this second wafer has one second active surface, and this second active surface is provided with a bonding film with B rank characteristic;
This bonding film by having B rank characteristic is with this second wafer configuration this first active surface in this first wafer, and this first wafer and this second wafer are electrically connected to each other by a plurality of solder projections, those solder projections are disposed between this first active surface of this second active surface of this second wafer and this first wafer, and this bonding film coats those solder projections; And
Form a packing colloid on this carrier, to cover this first wafer and this second wafer.
2. the manufacture method of wafer-wafer encapsulation body according to claim 1 is characterized in that wherein a plurality of wiring electrically connect between this carrier and this first wafer, and this bonding film with B rank characteristic covers the part of described wiring.
3. the manufacture method of wafer-wafer encapsulation body according to claim 1 is characterized in that wherein said solder projection is disposed at this first active surface of this first wafer.
4. the manufacture method of wafer-wafer encapsulation body according to claim 3 it is characterized in that having a plurality of connection pads and a plurality of solder pads on this first active surface of this first wafer wherein, and described solder projection is disposed on the described solder pads.
5. wafer-wafer encapsulation body is characterized in that it comprises:
Carrier;
First wafer is disposed on this carrier, and has one first active surface;
First bonding film is disposed between this carrier and this first wafer;
Second wafer has second active surface towards this first active surface;
Second bonding film is disposed between this second active surface of this first active surface of this first wafer and this second wafer, and has B rank characteristic;
A plurality of solder projections are in this second bonding film and be electrically connected between this second active surface of this first active surface of this first wafer and this second wafer;
A plurality of wiring electrically connect this carrier and this first wafer, and this second bonding film cover the part of described wiring; And
Packing colloid is disposed on this carrier, to cover this first wafer and this second wafer.
6. wafer-wafer encapsulation body according to claim 5 is characterized in that wherein this carrier is base plate for packaging or lead frame.
7. wafer-wafer encapsulation body according to claim 5 is characterized in that wherein this first bonding film has B rank characteristic.
CN2008101755291A 2006-06-06 2006-06-06 Wafer-wafer encapsulation body and manufacturing process therefor Expired - Fee Related CN101419963B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2008101755291A CN101419963B (en) 2006-06-06 2006-06-06 Wafer-wafer encapsulation body and manufacturing process therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2008101755291A CN101419963B (en) 2006-06-06 2006-06-06 Wafer-wafer encapsulation body and manufacturing process therefor

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CNA2006100833805A Division CN101086952A (en) 2006-06-06 2006-06-06 Wafer package body and crystal circle processing method for making wafer with rubber layer

Publications (2)

Publication Number Publication Date
CN101419963A CN101419963A (en) 2009-04-29
CN101419963B true CN101419963B (en) 2011-05-25

Family

ID=40630675

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008101755291A Expired - Fee Related CN101419963B (en) 2006-06-06 2006-06-06 Wafer-wafer encapsulation body and manufacturing process therefor

Country Status (1)

Country Link
CN (1) CN101419963B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103377951A (en) * 2012-04-20 2013-10-30 英飞凌科技股份有限公司 Manufacturing method for semiconductor device and semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102201348A (en) * 2010-03-26 2011-09-28 力成科技股份有限公司 Array cutting type quad flat non-leaded packaging method
TWI500130B (en) * 2013-02-27 2015-09-11 矽品精密工業股份有限公司 Package substrate, semiconductor package and methods of manufacturing the same
US9418974B2 (en) 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6380615B1 (en) * 1999-06-29 2002-04-30 Hyundai Electronics Industries Co., Ltd. Chip size stack package, memory module having the same, and method of fabricating the module
CN1577779A (en) * 2003-07-29 2005-02-09 南茂科技股份有限公司 Central welding pad memory body stacking encapsulating assembly and encapsulating process thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6380615B1 (en) * 1999-06-29 2002-04-30 Hyundai Electronics Industries Co., Ltd. Chip size stack package, memory module having the same, and method of fabricating the module
CN1577779A (en) * 2003-07-29 2005-02-09 南茂科技股份有限公司 Central welding pad memory body stacking encapsulating assembly and encapsulating process thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103377951A (en) * 2012-04-20 2013-10-30 英飞凌科技股份有限公司 Manufacturing method for semiconductor device and semiconductor device
US9318473B2 (en) 2012-04-20 2016-04-19 Infineon Technologies Ag Semiconductor device including a polymer disposed on a carrier
CN103377951B (en) * 2012-04-20 2016-11-23 英飞凌科技股份有限公司 The manufacture method of semiconductor device and semiconductor device

Also Published As

Publication number Publication date
CN101419963A (en) 2009-04-29

Similar Documents

Publication Publication Date Title
US20070215992A1 (en) Chip package and wafer treating method for making adhesive chips
USRE42349E1 (en) Wafer treating method for making adhesive dies
US20040262728A1 (en) Modular device assemblies
CN101312162B (en) Method for manufacturing semiconductor device
CN104769713B (en) Include the semiconductor devices of the independent film layer for being embedded in and/or separating semiconductor bare chip
TWI313048B (en) Multi-chip package
US20060151865A1 (en) Semiconductor chip stack package having dummy chip
TW201010020A (en) Semiconductor device and method for manufacturing it
KR20050022558A (en) BGA package, manufacturing method thereof and stacked package comprising the same
CA2392837A1 (en) Integrated circuit package formed at a wafer level
US20100314730A1 (en) Stacked hybrid interposer through silicon via (TSV) package
US6589812B2 (en) Pre-applied adhesion promoter
US20070080435A1 (en) Semiconductor packaging process and carrier for semiconductor package
JP2021129083A (en) Semiconductor device and method for manufacturing the same
CN101419963B (en) Wafer-wafer encapsulation body and manufacturing process therefor
TW200531241A (en) Manufacturing process and structure for a flip-chip package
JPH08153830A (en) Semiconductor device and manufacture thereof
KR100405771B1 (en) Method for manufacturing semiconductor device
US20030178715A1 (en) Method for stacking chips within a multichip module package
US7368322B2 (en) Method for mounting a chip on a base and arrangement produced by this method
CN101086952A (en) Wafer package body and crystal circle processing method for making wafer with rubber layer
KR100726892B1 (en) Three-dimensional chip stacking package module and preparation method thereof
US20080265393A1 (en) Stack package with releasing layer and method for forming the same
CN101131992A (en) Multi-chip stacking type packaging structure
JP2004063516A (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110525

Termination date: 20200606