CN101409241A - 半导体芯片封装、半导体芯片组件和制造器件的方法 - Google Patents

半导体芯片封装、半导体芯片组件和制造器件的方法 Download PDF

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Publication number
CN101409241A
CN101409241A CNA2008101661449A CN200810166144A CN101409241A CN 101409241 A CN101409241 A CN 101409241A CN A2008101661449 A CNA2008101661449 A CN A2008101661449A CN 200810166144 A CN200810166144 A CN 200810166144A CN 101409241 A CN101409241 A CN 101409241A
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semiconductor chip
layer
contact
material layer
semiconductor
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CN101409241B (zh
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T·迈耶
M·布伦鲍尔
J·波尔
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及了半导体芯片封装、半导体芯片组件和制造器件的方法。公开了制造器件的方法，半导体芯片封装和半导体芯片组件。一个实施例包括施加至少一个半导体芯片到第一成形元件上。施加至少一个元件到第二成形元件上。施加材料到该至少一个半导体芯片和该至少一个元件上。

Description

半导体芯片封装、半导体芯片组件和制造器件的方法
技术领域
本发明涉及用于制造至少一个器件的方法，半导体芯片封装和半导体芯片组件。
背景技术
在半导体芯片封装技术中的一个挑战是关于将半导体芯片的接触焊垫连接到外部的接触元件。另一个挑战是增长的通过芯片或者封装分层的功能密度。在芯片分层中，两个或者多个半导体芯片被分层并且容纳在一个芯片封装中。当将半导体芯片容纳到芯片封装中时，半导体芯片的接触焊垫就必须连接到芯片封装的外部接触元件。
附图说明
附图提供了对说明书的实施例的进一步的理解并且成为说明书的一部分。附图说明了实施例并且和说明书一起用于解释实施例的原理。其它实施例和实施例的优点将很容易理解，这是因为通过参考下面的详细描述将更容易理解它们。附图的元件没有必要按着相互的比例画出。相似的参考符号表示对应相似的部件。
图1是制造至少一个器件的方法的实施例的流程图。
图2A-I是表示中间产品和器件的横截面图，并且表示如图1所示的实施例的其它实施例的处理设备。
图3A-D是根据用于制造至少一个器件的方法的其它实施例制造的器件的不同实施例的横截面图。
图4是用于制造至少一个器件的方法的其它实施例的流程图。
图5A-F是中间产品和器件的横截面图，示出了如图1，2A-I，2A-D和4的其它实施例。
图6是用于制造半导体芯片组件的方法的实施例的流程图。
图7A和7B示出了中间产品和半导体芯片组件的横截面图，示出了如图6所示的实施例的其它实施例。
图8示出了半导体芯片封装的实施例的横截面图。
图9A-F是表示中间产品和器件的横截面图，并且表示制造至少一个器件的其它实施例的处理设备。
图10A和10B是表示中间产品和器件的横截面图，并且表示制造至少一个器件的其它实施例的处理设备。
图11A-C是表示中间产品和器件的横截面图，用于表示制造至少一个器件的其它实施例。
具体实施方式
在下面的参考附图进行的详细说明中，该附图是说明书的一部分，其中通过说明实现本发明的具体实施例的方式示出。在这一点上，方向术语，例如“顶部”、“底部”、“前面”、“后面”、“前沿”、“后沿”是参考被描述的图的方向来使用的。因为实施例的各部件以不同的方向被定向，所以使用方向术语的目的是说明性的而不是限制性的。可以理解，可以使用其它实施例，并且可以进行结构或逻辑变化而不脱离本发明的范围。因此，下面的详细描述不是限制性的，本发明的范围由权利要求书来限定。
可以理解，这里描述的各种示例性实施例的特征可以相互组合，除非另有特别说明。
现在参考附图描述实施例，其中通常用相似的参考符号表示相同的元件。在下面的描述中，出于解释的目的，设定了具体的数字以便提供对一个或者多个实施例的全面了解。然而，本领域的技术人员很清楚，可以使用更具体的细节来实现一个或者多个实施例。在其它的例子中，以示意性的形式描述了公知的结构和元件，以便简化描述一个或者多个实施例。因此下面的描述不是出于限制性目的，其范围由权利要求书来限定。
用于制造至少一个器件的方法的实施例，用于制造半导体芯片组件的方法的实施例和用于半导体芯片封装的实施例可以使用多种类型的半导体芯片或者半导体衬底，其中包括逻辑集成电路，模拟集成电路，混合信号集成电路，传感器电路，MEMS(微机电系统)，功率集成电路，具有集成的无源元件的芯片。
在多个实施例中，将多个层或者堆层应用到彼此上，或者涂覆或沉积材料到层上。可以理解，例如术语“涂覆”或者“沉积”的意思是完全覆盖了将多层涂覆到彼此上的所有技术。在一个实施例中，它们的意思是覆盖技术，其中将多层作为整体一次涂覆，例如叠置技术和将多层顺序沉积的技术，例如溅射、电镀、模制、CVD等。
半导体芯片可以包括在它们的外表面的一个或多个上的接触元件或接触垫，其中接触元件用于电接触半导体芯片。可以使用任何导电材料来制造接触元件，例如使用铝、金或者铜的材料，或者使用合金材料，或者使用导电的有机材料、或者使用导电的半导体材料。
在多个实施例中，半导体芯片可以被材料层覆盖。材料层的材料可以是任何电绝缘材料，例如任何种类的模塑材料，任何种类的环氧树脂材料，或者任何种类的树脂材料。在用材料层覆盖半导体芯片的过程中，“嵌入的芯片”能被制造。嵌入的芯片可以具有标准半导体晶片的形式，并且通常被称为“重构晶片”或者“再造晶片”。然而，可以了解，嵌入的晶片不受限于晶片的形式和形状，而且可以具有任意的尺寸和形状和任何适合的嵌入有半导体芯片的阵列。
图1示出了制造至少一个器件的方法的实施例的流程图。该方法包括将至少一个半导体芯片施加到第一成形元件上(S1)，施加至少一个元件到第二成形元件上(S2)，和施加材料到该至少一个半导体芯片和该至少一个元件上(S3)。
将被制造的器件可以是例如中间产品或者成品。例如，该器件可以是半导体芯片模块，例如是嵌入的晶片或重构晶片或再造晶片形式。例如，该器件还可以是通过将半导体芯片模块分成多个半导体芯片封装而得到的半导体芯片封装。
根据一个实施例，施加到第二成形元件上的元件可以是其它半导体芯片，通路元件，电阻器，线圈，层，金属层，箔片，金属箔片，铜箔片，引线框架，焊料球，夹具，接触元件，或者接触垫。
根据另一个实施例，该至少一个半导体芯片可以被施加到承载层上，在一个实施例中被施加到第一承载层上，其接着被施加到第一成形元件。单独的，至少一个元件可以被施加到承载层上，在一个实施例中是第二承载层，其接着被施加到第二成形元件。该至少一个半导体芯片可以被施加到第一承载层的主表面上，该至少一个元件可以被施加到第二承载层的主表面上，在施加材料之前，将第一和第二承载层相对彼此定位，以使得第一和第二承载层的主表面彼此面对。
根据另一个实施例，施加材料层包括模塑，在一个实施例中是传递模塑或者压缩模塑。更具体的，在传递模塑中通过将材料引入到通过第一成形元件和第二成形元件形成的空腔中来施加材料到至少一个半导体芯片上和至少一个元件上。更具体的，在压缩模塑中通过将材料压入到第一成形元件和第二成形元件之间来将材料施加到至少一个半导体芯片上和至少一个元件上。
根据另一个实施例，提供模塑装置，该模塑装置具有下模塑工具和上模塑工具，半导体芯片或者第一承载层被放置到该下模塑工具上，和元件或第二承载层被放置到该上模塑工具上，并且将模塑材料填满在下模塑工具和上模塑工具之间的中间空间中。在一个实施例中，低和上模塑工具相对于彼此被定位，以使得它们形成内部空腔，该内部空腔包含半导体芯片和元件，以及第一和第二承载层(如果存在的话)，并且将模塑材料充满该内部空腔。
根据另一个实施例，多个第一半导体芯片被施加到第一成形元件上和多个第二半导体芯片被施加到第二成形元件上。第一半导体元件的数目等于或者不等于第二半导体芯片的数目。
根据另一个实施例，第一半导体芯片和第二半导体芯片可以被施加为多个第一半导体芯片中的一个或者多个和多个第二半导体芯片中的一个或者多个可以是彼此相对地放置到要被制造的器件中，该器件可以是例如半导体芯片模块。
根据另一个实施例，第一和第二半导体芯片被施加为第一半导体芯片中的一个或者多个和第二半导体芯片中的一个或者多个可以是并排交替的方式被放置。
图2A-I示出了连同处理设备一起的中间产品和器件的横截面图，用于说明制造至少一个器件的方法的另一个实施例。
在图2A中示出了第一承载层1的实施例的横截面图。该第一承载层1例如是有任何结构的材料制成，例如是金属、塑料、陶瓷、或者硅、或者聚合物材料。它能够是例如刚性构造，使得它是稳定和可持的。因此它可以具有不小于200μm的厚度。
图2B示出了中间产品的横截面图，其中粘附性箔片2已经被叠置到第一承载层1上，该粘附性箔片2能够具有双面粘附性并且能够从第一承载层1去除掉，或者从它被施加到的任何其它层或者材料上被去除掉。
该第一承载层1可以用做释放层。在一个实施例中，其可包括释放系统，使得当外部预定条件，例如加热或者UV辐射，该粘附性箔片2从第一层1中被去除掉。可以从第一承载层1的侧面施加加热或者UV辐射，使得在粘附性箔片2是热释放箔片的情况中，该第一承载层1不需要是光学透明的，而在粘附性箔片2是UV辐射释放带的情况中，该第一承载层1对于UV辐射是光学透明的。
图2C示出了另一个中间产品的横截面图，其中半导体芯片3被放置在粘附性箔片2上，该半导体芯片3经受了测试，并且按顺序放置。然后，使用常规的拾取和放置机器来将多个半导体芯片3放置到粘附性箔片2上。该多个半导体芯片3的每一个包括至少一个接触垫3A，其中多个接触垫3A被放置到半导体芯片3的与粘附层2面对的表面上。该半导体芯片3被放置为具有充分的空间以允许分散电接触，如后面将要详细介绍的。
图2D示出了如在图2C中示出的中间产品的横截面图，其已经被放置到模塑装置的底部工具4中。该模塑装置的底部工具4能够具有包括空腔的盒子的形状和结构。
图2E示出了操作中的模塑装置的横截面图。图的底部示出了底部工具4，如在图2D中已经介绍的。图的上部示出了模塑装置的顶部工具5。顶部工具5承载了与图2C中所示相同的布置。该另一个布置包括具有其上施加了粘附层7的第二承载层6和附着到粘附层7的第二半导体芯片8。该第二半导体芯片8被定位成当第二承载层6施加到顶部工具5时该第二半导体芯片8与第一半导体芯片3横向错开，该顶部工具5连接到底部工具4以便制造半导体芯片模块。通过使用真空机构将第二承载层6固定到顶部工具5，其原理对于常规的晶片夹具是已知的。
在图2F中，示出了如图2E所示的模塑装置的横截面图。另外，其还示出了如何都将模制介质9填充到底部工具4的空腔中。通过使用分配嘴10来填充该模制介质9，该分配嘴延伸通过在底部工具4和顶部工具5之间的开口。这里使用的模塑技术可以是传递模塑技术或者压缩模塑技术。可能的模塑材料包括例如脂肪族和芳族聚合物，包括热塑性塑料和热固性的聚合物和这些聚合物的混合物，并且还可以包括其它类型的聚合物。
在图2G中，示出了如图2E和2F中已经示出的模塑装置的横截面图。另外，在图2G中示出了如何将顶部工具5向下移动以便固定连接到底部工具4。在该操作中，当通过向下移动第二半导体芯片8和第二承载层6的主表面来使模制介质9位移时，该模制介质9被压缩和分配。符号ΔT表示附加的预定量的加热被施加到底部工具4和顶部工具5上。
在图2H中，示出了顶部工具5固定连接到底部工具4中并且模制介质9沿着第一承载层1和第二承载层6的整个长度被分配，和该模制介质9覆盖了第一半导体芯片3和第二半导体芯片8以及第一承载层1和第二承载层6相互面对的主表面上。
之后，进行固化工艺以便使得模制介质9变硬，使得它成为刚性材料层。在图2I中，示出了在固化工艺之后，顶部工具5从底部工具4脱离开的情况。在这里没有示出的其它工艺中，被固化和硬化的模塑层9从底部工具4中被去除掉，和第一承载层1和第二承载层6从具有其中嵌入了第一半导体芯片3和第二半导体芯片8的固化和硬化的模塑层9中去叠置。
在图3A-D中，示出了以半导体芯片模块的形式制造器件的不同实施例的横截面。所有的这些实施例示出了固化和硬化的模塑材料层9、第一半导体芯片3和第二半导体芯片8。在所有的这些实施例中，第一半导体芯片3和第二半导体芯片8分别具有主表面，接触垫3A和8A布置到该主表面上。同样在所有的这些实施例中，第一半导体芯片3的主表面与模塑材料层9的上表面齐平或者共面，和第二半导体芯片8的主表面与模塑材料层9的下表面齐平或者共面。
图3A示出了第一半导体芯片3和第二半导体芯片8以并排交替的方式布置的实施例。在该实施例中，该模塑材料层9相对薄，因为在模塑材料层9的横向位置处存在最大仅一个半导体芯片，即或者是第一半导体芯片3或者是第二半导体芯片8。
在图3B中，示出了第一导体芯片3和第二半导体芯片8彼此相对放置的实施例。在该实施例中，模塑材料层9相对厚，因为存在模塑材料层9的多个横向位置，其中两个半导体芯片即第一半导体芯片3和第二半导体芯片8直接相互堆叠。
在图3A和3B的实施例中，第一半导体芯片3的数目等于第二半导体芯片8的数目。在图3C中，示出了第一半导体芯片3的数目不同于第二半导体芯片8_1，8_2的数目的实施例。在一个实施例中，在图3C示出的实施例中，第二半导体芯片8_1，8_2的数目是第一半导体芯片3的数目的两倍。更具体的，在图3C的实施例中，两个第二半导体芯片8_1，8_2放置在第一半导体芯片3的每一个上面。
在图3D中，示出了半导体芯片模块的实施例与图3C的实施例相似。在图3D的实施例中，放置在第一半导体芯片3的每一个上面的两个第二半导体芯片8_1，8_2具有不同的垂直延伸。
图4示出了用于制造至少一个器件的方法的另一个实施例的流程图。该方法包括提供至少一个半导体芯片(S1)，提供至少一个元件(S2)，施加材料层到至少一个半导体芯片和至少一个元件上，该材料层包括第一表面和与该第一表面相对的第二表面，其中材料层的第一表面与至少一个半导体芯片的表面共面，并且材料层的第二表面与至少一个元件的表面共面(S1)。
在图5A-F中，示出了中间产品和器件的横截面图，表示图1，2A-I，3A-D和4中示出的其它实施例。
在图5A中，示出了半导体芯片模块20的形式的器件，其根据图1-4的实施例中示出的方法制造的。在下面，图5B-F示出了半导体芯片模块20的一部分的横截面图，其中该部分是半导体芯片封装，其在后面的工艺中从半导体芯片模块20中被切割掉。对于第一处理步骤，用粘附性箔片21覆盖半导体芯片模块20以便保护将不被处理的半导体芯片模块20的那个面。该半导体芯片模块20包括模塑层29，多个第一半导体芯片23和多个第二半导体芯片28，其中第一半导体芯片23的每一个直接与第二半导体芯片28的每一个相对放置。该第一半导体芯片23的每一个都包括两个第一接触垫23A，该第二半导体芯片28的每一个都包括两个第二接触垫28A。
在图5B-F中，示出了下面的处理：施加多个接触元件到模塑材料层29的一面、连接接触元件到第一或第二接触垫23A和28A中被选择的一个。
在图5B、5C中，示出了第一处理，其中电通路连接被形成为穿过材料层29。根据图5B，通过激光钻孔将通孔29A形成在材料层29中。通孔29A从材料层的下表面到达上表面。根据图5C，通孔29A被填充了导电材料，因此形成了电通路连接29B。这例如通过电镀工艺和/或溅射工艺来实现。可选择的，可以施加印刷工艺。作为其它可能性，导电墨水可以被填充到通孔中29A。
也可以在施加模塑材料层5到半导体芯片23和28之间之前，放置电通路连接。因此聚合物或者金属(例如铜)的导电柱、焊料球或栏或者其它导电材料可以被放置到半导体芯片23和28之间，例如通过在模塑之前将它们连接到承载层1或6之一。然后将通路连接连同半导体芯片23和28一起嵌入到模塑化合物。通过背面研磨通路连接的顶部，能够将其从模塑材料中被清除掉和暴露出，并且然后被用作在布置到模塑材料层5的任一侧上的多个半导体芯片之间的通路接连。
根据图5D，将电介质层24和26沉积到材料层29的下表面和上表面。通过使用旋转涂覆技术将电介质层24和26沉积到材料层29的下表面和上表面。在电介质层24和25中，在接触垫23A和28A以及电通路连接29B处形成开口。
在图5E中，示出了在电介质层24和25中的开口被填充导电材料的工艺之后的结构。在材料层29的下表面上，沉积再分配层27，该再分配层27包括再分配垫27A、27B。再分配垫27A、27B的每一个分别连接到第一半导体芯片23的多个接触垫23A之一。再分配垫27A、27B用作再分布接触垫28A的表面区域，使得外部接触元件30被连接，如后面将介绍的。在图5E中，示出了通过电通路连接29B和桥层31将再分配垫27A、27B连接到第二半导体芯片28的第二接触垫28A。示意性的形式仅仅出于简化的原因。实际上，第一接触垫23A必须连接到再分配垫，如原理上阐述的，但是它可以连接到再分配层27的其它再分配垫。
在图5F中，示出了施加焊料停止层或者焊料保护层32之后的结构。在施加焊料停止层32之后，在焊料停止层32中形成开口以使得对该再分配垫27A、27B进行开口。之后，将焊料球33填充到焊料停止层32的开口中。
注意，图5A的半导体芯片模块的其它部分以如上所述的相同的方式被制造。在最后的工艺中，半导体芯片模块20被分开为多个半导体芯片封装，例如图5F所示。
图6示出了制造半导体芯片组件的方法的实施例的流程图。该方法包括提供第一半导体芯片和第二半导体芯片(S1)，通过使用粘附层将第一半导体芯片附着到第二半导体芯片上(S2)。
在图7A和7B中，示出了制造半导体芯片组件的另一个实施例。图7A示出了第一半导体芯片40、粘附层41和第二半导体芯片42的横截面图。第一半导体芯片40包括在其上表面上的接触垫40A。将粘附层41施加到第一半导体芯片40的下表面上。第二半导体芯片42也包括在其上表面上的接触垫42A。该接触垫42A位于第二半导体芯片42的上表面的中心区域42_1的外部，使得将第一半导体芯片40和施加到该第一半导体芯片40的下表面的粘附层41被附着到第二半导体芯片42的上表面的中心区域42_1中。
图7B示出了制造半导体芯片组件50。
图8示出了半导体芯片封装的横截面图，其是例如根据参考图1-7概述的实施例的一个或者多个或者在这些实施例中公开的一个或者更多的特征来制造的。另外，如图8所示的半导体芯片封装60包括根据图6和7制造的两个半导体芯片组件。这两个半导体芯片组件分别用51和52来表示。第一半导体芯片组件51包括第一半导体芯片51_2和第二半导体芯片51_1。第二半导体芯片组件52包括第一半导体芯片52_2和第二半导体芯片52_1。
半导体芯片模块60包括材料层69，其中嵌入两个半导体芯片组件51和52，使得更小的半导体芯片51_2和52_2的表面分别与材料层69的多个表面之一齐平或者共面。半导体芯片的接触垫通过桥垫或者再分配垫连接到施加的接触元件63，如结合图5F所解释的那样。
图9A-F示出了中间产品和器件的横截面图，以及处理设备，用于说明制造至少一个器件的其它实施例。
根据该实施例，以根据图2A-I的实施例中相同的方式将半导体芯片3施加到第一成形元件4中，其中第一成形元件4可以是模塑装置的下模塑工具。然而，根据该实施例，将电接触元件18施加到第二成形元件5上。该电接触元件18是由任意导电材料制作的，例如金属(如铜)或者聚合物材料。它们可以具有柱形状、焊料球或栏的形状或者凸起的任何形状。
根据图9A，示出了与图2F中所示相类似的结构。将半导体芯片3施加到第一承载层1，该第一承载层1被施加到模塑装置的下模塑工具4。电接触元件18被施加到第二承载层16，该第二承载层16被施加到模塑装置的上模塑工具5。该第二承载层16可以由导电材料制作，其原因将在下面解释。然而，其也可以由任何其它材料制作，如图2A-I的实施例的承载层6的那样。
根据图9B，示出了与图2I中所示相类似的结构。模塑材料9沿着器件被分配并且上模塑工具5已经被除掉。
根据图9B，已经除掉了下模塑工具4和第一承载层1。
根据图9D，通孔9A已经形成在模塑材料层9中。该通孔9A例如可以通过激光钻孔来形成。
根据图9E，已经用导电材料填充了通孔9A以便形成通路导体9B。这例如可以通过电镀工艺来实现，其中该导电的第二承载层6能够被用作电极。然而也能够通过其它装置来填充通孔9A。例如，也可以使用导电墨水来填充通孔9A，以便形成通路导体9B，在这种情况中第二承载层6不必是导电层。
根据图9F，已经除掉了第二承载层16。随后，进行制造再分配层的标准工艺。在一个实施例中，在模塑材料层9的下表面上，半导体芯片3的接触垫3A连接到通路导体9B的底部部分。在模塑材料层9的上表面上，包括再分配垫或者迹线的再分配层可以被形成，并且这些再分配垫或者迹线例如可以连接到焊料球。可选择的，如果第二承载层16是导电层，那么该第二承载层16不必在附图9E的状态和附图9F的状态之间被除掉，相反该第二承载层16可以被制成为再分配层。
图10A和10B示出了中间产品和器件的横截面图以及处理设备，用于说明制造至少一个器件的另一个实施例。
根据该实施例，以根据图2A-I的实施例中相同的方式将半导体芯片3施加到第一成形元件4中，其中第一成形元件4可以是模塑装置的下模塑工具。然而，根据该实施例，将电接触元件38施加到第二成形元件5上。与图9A-F的实施例中的电接触元件18相比，该电接触元件38是相对长的接触元件。
根据图10A，示出了与图2F中所示相类似的结构。将半导体芯片3施加到第一承载层1，该第一承载层1被施加到模塑装置的下模塑工具4。电接触元件18被施加到第二承载层6，该第二承载层6被施加到模塑装置的上模塑工具5。该电接触元件38是由任意导电材料制作的，例如金属(如铜)或者聚合物材料。它们可以具有柱形状、焊料球或栏的形状或者凸起的任何形状。
根据图10B，上模塑工具5已经被除掉。如根据图9A-F的实施例那样，除掉第二承载层。然而，可选择的，如果第二承载层66是导电层，那么该第二承载层66不必在附图10B的状态之后被除掉，相反该第二承载层16可以被制成为再分配层。
电接触元件38被示为它们没有完全到达通过模塑材料层9，以便为了将它们连接到接触垫6A，必须将对准了电接触元件38的开口形成在模塑材料层9中。然而，该电接触元件38也可以具有与模塑材料层9的厚度相对应的长度，使得它们将到达通过模塑材料层9。
图11A-C示出了中间产品和器件的横截面图，用于说明制造至少一个器件的其它实施例。
根据该实施例，以根据图2A-I的实施例中相同的方式将半导体芯片3施加到第一成形元件4中，其中第一成形元件4可以是模塑装置的下模塑工具。然而，根据该实施例，将电接触元件48施加到第二成形元件5上。另外，导电层48已经被施加到第二承载层6上，例如在前面的实施例中描述的那样。
根据图11A，下模塑工具4和上模塑工具5已经被除掉，并且也可能已经将第一承载层1和第二承载层6除掉。
根据图11B，通孔9A形成在模塑材料层9中，如上面所述的那样。
根据图11C，导电层48被形成为包括再分配垫或者迹线48的再分配层，它们的至少一部分位于通孔9A的上面。预先的，通过例如回蚀刻将导电层49变薄。在处理导电层48为再分配层之前或者之后，使用导电材料来填充通孔9A，如上面所述的那样。
尽管这里已经详细说明和描述了具体的实施例，但是本领域的技术人员可以理解，在不脱离本发明的范围内，可以有多种替换方案和/或等价实施来替换这里所示和所描述的具体实施例。本发明意图覆盖这里所讨论的具体实施例的任何变形和修改。因此，本发明将只受到权利要求书和其等价物的限制。

Claims (25)

1.一种制造至少一个器件的方法，包括：
施加至少一个半导体芯片到第一成形元件上；
施加至少一个元件到第二成形元件上；
施加材料到该至少一个半导体芯片和该至少一个元件上。
2.根据权利要求1的方法，其中该元件来自由其它半导体芯片、通路元件、电阻器、线圈、层、金属层、箔片、金属箔片、铜箔片、引线框架、焊料球、夹具、接触元件、或接触垫构成的组。
3.根据权利要求1的方法，其中施加材料包括传递模塑或者压缩模塑。
4.根据权利要求1的方法，还包括：施加材料到该至少一个半导体芯片和该至少一个元件上是通过将该材料引入到由第一成形元件和第二成形元件形成的空腔中来实现的。
5.根据权利要求1的方法，还包括：施加材料到该至少一个半导体芯片和该至少一个元件上是通过将该材料压入在第一成形元件和第二成形元件之间来实现的。
6.一种制造至少一个器件的方法，包括：
提供至少一个半导体芯片；
提供至少一个元件；和
施加材料层到该至少一个半导体芯片和该至少一个元件上，该材料层包括第一表面和与该第一表面相对的第二表面，其中
该材料层的第一表面与该至少一个半导体芯片的表面共面，并且该材料层的第二表面与该至少一个元件的表面共面。
7.根据权利要求6的方法，还包括：该元件来自由其它半导体芯片、通路元件、电阻器、线圈、层、金属层、箔片、金属箔片、铜箔片、引线框架、焊料球、夹具、接触元件、或接触垫构成的组。
8.根据权利要求6的方法，其中施加材料层包括传递模塑或者压缩模塑。
9.根据权利要求8的方法，还包括：施加材料到该至少一个半导体芯片和该至少一个元件上是通过将该材料引入到由第一成形元件和第二成形元件形成的空腔中来实现的。
10.根据权利要求8的方法，还包括：施加材料到该至少一个半导体芯片和该至少一个元件上是通过将该材料压入在第一成形元件和第二成形元件之间来实现的。
11.一种半导体芯片封装，包括：
材料层，其包括第一表面和与该第一表面相对的第二表面；
由该材料层覆盖的第一半导体芯片，其中该第一半导体芯片的第一表面与该材料层的第一表面共面；和
由该材料层覆盖的第二半导体芯片，其中该第二半导体芯片的第一表面与该材料层的第二表面共面。
12.根据权利要求11的半导体芯片封装，包括：
其中该第一和第二半导体芯片包括多个接触垫；
该多个接触垫位于该第一和第二半导体芯片的第一表面处。
13.根据权利要求12的半导体芯片封装，包括：
其中多个接触元件被提供到所述材料层的一个侧面上并且连接到该多个接触垫中被选择的接触垫。
14.根据权利要求13的半导体芯片封装，包括：
其中在材料层的表面中的一个或两个上形成再分配层；和
该再分配层包括多个再分配垫，该再分配层连接在多个第一或第二接触垫中的被选择的接触垫和多个接触元件中的被选择的接触元件之间。
15.根据权利要求11的半导体芯片封装，还包括穿通该材料层形成的电通路连接。
16.根据权利要求14的半导体芯片封装，还包括：
该电通路连接将位于材料层的与其一侧相对的另一侧上的多个接触垫电连接到再分配层的再分配垫中被选择的再分配垫。
17.一种半导体芯片封装，包括：
材料层；
由该材料层覆盖的第一半导体芯片，其包括多个第一接触垫；
由该材料层覆盖的第二半导体芯片，其包括多个第二接触垫；
在该材料层的一侧上提供的多个接触元件，其分别连接到多个第一或第二接触垫中被选择的接触垫。
18.根据权利要求17的半导体芯片封装，其中该材料层包括第一表面和与该第一表面相对的第二表面，其中该第一半导体芯片的第一表面与该材料层的第一表面共面，和该第二半导体芯片的第二表面与该材料层的第二表面共面。
19.根据权利要求18的半导体芯片封装，其中多个接触元件被提供到所述材料层的一个侧面上并且连接到该多个接触垫中被选择的接触垫。
20.根据权利要求19的半导体芯片封装，包括：
其中在材料层的表面中的一个或两个上形成再分配层；和
该再分配层包括多个再分配垫，该再分配层连接在多个第一或第二接触垫中的被选择的接触垫和多个接触元件中的被选择的接触元件之间。
21.根据权利要求17的半导体芯片封装，还包括穿通材料层形成的电通路连接。
22.根据权利要求20的半导体芯片封装，还包括：
该电通路连接将位于材料层的与其一侧相对的另一侧上的多个接触垫电连接到再分配层的再分配垫中被选择的再分配垫。
23.一种半导体芯片组件，包括：
第一半导体芯片，
第二半导体芯片，
其中该第一半导体芯片和第二半导体芯片通过使用粘附层而彼此粘附。
24.根据权利要求23的半导体芯片组件，其中第一和第二半导体芯片的每一个都包括主表面和背表面，多个接触垫在该主表面上；和
第一半导体芯片的背表面粘附到第二半导体芯片的主表面上。
25.根据权利要求23的半导体芯片组件，其中第一半导体芯片小于第二半导体芯片。
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