CN101401202A - 选择性沉积 - Google Patents
选择性沉积 Download PDFInfo
- Publication number
- CN101401202A CN101401202A CNA2007800091259A CN200780009125A CN101401202A CN 101401202 A CN101401202 A CN 101401202A CN A2007800091259 A CNA2007800091259 A CN A2007800091259A CN 200780009125 A CN200780009125 A CN 200780009125A CN 101401202 A CN101401202 A CN 101401202A
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- CN
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- Prior art keywords
- silicon
- deposition
- substrates
- etching
- mentioned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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Abstract
一种在基板表面上外延形成含硅材料的方法,通过调整处理反应室温度及压力来将含卤素气体用作蚀刻气体以及载气。将氯化氢用作该含卤素气体是有利的,因为可藉由调整该反应室压力轻易地将氯化氢从载气转换为蚀刻气体。
Description
发明背景
发明领域
本发明的实施例涉及电子生产工艺和器件的领域,尤其涉及在形成电子器件时沉积含硅薄膜的方法。
现有技术描述
在生产较小的晶体管时,制造超浅源极/漏极结变得日益困难。次100纳米CMOS(互补式金属氧化物半导体)器件需要深度小于30纳米的结。选择性外延沉积通常用来在这些结中形成含硅材料(例如硅、锗化硅和碳化硅)的外延层。选择性外延沉积使外延层可以在硅沟渠(siliconmoat)上而不在介电区域上成长。选择性外延可用在半导体器件中,例如升高的源极/漏极、源极/漏极延伸、接触插塞(contact plug)或双极器件的基底层沉积。
选择性外延处理包含沉积反应和蚀刻反应。沉积及蚀刻反应以相对不同的反应速率在外延层和多晶层上同时发生。在沉积处理期间,外延层在一单晶表面上形成,同时多晶层沉积在至少一第二层上,例如现有的多晶层或非晶层。但是,所沉积的多晶层以比该外延层快的速率蚀刻。因此,藉由改变蚀刻气体浓度,净选择处理会造成外延材料的沉积以及有限(或没有)多晶材料的沉积。例如,选择性外延处理可造成含硅材料的外延层形成在单晶硅表面上,而没有沉积遗留在隔离片上。
含硅材料的选择性外延沉积在升高的源极/漏极和源极/漏极延伸特征形成期间已变成一种有用技术,例如,在含硅MOSFET(金属氧化物半导体场效晶体管)器件形成期间。源极/漏极延伸特征藉由蚀刻硅表面来制造,以制出凹陷的源极/漏极特征并且随后以选择性成长的外延层填充蚀刻表面,例如锗化硅(SiGe)材料。选择性外延使原位掺杂能够几乎完全活化掺杂剂,因此可省略后退火(post annealing)处理。所以,可利用硅蚀刻和选择性外延精确地限定结的深度。另一方面,超浅源极/漏极结会不可避免地造成串联电阻的增加。此外,硅化物形成期间的结消耗(junction consumption)更进一步地增加串联电阻。为了补偿结消耗,将升高的源极/漏极外延地且选择性地成长在该结上。通常,该升高的源极/漏极是未掺杂的硅。
但是,目前的选择性外延处理有一些缺点。为了在当前外延处理期间保持选择性,必须在整个沉积处理期间控制并调整前驱物化学浓度以及反应温度。如果没有提供足够的硅前驱物,则蚀刻反应可能会主导而使整个处理速度减缓。此外,可能会发生有害的基板特征过蚀刻。如果没有提供足够的蚀刻剂前驱物,则沉积反应可能会主导从而降低在基板表面上形成单晶和多晶材料的选择性。另外,目前的选择性外延处理通常需要高反应温度,例如约800℃、1000℃或更高。因为热预算因素及可能发生的无法控制的基板表面的氮化反应,在生产过程期间使用此高温是不合需要的。
因此,需要一种用来选择性地且外延地沉积具有任选掺杂剂的硅和含硅化合物的工艺。此外,该工艺应该是多方适用的,以形成具有不同元素浓度的含硅化合物,同时具有快速的沉积速率。
发明概要
本发明提供一种在基板上外延沉积一个层的方法。一种在基板表面上外延形成含硅材料的方法,通过调整处理反应室温度及压力来将含卤素气体用作蚀刻气体以及载气。使将氯化氢用作该含卤素气体是有利的,因为可藉由调整该反应室压力轻易地将氯化氢从载气转换为蚀刻气体。
在第一实施例中,公开一种在基板表面上外延形成含硅材料的方法。该方法包含:将具有单晶表面及至少一第二表面的基板置于处理反应室内。该第二表面可以是非晶表面、多晶表面或其组合。将该基板暴露在沉积气体下以在该单晶表面上沉积一外延层,并且在该第二表面上沉积一多晶层。该沉积气体具有硅源及包含一含卤素化合物的载气。随后将该基板暴露在一蚀刻气体中以蚀刻该多晶层和该外延层。该多晶层的蚀刻速率比该外延层快。
根据该第一实施例的一方面,该含卤素化合物包含氯化氢,并且在沉积期间氯化氢被用作载气以及蚀刻气体。
根据该第一实施例的另一方面,在沉积期间含卤素气体被用作载气,但使用含有氯化的碳氢化合物的蚀刻气体。
在第二实施例中,公开一种在置于处理反应室内的基板上外延形成含硅材料的方法。该基板包含单晶表面,以及选自非晶表面、多晶表面及其组合的第二表面。该方法包含将进入该处理反应室的含卤素气体流控制在第一流速,以在该单晶表面上沉积一外延层并且在该第二表面上沉积一多晶层,以及将进入该处理反应室的含卤素气体流控制在第二流速,以蚀刻该多晶层和该外延层。
附图简述
因此可藉由参考实施例通过在前面简短概述过的本发明的更具体描述来详细了解上述本发明的特征,其中某些实施例在附图中示出。但是需要注意的是,附图只示出本发明的一般实施例,因此不应被认为是对其范围的限制,因为本发明可允许其它等效实施例。
图1是描述在此所述的一实施例中选择性地且外延地沉积含硅材料的过程的流程图;
图2A-2E示出在MOSFET内的源极/漏极延伸器件的制造技术的简要示图;
图3A-C标出若干器件,其含有藉由应用在此所述的实施例而选择性地及外延地沉积的含硅层;
图4是描述在此所述的另一实施例中选择性地且外延地沉积含硅材料的过程的流程图;以及
图5A-5C示出氟化氢流速、总压力、及源气体流速相对于时间的曲线图。
详细描述
本发明的实施例提供在电子器件制造期间,在基板的单晶表面上选择性地且外延地沉积含硅材料的过程。将含有单晶表面(例如硅或锗化硅)及至少一第二表面,例如非晶表面及/或多晶表面(例如氧化物或氮化物),的经图案化的基板暴露在外延处理下,以在该单晶表面上形成一外延层,同时在这些第二表面上形成有限的多晶层或不形成多晶层。该外延处理,也称为交替气体供应(AGS)处理,包含重复沉积处理和蚀刻处理所组成的周期直到长成预期厚度的外延层为止。
该沉积处理包含将该基板表面暴露在含有至少一硅源和一载气的沉积气体中。该沉积气体也可包含锗源或碳源,以及掺杂剂源。在沉积处理期间,外延层被形成在该基板的单晶表面上,而多晶层则形成在第二表面上,例如非晶及/或多晶表面。接着,将该基板暴露在一蚀刻气体中。该蚀刻气体包含载气和蚀刻剂,例如氯气或氢气。该蚀刻气体去除沉积处理期间沉积的含硅材料。在蚀刻处理期间,该多晶层以比该外延层快的速率移除。因此,该沉积和蚀刻处理的净效果形成在单晶表面上外延成长的含硅材料,同时最小化多晶含硅材料在这些第二表面上的成长(若有的话)。可按需重复该沉积和蚀刻处理周期,以得到预期厚度的含硅材料。可利用本发明的实施例沉积的含硅材料包含硅、锗化硅、碳化硅、碳化硅锗、及其掺杂剂变体。
一般来说,沉积处理可在比蚀刻反应低的温度下执行,因为蚀刻剂通常需要高温来活化。例如,硅烷可以在约500℃或更低的温度下热分解而沉积硅,而氯化氢需要约700℃或更高的活化温度方可发挥有效蚀刻剂的作用。因此,若在AGS处理期间使用氯化氢,则整个处理温度会被活化该蚀刻剂所需的较高温度支配。
在AGS处理的一个示例中,在该沉积及蚀刻处理期间将惰性气体,例如钝气或氮气,用作载气,取代传统载气,例如氢气。在AGS处理期间使用惰性载气有若干好处。其一是,惰性载气可增加含硅材料的沉积速率。虽然在沉积处理期间可将氢气用作载气,但是氢气具有吸附该基板或与其反应而形成氢终结端面(hydrogen-terminated surfaces)的倾向。氢终结端面对外延成长的反应比裸硅表面慢很多。因此,惰性载气的使用会藉由不会不利地影响沉积反应而增加沉积速率。
发现可将含卤素气体用作载气。在非常特殊的情况下,该含卤素气体不会蚀刻该材料。该含卤素气体会起惰性气体的作用。将该含卤素气体用作载气的好处在于该含卤素气体可经调整而在该蚀刻阶段期间用作蚀刻剂或在该沉积阶段期间用作惰性载气。该含卤素气体的任一种用法的调整由温度及压力控制。藉由将该含卤素气体保持在蚀刻阈值之下,该含卤素气体会起有效载气的作用。该蚀刻阈值取决于所使用的特定含卤素气体而改变。
可使用双原子卤素,但其需要在低处理反应室温度(即,低于约550℃)以及非常低的浓度下使用。使用双原子卤素及含卤素气体的混合物是可能的。较佳地,该含卤素气体选自氯化氢、溴化氢、及碘化氢,且氯化氢是最佳的。可添加微量氯气至氯化氢内以增加蚀刻阶段期间氯化氢的反应性。可添加微量的氢气或氮气或任何惰性气体,例如氩气或氦气,以控制沉积阶段氯化氢的反应性。这些具体参数包含介于约500℃和约650℃之间的处理反应室操作温度,以及约1托至约100托的处理反应室操作压力。使用氯化氢来取代氯气有若干优点。氯化氢不会跟氯气一样强力攻击成长中的薄膜。氯化氢更选择性地蚀刻。相对于氯气,使用氯化氢所形成的薄膜有较少缺陷。
在处理反应室沉积温度下(即,介于约500℃和约650℃之间),氯化氢蚀刻效率通常会大幅度降低。因此,就500℃-650℃的处理反应室沉积温度而言,氯化氢起惰性气体的作用。当在这些低处理反应室温度下操作时,氯化氢不会有效地蚀刻。要使用氯化氢在这些低处理反应室温度下蚀刻,必须增加压力。
藉由在低流速(即,约60至约600sccm)及高流速(即,约2,000至约20,000sccm)之间调制氯化氢流,可达到交替的沉积/蚀刻循环。该沉积步骤是氯化氢流速低的无效率的蚀刻,或成长步骤。有效的蚀刻步骤在高氯化氢流速下发生。藉由调制流速,高压蚀刻在抽吸速度极少改变的情况下在低压沉积步骤之间进行。该压力控制并非极大的负担。图5A-5C示出氯化氢流速、总反应室压力、及源气体流相对于时间的比较。源气体在沉积阶段期间提供给该反应室。氯化氢气体被持续供应,但在沉积阶段期间,以较低流速供应氯化氢(即,约60至约600sccm)。沉积阶段期间的总反应室压力约1至约100托。沉积阶段期间可能发生小量蚀刻,但这会是最小量的。在蚀刻阶段期间,关闭该源气体并且增加氯化氢气流(即,约2,000至约20,000sccm)。总反应室压力被增加至约30至约100托。在蚀刻阶段期间,不会发生沉积。沉积阶段及蚀刻阶段的持续时间约相等。沉积阶段持续约5至约25秒,而蚀刻阶段持续约10至约30秒。该源气体可含有硅、锗、碳、及其组合。
有时候,在低反应室沉积温度下、但也在低反应室压力下(即,低于约50托)运作是较佳的(即,约500℃至约650℃)。但是,在低压下,氯化氢不会有效蚀刻。在低温及低压下添加氯气并不是一个选择,因为氯气太具侵蚀性。氯化的碳氢化合物是一个具吸引力的替代方案。
根据氯化的碳氢化合物,了解到其包含一含C-Cl键的碳氢化合物。示例性的氯化的碳氢化合物的示例包含作为示例的氯烷(即,氯甲烷、二氯甲烷、氯仿、四氯化碳、氯乙烷等)、氯烯烃(chloroalkene)、氯取代的苯基、以及氯炔烃(chloroalkyne)。
为了使氯化的碳氢化合物可有效蚀刻硅基薄膜,该C-Cl键强度应比该Si-CI键强度低,因此氯会是取代型而非填隙型(interstitial)。结合氯的碳氢化合物的性质决定可得的氯的键合强度。该氯化的碳氢化合物可与任何硅和碳源气体同时(即,共流)或交替(即,循环的沉积/蚀刻组合)使用。该氯化的碳氢化合物可在任何处理反应室温度或压力下使用。该氯化的碳氢化合物可以是气体、液体、或固体,但较佳地具有高的蒸汽压。此外,该氯化的碳氢化合物应具有高纯度。
在上面示例中,在氯化氢于沉积阶段期间被用作惰性载气的处理中,该氯化的碳氢化合物被用作蚀刻剂。但是,在沉积阶段期间,该氯化的碳氢化合物可与任何惰性载气或背景气体组合用作蚀刻剂。该氯化的碳氢化合物使蚀刻阶段可在约50托或更低的处理反应室压力下进行。
在本申请中,“含硅“材料、化合物、薄膜或层一词应被理解为包含一组合,其至少含有硅并且可含有锗、碳、硼、砷、磷、镓及/或铝。其它元素,例如金属、卤素或氢可被结合在含硅材料、化合物、薄膜或层中,通常是ppm等级的浓度。含硅材料的化合物或合金可由缩写表示,例如Si表示硅、SiGe表示锗化硅、SiC表示碳化硅、而SiGeC表示碳化硅锗。缩写并不以计量关系表示出化学式,也不表示出含硅材料的任何特定还原/氧化状态。
图1示出用来沉积含硅层的外延处理100的一示例。处理100包含用来将图案化的基板加载到处理反应室并将处理反应室的状态调整至预期温度和压力的步骤110。步骤120提供沉积处理,以在该基板的单晶表面上形成外延层,同时在该基板的非晶及/或多晶表面上形成多晶层。在步骤130期间,该沉积处理终止。步骤140提供一蚀刻处理,以蚀刻该基板表面。较佳地,该多晶层以比该外延层快的速率蚀刻。该蚀刻步骤最小化或完全移除该多晶层,同时只移除最低限度的外延层部分。在步骤150期间,该蚀刻处理终止。该外延层及该多晶层(若存在的话),的厚度在步骤160期间确定。若达到预定的外延层或多晶层厚度,则外延处理100在步骤170终止。但是,若没有达到预定厚度,则重复步骤120-160作为一循环直到达到预定厚度为止。
在步骤110期间将一图案化的基板加载到处理反应室中。图案化的基板是含有形成在该基板表面内或在其上的电子特征的基板。该图案化基板通常含有单晶表面和至少一非单晶的第二表面,例如多晶或非晶表面。单晶表面包含裸晶基板或通常由例如硅、锗化硅或碳化硅的材料组成的沉积单晶层。多晶或非晶表面可包含介电材料,例如氧化物或氮化物,具体是氧化硅或氮化硅,以及非晶硅表面。
外延处理100由在步骤110期间将含有该图案化基板的处理反应室调整至预定温度和压力开始。温度适合特定的执行处理。在外延处理100期间,处理反应室保持在固定温度下。但是,某些步骤可在不同温度下执行。处理反应室保持在从约250℃至约1,000℃范围内的温度下,较佳地,为约500℃至约800℃,并且更佳地,为约550℃至约750℃。执行外延处理100的适当温度可取决于在步骤120和140期间用来沉积及/或蚀刻该含硅材料的特定前驱物。当将氯化氢用作载气及蚀刻气体两者时,该处理反应室压力在蚀刻步骤期间限定出的高压以及沉积步骤期间限定出的低压之间变换。
沉积处理在步骤120期间执行。图案化基板被暴露在沉积气体中以在该单晶表面上形成外延层,同时在该第二表面上形成多晶层。该基板被暴露在该沉积气体中约0.5秒至约30秒的时段,较佳地,为约5秒至约25秒。该沉积处理的具体暴露时间关于在步骤140中蚀刻处理期间的暴露时间,以及在处理中所使用的特定前驱物和温度来决定。该基板被暴露在沉积气体中足够长的时间以形成最厚厚度的外延层,同时形成最薄厚度的多晶层,其可在随后的步骤140期间轻易地蚀刻去除。
该沉积气体至少包含硅源和载气,并且可包含至少一种第二元素源,例如锗源及/或碳源。此外,该沉积气体可进一步包含掺杂剂化合物以提供掺杂剂源,例如硼、砷、磷、镓及/或铝。
硅源通常以范围从每分钟约5标准立方厘米(sccm)至约500sccm内的速率供给至该处理反应室中,较佳地,为约10sccm至约300sccm,并且更佳地,为约50sccm至约200sccm,例如,约100sccm。可用于沉积气体中以沉积含硅化合物的硅源包含硅烷、卤化硅烷和有机硅烷。硅烷包含硅烷(SiH4)及实验式为SixH(2X+2)的较长链硅烷,例如二硅烷(Si2H6)、三硅烷(Si3H8)、以及四硅烷(Si4H10)等。卤化硅烷包含实验式为X’ySixH(2X+2-y)的化合物,其中X’=氟、氯、溴或碘,例如六氯二硅烷(Si2Cl6)、四氯硅烷(SiCl4)、二氯硅烷(Cl2SiH2)及三氯硅烷(Cl3SiH)。有机硅烷包含实验式为RySixH(2X+2-y)的化合物,其中R=甲基、乙基、丙基或丁基,例如甲基硅烷((CH3)SiH3)、二甲基硅烷((CH3)2SiH2)、乙基硅烷((CH3CH2)SiH3)、甲基二硅烷((CH3)Si2H5)、二甲基二硅烷((CH3)2Si2H4)及六甲基二硅烷((CH3)6Si2)。已发现有机硅烷化合物在将碳结合到沉积的含硅化合物内的实施例中是有利的硅源和碳源。较佳的硅源包含硅烷、二氯硅烷和二硅烷。
硅源通常连同载气一起供给至该处理反应室内。载气流速为从约60至约600sccm。载气可包含氮气(N2)、氢气(H2)、氩气、氦气及其组合。氯化氢是较佳的载气。可基于外延处理100期间使用的前驱物及/或处理温度来选择载气。通常载气在每一个步骤110-150期间是相同的。但是,某些实施例可在特定步骤中使用不同载气。氯化氢可在步骤120与该硅源以及在步骤140与该蚀刻剂一起用作载气。
在步骤120期间使用的沉积气体也可包含至少一种第二元素源,例如锗源及/或碳源。锗源可连同硅源和载气一起加入该处理反应室中以形成含硅化合物,例如锗化硅材料。通常以约0.1sccm至约20sccm范围内的速率供给锗源至该处理反应室中,较佳地,为约0.5sccm至约10sccm,并且更佳地,为约1sccm至约5sccm,例如,约2sccm。可用来沉积含硅化合物的锗源包含锗烷(GeH4)、较长链的锗烷及有机锗烷。较长链的锗烷包含实验式为GexH(2X+2)的化合物,例如二锗烷(Ge2H6)、三锗烷(Ge3H8)、以及四锗烷(Si4H10)等。有机锗烷包含例如甲基锗烷((CH3)GeH3)、二甲基锗烷((CH3)2GeH2)、乙基锗烷((CH3CH2)GeH3)、甲基二锗烷((CH3)Ge2H5)、二甲基二锗烷((CH3)2Ge2H4)及六甲基二锗烷((CH3)6Ge2)的化合物。已发现锗烷和有机锗烷化合物在将锗和碳结合到沉积的含硅化合物内的实施例中,也就是锗化硅和碳化硅锗化合物,是有利的锗源和碳源。外延层的锗浓度范围从约1原子百分比(at%)至约30at%,例如,约20at%。锗浓度可在外延层中逐渐变化,较佳地变化是在该外延层下半部具有比该外延层上半部高的浓度。
或者,可在步骤120期间连同硅源和载气一起添加碳源至该处理反应室中以形成含硅化合物,例如硅碳材料。通常以约0.1sccm至约20sccm范围内的速率供给碳源至该处理反应室中,较佳地,为约0.5sccm至约10sccm,并且更佳地,为约1sccm至约5sccm,例如,约2sccm。可用来沉积含硅化合物的碳源包含有机硅烷、烷类、乙基、丙基和丁基的烯类及炔类。此种碳源包含甲基硅烷((CH3)SiH3)、二甲基硅烷((CH3)2SiH2)、乙基硅烷((CH3CH2)SiH3)、甲烷(CH4)、乙烯(C2H4)、乙炔(C2H2)、丙烷(C3H8)、丙烯(C3H6)、丁炔(C4H6)等。外延层的碳浓度范围从约200ppm至约5at%,较佳地,从约1at%至约3at%,例如1.5at%。在一实施例中,碳浓度可在外延层中逐渐变化,较佳的变化是在该外延层下半部具有比该外延层上半部高的浓度。或者,可在步骤120期间连同硅源和载气一起添加锗源及碳源两者进入该处理反应室中以形成含硅化合物,例如硅锗碳材料。
在步骤120期间所用的沉积气体可进一步包含至少一种掺杂剂化合物以提供元素掺杂剂源,例如硼、砷、磷、镓或铝。掺杂剂提供具有若干导电特性的沉积的含硅化合物,例如电子器件所需的在受到控制的及预期的路径中的具方向性的电子流。以特定掺杂剂掺杂含硅化合物薄膜以达到预期导电特性。在一实例中,该含硅化合物被掺杂为p型,例如藉由使用二硼烷以添加浓度范围约1015原子/立方厘米至约1021原子/立方厘米的硼。在一实例中,该p型掺杂剂的浓度至少是5×1019原子/立方厘米。在另一实例中,该p型掺杂剂在约1×1020原子/立方厘米至约2.5×1021原子/立方厘米范围内。在另一实例中,该含硅化合物被掺杂为n型,例如利用磷及/或砷掺杂至约1015原子/立方厘米至约1021原子/立方厘米的浓度范围内。
通常以约0.1sccm至约20sccm范围内的速率供给掺杂剂源至该处理反应室中,较佳地,为约0.5sccm至约10sccm,并且更佳地,为约1sccm至约5sccm,例如,约2sccm。可用作掺杂剂源的含硼掺杂剂包含硼烷和有机硼烷。硼烷包含硼烷、二硼烷(B2H6)、三硼烷、四硼烷和五硼烷,而烷基硼烷(alkylboranes)包含实验式为RxBH(3-x)的化合物,其中R=甲基、乙基、丙基或丁基,而x=1、2或3。烷基硼烷包含三甲基硼烷((CH3)3B)、二甲基硼烷((CH3)2BH)、三乙基硼烷((CH3CH2)3B)及二乙基硼烷((CH3CH2)2BH)。掺杂剂也可包含砷化氢(AsH3)、磷化氢(PH3)和烷基磷化氢,例如实验式为RxPH(3-x)者,其中R=甲基、乙基、丙基或丁基,而x=1、2或3。烷基磷化氢包含三甲基磷化氢((CH3)3P)、二甲基磷化氢((CH3)2PH)、三乙基磷化氢((CH3CH2)3P)及二乙基磷化氢((CH3CH2)2PH)。铝和镓掺杂剂源可包含烷化(alkylated)和/或卤化的衍生物,例如以实验式RxMX(3-x)描述地,其中M=铝或镓,R=甲基、乙基、丙基或丁基,X=氯或氟,而x=1、2或3。铝和镓掺杂剂源的示例包含三甲基铝(Me3Al)、三乙基铝(Et3Al)、二甲基氯化铝(Me2AlCl)、氯化铝(AlCl3)、三甲基镓(Me3Ga)三乙基镓(Et3Ga)、二甲基氯化镓(Me2GaCl)、以及氯化镓(GaCl3)。
在步骤130期间,沉积处理终止。在一示例中,可将处理反应室注满清洁气体或载气及/或可利用真空泵将该处理反应室排空。该清洁及/或排空处理去除过量的沉积气体、反应副产物和其它污染物。在另一示例中,一旦沉积处理终止,步骤140的蚀刻处理立即开始,而不需要清洁及/或排空该处理反应室。
步骤140的蚀刻处理从该基板表面去除在步骤120期间沉积的含硅材料。该蚀刻处理去除外延或单晶材料和非晶或多晶材料两者。沉积在基板表面上的多晶层(若有的话)以比外延层快的速率移除。蚀刻处理的持续时间与沉积处理的持续时间平衡以造成选择性形成在该基板预期区域上的外延层净沉积。因此,步骤120的沉积处理和步骤140的蚀刻处理的净效果在于形成选择且外延成长的含硅材料,同时最小化(若有的话)多晶含硅材料的成长。
在步骤140期间,将该基板暴露在蚀刻气体中范围约10秒至约30秒内的时段。就氯化的碳蚀刻剂而言,其可以约10sccm至约700sccm范围内的速率被提供至该处理反应室中,较佳地为约50sccm至约500sccm,并且更佳地为约100sccm至约400sccm,例如,约200sccm。就氯化氢而言,可以约2,000至约20,000sccm的速率供应。
该蚀刻处理在步骤150期间终止。在一示例中,可将处理反应室注满清洁气体或载气及/或可利用真空泵将该处理反应室排空。该清洁及/或排空处理去除过量的蚀刻气体、反应副产物和其它污染物。在另一示例中,一旦蚀刻处理终止,步骤160就立即开始,而不需要清洁及/或排空该处理反应室。
外延层和多晶层的厚度可在步骤160期间确定。若已达到预定厚度,则外延处理100在步骤170终止。但是,若未达到预定厚度,则重复步骤120-160作为一循环直到达到预定厚度为止。通常将外延层成长至约10埃至约2,000埃的厚度范围,较佳地,为约100埃至约1,500埃,并且更佳地,为约400埃至约1,200埃,例如,约800埃。通常将多晶层沉积至(若有的话)从一个原子层至约500埃的厚度范围内。该外延含硅层或该多晶含硅层的预期或预定厚度对于特定生产处理来说是独有的。在一示例中,该外延层可达到该预定厚度,但该多晶层却过厚。过量的多晶层可在略过步骤120和130的同时藉由重复步骤140-160进一步蚀刻。
在一示例中,如第2A-2E图所描绘地,将源极/漏极延伸形成在MOSFET器件中,其中该含硅层外延地且选择性地沉积在该基板表面上。图2A描绘藉由将离子植入基板230表面而形成的源极/漏极区域232。源极/漏极区域232的区段由形成在闸极氧化层235和隔离片234上的闸极236桥接。为了形成源极/漏极延伸,蚀刻并湿式清洁(wet-clean)一部分的源极/漏极区域232以产生一凹陷238,如图2B所示者。可藉由在蚀刻源极/漏极区域232的该部分之前先行沉积硬掩模来避免栅极236的蚀刻。
图2C示出在此描述的外延处理的一实施例,其中含硅外延层240和任选的多晶层242同时且选择性地沉积,但没有沉积在该隔离片234上。多晶层242藉由调整外延处理100的步骤120和140中的沉积和蚀刻处理可任选地形成在栅极236上。或者,多晶层242在外延层240沉积于该源极/漏极区域232上时持续从栅极236上蚀刻去除。
在另一示例中,含硅外延层240和多晶层242是含锗化硅层,其锗浓度范围从约1at%至约50at%,较佳地约24at%或更低。含有不同量的硅和锗的多个含锗化硅层可堆叠而形成元素浓度逐渐变化的含硅外延层240。例如,第一锗化硅层可被沉积为具有范围为约15at%至约25at%的锗浓度,而第二锗化硅层可经沉积为具有范围为约25at%至约35at%的锗浓度。
在又一示例中,含硅外延层240和多晶层242是含碳化硅层,其碳浓度范围从约200ppm至约5at%内,较佳地约3at%或更低,更佳地从约1at%至约2at%,例如,约1.5at%。在另一实施例中,含硅外延层240和多晶层242是含碳化硅锗层,其锗浓度范围从约1at%至约50at%,较佳地约24at%或更低,而碳浓度约在200ppm至约5at%,较佳地约3at%或更低,更佳地从约1at%至约2at%,例如,约1.5at%。
可以不同顺序沉积含硅、锗化硅、碳化硅或碳化硅锗的多个层,以在该含硅外延层240内形成逐渐变化的元素浓度。这些含硅层以掺杂剂掺杂(例如硼、砷、磷、镓或铝),其浓度范围从约1×1019原子/立方厘米至约2.5×1021原子/立方厘米,较佳地,为约5×1019原子/立方厘米至约2×1020原子/立方厘米。添加至含硅材料的个别层内的掺杂剂形成逐渐变化的掺杂剂。例如,含硅外延层240藉由沉积掺杂剂浓度(例如硼)在约5×1019原子/立方厘米至约1×1020原子/立方厘米范围内的第一含锗化硅层以及沉积掺杂剂浓度(例如硼)在约1×1020原子/立方厘米至约2×1020原子/立方厘米范围内的第二含锗化硅层来形成。
结合到含碳化硅层及含碳化硅锗层内的碳直接随着该含硅层的沉积定位在晶格的填隙位置中。该填隙碳含量约10at%或更少,较佳地低于约5at%并且更佳地从约1at%至约3at%,例如,约2at%。该含硅外延层240可被退火以将至少一部分(若非全部)的填隙碳结合到晶格的取代位置中。该退火处理可包含峰值退火(spike anneal),例如快速热退火(RTP)、激光退火或利用气体气氛的热退火,例如氧气、氮气、氢气、氩气、氦气或其组合。退火处理在约800℃至约1,200℃的温度下执行,较佳地从约1,050℃至约1,100℃。退火处理可紧接在含硅层沉积后或在基板将承受的各种其它处理步骤后发生。
在下一个步骤期间,图2D示出隔离片244,沉积在隔离片234上的氮化物隔离片(例如四氮化三硅)。隔离片244通常在不同反应室中利用CVD或ALD技术沉积。因此,将该基板从用来沉积含硅外延层240的处理反应室移出。在两个反应室间的传送期间,该基板可能会暴露在环境条件下,例如温度、压力或含有水和氧的大气。在沉积该隔离片244后,或执行其它半导体处理后(例如退火、沉积或植入),可在沉积升高层248前第二次将基板暴露在周围环境下。在一实施例中,在将该基板暴露在环境条件前先将没有或具有极微量锗(例如低于约5at%)的外延层(未示出)沉积在外延层240上,因为与从以大于约5at%的锗浓度形成的外延层上去除相比较,原氧化物可以较轻易地从含有最小量锗浓度的外延层上去除。
图2E描绘出另一示例,其中含有含硅材料的升高层248选择性地且外延地沉积在外延层240(例如掺杂的锗化硅)上。在沉积处理期间,多晶层242进一步在栅极236上成长、沉积或蚀刻去除。
在一较佳实施例中,升高层248是含有少量或没有锗或碳的外延沉积的硅。但是,在另一实施例中,升高层248确实含有锗和/或碳。例如,升高层248可具有约5at%或更少的锗。在另一实例中,升高层248可具有约2at%或更少的碳。也可用掺杂剂来掺杂该升高层248,例如硼、砷、磷、铝或镓。
在本处理的实施例内使用含硅化合物来沉积用于双极器件制造(例如基极、发射极、集电极、发射极触点)、双CMOS器件制造(例如基极、发射极、集电极、发射极触点)和CMOS器件制造(例如沟道、源极/漏极、源极/漏极延伸、升高的源极/漏极、基板、应变硅(strained silicon)、绝缘层上硅及触点插捎)的含硅层。处理的其它实施例示教含硅层的成长,其可用作栅极、基极触点、集电极触点、发射极触点、升高的源极/漏极及其它用途。
本处理在MOSFET和双极晶体管中沉积选择性的、外延的含硅层上是特别有用的,如图3A-3C所描绘。图3A-3B示出MOSFET器件上的外延成长的含硅化合物。该含硅化合物沉积在该器件的源极/漏极特征上。该含硅化合物粘贴于下层的晶格并从其成长出,并且在含硅化合物成长至预期厚度时保持此配置。图3A示出沉积为凹陷的源极/漏极层的含硅化合物,而图3B示出沉积为凹陷的源极/漏极层以及升高的源极/漏极层的含硅化合物。
该源极/漏极区312通过离子植入形成。该基板310被掺杂为n型,而该源极/漏极区312被掺杂为p型。含硅外延层313选择性地成长在该源极/漏极区312上及/或直接在基板310上。含硅外延层314根据此文中的各方面选择性地成长在该含硅层313上。栅极氧化层318桥接分段的含硅层313。栅极氧化层318由二氧化硅、氮氧化硅或氧化铪组成。部份围绕该栅极氧化层318的是隔离片316,其通常是一绝缘材料,例如氮化物/氧化物叠层(例如四氮化三硅/二氧化硅/四氮化三硅)。栅极层322(例如多晶硅)可沿着垂直侧具有一保护层319,例如二氧化硅,如第3A图所示。或者,栅极层322可具有隔离片316和沉积在两侧上的偏移层320(例如四氮化三硅)。
在另一示例中,图3C描绘沉积为双极晶体管的基极层的含硅外延层334。含硅外延层334利用本发明的各实施例选择性地成长。含硅外延层334被沉积在先前沉积于基板330上的n型集电极层332上。该晶体管进一步包含绝缘层333(例如二氧化硅或四氮化三硅)、接触层336(例如重掺杂的多晶硅)、偏移层338(例如四氮化三硅)、以及第二绝缘层340(例如二氧化硅或四氮化三硅)。
在另一实施例中,图4示出一外延处理400,其可用来选择性沉积含硅材料/层。外延处理400包含至少两个沉积处理,接着是蚀刻处理。该第一沉积处理包含一沉积气体,其含有一硅源,而该第二沉积处理包含一沉积气体,其含有一第二元素源,例如锗、碳或掺杂剂(例如硼、砷、磷、镓或铝)。在外延处理400中使用与外延处理100中所使用相似的工艺参数,例如温度、压力、流速、载气和前驱物。
外延处理400包含用来将图案化的基板加载到处理反应室并将处理反应室的状态调整至预期温度的步骤410。步骤420提供第一沉积处理,以在单晶表面上形成外延层,同时在第二表面上形成多晶层,例如非晶及/或多晶表面。该外延层和该多晶层由含有硅源的沉积气体形成。在步骤430期间,该第一沉积处理终止。步骤440提供第二沉积处理,以继续在单晶表面上成长该外延层,并且继续在该第二表面上形成该多晶层。该外延层和该多晶层藉由将该基板表面暴露在含有第二元素源的沉积气体中进一步成长。在步骤450期间,该第二沉积处理终止。步骤460提供蚀刻处理,以蚀刻暴露出的含硅层。该蚀刻处理最小化或完全移除该多晶层,同时因为每一种材料的移除速率而只移除最低限度的外延层部分。在步骤470期间,该蚀刻处理终止。该外延层及该多晶层,(若存在的话)的厚度在步骤480期间确定。若达到预定厚度,则外延处理400在步骤490终止。但是,若任一个层没有达到预定厚度,则重复步骤420-480作为一循环直到达到预定厚度为止。
外延处理400由在步骤410处将含有该图案化基板的处理反应室调整至预定温度开始。温度和压力适合特定的执行处理。在外延处理400期间,处理反应室被保持在一固定温度下。但是,某些步骤可在不同温度下执行。处理反应室温度被保持在约500℃至约650℃范围内。执行外延处理400的适当温度可取决于在步骤420-480期间用来沉积和/或蚀刻该含硅材料的特定前驱物。通常将该处理反应室保持在从约1托至约100托的压力下。
该第一沉积处理在步骤420期间执行。该图案化基板被暴露在第一沉积气体中以在该单晶表面上形成外延层,同时在这些第二表面上形成多晶层。该基板被暴露在该第一沉积气体中约5至约25秒的时段。该沉积处理的具体暴露时间关于在步骤460中蚀刻处理期间的暴露时间,以及在处理中所使用的特定前驱物和温度来确定。该基板被暴露在该第一沉积气体中足够长的时间以形成最厚厚度的外延层,同时形成最薄厚度的多晶层,其可在随后的步骤460期间轻易蚀刻去除。
该第一沉积气体至少包含一硅源和一载气。该第一沉积气体也可包含第二元素源及/或掺杂剂化合物,但较佳地,该第二元素源及该掺杂剂化合物在该第二沉积气体中。因此,在一方面中,该第一沉积气体可包含硅源、第二元素源和掺杂剂源。在另一方面中,该第一沉积气体可包含硅源和第二元素源。在又一方面中,该第一沉积气体可包含硅源和掺杂剂源。在另一实施例中,该第一沉积气体也可包含至少一种蚀刻剂,例如氯化氢或氯气。
硅源通常以范围约5sccm至约500sccm内的速率供给至该处理反应室中,较佳地为约10sccm至约300sccm,并且更佳地为约50sccm至约200sccm,例如,约100sccm。较佳的硅源包含硅烷、二氯硅烷和二硅烷。
硅源通常是在一载气中供给至该处理反应室内的。载气流速为约60至约600sccm。载气可包含氮气(N2)、氢气(H2)、氩气、氦气、氯化氢及其组合。氯化氢是较佳的载气,因为其具有在特定条件下用作为蚀刻剂或惰性气体的能力。
在步骤430期间,该第一沉积处理终止。在一示例中,可将处理反应室注满清洁气体或载气及/或可利用真空泵将该处理反应室排空。该清洁及/或排空处理去除过量的沉积气体、反应副产物和其它污染物。在另一示例中,一旦第一沉积处理终止,步骤440的第二沉积处理就立即开始,而不需要清洁及/或排空该处理反应室。
在步骤440期间使用的沉积气体含有载气和至少一种第二元素源,例如锗源、碳源及/或掺杂剂化合物。或者,硅源可包含在该第二沉积气体中。该第二元素源连同该载气一起被添加至该处理反应室中,以继续步骤420期间沉积的含硅化合物的成长。这些含硅化合物可具有由该特定第二元素源和该第二元素源的浓度控制的不同成分。第二元素源通常以约0.1sccm至约20sccm范围内的速率供给至该处理反应室中,较佳地为约0.5sccm至约10sccm,并且更佳地为约1sccm至约5sccm,例如,约2sccm。锗源、碳源和掺杂剂化合物从上面讨论的前驱物选出。
在步骤450期间,该第二沉积处理终止。在一示例中,可将处理反应室注满清洁气体或载气和/或可利用真空泵将该处理反应室排空。该清洁和/或排空处理去除过量的沉积气体、反应副产物和其它污染物。在另一示例中,一旦第二沉积处理终止,步骤460的蚀刻处理就立即开始,而不需要清洁和/或排空该处理反应室。
步骤460的蚀刻处理从该基板表面去除在步骤420和440期间沉积的材料。该蚀刻处理去除外延或单晶材料和非晶和/或多晶材料两者。沉积在基板表面上的多晶层(若有的话)以比外延层快的速率移除。蚀刻处理的持续时间与两个沉积处理的持续时间平衡。因此,步骤420和440的沉积处理和步骤460的蚀刻处理的净效果在于形成选择性且外延成长的含硅材料,同时最小化(若有的话)多晶含硅材料的成长。
在步骤460期间,将该基板暴露在蚀刻气体中范围约10秒至约30秒的时段。
该蚀刻处理在步骤470期间终止。在一示例中,可将处理反应室注满清洁气体或载气和/或可利用真空泵将该处理反应室排空。该清洁和/或排空处理去除过量的蚀刻气体、反应副产物和其它污染物。在另一示例中,一旦蚀刻处理终止,步骤480就立即开始,而不需要清洁和/或排空该处理反应室。
外延层和多晶层的厚度可在步骤480期间确定。若已达到预定厚度,则外延处理400在步骤490终止。但是,若未达到预定厚度,则重复步骤420-480作为一循环直到达到预定厚度为止。通常将外延层成长至约10埃至约2,000埃范围的厚度,较佳地为约100埃至约1,500埃,并且更佳地为约400埃至约1,200埃,例如,约800埃。通常将多晶层沉积至(若有的话)从一个原子层至约500埃范围内的厚度。该外延含硅层或该多晶含硅层的预期或预定厚度对于特定生产工艺来说是独有的。在一示例中,该外延层可达到该预定厚度,但该多晶层却过厚。过量的多晶层可在略过步骤420和440的同时藉由重复步骤460-480进一步蚀刻。同样地,在其它示例中,可在进行外延处理400时个别地略过步骤420、440和460。藉由略过步骤420、440和460,元素浓度和所沉积的含硅材料厚度可受到控制。
本发明的实施例示教在各种基板上沉积含硅化合物的处理。可在其上使用本发明实施例的基板包含,但不限于,半导体晶圆,例如结晶硅(例如Si<100>和Si<111>)、氧化硅、锗化硅、掺杂或未掺杂的晶圆及图案化或未图案化的晶圆。基板具有各种几何形状(例如圆形、方形和矩形)及尺寸(例如外径200毫米、外径300毫米)。
在一实施例中,由在此所述处理所沉积的含硅化合物包含浓度范围为约0at%至约95at%的锗。在另一实施例中,锗浓度在约1at%至约30at%范围内,较佳地为约15at%至约30at%,例如,约20at%。含硅化合物也包含浓度范围约0at%至约5at%的碳。在其它方面中,碳浓度在约200ppm至约3at%的范围内,较佳地约1.5at%。
锗和/或碳的含硅化合物薄膜由本发明的各种处理制造,并且可具有不变的、分散的或逐渐变化的元素浓度。逐渐变化的锗化硅薄膜在美国专利No.6,770,134和美国专利申请S/N 10/014,466,公开为美国专利公开20020174827中揭示,两者皆转让给应用材料公司,并且在此藉由引用其全文的方式结合到本文中,以描述沉积逐渐变化的含硅化合物薄膜的方法。在一示例中,硅源(例如SiH4)及锗源(例如GeH4)用来选择性地且外延地沉积含锗化硅薄膜。在此示例中,硅源和锗源的比例可在成长逐渐变化的薄膜时改变,以提供对元素(例如硅和锗)浓度的控制。在另一示例中,硅源及碳源(例如CH3SiH3)用来选择性地且外延地沉积含碳化硅的薄膜。硅源和碳源的比例可在成长同质或逐渐变化的薄膜时改变,以提供对元素浓度的控制。在另一示例中,硅源、锗源和碳源用来选择性地且外延地沉积含碳化硅锗薄膜。硅、锗和碳源的比例在成长同质或逐渐变化的薄膜时独立变化,以提供对元素浓度的控制。
由在此所述处理所形成的MOSFET器件可包含PMOS构件或NMOS构件。具有一p型沟道的该PMOS构件具有负责沟道传导(channel conduction)的空穴,而,具有一n型沟道的该NMOS构件具有负责沟道传导的电子。因此,例如,例如锗化硅的含硅材料可沉积在一凹陷区域中以形成一PMOS构件。在另一示例中,例如碳化硅的含硅薄膜可沉积在一凹陷区域中以形成一NMOS构件。在PMOS应用中使用锗化硅有几个原因。锗化硅材料会比单独的硅结合更多硼,因此可降低结电阻。此外,基板表面处的锗化硅/硅化物层界面具有比硅/硅化物界面低的肖特基势垒。
此外,外延成长在硅之上的锗化硅具有位于薄膜内部的压应力,因为锗化硅的晶格常数比硅大。该压应力在横向尺寸上传递以在PMOS沟道中产生压应变并且增加空穴的迁移率。对NMOS应用而言,碳化硅可用于这些凹陷区域中以在该沟道中产生张应力,因为碳化硅的晶格常数比硅的小。该张应力传递至该沟道内并且增加电子迁移率。因此,在一实施例中,第一含硅层被形成有第一晶格应变值,而第二含硅层则被形成有第二晶格应变值。例如,在基板表面上沉积厚度约50埃至约200埃的碳化硅层,接着在该碳化硅层上沉积厚度约150埃至约1,000埃的锗化硅层。该碳化硅层可以外延成长,且具有比外延成长在该碳化硅层上的锗化硅层低的应变。
在本文所述的实施例中,含硅化合物薄膜藉由化学气相沉积(CVD)处理选择性地且外延地沉积。化学气相沉积处理包含原子层沉积(ALD)处理和/或原子层外延(ALE)处理。化学气相沉积包含许多技术的使用,例如等离子体辅助CVD(PA-CVD)、原子层CVD(ALCVD)、有机金属或金属有机CVD(OMCVD或MOCVD)、激光辅助CVD(LA-CVD)、紫外光CVD(UV-CVD)、热钨丝CVD(HWCVD)、减压CVD(RP-CVD)、超高真空CVD(UHV-CVD)等。在一实施例中,较佳处理是使用热CVD来外延成长或沉积该含硅化合物,而该含硅化合物包含硅、锗化硅、碳化硅、碳化硅锗、其掺杂的变体或其组合。
本发明的处理可在ALE、CVD和ALD技术中已知的设备内执行。该设备可含有多个气线以使沉积气体和蚀刻气体在进入该处理反应室前维持分离。之后,使这些气体与加热的其上成长有含硅化合物薄膜的基板接触。可用来沉积含硅薄膜的硬件包含可从加州圣塔克拉拉的应用材料公司购得的Epi 系统和Poly 系统。一种ALD设备在2001年12月21号提出申请的转让给应用材料公司,并且标题为“ALD的气体输送设备及方法”(Gas Delivery Apparatus and Methods forALD)的美国专利申请S/N.10/032,284,公开为美国专利公开No.20030079686中揭示,并且在此藉由引用其全文的方式结合到本文中,以描述该设备。其它设备包含批次式(batch)、高温熔炉,如本领域中已知地。
本发明的处理可由一计算机可读取程序执行,其能够执行以进行上面讨论的方法。
虽然前述内容针对本发明的实施例,但本发明的其它及进一步的实施例可在不背离其基本范围下设计出,并且其范围由所附权利要求确定。
Claims (36)
1.一种在基板表面上外延形成含硅材料的方法,包括:
将具有单晶表面和第二表面的基板置于一处理反应室内,所述第二表面选自非晶表面、多晶表面及其组合所组成的组中;
将所述基板暴露在一沉积气体中,以在所述单晶表面上沉积外延层并在所述第二表面上沉积多晶层,其中所述沉积气体包含硅源和含有含卤素化合物的载气;以及
将所述基板暴露在一蚀刻气体中,以蚀刻所述多晶层和所述外延层。
2.如权利要求1所述的方法,其特征在于,上述的含卤素化合物包含氯化氢、溴化氢、碘化氢、或其组合。
3.如权利要求2所述的方法,其特征在于,上述的含卤素化合物包含氯化氢。
4.如权利要求1所述的方法,其特征在于,上述的沉积气体另外包含氯气、氢气、氮气、一惰性气体、或其组合。
5.如权利要求1所述的方法,其特征在于,上述的含卤素化合物在所述基板暴露在所述沉积气体中期间以约60sccm至约600sccm的速率流入所述反应室内。
6.如权利要求1所述的方法,其特征在于,上述的蚀刻气体包含所述含卤素化合物。
7.如权利要求6所述的方法,其特征在于,上述的含卤素气体交替以所述基板暴露在所述沉积气体中期间约60sccm至约600sccm的速率和所述基板暴露在所述蚀刻气体中期间约2,000sccm至约20,000sccm的速率流入所述反应室。
8.如权利要求1所述的方法,其特征在于,上述的反应室压力在所述基板暴露在一蚀刻气体中期间是约30托至约100托。
9.如权利要求1所述的方法,其特征在于,沉积循环包含重复使所述基板暴露在所述沉积气体及蚀刻气体中,以形成具有预定厚度的含硅材料。
10.如权利要求1所述的方法,其特征在于,所述沉积循环至少重复两次。
11.如权利要求1所述的方法,其特征在于,所述外延层包含选自锗化硅、碳化硅、碳化硅锗和其组合组成的组的材料。
12.如权利要求1所述的方法,其特征在于,所述处理反应室温度在所述基板暴露在一沉积气体中以及所述基板暴露在一蚀刻气体中期间是约500℃至约650℃。
13.一种在基板表面上外延形成含硅材料的方法,包括:
将具有单晶表面和第二表面的基板置于一处理反应室内,所述第二表面选自非晶表面、多晶表面及其组合所组成的群组中;
将所述基板暴露在一沉积气体中,以在所述单晶表面上沉积外延层并在所述第二表面上沉积多晶层,其中所述沉积气体含有硅源和载气;以及
在低于约650℃的处理反应室温度下将所述基板暴露在氯化的碳氢化合物蚀刻气体中,以蚀刻所述多晶层和所述外延层。
14.如权利要求13所述的方法,其特征在于,上述的载气包含一含卤素化合物。
15.如权利要求14所述的方法,其特征在于,上述的含卤素化合物包含氯化氢、溴化氢、碘化氢、或其组合。
16.如权利要求15所述的方法,其特征在于,上述的含卤素化合物包含氯化氢。
17.如权利要求13所述的方法,其特征在于,上述的氯化的碳氢化合物包含氯甲烷、二氯甲烷、氯仿、四氯化碳、氯乙烷、氯烯、或其组合。
18.如权利要求13所述的方法,其特征在于,上述的氯化的碳氢化合物与所述沉积气体同时流入所述反应室。
19.如权利要求13所述的方法,其特征在于,上述的氯化的碳氢化合物与所述沉积气体交替流入所述反应室。
20.如权利要求13所述的方法,其特征在于,上述的将所述基板暴露在所述蚀刻气体中在约50托或更低的处理反应室压力下进行。
21.如权利要求13所述的方法,其特征在于,沉积循环包含重复使所述基板暴露在所述沉积气体及蚀刻气体中,以形成具有预定厚度的含硅材料。
22.如权利要求21所述的方法,其特征在于,上述的沉积循环至少重复两次。
23.如权利要求13所述的方法,其特征在于,所述外延层包含一选自锗化硅、碳化硅、碳化硅锗和其组合所组成的组的材料。
24.一种在基板表面上外延形成含硅材料的方法,包括:
将所述基板暴露在一沉积气体中,其中所述沉积气体包含硅源以及作为载气的氯化氢;以及
使用氯化氢作为蚀刻气体来进行蚀刻。
25.如权利要求24所述的方法,其特征在于,上述的沉积气体另外包含氯气、氢气、氮气、一惰性气体、或其组合。
26.如权利要求24所述的方法,其特征在于,所述氯化氢在所述基板暴露在所述沉积气体中期间以约60sccm至约600sccm的速率流入所述反应室内。
27.如权利要求24所述的方法,其特征在于,所述氯化氢在所述蚀刻期间以约2,000sccm至约20,000sccm的速率流入所述反应室内。
28.如权利要求24所述的方法,其特征在于,上述的氯化氢交替以所述基板暴露在所述沉积气体中期间约60sccm至约600sccm的速率和所述蚀刻期间约2,000sccm至约20,000sccm的速率流入所述反应室。
29.如权利要求24所述的方法,其特征在于,所述处理反应室温度在所述基板暴露在一沉积气体中以及所述蚀刻期间是约500℃至约650℃。
30.一种在置于处理反应室内的基板上外延形成含硅材料的方法,所述基板包含单晶表面和第二表面,所述第二表面选自非晶表面、多晶表面及其组合所组成的组中,所述方法包括:
将进入所述处理反应室的含卤素气体流控制在第一流速,以在所述单晶表面上沉积外延层,并在所述第二表面上沉积多晶层;以及
将进入所述处理反应室的含卤素气体流控制在第二流速,以蚀刻所述多晶层和所述外延层。
31.如权利要求30所述的方法,其特征在于,所述第一流速下的含卤素气体和第二流速下的含卤素气体是相同的。
32.如权利要求31所述的方法,其特征在于,上述的含卤素气体包含氯化氢。
33.如权利要求32所述的方法,其特征在于,上述的含卤素气体在所述第一流速时以约60sccm至约600sccm的速率流入所述反应室。
34.如权利要求32所述的方法,其特征在于,上述的含卤素气体在所述第二流速时以约2,000sccm至约20,000sccm的速率流入所述反应室。
35.如权利要求30所述的方法,其特征在于,上述的处理反应室温度在所述方法期间是约500℃至约650℃。
36.一种计算机可读介质,具有储存在其内的程序指令,以执行如权利要求30所述的方法。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102117741B (zh) * | 2010-01-06 | 2013-03-13 | 上海华虹Nec电子有限公司 | 改善锗硅或锗硅碳单晶与多晶交界面形貌的方法 |
CN103556219A (zh) * | 2013-10-31 | 2014-02-05 | 国家电网公司 | 一种碳化硅外延生长装置 |
CN103556219B (zh) * | 2013-10-31 | 2016-04-20 | 国家电网公司 | 一种碳化硅外延生长装置 |
Also Published As
Publication number | Publication date |
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US7560352B2 (en) | 2009-07-14 |
KR20080112298A (ko) | 2008-12-24 |
TWI419204B (zh) | 2013-12-11 |
WO2007109491A3 (en) | 2007-12-13 |
TW200802547A (en) | 2008-01-01 |
JP2009533546A (ja) | 2009-09-17 |
CN101401202B (zh) | 2011-09-28 |
WO2007109491A2 (en) | 2007-09-27 |
US20060166414A1 (en) | 2006-07-27 |
KR101037524B1 (ko) | 2011-05-26 |
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