CN101388382B

CN101388382B - Staggered offset stacking encapsulation construction having omnibus bar of metal welding pad in conductive wire support

Info

Publication number: CN101388382B
Application number: CN2007101489015A
Authority: CN
Inventors: 陈煜仁; 沈更新
Original assignee: BERMUDA CHIPMOS TECHNOLOGIES Co Ltd; Chipmos Technologies Inc
Current assignee: BERMUDA CHIPMOS TECHNOLOGIES Co Ltd; Chipmos Technologies Inc
Priority date: 2007-09-12
Filing date: 2007-09-12
Publication date: 2011-06-29
Anticipated expiration: 2027-09-12
Also published as: CN101388382A

Abstract

The invention provides a package structure which comprises bus-bars with metal bonding pads which are stacked in stagger offset in a lead frame, which comprises a lead frame which is formed by a plurality of inner pin groups oppositely arranged, a plurality of outer pin groups and chip holders, wherein the chip holders are arranged among the inner pin groups which are oppositely arranged, and have a height difference with the inner pin groups which are oppositely arranged, a stacking type chip device which is stacked by a plurality of chips, and is arranged on the chip holders, and the chips are electrically connected with the inner pin groups which are oppositely arranged, and a package body for coating the stacking type chip device and the lead frame. The lead frame comprises at least one bus-bar which is arranged between the inner pin groups which are oppositely arranged and the chip holder, and the bus-bar is coated with an insulating layer, the insulating layer can selectively form a plurality of metal bonding pads.

Description

The staggered offset stacking encapsulation construction that has the busbar of metal pad in the lead frame

Technical field

The present invention relates to a kind of multi-chip interleaving offset stacking encapsulation construction, particularly disposing the multi-chip interleaving offset stacking encapsulation construction that disposes metal pad on busbar and the busbar on the lead frame relevant for a kind of.

Background technology

In recent years, semi-conductive back segment preparation method is carrying out three-dimensional space (Three Dimension; Encapsulation 3D) reaches big relatively semiconductor integrated level (Integrated) or capacity of internal memory etc. in the hope of utilizing minimum area.In order to reach this purpose, the mode that present stage has been developed use chip-stacked (chip stacked) is reached three-dimensional space (ThreeDimension; Encapsulation 3D).

In the prior art, the stack manner of chip is that a plurality of chips are stacked on the substrate mutually, uses the preparation method (wire bonding process) of routing that a plurality of chips are connected with substrate then.Figure 1A is the existing the generalized section identical or stack chip packaging structure of close chip size that has.Shown in Figure 1A, existing stack chip packaging structure comprises a circuit substrate (package substrate) 110, chip 120a, chip 120b, a sept (spacer) 130, many leads 140 and a packing colloid (encapsulant) 150.Have a plurality of weld pads 112 on the circuit substrate 110, and also have a plurality of

weld pad

122a and 122b respectively on chip 120a and the 120b, wherein

weld pad

122a and 122b are arranged on chip 120a and the 120b with kenel (peripheral type) on every side.Chip 120a is disposed on the circuit substrate 110, and chip 120b is disposed at the top of chip 120a via sept 130.The two ends of lead 140 are to be connected to

weld pad

112 and 122a via the routing preparation method, so that chip 120a is electrically connected at circuit substrate 110.And the two ends of other parts lead 140 also are connected to

weld pad

112 and 122b via the routing preparation method, so that chip 120b is electrically connected at circuit substrate 110.Be disposed on the circuit substrate 110 as for 150 of packing colloids, and coat these leads 140,

chip

120a and 120b.

Because

weld pad

122a and 122b are arranged on chip 120a and the 120b with kenel on every side, therefore the direct carries chips 120b of chip 120a, be with prior art must be between

chip

120a and 120b configuration space thing 130, make between chip 120a and the 120b at a distance of a suitable distance, in order to follow-up routing preparation method's carrying out.Yet the use of sept 130 but causes the thickness of existing stack chip packaging structure 100 to reduce further easily.

In addition, prior art proposes another kind of stack chip packaging structure with different chip sizes, and its generalized section is shown in Figure 1B.Please refer to Figure 1B, existing stack chip packaging structure 10 comprises a circuit substrate (package substrate) 110, chip 120c, chip 120d, many leads 140 and a packing colloid 150.Have a plurality of weld pads 112 on the circuit substrate 110.The size of chip 120c is the size greater than chip 120d, and also has a plurality of weld pad 122c and 122d respectively on chip 120c and the 120d, and wherein weld pad 122c and 122d are arranged on chip 120c and the 120d with kenel (peripheral type) on every side.Chip 120c is disposed on the circuit substrate 110, and chip 120d is disposed at the top of chip 120c.The two ends of part lead 140 are to be connected to

weld pad

112 and 122c via routing preparation method (wire bonding process), so that chip 120c is electrically connected at circuit substrate 110.And the two ends of other parts lead 140 also are connected to weld pad 112 and 122d via the routing preparation method, so that chip 120d is electrically connected at circuit substrate 110.Be disposed on the circuit substrate 110 as for 150 of packing colloids, and coat these leads 140,

chip

120c and 120d.

Because chip 120d is less than chip 120c, therefore when chip 120d was disposed on the chip 120c, chip 120d can not cover the weld pad 122c of chip 120c.But when prior art piles up stack chip packaging structure 10 with the chip of a plurality of different size sizes in above-mentioned mode, because the chip size on upper strata must be more little more, so stack chip packaging structure 10 has the restriction of piling up quantity of chip.

In above-mentioned two kinds of stack manners, Figure 1A uses the mode of sept 130, the shortcoming that causes the thickness of stack chip packaging structure 100 to reduce further easily; And Figure 1B because the chip size on upper strata must be more little more, so can produce the problem that chip can be restricted when design or use.No. the 6252305th, United States Patent (USP), No. the 6359340th, United States Patent (USP) and United States Patent (USP) then provide the structure of another kind of multi-chip stacking encapsulation for No. 6461897, shown in Fig. 1 C, this stacked structure can use measure-alike chip, and does not need to use sept 130 to form connection.Yet, these chips are in the process of piling up, to pile up alternately and must use weld pad configuration more than 2 kinds at least in order to form, for example the weld pad on certain first chip is to be configured on first chip, one side, and the weld pad on another second chip then is to be configured on the two adjacent sides; In addition, this structure also must connect (wire bonding) at the routing of the enterprising row metal lead of both direction.Therefore, in the structure of Fig. 1 C, except the time that might increase the routing preparation method, in the process of carrying out sealing, might cause the inhomogeneous of mould stream and cause defective, and the plain conductor that may cause a certain direction is subjected to horizontal mould stream and impacts strength, causes the plain conductor contact and produces the problem of chip failure.

In addition, United States Patent (USP) US6900528 number, US publication US20030137042A1, US20050029645A1 and US20060267173A1 then provide the structure of another kind of multi-chip stacking encapsulation, shown in Fig. 1 D.Fig. 1 D discloses a kind of encapsulating structure that piles up alternately, clearly, it utilizes the height of chip chamber to replace sept, make the density of encapsulation to increase, but still there is the trouble on the preparation method in this kind encapsulating structure, after must finishing the connection of two chips earlier exactly, carry out after primary plain conductor connects, just can carry out the connection of two other chip after, carry out secondary plain conductor again and connect, so when number of chips the more the time, the preparation method is with regard to relative complex and difficulty.

Summary of the invention

Because the shortcoming and the problem of the chip-stacked mode described in the background of invention, the object of the invention provides a kind of mode of using the multi-chip interleaving offset stacked, and the akin chip staggered offset of a plurality of sizes is stacked into a kind of tridimensional encapsulating structure.

Main purpose of the present invention provides a kind of busbar that disposes metal pad in lead frame and carries out the encapsulation of multi-chip interleaving offset stacked, makes it have higher encapsulation integration and thin thickness.

Another main purpose of the present invention makes it in the sealing process providing a kind of structure that disposes the busbar of metal pad in lead frame to carry out the encapsulation of multi-chip interleaving offset stacked, has the mould stream effect than balance.

The present invention also has a main purpose to provide the busbar that configuration one in a kind of encapsulating structure of multi-chip interleaving offset stacked has metal pad, makes it have preferable circuit design elasticity and better reliability degree.

A main purpose more of the present invention provides a kind of encapsulating structure of multi-chip interleaving offset stacked, and it can be reshuffled layer by one the pad on the chip is reconfigured on the side of chip, makes it can simplify the preparation method of encapsulation.

A main purpose more of the present invention provides a kind of encapsulating structure of multi-chip interleaving offset stacked, it can finish a plurality of chips that staggered offset piles up and with after substrate is connected, carry out routing preparation method once again, just can finish electric connection, so also can further simplify the preparation method of encapsulation.

In view of the above, the invention provides a kind of multi-chip migration stack package structure that disposes the busbar of metal pad in lead frame, comprise: the lead frame that the interior pin group by a plurality of relative arrangements, a plurality of outer pin group and a chip bearing are formed, its chips bearing is to be disposed between the interior pin group of a plurality of relative arrangements, and forms a difference in height with the interior pin group of a plurality of relative arrangements; One multi-chip interleaving offset stacked structure, be to be fixed on the chip bearing, multi-chip interleaving offset stacked structure by a plurality of first chips and a plurality of second chip staggered alternately and with a side-play amount pile up form and an active face of each first chip on a side near configuration and exposing also dispose near another side on the active face of a plurality of weld pads and each second chip and expose a plurality of weld pads with respect to a plurality of exposure weld pads of first chip, wherein a plurality of first chips of multi-chip interleaving offset stacked structure and a plurality of second chip are by the interior pin group electric connection of the relative arrangement with a plurality of one-tenth of many strip metals lead; One packaging body coats multi-chip interleaving offset stacked structure and lead frame, a plurality of outer pins are to stretch out in packaging body to reach lead frame outward; Wherein comprise at least one busbar in the lead frame, be to be disposed between the interior pin group of a plurality of relative arrangements and the chip bearing and the insulating barrier that also is covered on the busbar, and optionally form a plurality of metal pads on the insulating barrier.

The present invention then provides a kind of multi-chip migration stack package structure that disposes the busbar of metal pad in lead frame again, comprise: the lead frame of being formed by the interior pin group and a chip bearing of a plurality of outer pin groups, a plurality of relative arrangements, its chips bearing is to be disposed between the interior pin group of a plurality of relative arrangements, and forms a difference in height with the interior pin group of a plurality of relative arrangements; One multi-chip interleaving offset stacked structure is to be fixed on the chip bearing, multi-chip interleaving offset stacked structure by a plurality of first chips and a plurality of second chip staggered alternately and with a side-play amount pile up form and an active face of each first chip on a side near configuration and exposing also dispose near another side on the active face of a plurality of weld pads and each second chip and expose a plurality of weld pads with respect to this a plurality of exposure weld pads of first chip, wherein a plurality of first chips of multi-chip interleaving offset stacked structure and a plurality of second chip are by the interior pin group electric connection of the relative arrangement with these a plurality of one-tenth of many strip metals lead; And a packaging body, coating multi-chip interleaving offset stacked structure and lead frame, a plurality of outer pins stretch out in outside the packaging body; Wherein comprise at least one busbar in the lead frame, be disposed between the interior pin of a plurality of relative arrangements and the chip bearing and with etc. in pin form a copline, and the insulating barrier that more is covered on the busbar optionally forms a plurality of metal pads on this insulating barrier.

The present invention further provides a kind of conducting wire frame structure with busbar of metal pad, comprise the interior pin of a plurality of relative arrangements and one be disposed between the pin and interior pin to form the chip bearing of a difference in height and at least one busbar be to be disposed between the interior pin of a plurality of relative arrangements and the chip bearing and the insulating barrier that also is covered on the busbar, optionally form a plurality of metal pads on this insulating barrier.

Description of drawings

Figure 1A, Figure 1B, Fig. 1 C and Fig. 1 D are the schematic diagram of prior art;

Fig. 2 A, Fig. 2 C are the top view of chip structure of the present invention;

Fig. 2 B, Fig. 2 D are the cutaway view of chip structure of the present invention;

Fig. 2 E is the cutaway view of multi-chip interleaving offset stacked structure of the present invention;

Fig. 3 A, Fig. 3 B and Fig. 3 C are schematic diagrames of reshuffling layer manufacture process of the present invention;

Fig. 4 A, Fig. 4 B are cutaway views of reshuffling the wire bonds district in the floor of the present invention;

Fig. 5 is the cutaway view with the multi-chip interleaving offset stacked structure of reshuffling layer of the present invention;

Fig. 6 is the cutaway view of another embodiment of multi-chip interleaving offset stacked structure of the present invention;

Fig. 7 A, Fig. 7 B, Fig. 7 C and Fig. 7 D are the cutaway views with the multi-chip interleaving offset stacked structure of reshuffling layer of the present invention;

Fig. 8 is the cutaway view of multi-chip interleaving offset stacked construction packages of the present invention;

Fig. 9 is the cutaway view of another embodiment of multi-chip interleaving offset stacked construction packages of the present invention;

Figure 10 is the cutaway view of another embodiment of multi-chip interleaving offset stacked construction packages of the present invention;

Figure 11 is the cutaway view of another embodiment of multi-chip interleaving offset stacked construction packages of the present invention; And

Figure 12 is the cutaway view of another embodiment of multi-chip interleaving offset stacked construction packages of the present invention.

[primary clustering symbol description]

10,100,400: stack chip packaging structure

110,410: circuit substrate

112,122a, 122b, 122c, 122d: weld pad

120a, 120b, 120c, 120d: chip

130: sept

140,242,420,420a, 420b: lead

150,430: packing colloid

200: chip

210: the chip active face

220: chip back

230: adhesion coating

240: weld pad

250: the wire bonds district

260: the wire welding area edge

30: multi-chip interleaving offset stacked structure

310: the chip body

312a: first weld pad

312b: second weld pad

320: the wire bonds district

330: the first protective layers

332: the first openings

340: reconfiguration line layer

344: the three weld pads

350: the second protective layers

352: the second openings

300: chip structure

400: reshuffle layer

50: multi-chip interleaving offset stacked structure

500 (a, b, c, d): chip structure

600: lead frame

610: interior pin group

6101～6105: interior pin

6102～6106: interior pin

620: the chip bearing

630: busbar

632: insulating barrier

634: metal pad

630n (n=1,2,3 ... .): metal pad

6301～63010: metal pad

640n (n=a, b, c ... .): plain conductor

Embodiment

The present invention is a kind of mode of using the chip staggered offset to pile up in this direction of inquiring into, and the chip stack that a plurality of sizes are close or different builds up a kind of tridimensional encapsulating structure.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Obviously, execution of the present invention does not limit the specific details that skill person had the knack of of chip-stacked mode.On the other hand, back segment preparation methods' such as well-known chip generation type and chip thinning detailed step is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet, for preferred embodiment of the present invention, can be described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, its with after claim be as the criterion.

In the semiconductor packages preparation method in modern times, all be that a wafer (wafer) of having finished leading portion preparation method (Front End Process) is carried out thinning place (ThinningProcess) earlier, for example the thickness with chip is ground between 2～20mil; Then, coating (coating) or wire mark (printing) one deck macromolecule (polymer) material are in the back side of chip again, and this macromolecular material can be a kind of resin (resin), particularly a kind of B-Stage resin.Via a baking or irradiation preparation method, make macromolecular material present a kind of semi-curing glue again with viscosity; Follow again, an adhesive tape that can remove (tape) is attached on the macromolecular material of semi-solid preparation shape; Then, the cutting (sawing process) of carrying out wafer is to form many chip (die); At last, just many chip can be connected with substrate and chip is formed the stacked chips structure.

Shown in Fig. 2 A and Fig. 2 B, be floor map and the generalized section of finishing aforementioned preparation method's chip 200.Shown in Fig. 2 A, chip 200 has the back side 220 (shown in Fig. 2 B) of an active face 210 and a relative active face, and has formed an adhesion coating 230 (shown in Fig. 2 B) on the chip back 220; To emphasize that at this adhesion coating 230 of the present invention is not defined as aforesaid semi-curing glue,, be enforcement aspect of the present invention, for example: glued membrane (die attached film) so long as can form the sticky material that engages with lead frame or chip.Secondly, in an embodiment of the present invention, a plurality of weld pads 240 are disposed on the side of active face 210 of chip 200.Moreover shown in figure 2C and Fig. 2 D, with chip 200 different parts, a plurality of weld pads 240 on the active face 210 of another chip 20 are configured on another side, and promptly chip 20 is to be configured on the relative side with a plurality of separately weld pads 240 on the chip 200.Secondly, definition one edge line 260 is stressed that as the alignment line in wire bonds district 250 edge line 260 is actually and does not exist on the chip 200 on each chip, and it is only as a reference line.

Utilize above-mentioned chip 20 and 200 can form a kind of multi-chip interleaving offset stacked structure.Fig. 2 E is depicted as a kind of generalized section of multi-chip interleaving offset stacked structure, the structure 30 of multi-chip interleaving offset stacked is to determine the overlapping area that the mutual staggered offset of each chip piles up according to the number of chips of piling up, for example, when undermost two chip 20a and 200a engage with adhesion coating 230, chip 200a covers chip 20a alternately greater than area over half, the area that chip 20b covers chip 200a alternately then covers the area of chip 20a greater than chip 200a, and the chip on the upper strata of healing covers lower floor's area of chip more alternately.Simultaneously, each chip is that alignment line forms with the edge line 260 in wire bonds district, therefore can form similar stair-stepping multi-chip interleaving offset stacked structure, and the feasible weld pad that is configured on the chip is not all covered by the chip on upper strata or covers.Illustrate with a specific embodiment, the size of chip 20a, 20b, 20c and 20d or chip 200a, 200b, 200c and 200d is about 10mm * 13mm * 75 μ m, the thickness of each adhesion coating 230 is about 60 μ m, and the substrate thickness that then carries multi-chip interleaving offset stacked structure is about 200 μ m to 250 μ m.According to above-mentioned, the maximum that the structure 30 of multi-chip interleaving offset stacked is finished after piling up is piled up spreading width (overhang): with 6 layers of chip is that example is about 1mm; With 8 layers of chip is that example then can be less than 1.5mm.Be stressed that once more, quantity and size thereof for the chip of the structure of above-mentioned formation multi-chip interleaving offset stacked, the present invention is not limited, as long as the structure of formed multi-chip interleaving offset stacked that can be according to the previous description, be enforcement aspect of the present invention, for example the staggered offset stacked structure of 2 layers of chip or the staggered offset stacked structure of 4 layers of chip.

Next another embodiment of chip pad design of the present invention to be described, be to use a position change, as shown in Figure 3A with chip structure of reconfiguration line layer with chip pad.One chip body 310 at first is provided, and cooks up wire bonds district 320 at the single side of adjacent chips body 310.Pad zone on the active surface of chip body 310 is divided into the first weld pad 312a and the second weld pad 312b, and wherein the first weld pad 312a is positioned at wire bonds district 320, the second weld pad 312b and then is positioned at outside the wire bonds district 320.

Then with reference to figure 3B, form first protective layer 330 on the active surface of chip body 310, wherein first protective layer 330 has a plurality of first openings 332, to expose the first weld pad 312a and the second weld pad 312b.Form reconfiguration line layer 340 then on first protective layer 330, it comprises many leads 342 and a plurality of the 3rd weld pads 344.In this embodiment, the 3rd weld pad 344 is positioned at wire bonds district 320, and lead 342 can electrically connect from the second weld pad 312b and extend to the 3rd weld pad 344, or is electrically connected to the first weld pad 312a from the second weld pad 312b.Secondly, the 3rd weld pad 344 and the first weld pad 312a are arranged in two row, and arrange along the single side of chip body 310, still the 3rd weld pad 344 and the first weld pad 312a can also be single-row, multiple row or other mode is arranged in the wire bonds district 320.In addition, the material of reconfiguration line layer 340 can be gold, copper, nickel, titanizing tungsten, titanium or other electric conducting material.

With reference to figure 3C; after forming reconfiguration line layer 340; second protective layer 350 is covered on the reconfiguration line layer 340 to form the structure of chip 300, and wherein second protective layer 350 has a plurality of second openings 352, to expose the first weld pad 312a and the 3rd weld pad 344.Be stressed that, the first weld pad 312a and the second weld pad 312b kenel on every side are arranged on the active surface of chip body 310, yet the first weld pad 312a and the second weld pad 312b can also be arranged on the chip body 310 via face array kenel (areaarray type) or other kenel.

With reference to figure 4A and Fig. 4 B, be the generalized section that is illustrated along hatching A-A ' and B-B ' respectively among Fig. 3 C.Chip 300 mainly comprises chip body 310 and reshuffles layer 400, wherein reshuffles layer 400 and comprises first protective layer 330, reconfiguration line layer 340 and second protective layer 350.First protective layer 330 has a plurality of first openings 332, to expose these the first weld pad 312a and the second weld pad 312b.Reconfiguration line layer 340 is disposed on first protective layer 330; second protective layer 350 is covered on the reconfiguration line layer 340; wherein second protective layer 350 has a plurality of second openings 352, to expose the 3rd weld pad 344 of these first weld pad 312a and reconfiguration line layer 340.Clearly; the first weld pad 312a and the 3rd weld pad 344 are positioned at the wire bonds district, and therefore the zone beyond the wire bonds district on second protective layer 350 provides the platform of a carrying, to carry another chip structure; therefore, can form a kind of structure of multi-chip interleaving offset stacked.According to above-mentioned, the structure of multi-chip interleaving offset stacked can comprise the chip that has reconfiguration line layer or one-sided weld pad directly is set, also can only comprise chip with reconfiguration line layer or the structure that only has the formed multi-chip interleaving offset stacked of the chip that one-sided weld pad directly is set, for example extremely shown in Figure 4 with reference to the Fig. 2 in same applicant's the U.S. Pat 7170160, repeat no more in this.

Please refer to shown in Figure 5ly, is the structure 50 of a kind of multi-chip interleaving offset stacked of the present invention.Multi-chip interleaving offset stacked structure 50 is to be piled up by a plurality of chips 500 to form, for example pile up by 4 chip staggered offsets, wherein have on each chip and reshuffle layer 400, so the weld pad on the chip 312 can be disposed on the wire bonds district of chip, and form multi-chip interleaving offset stacked structure 50.Because the stack manner of multi-chip interleaving offset stacked structure 50 is identical with above-mentioned multi-chip interleaving offset stacked structure 30, does not repeat them here.In addition, be to connect between a plurality of chips 500 of formation multi-chip interleaving offset stacked structure 50 with the formed adhesion coating 230 of a macromolecular material.

Multi-chip interleaving offset stacked structure of the present invention is except above-mentioned structure, it is multi-chip interleaving offset stacked structure 30 and 50, also can and have the chip 500 of reshuffling layer 400 with chip 20 piles up alternately to form another kind of multi-chip interleaving offset stacked structure 70, as shown in Figure 6, it is piled up by 6 chip staggered offsets and forms.Because it is identical with the stack manner that forms multi-chip interleaving offset stacked structure 30 and 50 to form the stack manner of multi-chip interleaving offset stacked structure 70, does not repeat them here.Yet be stressed that, present embodiment do not limit chip 20 and chip 500 which layer on the upper strata which layer in lower floor, the present invention is not limited, it is enforcement aspect of the present invention so long as form multi-chip interleaving offset stacked structure of the present invention with chip 20 or chip 200 and chip 500.Simultaneously, will will emphasize once more also that for the quantity of the chip of the structure of above-mentioned formation multi-chip interleaving offset stacked, the present invention is not limited, for example shown in Fig. 2 E, it is piled up by 8 chip staggered offsets and forms; Shown in Figure 5, it is piled up by 4 chip staggered offsets and forms; Shown in Figure 6, it is piled up by 6 chip staggered offsets and forms; Certainly also can be by other the mode of forming, so as long as the structure of formed multi-chip interleaving offset stacked that can be according to the previous description is enforcement aspect of the present invention.

Then, the present invention also proposes a kind of stack type chip packaging structure according to above-mentioned multi-chip interleaving offset stacked

structure

30,50 and 70, and is described in detail as follows.Simultaneously, in following declarative procedure, will be embodiment, yet be stressed that multi-chip interleaving offset stacked

structure

30 and 70 also is suitable for the disclosed content of present embodiment with multi-chip interleaving offset stacked structure 50.

Then, will the floor map of multi-chip interleaving offset stacked formula encapsulating structure of the present invention be described.Shown in Fig. 7 A, the multi-chip interleaving offset stacking encapsulation construction is to comprise lead frame 600 and multi-chip interleaving offset stacked structure 50.Lead frame 600 comprises interior pin group 610, a plurality of outer pin groups (not being shown on the figure) and the chip bearing 620 that a plurality of one-tenth are arranged relatively, and its chips bearing 620 is to be disposed between the interior pin group 610 of a plurality of relative arrangements.Can form a difference in height or form a copline between the interior pin group 610 of a plurality of relative arrangements and the chip bearing 620.In the present embodiment, multi-chip interleaving offset stacked structure 50 is to be configured on the chip bearing 620, and via plain conductor 640 multi-chip interleaving offset stacked structure 50 is connected with the interior pin group 610 of lead frame 600.

Continue with reference to figure 7A, in the lead frame 600 of multi-chip interleaving offset stacking encapsulation construction, comprise that further at least one busbar 630 (bus bar) is disposed between the interior pin group 610 of chip bearing 620 and a plurality of relative arrangements, wherein busbar 630 can adopt at least one strip configuration, (n is an integer and more dispose an insulating barrier 632 and dispose at least one metal pad 634n again on insulating barrier 632 on the busbar 630 of each strip configuration, n=1,2,3,4 ... .) form, shown in Fig. 7 A and Fig. 7 B.And in another embodiment, also be to dispose an insulating barrier 632 earlier and on insulating barrier 632, dispose at least one metal pad 634n (n=1,2,3 again on the busbar 630 that busbar 630 also can adopt ring-type configuration and each ring-type to dispose, 4 ... .) form, shown in Fig. 7 C and Fig. 7 D.In addition, as previously mentioned, the weld pad in the wire bonds district of chip can be that single-row arrangement or multiple row are arranged, and the present invention does not limit.According to above-mentioned, busbar 630 comprises a plurality of metal pad 634n (n=1 independent of each other, 2,3,4 ... .), make lead frame 600 increase many metal pad 634n (n=1,2,3,4 ... .) with electric connection, so more elasticity and application on the circuit design can be provided as power supply contact, ground contact or signal contact.

In addition, with regard to above-mentioned insulating barrier 632, it can utilize coating (coating) or wire mark (printing) macromolecular material forms, for example: pi (polyimide, PI), or also can utilize the mode of stickup (attaching) to form, for example use adhesive tape (dieattached film).And metal pad 634n (n=1,2,3,4 ... .) then can utilize plating (plating) preparation method or etching (etching) preparation method, with a metal level be formed on insulating barrier 632 on.To emphasize that at this insulating barrier 632 of the present invention can be to be configured on the whole busbar 630, can certainly with multisegment mode be formed on busbar 630 on, the present invention is not limited yet.Furtherly, the present invention can also be in metal pad 634n (n=1,2,3,4 ... .) on form another insulating barrier 632 again, and again formation metal pad 634 on this insulating barrier 632 more so can make many more many metal pads on the busbar 630.

Illustrate that then the present invention uses busbar 630 to reach the process that the plain conductor wire jumper connects, refer again to Fig. 7 A, present embodiment is with a plurality of metal pad 634n (n=1,2,3, ... .) as transit point (transfer pad), be used for reaching the weld pad a on chip 500a～chip 500d (a ') is connected with interior pin 6101 (6102) to interior pin 6107 (6108) wire jumpers to weld pad d (d '), and can not produce the situation that plain conductor is crossed over mutually.For example, the weld pad a on the multi-chip interleaving offset stacked structure 50 is connected to the metal pad 6341 of busbar 630 earlier, and then metal pad 6341 is connected with interior pin 6103 with another strip metal lead 640 with a plain conductor 640.Then, with plain conductor 640 weld pad b is directly connected to interior pin 6101 again.In like manner, electrically connect weld pad c behind metal pad 6343, by another plain conductor 640 metal pad 6343 and interior pin 6107 are electrically connected again with plain conductor 640; Then, with plain conductor 640 weld pad d is directly connected to interior pin 6105 again.Therefore, finish when being connected the situation that to avoid crossing over the plain conductor 640 that connects weld pad a and interior pin 6103 and weld pad c and interior pin 6107 when pin 6105 in weld pad b and weld pad d and the interior pin 6101.And at the weld pad a ' of another side to weld pad d ' and the wire jumper connection procedure of interior pin 6102 to interior pin 6108, also be to use the metal pad 6342 that forms busbar 630 to metal pad 6344 to form connection as transit point, and this connection procedure as hereinbefore, therefore finishing weld pad a ' after being connected to weld pad d ' and interior pin 6102 to interior pin 6108, can not produce plain conductor 640 situations of leaps mutually yet.

And in another embodiment, when having a plurality of weld pads must carry out the wire jumper connection on the multi-chip interleaving offset stacked structure 50, can use the structure of many busbars 630 to reach, shown in Fig. 7 B.Fig. 7 B shows the schematic diagram that the structural weld pad of multi-chip interleaving offset stacked is connected with interior pin.Clearly, present embodiment can utilize a plurality of metal pad 634n (n=1,2,3 that form busbar 630, ... .) reach as transit point weld pad (a/a '～f/f ') is connected with the wire jumper of interior pin 610, and can not produce the situation of plain conductor 640 interlaced leaps.For example, with a strip metal lead 640 weld pad a on the multi-chip interleaving offset stacked structure 50 or a ' are connected to metal pad 6301 or 6302 earlier earlier, this metal pad 6341 or 6342 then can be used as a ground connection tie point or a power supply contact; Then, with a strip metal lead 640 weld pad b on the multi-chip interleaving offset stacked structure 50 or b ' are connected to earlier on metal pad 6347 or 6348 again, then, with another strip metal lead 640 metal pad 6347 or 6348 is connected with interior pin 6103 or 6104 again.Follow pin 6101 or 6102 in directly weld pad c (c ') being connected to plain conductor 640 again.Therefore, when weld pad c or c ' and in pin 6101 or 6102 plain conductor 640 when connecting, can avoid connecting weld pad c or c ' and in pin 6101 or 6102 plain conductor 640 cross over the plain conductor 640 that connects weld pad b or b ' and interior pin 6103 (6104).Then, carry out weld pad d or d ' are connected with the wire jumper of interior pin 6107 or 6108, with a strip metal lead 640 weld pad d on the multi-chip interleaving offset stacked structure 50 or d ' are connected to earlier on metal pad 6303 or 6304 earlier, and then metal pad 6303 or 6304 is connected with metal pad 6309 or 63010 with another strip metal lead 640, at last, with another strip metal lead 640 metal pad 6309 or 63010 is connected with interior pin 6107 or 6108 again.Then, with plain conductor 640 weld pad e or e ' are connected with metal pad 6345 or 6346; Follow pin 6109 or 61010 in another strip metal lead 640 metal pad 6345 or 6346 being connected to again.Follow again, weld pad f or f ' are directly connected on the interior pin 6305 or 6306 with plain conductor 640.

Clearly, in the connection in the past of above-mentioned plain conductor, when weld pad c or c ' and in

6101 or 6102 plain conductor 640 when directly connecting, can avoid connecting weld pad c or c ' and in

6101 or 6102 plain conductor 640 directly cross over the plain conductors 640 that another connects weld pad b or b ' and

interior pin

6103 or 6104; Similarly, when weld pad f or f ' and in

6105 or 6106 the plain conductor 640 direct-connected processes, can avoid connecting weld pad f or f ' and in

6105 or 6106 plain conductor 640 directly cross over the plain conductors 640 that another connects weld pad d or d ' and interior pin 6107 or 6108.In addition, Fig. 7 C and Fig. 7 D are metal pad 634n (n=1,2,3 of another embodiment of the present invention, ... .) the design of various kenels, in the present embodiment, use many busbars 630 or a plurality of ring-type busbar in its lead frame 600, because of it forms n (n=1,2,3 ... .) with finish the process of encapsulation and Fig. 7 A and Fig. 7 category-B seemingly, repeat no more in this.

Therefore, the present invention is by forming a plurality of metal pad 634n (n=1 on busbar 630,2,3, ... .) structure of the transit point of the lead frame that is used as 600, when must wire jumper carrying out circuit to connect connecting, can avoid the staggered leap of plain conductor, and cause unnecessary short circuit, so can improve the reliability of packaged chip.Particularly that busbar 630 is own as a common earth point, for example with a among Fig. 7 A～Fig. 7 D (a ') point, when directly being connected (not being shown among the figure) with busbar 630, it also is enforcement aspect of the present invention, so can make the lead frame 600 with metal pad of the present invention when cooperating circuit design, can have better elasticity.

In addition, to emphasize once more, multi-chip interleaving offset stacked structure 50 of the present invention is to be fixed on the lead frame 600, a plurality of chips in the multi-chip interleaving offset stacked structure 50 wherein, its can be same size and identical function chip (for example: memory chip), or the chip size in a plurality of chips and function (for example: the chip of the superiors is that other chip of chip for driving then is a memory chip) inequality, repeat no more in this.

Then please refer to Fig. 8, is Fig. 7 A of the present invention and Fig. 7 C generalized section along the multi-chip migration stack package structure of AA line segment section.Between lead frame 600 and the multi-chip interleaving offset stacked structure 50 is to be connected by many strip metals lead 640, wherein lead frame 600 is the interior pin groups 610 by a plurality of relative arrangements, a plurality of outer pin groups (not being shown on the figure) and a chip bearing 620 are formed, and chip bearing 620 is to be disposed between the interior pin group 610 of a plurality of relative arrangements, and form a difference in height with the interior pin group 610 of a plurality of relative arrangements, and one strip or ring-type busbar 630 be disposed between pin group 610 and the chip bearing 620, then dispose one or more insulating barriers 632 on the busbar 630 and be positioned at a plurality of metal pad 634n (n=1 on the insulating barrier 632,2,3 ... .).Busbar 630 in the present embodiment is the configurations with 620 one-tenth one coplines of chip bearing.

Plain conductor 640n (n=a, b, c,) be the end of plain conductor 640a to be connected in first weld pad or the 3rd weld pad (for example first weld pad 312a or the 3rd weld pad 344 among earlier figures 3A, Fig. 3 B and Fig. 3 C) of chip 500d with the routing preparation method, the other end of plain conductor 640a then is connected in first weld pad or the 3rd weld pad of chip structure 500b; Then, with plain conductor 640b the weld pad on the chip 500b (for example b ') and interior pin (for example 6102) are connected, then, with plain conductor 640c the metal pad on the weld pad on the chip 500b (for example a ' or c ') and the busbar 630 (for example 6342 or 6344) is connected again.Then, with another strip metal lead 640d metal pad 6344 is finished with interior pin 6106 again and be connected; Then, repeat above-mentioned routing process, in regular turn weld pad the d '～f ' on the chip 500b is finished electric connection with interior pin 6104,6108 and 61010.Thus, successively finish connection via plain conductor 640a to 640h etc. after, just chip 500d, 500c, 500b and 500a can be electrically connected at lead frame 600, wherein the material of these plain conductors 640 can be used gold.To emphasize once more and since the busbar 630 of present embodiment on can optionally dispose a plurality of metal pad 634n (n=1,2,3 ... .), so make lead frame 600 of the present invention can be used as the electric connection that comprises power supply contact, ground contact or signal contact.

Via above-mentioned explanation, in an embodiment of the present invention, selectively an end of plain conductor is connected in the weld pad of chip, and the other end of plain conductor is connected on the busbar 630 or optionally be connected to one or more metal pad 634n (n=1,2,3 ... .) on.Owing to disposed one or more metal pad 634n (n=1 on the busbar 630,2,3, ... .), can be so that the utilization of the weld pad on the multi-chip stacking structure has more elasticity, for example, can utilize the structure of this busbar 630, certain several metal pad is set at ground contact, the metal pad 6341 among Fig. 7 A and Fig. 7 C for example, certain several metal pad then is set at power supply contact, certain several metal pad also can be set at signal contact even, for example the metal pad 6343 and 6345 among Fig. 7 C.Therefore, the configuration of these metal pads then forms the function of similar electrical transit point.So when the weld pad on the multi-chip stacking structure needs wire jumper or cross-line just can finish the connection of circuit, just do not need laterally to stride across other plain conductor, and can via metal pad 634n (n=1,2,3 ... .) switching finish.So, increase with regard to not producing the radian that makes the plain conductor that will cross in order to cross over other plain conductor, the elasticity that also so not only can increase circuit design or use also can effectively improve the production capacity and the reliability that encapsulate the preparation method.In addition, because busbar 630 and metal pad 634n (n=1,2,3 ... .) between be to have adhesive insulating barrier via one to isolate, therefore can be further with whole busbar 630 as a common earth point, except can making metal pad 634n (n=1,2 so that the current potential unanimity of whole packaging body, 3 ... .) more applications arranged.

Then please refer to Fig. 9, Figure 10 and Figure 11, is Fig. 7 A of the present invention and Fig. 7 C generalized section along another embodiment of the multi-chip migration stacked structure of AA line segment section.The configuration mode of the busbar 630 of the lead frame 600 of Fig. 9, Figure 10 and Figure 11 can be the strip configuration of Fig. 7 A, also can be the ring-type configuration among Fig. 7 C.Same, also dispose one or more insulating barriers 632 on the busbar 630 in the present embodiment and be positioned at a plurality of metal pads 634 on the insulating barrier 632.Clearly, the difference of Fig. 9, Figure 10 and Figure 11 and Fig. 8 is in only inequality in the structure of lead frame 600, for example the height of the busbar 630 of the lead frame among Fig. 9 600 and interior pin 610 coplines and form a difference in height with chip bearing 620; 620 of the busbar 630 of the lead frame 600 among Figure 10 and interior pin 610 and chip bearings form a difference in height; And the interior pin 610 of the lead frame 600 among Figure 11 forms copline and forms a difference in height with busbar 630 with chip bearing 620.In addition, Fig. 9, Figure 10 and Figure 11 use connection procedure and Fig. 8 of many strip metals lead 640 identical between lead frame 600 and multi-chip interleaving offset stacked structure 50, do not repeat them here.

Then again, please refer to shown in Figure 12ly, is Fig. 7 B of the present invention and Fig. 7 D generalized section of an embodiment again along the multi-chip migration stacked structure of AA line segment section.As shown in figure 12, lead frame 600 in the present embodiment is the interior pin groups 610 by a plurality of relative arrangements, a plurality of outer pin groups (not being shown on the figure) and a chip bearing 620 are formed, and chip bearing 620 is to be disposed between the interior pin group 610 of a plurality of relative arrangements, and form the structure of a difference in height with the interior pin group 610 of a plurality of relative arrangements, and at least one be configured in busbar 630 between pin group 610 and the chip bearing 620, wherein can form a copline between busbar 630 and the chip bearing 620, and busbar 630 also is by a plurality of metal pad 634n (n=1,2,3 ... .) form.Same, when multi-chip interleaving offset stacked structure with after lead frame 600 engages, the routing that carries out plain conductor 640 connects, because it is lead frame 600 is same as the previously described embodiments with the process that plain conductor is connected with multi-chip interleaving offset stacked structure, and the routing preparation method is not a feature of the present invention, just repeats no more in this.Still to emphasize at this,, yet in the application of implementing, can look the design of circuit and complicated case and use many busbars though the busbar 630 of Figure 12 is at least one strip structure or the schematic diagram of at least one circulus; And identical to the application between the many busbars 630 with the embodiment of Fig. 7 B, Fig. 7 D, also repeat no more in this.In addition, Figure 12 also only is an embodiment, and it is in the structure of lead frame 600, also can be identical with the structure of lead frame 600 among Fig. 8 to Figure 11, so its detailed connection procedure also repeats no more.

Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need be understood in the scope of its additional claim item, except above-mentioned detailed description, the present invention can also implement widely in other embodiments.Above-mentioned is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the following claim.

Claims

1. the encapsulating structure of a multi-chip stacking is characterized in that comprising:

One lead frame, formed by the interior pin of a plurality of relative arrangements, a plurality of outer pin, at least one busbar and a chip bearing, wherein this chip bearing is to be disposed between the interior pin of these a plurality of relative arrangements, and form a difference in height with the interior pin of these a plurality of relative arrangements, and this busbar is to be disposed between the interior pin and this chip bearing of these a plurality of relative arrangements, and form a copline with this chip bearing, and the insulating barrier that also is covered on this busbar optionally forms a plurality of metal pads on this insulating barrier;

One multi-chip interleaving offset stacked structure, be to be fixed on this chip bearing, this multi-chip interleaving offset stacked structure, staggered alternately and pile up with a side-play amount and to form by a plurality of first chips and a plurality of second chip, and configuration and exposing is also disposed near another side with respect to this a plurality of exposure weld pads of this first chip on the active face of a plurality of weld pads and each this second chip and is exposed a plurality of weld pads near the side on the active face of each this first chip;

Many strip metals lead electrically connects in order to these a plurality of first chips and the relative interior pin group who arranges with these a plurality of one-tenth of a plurality of weld pads on this a plurality of second chips with this multi-chip interleaving offset stacked structure; And

One packaging body coats this multi-chip interleaving offset stacked structure and this lead frame, and these a plurality of outer pins are to stretch out in outside this packaging body;

Wherein to cover lower floor's area of chip alternately big more for this multi-chip interleaving offset stacked structure chip that is upper strata more, and the weld pad that is formulated on the active face of lower floor's chip is not all hidden by the upper strata chip.

2. the encapsulating structure of a multi-chip stacking is characterized in that comprising:

One lead frame, formed by the interior pin of a plurality of outer pins, a plurality of relative arrangements, at least one busbar and a chip bearing, wherein this chip bearing is to be disposed between the interior pin of these a plurality of relative arrangements, and form a difference in height with the interior pin of these a plurality of relative arrangements, and this busbar is to be disposed between the interior pin and this chip bearing of these a plurality of relative arrangements, and form a copline with pin in these, and the insulating barrier that also is covered on this busbar optionally forms a plurality of metal pads on this insulating barrier;

One multi-chip interleaving offset stacked structure, be fixed in this chip bearing on, this multi-chip interleaving offset stacked structure by a plurality of first chips and a plurality of second chip staggered alternately and with a side-play amount pile up form and an active face of each this first chip on a side near configuration and exposing also dispose near another side on the active face of a plurality of weld pads and each this second chip and expose a plurality of weld pads with respect to this a plurality of exposure weld pads of this first chip;

3. the encapsulating structure of a multi-chip stacking is characterized in that comprising:

One lead frame, formed by the interior pin of a plurality of outer pins, a plurality of relative arrangements, at least one busbar and a chip bearing, wherein this chip bearing is to be disposed between the interior pin of these a plurality of relative arrangements, and form a difference in height with the interior pin of these a plurality of relative arrangements, this busbar is disposed between the interior pin and this chip bearing of these a plurality of relative arrangements, and form a difference in height with interior pin and this chip bearing of these a plurality of relative arrangements, and the insulating barrier that also is covered on this busbar optionally forms a plurality of metal pads on this insulating barrier;

One multi-chip interleaving offset stacked structure, one multi-chip interleaving offset stacked structure, be fixed on this chip bearing, this multi-chip interleaving offset stacked structure by a plurality of first chips and a plurality of second chip staggered alternately and with a side-play amount pile up form and an active face of each this first chip on a side near configuration and exposing also dispose near another side on the active face of a plurality of weld pads and each this second chip and expose a plurality of weld pads with respect to this a plurality of exposure weld pads of this first chip;

4. the encapsulating structure of a multi-chip stacking is characterized in that comprising:

One lead frame, formed by the interior pin of a plurality of outer pins, a plurality of relative arrangements, at least one busbar and a chip bearing, wherein this chip bearing is to be disposed between the interior pin of these a plurality of relative arrangements, and form a copline with the interior pin of these a plurality of relative arrangements, and form a difference in height between the interior pin that this busbar is disposed at these a plurality of relative arrangements and this chip bearing and with interior pin and this chip bearing of these a plurality of relative arrangements, and the insulating barrier that also is covered on this busbar optionally forms a plurality of metal pads on this insulating barrier;

One multi-chip interleaving offset stacked structure, be to be fixed on this chip bearing, this multi-chip interleaving offset stacked structure by a plurality of first chips and a plurality of second chip staggered alternately and with a side-play amount pile up form and an active face of each this first chip on a side near configuration and exposing also dispose near another side on the active face of a plurality of weld pads and each this second chip and expose a plurality of weld pads with respect to this a plurality of exposure weld pads of this first chip;

5. as claim 1,2,3 or 4 described encapsulating structures, it is characterized in that: each this chip in this multi-chip interleaving offset stacked structure comprises:

One chip body, has a wire bonds zone, this wire bonds zone is single side or the adjacent dual-side that is adjacent to this chip body, and wherein this chip body has a plurality of first weld pad and a plurality of extra-regional second weld pads of this wire bonds that are positioned at that are positioned at this wire bonds zone;

One first protective layer is disposed on this chip body, and wherein this first protective layer has a plurality of first openings, to expose these first weld pads and these second weld pads;

One reconfiguration line layer is disposed on this first protective layer, and wherein this reconfiguration line layer extends in this wire bonds zone from these second weld pads, and this reconfiguration line layer has a plurality of the 3rd weld pads that are positioned at this wire bonds zone; And

One second protective layer is covered on this reconfiguration line layer, and wherein this second protective layer has a plurality of second openings, to expose these first weld pads and these the 3rd weld pads.

6. the encapsulating structure of a multi-chip stacking is characterized in that comprising:

Formed by the interior pin of a plurality of relative arrangements, a plurality of outer pin, at least one busbar and a chip bearing, wherein this chip bearing is to be disposed between the interior pin of these a plurality of relative arrangements, and form a difference in height with the interior pin of these a plurality of relative arrangements, and this busbar is to be disposed between the interior pin and this chip bearing of these a plurality of relative arrangements, and form a copline with this chip bearing, and the insulating barrier that also is covered on this busbar optionally forms a plurality of metal pads on this insulating barrier;

One multi-chip interleaving offset stacked structure, be to be fixed on this chip bearing, this multi-chip interleaving offset stacked structure by two first chips and two second chips are staggered alternately and with a side-play amount pile up form and an active face of each this first chip on a side near configuration and exposing also dispose near another side on the active face of a plurality of weld pads and each this second chip and expose a plurality of weld pads with respect to this a plurality of exposure weld pads of this first chip;

Many strip metals lead is that the relative interior pin group who arranges with these a plurality of one-tenth of a plurality of weld pads that exposed on these two first chips and this two second chips is electrically connected; And

7. the encapsulating structure of a multi-chip stacking is characterized in that comprising:

Formed by the interior pin of a plurality of outer pins, a plurality of relative arrangements, at least one busbar and a chip bearing, wherein this chip bearing is to be disposed between the interior pin of these a plurality of relative arrangements, and form a difference in height with the interior pin of these a plurality of relative arrangements, and this busbar is to be disposed between the interior pin and this chip bearing of these a plurality of relative arrangements, and form a copline with pin in these, and the insulating barrier that also is covered on this busbar optionally forms a plurality of metal pads on this insulating barrier;

8. the encapsulating structure of a multi-chip stacking is characterized in that comprising:

Formed by the interior pin of a plurality of outer pins, a plurality of relative arrangements, at least one busbar and a chip bearing, wherein this chip bearing is to be disposed between the interior pin of these a plurality of relative arrangements, and form a difference in height with the interior pin of these a plurality of relative arrangements, this busbar is disposed between the interior pin and this chip bearing of these a plurality of relative arrangements, and form a difference in height with interior pin and this chip bearing of these a plurality of relative arrangements, and the insulating barrier that also is covered on this busbar optionally forms a plurality of metal pads on this insulating barrier;

9. the encapsulating structure of a multi-chip stacking is characterized in that comprising:

One packaging body coats this multi-chip interleaving offset stacked structure and this lead frame, and these a plurality of outer pins are to stretch out in outside this packaging body; Wherein to cover lower floor's area of chip alternately big more for this multi-chip interleaving offset stacked structure chip that is upper strata more, and the weld pad that is formulated on the active face of lower floor's chip is not all hidden by the upper strata chip.

10. as claim 6,7,8 or 9 described encapsulating structures, it is characterized in that: each this chip in this multi-chip interleaving offset stacked structure comprises: