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Publication numberCN101385140 A
Publication typeApplication
Application numberCN 200680053236
PCT numberPCT/US2006/048423
Publication date11 Mar 2009
Filing date19 Dec 2006
Priority date23 Dec 2005
Also published asCN101385140B, CN102931103A, CN102931103B, US8067267, US20070148819, WO2007075678A2, WO2007075678A3
Publication number200680053236.5, CN 101385140 A, CN 101385140A, CN 200680053236, CN-A-101385140, CN101385140 A, CN101385140A, CN200680053236, CN200680053236.5, PCT/2006/48423, PCT/US/2006/048423, PCT/US/2006/48423, PCT/US/6/048423, PCT/US/6/48423, PCT/US2006/048423, PCT/US2006/48423, PCT/US2006048423, PCT/US200648423, PCT/US6/048423, PCT/US6/48423, PCT/US6048423, PCT/US648423
InventorsB哈巴, CS米切尔
Applicant泰塞拉公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Microelectronic assemblies having very fine pitch stacking
CN 101385140 A
Abstract
A method of making a stacked microelectronic assembly includes providing a first microelectronic package (122A) having a first substrate (124A) and conductive posts (130A) extending from a surface (128A) of the first substrate (124A), and providing a second microelectronic package (122B) having a second substrate (122B) and conductive, fusible masses (148B) extending from a surface (126B) of the second substrate (124B). A microelectronic element (154A) is secured over one of the surfaces of the first and second substrates (124A), (124B), the microelectronic element (154A) defining a vertical height H1 that extends from the one of the surfaces of the first and second substrate to which the microelectronic element is secured. The tips (131A) of the conductive posts (130A) of the first substrate are abutted against the apexes of the fusible masses (148B) of the second substrate, whereby the vertical height of each conductive post/fusible mass combination is equal to or greater than the vertical height of the microelectronic element (154A) secured to the one of the surfaces of said first and second substrates .
Claims(45)  translated from Chinese
1、一种制造堆叠微电子组件的方法,包括:提供第一微电子封装,所述第一微电子封装包括第一衬底以及从所述第一衬底的表面延伸的导电柱,每个所述导电柱具有从所述第一衬底的所述表面延伸到所述导电柱的末端的垂直高度;提供第二微电子封装,所述第二微电子封装包括第二衬底以及从所述第二衬底的表面延伸的导电可熔块,每个所述可熔块具有从所述第二衬底的所述表面延伸到所述可熔块的顶点的垂直高度;在所述第一和第二衬底的所述表面之一上固定微电子元件,所述微电子元件界定从所述第一和第二衬底的固定了所述微电子元件的所述表面之一延伸的垂直高度;使所述第一衬底的所述导电柱的末端抵靠到所述第二衬底的所述可熔块的顶点,其中每个所述导电柱/可熔块组合的垂直高度等于或大于固定到所述第一和第二衬底的所述表面之一的所述微电子元件的垂直高度。 1. A method of manufacturing a stacked microelectronic assembly, comprising: providing a first microelectronic package, the first package includes a first microelectronic substrate and a conductive post extending from a surface of said first substrate, each The conductive stud extending from the surface of the first substrate to the end of the vertical height of the conductive pillar; providing a second microelectronic package, said second microelectronic package includes a second substrate, and from the conductive surface of said second substrate extending frit may, each said frit extending from said surface of said substrate to said second vertical height frit vertices; in the first one of said first and second surface of the substrate fixing microelectronic element, extending from said microelectronic element defining one of said microelectronic element is fixed to the surface of the said first and second substrates of vertical height; end of said first substrate abuts said conductive pillar to the second substrate, the frit may vertices, wherein each of said conductive pillar / frit combination available vertical height is equal to or greater than the vertical height of said fixed and said first member of said microelectronic substrate surface of the second one.
2、 根据权利要求1所述的方法,还包括使所述可熔块回流,使得所述回流的可熔块吸附到所述导电柱的外表面周围,其中来自所述回流的可熔块的表面张力将所述导电柱拉向所述第二衬底。 2. The method according to claim 1, further comprising said clinker reflux, the reflux may be such that adsorption of the frit surrounding an outer surface of said electrically conductive column, wherein the reflux from the frit may The surface tension of the conductive pillar is pulled toward the second substrate.
3、 根据权利要求2所述的方法,其中所述第二衬底的所述表面包括支撑所述可熔块的接触,且其中来自所述回流的可熔块的表面张力使所述导电柱的末端在所述第二衬底的接触上居中。 3. The method according to claim 2, wherein said surface of the second substrate wherein the frit comprises contacting said support, and wherein the surface tension from the reflux may be made of the conductive pillars frit The end of the contact center of the second substrate.
4、 一种制造堆叠微电子组件的方法,包括:提供第一微电子衬底,所述第一微电子衬底具有从其底表面延伸的导电柱;提供第二微电子衬底,所述第二微电子衬底具有可在其顶表面触及的导电块;将每个所述导电柱抵靠到所述导电块之一; 在所述第一微电子衬底的底表面和所述第二微电子衬底的顶表面中的至少一个表面上固定至少一个微电子元件,其中所述至少一个微电子元件的高度小于所述导电块之一和所述导电柱之一的组合高度;使所述导电块回流,使得所述回流的导电块吸附到所述导电柱的外表面周围,其中所述回流的导电块的表面张力将所述导电柱拉向所述第二微电子衬底且使所述导电柱位于所述回流的导电块之内的中心。 4, a method of manufacturing a stacked microelectronic assembly, comprising: providing a first microelectronic substrate, said microelectronic substrate having a first surface extending from the bottom of the conductive pillars; providing a second microelectronic substrate, wherein The second microelectronic substrate having at its top surface accessible conductive block; each of said conductive pillar to one of said conductive abutment block; a bottom surface of the first substrate and the first microelectronic the top surface of the second microelectronic substrate at least one surface of at least one fixed microelectronic components, wherein the at least one microelectronic element is less than the height of one of the conductive block and the combination of highly conductive column one; make The conductive block refluxed, such that the conductive block adsorbed to reflux around the outer surface of the conductive pillar, wherein the surface tension of the conductive block refluxing pull the conductive pillar and the substrate to the second microelectronic so that the conductive pillar in the center of the return of the conductive block within.
5、 一种制造堆叠微电子组件的方法,包括:提供第一微电子封装,所述第一微电子封装具有有着顶表面和底表面的第一衬底、位于所述第一衬底的底表面上的微电子元件以及从所述第一衬底的底表面延伸的导电柱;提供第二微电子封装,所述第二微电子封装具有有着顶表面和底表面的第二衬底以及可在所述第二衬底的顶表面触及的导电可熔块;使所述导电柱的末端抵靠到所述导电可熔块以电互连所述第一和第二衬底,其中每个所述导电柱/导电可熔块组合的高度等于或大于固定到所述第一衬底的底表面的所述微电子元件的高度。 5. A method of manufacturing stacked microelectronic assembly, comprising: providing a first microelectronic package, the first substrate has a first microelectronic package having a top surface and a bottom surface, located on the bottom of said first substrate on the surface of the microelectronic element and a conductive post extending from a bottom surface of said first substrate; providing a second microelectronic package, with the second microelectronic package having a top surface and a bottom surface and a second substrate frit may be in the top surface of the second substrate accessible conductive; end of said conductive pillar abutment to the conductive frit may be electrically interconnecting said first and second substrates, wherein each The conductive pillar / electroconductive frit composition may be equal to or greater than the height of the height of the microelectronic element is fixed to the bottom surface of the first substrate.
6、 根据权利要求5所述的方法,还包括使所述导电可熔块回流,使得所述回流的可熔块与所述导电柱的侧面配合。 6. The method of claim 5, further comprising said conductive frit may be refluxed, so that the side with the conductive frit may be the column with reflux.
7、 根据权利要求5所述的方法, 所述导电柱具有的高度大于所述第一局度。 7. A method according to claim 5, wherein the conductive post has a height greater than the first game degree.
8、 根据权利要求5所述的方法, 延伸的第二导电柱。 8. A method according to claim 5, wherein, the second conductive studs extend.
9、 根据权利要求8所述的方法, 的第二微电子元件。 9. A method according to claim 8, wherein, the second microelectronic element. 其中从所述第一衬底的底表面延伸的衬底的底表面上的所述微电子元件的还包括提供从所述第二衬底的底表面还包括提供所述第二衬底的底表面上 Wherein said microelectronic element on the bottom surface extending from the bottom surface of the first substrate further comprises providing a substrate providing the second substrate from the bottom surface of the second substrate further includes a bottom ostensibly
10、 根据权利要求9所述的方法,其中从所述第二衬底的底表面延伸的所述第二导电柱具有的高度大于所述第二衬底的底表面上的所述第二微电子元件的高度。 10. A method according to claim according to claim 9, wherein said extending from a bottom surface of the second substrate having a second conductive pillar height greater than on the bottom surface of the second substrate a second micro- the height of the electronic components.
11、 根据权利要求8所述的方法,还包括在电互连所述第一和第二衬底之后,使所述第二导电柱的末端抵靠在第三衬底的导电焊盘上,以便使所述第一和第二衬底与所述第三衬底电互连。 11. A method according to claim 8, wherein, further comprising, after said electrically interconnecting first and second substrates, so that the end of the second conductive studs abutting against the conductive pads of the third substrate, so that said first and second substrate and the third substrate are electrically interconnected.
12、 根据权利要求5所述的方法,其中所述第一微电子元件包括半导体芯片。 12. A method according to claim according to claim 5, wherein said first microelectronic element comprises a semiconductor chip.
13、 根据权利要求9所述的方法,其中所述第二微电子元件包括半导体芯片。 13. A method according to claim 9 or claim, wherein said second microelectronic element comprises a semiconductor chip.
14、 根据权利要求5所述的方法,其中所述导电可熔块包括焊料。 14. A method according to claim 5 or claim, wherein the electrically conductive frit may comprise solder.
15、 根据权利要求5所述的方法,其中所述导电可熔块包括球体。 15. A method according to claim 5 or claim, wherein the electrically conductive frit may comprise a sphere.
16、 根据权利要求5所述的方法,还包括至少部分地密封所述第一衬底的底表面上的所述第一微电子元件。 16. A method according to claim 5, wherein, further comprising at least partially the sealing on the bottom surface of said first substrate, a first microelectronic element.
17、 根据权利要求9所述的方法,还包括至少部分地密封所述第二衬底的底表面上的所述第二微电子元件。 17. A method according to claim 9 or claim, further comprising at least partially sealing said second substrate on the bottom surface of the second microelectronic element.
18、 根据权利要求5所述的方法,其中所述第一和第二衬底包括电介质材料。 18. The method according to claim 5 or claim, wherein said first and second substrates comprises a dielectric material.
19、 根据权利要求ll所述的方法,其中所述第三衬底包括带电路的衬底。 19. A method according to claim according to claim ll, wherein said third substrate comprises a substrate with circuit.
20、 根据权利要求5所述的方法,其中所述微电子元件包括彼此堆叠且位于所述第一衬底的底表面上的两个微电子元件。 20. The method according to claim 5 or claim, wherein said microelectronic element comprises a stack of two microelectronic elements to each other and located on the bottom surface of the first substrate.
21、 根据权利要求1所述的方法,其中所述第一和第二衬底包括电介质衬底。 21. The method according to claim 1 or claim 2, wherein said first and second substrates comprises a dielectric substrate.
22、 根据权利要求21所述的方法,其中所述电介质衬底是柔性的。 22. The method according to claim 21, wherein said dielectric substrate is flexible.
23、 根据权利要求4所述的方法,其中所述第一和第二微电子衬底包括电介质衬底。 23. A method according to claim 4, wherein, wherein said first and second microelectronic substrate includes a dielectric substrate.
24、 根据权利要求23所述的方法,其中所述电介质衬底是柔性的。 24. The method according to claim 23, wherein said dielectric substrate is flexible.
25、 根据权利要求4所述的方法,其中所述第一和第二衬底包括柔性电介质衬底。 25. The method according to claim according to claim 4, wherein said first and second substrates comprises a flexible dielectric substrate.
26、 根据权利要求25所述的方法,其中所述电介质衬底是柔性的。 26. The method according to claim 25, wherein said dielectric substrate is flexible.
27、 一种堆叠微电子组件,包括:提供第一微电子封装,所述第一微电子封装包括第一衬底以及从所述第一衬底的表面延伸的导电柱,每个所述导电柱具有从所述第一衬底的所述表面延伸到所述导电柱的末端的垂直高度;与所述第一微电子封装并置的第二微电子封装,所述第二微电子封装包括第二衬底以及从所述第二衬底的表面延伸的导电可熔块,每个所述可熔块具有从所述第二衬底的所述表面延伸到所述可熔块的顶点的垂直高度;固定在所述第一和第二衬底的所述表面之一上的微电子元件,所述微电子元件界定从所述第一和第二衬底的固定了所述微电子元件的所述表面之一延伸的垂直高度,其中所述第一衬底的所述导电柱末端抵靠在所述第二衬底的所述可熔块的顶点,且其中每个所述导电柱/可熔块组合的垂直高度等于或大于固定到所述第一和第二衬底的所述表面之一的所述微电子元件的垂直高度。 27. A stacked microelectronic assembly, comprising: providing a first microelectronic package, the first package includes a first microelectronic substrate and a conductive post extending from a surface of said first substrate, each of said conductive post extending from the surface of the first substrate to the end of the vertical height of the conductive pillar; with the first microelectronic package and a second microelectronic package opposite said second microelectronic package comprising a second substrate, and extending from the conductive surface of the second substrate may be frit, frit having each said apex extending from said surface of said substrate to said second frit of vertical height; immobilized on the surface of one of said first and second substrate microelectronic components, defined in terms of the microelectronic element fixed to the first and second substrates of the microelectronic components The vertical height of said one surface extending, wherein said conductive substrate of said first end of the column of the second substrate abuts the frit may vertices, and wherein each of said conductive pillar / frit combination of vertically a height equal to or greater than the vertical height of said first fixed and said one surface of the second substrate of the microelectronic element.
28、 根据权利要求27所述的组件,其中所述可熔块是可回流的,使得所述回流的可熔块吸附到所述导电柱的外表面周围,以便产生将所述导电柱拉向所述第二衬底的表面张力。 28. The assembly according to claim 27, wherein said frit is refluxed, such that the frit may be adsorbed to reflux around the outer surface of the electrically conductive column, to produce the conductive pillar is pulled toward the The surface tension of the second substrate.
29、 根据权利要求28所述的组件,其中所述第二衬底的表面包括支撑所述可熔块的接触,且其中来自所述回流的可瑢块的表面张力使所述导电柱的末端在所述第二衬底的接触上居中。 29. The assembly according to claim according to claim 28, wherein the surface of the second substrate supporting said frit comprises contacting, and wherein the surface tension-rong block from the reflux of the column so that the end of the conductive centered on contacting the second substrate.
30、 一种堆叠微电子组件,包括:第一微电子衬底,所述第一微电子衬底具有从其底表面延伸的导电柱; 第二微电子衬底,所述第二微电子衬底具有可在其顶表面触及的导电块;每个所述导电柱抵靠到所述导电块其中之一上;在所述第一微电子衬底的底表面和所述第二微电子衬底的顶表面中的至少一个表面上固定的至少一个微电子元件,其中所述至少一个微电子元件的高度小于所述导电块之一和所述导电柱之一的组合高度,其中所述导电块是可回流的,使得所述回流的导电块吸附到所述导电柱的外表面周围。 30. A stacked microelectronic assembly, comprising: a first microelectronic substrate, said microelectronic substrate having a first surface extending from a bottom conductive pillars; second microelectronic substrate, said second microelectronic substrate bottom having on its top surface accessible conductive block; each of said conductive pillar to abut one of the conductive block wherein; a bottom surface of said first substrate and said second microelectronic microelectronic substrate the top surface of the bottom of at least one surface of at least one fixed microelectronic components, wherein the at least one microelectronic element is less than the combined height of the height of one of the conductive block and one of the conductive column, wherein the conductive block is refluxed, such that an outer peripheral surface of the adsorbent to the reflux conductive stud conductive block.
31、 根据权利要求30所述的组件,其中所述回流的导电块的表面张力将所述导电柱拉向所述第二微电子衬底,并使所述导电柱位于所述回流的导电块之内的中心。 31. The assembly according to claim according to claim 30, wherein the surface tension of the conductive block backflow of the conductive pillar is pulled toward the second microelectronic substrate, and the conductive studs located at the reflux conductive block center within.
32、 一种堆叠微电子组件,包括:第一微电子封装,所述第一微电子封装具有有着顶表面和底表面的第一衬底、所述第一衬底的底表面上的微电子元件以及从所述第一衬底的底表面延伸的导电柱;与所述第一微电子封装并置的第二微电子封装,所述第二微电子封装具有有着顶表面和底表面的第二衬底以及可在所述第二衬底的顶表面触及的导电可熔块;所述导电柱的末端抵靠到所述导电可熔块以电互连所述第一和第二衬底,其中每个所述导电柱/导电可熔块组合的高度等于或大于固定到所述第--衬底的底表面的所述微电子元件的高度。 32. A stacked microelectronic assembly comprising: a first microelectronic package, the first substrate having a first microelectronic package has a top surface and a bottom surface, microelectronics on the bottom surface of the first substrate element and a conductive post extending from a bottom surface of said first substrate; said first microelectronic package and a second microelectronic package set, with the second microelectronic package having a top surface and a bottom surface of the first and a second substrate may be a top surface of the second frit on the accessible conductive substrate; end of the conductive pillar abutment to the conductive frit may be electrically interconnecting said first and second substrates wherein each of the conductive pillar / frit combination of conductive and a height equal to or greater than the fixed to the first - the height of the bottom surface of the substrate of the microelectronic components.
33、 根据权利要求32所述的组件,其中所述导电可熔块是可回流的, 使得所述回流的可熔块与所述导电柱的侧面配合。 33. The assembly as claimed in claim 32, wherein said conductive frit may be refluxed so that the side with the conductive frit may be the column with reflux.
34、 根据权利要求32所述的组件,其中从所述第一衬底的底表面延伸的所述导电柱具有的高度大于所述第一衬底的底表面上的所述微电子元件的高度。 34. The assembly as claimed in claim 32, wherein said conductive post extending from a bottom surface of said first substrate having a height greater than the height of said microelectronic element on the bottom surface of the first substrate .
35、 根据权利要求32所述的组件,还包括从所述第二衬底的底表面延伸的第二导电柱。 35. The assembly according to claim 32, further comprising extending from the bottom surface of the second substrate, a second conductive studs.
36、 根据权利要求35所述的组件,还包括所述第二衬底的底表面上的第二微电子元件。 36. The assembly according to claim 35, further comprising a second microelectronic element on the bottom surface of the second substrate.
37、 根据权利要求36所述的组件,其中从所述第二衬底的底表面延伸的所述第二导电柱具有的高度大于所述第二衬底的底表面上的所述第二微电子元件的高度。 37. The assembly according to claim according to claim 36, wherein said extending from a bottom surface of the second substrate having a second conductive pillar height greater than on the bottom surface of the second substrate a second micro- the height of the electronic components.
38、 根据权利要求35所述的组件,还包括第三衬底,其具有可在其表面触及的导电焊盘,其中所述第二导电柱的末端与所述第三衬底的导电焊盘电互连。 38. The assembly according to claim 35, further comprising a third substrate having on its surface can be touched conductive pads, wherein the second end of the column and the third conductive substrate conductive pads electrical interconnection.
39、 根据权利要求32所述的组件,其中所述第一微电子元件包括半导体芯片。 39. The assembly according to claim according to claim 32, wherein said first microelectronic element comprises a semiconductor chip. 200680053236.5权利要求书第7/7页 Page 7/7 200,680,053,236.5 claim
40、 根据权利要求36所述的组件,其中所述第二微电子元件包括半导体芯片。 40. The assembly according to claim according to claim 36, wherein said second microelectronic element comprises a semiconductor chip.
41、 根据权利要求32所述的组件,其中所述导电可熔块包括焊料。 41. The assembly as claimed in claim 32, wherein said conductive frit may comprise solder.
42、 根据权利要求32所述的组件,还包括至少部分地密封所述第一衬底的底表面上的所述第一微电子元件的密封剂材料。 42. The assembly according to claim 32, further comprising sealing the at least partially on the bottom surface of said first substrate, a first microelectronic element sealant material.
43、 根据权利要求36所述的组件,还包括至少部分地密封所述第二衬底的底表面上的所述第二微电子元件的密封剂材料。 43. The assembly according to claim 36, further comprising at least partially sealing said second substrate on the bottom surface of the second microelectronic element sealant material.
44、 根据权利要求32所述的组件,其中所述第一和第二衬底包括电介质材料。 44. The assembly as claimed in claim 32, wherein said first and second substrates comprises a dielectric material.
45、 根据权利要求44所述的组件,其中所述电介质衬底是柔性的。 45. The assembly as claimed in claim 44, wherein said dielectric substrate is flexible.
Description  translated from Chinese

具有极细间距堆叠的微电子组件 Having fine pitch stacked microelectronic assembly

对相关申请的交叉引用 CROSS-REFERENCE TO RELATED APPLICATIONS

本申请要求享有于2005年12月23日提交的美国专利申请No. 11/318164的权益,在此通过引用将其并入本文。 This application claims the benefit of U.S. Patent December 23, 2005 filed Application No. 11/318164, and in which is incorporated by reference herein.

本发明涉及微电子组件以及制造和测试可堆叠微电子组件的方法。 The present invention relates to a method of manufacturing microelectronic components and test and stackable microelectronic components.

背景技术 Background

诸如半导体芯片的微电子器件通常需要很多通往其它电子元件的输入和输出连接。 Microelectronic device such as a semiconductor chip typically requires a lot of access to other electronic components input and output connections. 半导体芯片或其它类似器件的输入和输出接触通常设置成基本覆盖器件表面的格栅状图案(通常称为"区域阵列")或细长的排,所述排可以平行延伸到器件正面的每个边缘并与其相邻,或者在正面的中心位置。 Input and output contacts of the semiconductor chip or other similar devices are typically configured to substantially cover the surface of the device grid-like pattern (often called "area array") or elongated row, the row may extend parallel to the front of each device edge and adjacent to, or in front of the center position. 典型地,必须要把诸如芯片的器件物理地安装在诸如印刷电路板的衬底上,器件的接触必须要电连接到电路板的导电部件上。 Typically, such devices should be physically chips mounted on a substrate such as a printed circuit board, the contact device must be electrically connected to the conductive member on the circuit board.

半导体芯片通常设置在封装中,在制造期间,以及在将芯片安装在诸如电路板或其它电路面板的外部衬底上期间,封装有助于对芯片的操作。 The semiconductor chip is usually provided in the package during manufacture, as well as the chip is mounted on an external substrate such as a circuit board or other circuit panel during operation of the chip package will help. 例如,很多半导体芯片设置在适于表面安装的封装中。 For example, many semiconductor chips are provided in packages suitable for surface mounting. 己经针对各种应用提出了这一大类的很多种封装。 Already proposed for various applications are a variety of packages of this class. 最常见的是,这种封装包括电介质元件, 其通常称为"芯片载体",电介质上形成有作为电镀或蚀刻金属结构的端子。 Most commonly, this package includes a dielectric member, which is generally referred to as "chip carriers", formed on the medium as an electrical terminal plating or etching a metal structure. 通常通过诸如沿芯片载体自身延伸的细迹线的部件、并通过延伸于芯片接触和端子或迹线之间的细引线或导线,将这些端子连接到芯片自身的接触。 Typically by components such as thin traces extending along the chip carrier itself, and through the thin wire or wires extending chip contact and terminal or between the traces, to connect these terminals to contact the chip itself. 在表面安装操作中,将封装置于电路板上,使得封装上的每个端子与电路板上对应的接触焊盘对准。 In the surface mounting operation, the package will be placed on the circuit board, so that each terminal on the circuit board corresponding package contact pads aligned. 在端子和接触焊盘之间提供焊料或其它接合材料。 Between the terminal and the contact pad to provide a solder or other bonding material. 可以通过加热组件以熔化或"回流"焊料或激活接合材料来将封装永久键合在适当的位置。 By heating the assembly to melt or "reflux" or solder bonding material to encapsulate activated permanently bonded in place.

很多封装包括附着于封装端子的焊球形式的焊料块,其直径通常大约为0. lmm和大约0. 8mm (5和30密耳)。 Many package includes a package terminals attached to form balls of solder bumps, which usually have a diameter of about 0. lmm and about 0. 8mm (5 and 30 mils). 具有从其底面突出的焊球阵列的封 Having a seal from the bottom surface of the protruding ball grid array

装通常被称为球栅阵列或"BGA"封装。 Commonly referred mounted ball grid array or "BGA" packaging. 被称为栅格阵列或"LGA"封装的其它封装,它们是通过焊料形成的薄层或焊接区而固定到衬底。 Other packages are called grid array or "LGA" package, which is a thin layer of solder or weld zone formed by the fixed to the substrate. 这种类型的封装可以相当紧凑。 This type of package can be quite compact. 某些封装,通常称为"芯片尺度封装",其占据的电路板面积等于或仅稍大于封装中所包括的器件的面积。 Some package, commonly referred to as "chip scale package", which occupies board area equal to or only slightly larger than the area of the devices included in the package. 这样的有利之处在于,其减小了组件的总体尺寸,并允许使用衬底上各器件之间的短互连, 这又限制了器件之间的信号传播时间,并且由此便于以高速操作组件。 This is advantageous in that it reduces the overall size of the assembly, and allows the use of short interconnections between devices on the substrate, which in turn limits the signal propagation time between devices, and thereby facilitating high speed operation components.

包括封装的组件可能会有因器件和衬底的不同热膨胀和收縮而被施加应力的问题。 Including those components may be packaged device and the substrate due to difference in thermal expansion and contraction stress is applied. 在工作期间以及在制造期间,半导体芯片膨胀和收縮的量往往与电路板膨胀和收縮的量不同。 And during manufacture, the amount of expansion and contraction of the semiconductor chip of the circuit board is often different from the amount of expansion and contraction during operation. 在例如通过利用焊料将封装端子相对于芯片或其它器件加以固定的情况下,这些效应往往会导致端子相对于电路板上的接触焊盘移动。 In the example, by using a solder with respect to the chip package terminals or other devices to be fixed, these effects tend to cause the mobile terminal with respect to the contact pads on the circuit board. 这可能会在将端子连接到电路板上的接触焊盘的焊料中施加应力。 This may stress applied to the connecting terminals to the circuit board contact pads of solder. 如美国专利5679977、5148266、 5148265、 5455390和5518964 (在此通过引用将其公开并入本文)的某些优选实施例所公开的,半导体芯片封装可以具有相对于芯片或封装中包括的其它器件可移动的端子。 As described in U.S. Patent No. 5679977,5148266, 5,148,265, 5,455,390 and 5,518,964 (herein incorporated by reference in the disclosure herein) of some of the preferred embodiments of the disclosed embodiment, the semiconductor chip package may have a chip or other device with respect to the package may include mobile terminals. 这种移动可以在相当程度上补偿膨胀和收縮的差异。 This movement can be compensated expansion and contraction to a considerable extent on differences.

测试已封装的器件提出了另一个困难的问题。 Test the packaged device presents another difficult problem. 在一些制造工艺中,必须要在被封装器件的端子和测试夹具之间形成临时连接,并通过这些连接操作器件,以确保器件实现全面功能。 In some manufacturing processes must be between the terminal and the test fixture is packaged devices formed temporary connections, and those connections through operation of the device to ensure the device to achieve full functionality. 通常,必需要在不将封装端子接合到测试夹具的情况下形成这些临时连接。 Typically, these temporary connections will need to be formed without the package terminals bonded to the test fixture. 确保所有端子都可靠地连接到测试夹具的导电元件是非常重要的。 Ensure that all terminals are securely connected to the conductive element of the test fixture is very important. 然而,难以通过把封装压到诸如具有平面接触焊盘的普通电路板的简单测试夹具上来形成连接。 However, it is difficult to push through a package is a simple test fixture planar contact pads of the conventional circuit boards such as those having up to form a connection. 如果封装的端子不是共平面的,或者测试夹具的导电元件不是共平面的,那么一些端子将无法接触到测试夹具上它们相应的接触焊盘。 If the package is not coplanar terminal, or test fixture conductive element is not co-planar, then some terminals will not have access to the test fixture to their respective contact pads. 例如,在BGA封装中,附着于端子的焊球直径的差异以及芯片载体不平坦可能导致一些焊球位于不同的高度。 For example, in the BGA package, the solder balls attached to the terminals of the chip carrier and the diameter difference may cause some unevenness of solder balls located at different heights.

可以通过使用特殊构造的、具有被设置成补偿非平坦的特征的测试夹具减轻这些问题。 Through the use of specially constructed, it has been set up to compensate for non-planar features a test fixture to alleviate these problems. 然而,这样的特征增加了测试夹具的成本,并且在一些情况下,给测试夹具自身带来了一些不可靠性。 However, such features increase the cost of the test fixture, and in some cases, to the test fixture itself brings some unreliability. 这一点尤其不合乎需要, 因为测试夹具以及器件与测试夹具的配合应当比被封装器件自身更加可靠,以便提供有意义的测试。 This is particularly undesirable because the test fixture and test fixture with the device itself should be more reliable than the packaged devices, in order to provide a meaningful test. 此外,通常通过施加高频信号来测试用于高 Further, by applying a high frequency signal typically used to test high-

频操作的器件。 Device operation frequency. 这种要求对测试夹具中的信号路径的电学特性提出了约束, 这进一步使测试夹具的构造复杂化。 This requirement on the electrical characteristics of the test fixture signal path proposed constraints, which further complicates the construction of the test fixture.

此外,在测试焊球与端子连接的已封装器件时,焊料往往会积聚在测试夹具结合焊球的那些部分上。 Also, when packaged device testing solder balls connected to a terminal, the solder tends to accumulate in those parts of the test fixture binding balls. 残余焊料的这种积聚可能会縮短测试夹具的寿命并减损其可靠性。 This accumulation of residual solder may shorten the life of the test fixture and detract from its reliability.

已经提出了多种方案来解决上述问题。 Various solutions have been proposed to solve the above problems. 上述专利中公开的某些封装具有可相对于微电子器件移动的端子。 Some package disclosed in the above patents with respect to the microelectronic device having a mobile terminal. 这种移动在测试期间可以在一定程度上补偿端子非平面性。 This movement during the test to some extent can compensate for non-planarity of the terminals.

Nishiguchi等人的美国专利5196726和5214308公开了一种BGA型的方法,其中在衬底上的杯状插座中接收芯片表面上的凸点引线并通过低熔点材料在其中焊接它们。 Nishiguchi et al U.S. Patents 5,196,726 and 5,214,308 disclose a BGA type, wherein the cup-shaped socket lead bumps on the substrate surface and the receiver chip in which they are welded by a low melting point materials. Beaman等人的美国专利4975079公开了一种用于芯片的测试插座,其中在锥形导向体之内设置了处于测试衬底上的穹顶形接触。 Beaman et al., U.S. Patent No. 4,975,079 discloses a test socket for the chip, which in the body of tapered guide is provided in a dome-shaped contact on the test substrate. 通过将芯片压到衬底上,使得焊球进入锥形导向体并与衬底上的穹顶形管脚相啮合。 By pressing the chip to the substrate, so that the solder balls enter the conical guides and with the dome-shaped pins on the substrate is engaged. 通过施加充分大的力,使得穹顶形管脚实际上使芯片的焊球变形。 By applying sufficient force so that the dome-shaped pin balls deform actually make chips.

可以在1998年9月8日授权的共同转让美国专利5802699中找到BGA 插座的其它范例,在此通过引用将其公开并入本文。 You can find other examples of BGA socket in September 8, 1998 authorized the commonly assigned U.S. Patent No. 5,802,699, herein incorporated by reference herein disclosed. '699专利公开了一种具有多个孔的片状连接器。 '699 patent discloses a sheet-like connector having a plurality of apertures. 每个孔具备至少一个在孔上方、向内延伸的弹性分层接触。 Each hole has at least one hole in the top, inwardly extending resilient contacting layered. BGA器件的凸点引线进入孔中,使得凸点引线与接触配合。 BGA bumps wire access hole in the device, such that the bumps contact with the leads. 可以对该组件进行测试,且如果发现可以接受,可以将凸点引线永久地焊接到接触。 You can test the component, and if found acceptable, you can bump the lead permanently welded to the touch.

2001年3月20日授权的共同转让美国专利6202297 (在此通过引用将其并入本文)公开了一种具有凸点引线的用于微电子器件的连接器以及制造和使用连接器的方法。 March 20, 2001 authorized the commonly assigned U.S. Patent bump leads having connector for microelectronic devices and methods of making and using the connector (in this case, which is incorporated herein by reference) discloses 6,202,297. 在'297专利的一个实施例中,电介质衬底具有从正面向上延伸的多个柱体。 In the '297 patent in one embodiment, a dielectric substrate having a plurality of cylinders extending upwards from the front. 柱体可以设置成柱体组的阵列,每个柱体组在其间界定一间隙。 Cylinder can be arranged in an array column groups, each cylinder group to define a gap therebetween. 一般分层的接触从每个柱体顶部延伸。 Generally layered contact extends from the top of each cylinder. 为了测试器件, 将器件的每个凸点引线插入相应间隙之内,由此在凸点引线被不断地插入期间使其与凸点引线相擦触的接触相配合。 To test the device, the device is inserted into each bump leads of the corresponding gap, thereby continuously during the bump leads are inserted into the lead with a bump rub it with a touch of the contact mating. 通常,在将凸点引线插入间隙中时,接触的远侧部向下朝着衬底偏转,向外远离间隙的中心。 Typically, the distal portion when the bump lead inserted into the gap, down toward the substrate contact to deflect outward away from the center of the gap.

共同转让的美国专利6177636 (在此通过引用将其公开并入本文)公开 Commonly assigned U.S. Patent No. 6,177,636 (herein incorporated by reference in the disclosure herein) is disclosed

了一种用于在微电子器件和支撑衬底之间提供互连的方法和设备。 A method and apparatus between the microelectronic device and supporting substrate to provide interconnection. 在'636 专利的一个优选实施例中,制造微电子器件的互连组件的方法包括提供具有第一和第二表面的柔性芯片载体以及将导电片耦合到芯片载体的第一表面。 The method in the '636 patent in a preferred embodiment, the fabrication of microelectronic devices interconnect assembly includes providing a flexible chip carrier having first and second surfaces of the conductive sheet, and is coupled to a first surface of the chip carrier. 然后有选择地蚀刻导电片,以制作出多个基本刚性的柱体。 Then selectively etching the conductive sheet, so as to produce a plurality of substantially rigid column. 在支撑结构的第二表面上提供应力缓冲(compliant)层,并将诸如半导体芯片的微电子器件与应力缓冲层配合,使得应力缓冲层位于微电子器件和芯片载体之间,保留柱体从芯片载体的暴露表面突出。 Provided on a second surface of the supporting structure of the stress-buffering (compliant) layer, and the semiconductor chip and a microelectronic device such as a stress buffer layer with such microelectronic devices located between the chip carrier and the stress buffer layer, from the chip to retain the cylinder an exposed surface of the projection. 柱体电连接到微电子器件。 Column is electrically connected to a microelectronic device. 柱体形成突出的封装端子,其可以配合在插座中或由焊料结合到诸如电路面板的衬底的部件上。 Forming protruding cylinder package terminals, which can fit in the socket or by a solder bonded to the components such as circuit panel substrate. 由于柱体可以相对于微电子器件移动,因此这种封装基本适应器件使用时器件和支撑衬底之间的热膨胀系数的不匹配。 Since the cylinder can be moved with respect to microelectronic devices, and therefore adapt this package does not substantially match the coefficient of thermal expansion between the device and the supporting substrate when the device is used. 此外, 柱体的端部可以是共面的或几乎共面的。 In addition, the end of the cylinder can be coplanar or nearly coplanar.

如2004年11月IO日提交的共同审查中、共同转让的题为"MICRO PIN GRID ARRAY WITH WIPING ACTION" [TESSERA 3. 0-375]的美国专利申请No. 10/985126 (在此通过引用将其公开并入本文)的某些优选实施例所公开的,微电子封装包括了促进擦触作用(wiping action)且有助于导电柱和接触相配合的导电柱。 Such as joint review in November 2004 filed the IO, commonly assigned, entitled "MICRO PIN GRID ARRAY WITH WIPING ACTION" [TESSERA 3. 0-375] U.S. Patent Application No. 10/985126 (incorporated by reference herein Example disclose certain disclosure is incorporated herein) is a preferred embodiment, the microelectronic package includes a catalytic role in wiping contact (wiping action) and helps mating conductive pillar and the contact conductive pillar. 在一个优选实施例中,每个柱体的尖端或上端可以从柱体基底的中心水平偏移。 In a preferred embodiment, the tip or upper end of each cylinder may be offset from the center of the horizontal cylinder base. 除了上述部件之外,或者作为其替代,可以使用这种偏移用于促进柱体倾斜。 In addition to the above components, or as an alternative, it may be used for promoting this shift tilt cylinder. 而且,可以为柱体提供诸如陡沿或粗糙体的特征,用于促进与接触焊盘更可靠的配合。 Also, it can provide, such as sharp edges or rough body characterized cylinder for engaging the contact pads to promote more reliable.

如2004年12月16日提交的共同审查中、共同转让的题为"MICROELECTRONIC PACKAGES認D METHODS THEREFOR" [TESSERA 3. 0-374] 的美国专利申请No. 11/014439 (在此通过引用将其公开并入本文)所详细讨论的,支撑结构可以包括多个间隔开的支撑元件且还可以包括覆盖该支撑元件的柔性片。 Such as joint review December 16, 2004 submission, commonly assigned, entitled "MICROELECTRONIC PACKAGES recognize D METHODS THEREFOR" [TESSERA 3. 0-374] U.S. Patent Application No. 11/014439 (herein by reference in its disclosure is incorporated herein) is discussed in detail, the support structure may comprise a plurality of spaced apart support member and a flexible cover sheet may also include the support member. 导电柱可以在水平方向上从支撑元件偏移开。 Conductive pillars may be offset away from the support member in the horizontal direction. 柱体和支撑元件之间的偏移允许柱体,尤其是柱体的基底相对微电子元件彼此独立地移动。 The offset between the cylinder and the support element allows the column, especially the base of the cylinder to move independently relative to each other microelectronic components.

在2004年11月10日提交的共同审查中、共同转让的题为"MICRO PIN GRID WITH PIN MOTION ISOLATION" [TESSERA 3, 0-376]的美国专利申请No. 10/985119中也更详细地公开了具有能彼此独立地移动的导电端子或柱体的微电子封装,在此通过引用将其公开并入本文。 In the joint review November 10, 2004 submission, commonly assigned, entitled "MICRO PIN GRID WITH PIN MOTION ISOLATION" [TESSERA 3, 0-376] U.S. Patent Application No. 10/985119 also disclosed in more detail can independently of each other with the conductive terminals or mobile cylinder microelectronic package, herein incorporated by reference in the disclosure herein.

通常将诸如半导体芯片的微电子元件安装在诸如电路板的电路面板上。 Typically microelectronic device such as a semiconductor chip is mounted on a circuit board such as a panel. 例如,已封装的半导体芯片可以在封装的底表面上具有结合接触的阵列。 For example, packaged semiconductor chip can have an array of binding contacts on the bottom surface of the package. 通过将这种封装放在电路板上,使封装的底表面面朝下并且抵靠电路板的顶表面,使得封装上的每个接合接触与电路板上对应的接合接触对准, 可以将封装安装到电路板顶表面暴露的对应结合接触阵列上。 By this package on a circuit board, so that the bottom surface of the package and the face-down against the top surface of the circuit board so that the contact engagement with the contact engaging each package on the circuit board corresponding alignment, can be encapsulated the corresponding circuit board mounted to the top surface of the exposed binding on the contact array. 在封装的结合接触和电路板的结合接触之间提供通常为焊球形式的导电接合材料块。 The contact between the combined package and circuit board contacts combined to provide solder balls generally in the form of a conductive bonding material block. 在典型的表面安装技术中,在将封装施加到电路板之前,在封装的结合接触上放置焊球。 In a typical surface mount technology, before the package is applied to the circuit board, the combination of contact with the package placed balls.

通常,在电路板上并排安装大量的微电子元件,并通过连接各结合接触的导电迹线将微电子元件彼此互连。 Typically, a circuit board mounted side by side in a large number of microelectronic components, and each combination of conductive contact via connecting traces microelectronic components interconnected with each other. 然而,利用这种常规的方法,电路板必须要具有至少等于所有微电子元件的总计面积的面积。 However, with this conventional method, the board must have at least equal to the total area of all the elements of the microelectronic area. 此外,电路板必须要具有在微电子元件之间形成所有互连所需的所有迹线。 In addition, the board must have between microelectronic elements form all traces all interconnections required. 在一些情况下,电路板必须包括很多层迹线,以容纳所需的互连。 In some cases, circuit board traces must include many layers, to accommodate the required interconnections. 这实质上增加了电路板的成本。 This substantially increases the cost of the circuit board. 通常,每层都在电路板的整个区域上延伸。 Typically, each layer extends over the entire area of the board. 换言之,整个电路板中的层数由电路板中具有最复杂、最密集包封的互连的区域中所需的层数决定。 In other words, the entire board of layers with the most complex, the most densely interconnected encapsulated region is determined by the desired number of layers in the circuit board. 例如,如果特定的电路在一个小区域中需要六层迹线,而在电路板的其它区域中只需要四层,则必须要把整个电路板制造为六层结构。 For example, if a particular circuit in a small area needs six tracks, while in other areas of the board requires only four, you have to put the entire circuit board manufacturing to six-layer structure.

通过利用附加电路面板使相关微电子元件彼此连接以便形成子电路或模块,子电路或模块又安装到主电路板上,这样可以在一定程度上减轻这些困难。 By making use of the additional panel associated microelectronic circuit elements are connected to each other so as to form sub-circuits or modules, sub-circuits or modules in turn mounted to the main circuit board, so that these difficulties can be reduced to some extent. 主电路板不需要包括由模块的电路面板所形成的互连。 The main circuit board need not be included by the module interconnect circuit panel formed. 可以用"堆叠"配置制造这种模块,使得模块中的一些芯片或其它微电子元件设置于同一模块中其它芯片或微电子元件的顶部。 You can use the "stacked" configuration of manufacturing such a module, the module makes some chips or other microelectronic element is disposed on the top of the same module chip or other microelectronic components. 所以,可以将模块整体安装在主电路板上小于模块中各微电子元件累积面积的区域中。 Therefore, the entire module can be mounted on the main circuit board of each module is less than the cumulative area of microelectronic components area. 然而,附加电路面板和该电路面板与主电路板之间附加互连层会占据额外的空间。 However, additional circuitry between the panel and the circuit panel and the main circuit board additional interconnect layers will occupy extra space. 具体而言,该附加电路面板和附加电路面板与主电路面板之间的附加互连层增加了模块的高度,即,增加了模块在主电路板顶表面上方突出的距离。 Specifically, an additional interconnection layer between the panel and the additional circuit panels with additional circuitry increases the height of the main circuit panel module, i.e., an increase of the module above the main circuit board protruding from the top surface. 在以堆叠配置提供模块,且低高度非常重要(例如,在用于微型化的手机和将被用户佩戴或携带的其它设备中的组件中)的情况下,这一点尤其显著。 In a stacked configuration to provide modules and low height is very important (for example, for the miniaturization of mobile phones and other devices will be worn or carried by the user in the kit) case, which is particularly remarkable.

通过把模块的电路面板与封装自身的一部分(通称为封装衬底)集成可以节省在独立模块电路面板上安装预封装的半导体芯片所占用的额外空 By the part of the circuit panel and the package module itself (commonly known as a package substrate) integration can save additional space to install pre-packaged on a separate semiconductor chip module circuit panel occupied

间。 Room. 例如,在芯片封装操作期间,可以将若干裸露或未封装的半导体芯片连接到公共衬底。 For example, during operation of the chip package, a plurality of bare semiconductor chip can be packaged or connected to a common substrate. 这种性质的封装也可以制造成堆叠的设置。 Packaging of this nature can also be made into a stacked set. 这种多芯片封装可以包括封装中各芯片间的一些或所有互连,并能够提供非常紧凑的组件。 This multi-chip package may include some or all of the interconnections between chips package, and can provide a very compact assembly. 主电路板可以比在同一电路中安装单个已封装芯片所需的电路板更简单。 The main circuit board can be easier than installing a single packaged chips required in a circuit board. 然而,这种方法需要针对封装中要包括的芯片的每个组合的唯一封装。 However, this method requires a unique package for each combination of chips to be included in the package. 例如,在手机行业中,通行做法是使用具有静态随机存取存储器 For example, in the mobile phone industry, the common practice is to use a static random access memory

("SRAM")和闪速存储器的不同组合的同样现场可编程门阵列("FPGA") 或专用集成电路("ASIC"),以便在不同手机中提供不同的特征。 Different combinations ("SRAM") and the same flash memory field programmable gate array ("FPGA") or Application Specific Integrated Circuit ("ASIC"), in order to provide different characteristics in different phones. 这增加了与生产、处理和存储各种封装相关的成本。 This increases the costs associated with the production, processing and storage of various packaging-related.

尽管现有技术中已经存在以上所有这些进步,但仍期望在制造和测试微电子封装方面的进一步改进。 Although the prior art already exists All of these advances, it is expected that further improvements in manufacturing and testing microelectronic packaging area.

发明内容 DISCLOSURE

在本发明的某些优选实施例中, 一种制造堆叠微电子组件的方法包括: 提供第一微电子封装,所述第一微电子封装具有第一衬底以及从所述第一衬底的表面延伸的导电柱,每个导电柱具有从所述第一衬底的所述表面延伸到所述导电柱末端的垂直高度。 In certain preferred embodiments of the present invention, a method of manufacturing stacked microelectronic assembly comprising: providing a first microelectronic package, said first microelectronic package having a first substrate from the first substrate and conductive pillars extending surface of each conductive stud extending from the surface of the first substrate to the end of the vertical height of the conductive pillar. 该方法优选包括:提供第二微电子封装, 所述第二微电子封装包括第二衬底以及从所述第二衬底的表面延伸的导电可熔块,每个可熔块具有从所述第二衬底的表面延伸到所述可熔块顶点的垂直高度。 The method preferably comprises: providing a second microelectronic package, said second microelectronic package comprising a substrate and a second frit extending from the conductive surface of the second substrate, each may have a frit from the extending surface of the second substrate to the vertical height of the frit may vertices. 在所述第一和第二衬底的表面之一上根据需要固定微电子元件, 所述微电子元件界定从固定所述微电子元件的所述第一和第二衬底的所述表面延伸的垂直高度。 On one of the surfaces of said first and second microelectronic substrate fixing member according to the need, the microelectronic element extending from said surface defining said fixed member of said first and second microelectronic substrate The vertical height. 第一衬底的表面优选与第二衬底的表面并置 Preferably the surfaces of the first substrate and the second substrate and opposed

(juxtapose),使得导电柱基本与可熔块对准。 (Juxtapose), such that the conductive pillar can be substantially aligned frit. 希望所述导电柱的末端抵 Hope abutting ends of the conductive pillar

靠到所述可熔块的顶点,由此每个所述导电柱/可熔块组合的垂直高度等于或大于固定到所述第一和第二衬底的表面之一的微电子元件的垂直高度。 Against the apex of said frit, whereby each of said conductive pillar / frit combination of vertically a height equal to or more than a fixed vertical surface of one of said first and second substrate microelectronic components height.

在其它优选实施例中, 一种微电子组件优选包括以微细间距堆叠的两个或更多微电子封装,该间距比利用焊球制造连接可能实现的间距更微细。 In other preferred embodiments, a microelectronic assembly preferably comprises a fine pitch two or more stacked microelectronic packages, the solder ball pitch than with manufacturing the connector may achieve finer pitch. 每个可堆叠封装最好包括衬底,其具有从衬底一个表面突出的管脚和从衬底另一个表面突出的焊球。 Each stackable package preferably comprises a substrate having a surface projecting from the substrate and pins protruding from the other surface of the substrate balls. 结果,每个封装可以与另一个类似构造的封装堆叠在一起和/或放置在多层堆叠组件中。 As a result, each package can be configured with another similar package stacked and / or placed in a multi-layer stack assembly. 每个可堆叠封装可以具有一个或 Each stackable package may have one or

多个附着于衬底的一个或多个表面的管芯。 Attached to a substrate, a plurality of or a plurality of the die surface. 在某些实施例中,管芯可以附着于衬底的两个表面。 In certain embodiments, the die may be attached to both surfaces of the substrate. 可以利用本领域的技术人员公知的任何方法,包括利用引线键合、倒装芯片结合、引线和/或螺柱凸点技术将管芯与衬底电互 Any method may utilize techniques known in the art, including the use of wire bonding, flip-chip bonding, lead and / or stud bumping the die and the substrate electric interaction

连。 Even. 管芯可以密封在密封剂材料中,被底填或进行顶端水滴化(glob topped)。 The die can be sealed in a sealant material is filled or top water drops (glob topped) bottom. 在某些优选实施例中,导电柱高度和球高度的组合等于或大于设置在衬底上的密封或模制芯片结构的高度。 In certain preferred embodiments, a combination of a conductive column height and the height of the ball is equal to or greater than the height of the sealing or molded chip structure is provided on the substrate. 导电柱高度和球高度的组合必须至少等于密封芯片结构的高度,使得导电元件(例如导电柱和相对的焊球)能够跨越组件层之间的间隙。 The combination of highly conductive column height and the ball must be at least equal to the height of the seal chip structure, so that the conductive member (e.g. conductive pillar and the opposing solder balls) can span the gap between the component layers.

在导电焊盘末端与焊料块接触之后,按照期望使焊料块回流以形成堆叠微电子封装之间的永久电互连。 After the end of the conductive pads and the solder bump contacts, as desired so that the solder bumps reflux permanently electrically interconnected to form a stacked microelectronic package between. 在回流期间,回流的焊料将吸附(wick up) 到导电柱周围,形成细长的焊料柱。 During the reflow solder reflow adsorption (wick up) into the surrounding conductive pillar to form an elongated solder column. 此外,在回流焊料时,表面张力将组件的相对层彼此拉到一起,并为导电柱提供自定心作用。 Further, when the reflow material, the surface tension of the layer assembly relative to each other to pull together and provide a self-centering effect for the conductive pillars.

虽然本发明不限于任何特定的操作理论,但据信,提供具有从衬底一个表面突出的导电柱和从衬底另一表面突出的可熔块的可堆叠封装相对于常规封装具有很多优点。 Although the present invention is not limited to any particular theory of operation, it is believed that providing a substrate having a surface protruding from the conductive pillar and protruding from the other surface of the substrate can be frit stackable package relative to a conventional package has many advantages. 首先,利用导电柱来跨越堆体层间间隙的一部分允许为电互连使用更微细的间距。 First, a portion of the conductive pillar to span the gap between the stack layers allows the use of finer pitch electrical interconnection. 第二,导电柱可以跨越堆体层间的间隙的大部分,使得相对的焊球可以非常小,这进一步便于使用微细间距。 Second, most of the conductive studs can span the gap between the pile layer, so that the solder balls can be very small relative to, which further facilitates the use of a fine pitch. 此外,利用拉长的导电柱为回流的可熔材料提供了更大的吸附表面积,从而增大柱体和回流的材料之间的表面张力。 In addition, the use of the column as reflux elongated conductive fusible material provides greater adsorption surface area, thereby increasing the surface tension between the cylinder and the reflux material. 此外,回流的可熔材料将试图完全包围导电柱的外表面,这将容易使柱体居于导电可熔块的中心或使二者对准。 In addition, refluxing attempt fusible material completely surrounds the outer surface of the conductive pillar, which would be easy to make the conductive frit cylinder living center or to both align.

在某些优选实施例中,衬底可以是柔性的,并且可以包括诸如聚酰亚胺的电介质材料。 In certain preferred embodiments, the substrate may be flexible, and may include a dielectric material such as polyimide. 例如使用导电引线、导线或迹线使微电子元件按照期望与衬底电互连。 Such as the use of conductive leads, wires or traces microelectronic element and the substrate electrically interconnected as desired. 微电子元件可以是半导体芯片,其具有带接触的正面和远离其的背面。 Microelectronic element may be a semiconductor chip having a front side and away from contact with the back surface thereof. 在某些优选实施例中,半导体芯片的正面面对衬底。 In certain preferred embodiments, the front face of the substrate of the semiconductor chip. 在其它优选实施例中,然而,半导体芯片的正面远离衬底,而半导体芯片的背面面对衬底。 In other preferred embodiments, however, the front side of the semiconductor chip away from the substrate, and the back surface of the semiconductor chip facing the substrate. 可以在微电子元件和衬底之间设置应力缓冲层。 You can set the stress buffer layer between the microelectronic element and the substrate. 在其它优选实施例中,封装可以包括在衬底上的两个或更多微电子元件。 In other preferred embodiments, the package may include two or more on a substrate a microelectronic device. 在一个优选实施例中,在衬底顶表面上有一个或多个微电子元件。 In a preferred embodiment, the top surface of the substrate with one or more microelectronic elements. 在第二优选实施例中, 一个或多个微电子元件覆盖在衬底的底表面上。 In a second preferred embodiment, the one or more microelectronic elements coated on the bottom surface of the substrate. 在又一个优选实施例中,一个或多个微电子元件覆盖衬底的第一表面,并且一个或多个微电子元件可以覆盖衬底的第二表面。 In a further preferred embodiment the second surface of the embodiment, the one or more microelectronic elements covering a first surface of the substrate, and one or more microelectronic elements may cover the substrate. 微电子元件可以被密封。 Microelectronic element may be sealed.

本发明的又一方面提供了处理微电子封装的方法。 Yet another aspect of the present invention provides a method for processing a microelectronic package. 根据本发明该方面的方法有利地包括如下步骤:推进具有支撑于微电子元件表面上的柔性衬底并具有从所述衬底突出的导电柱的微电子封装,直到所述柱体的末端与测试电路面板上的接触焊盘配合,且衬底发生弯曲,使得与所述柔性衬底相邻的所述柱体的至少一些基底部分相对于微电子元件移动。 The method according to this aspect of the present invention advantageously comprises the steps of: advancing a flexible substrate having a supporting surface on the microelectronic element and protruding from the substrate having conductive pillars microelectronic package, until the end of the cylinder and contact pads on the test circuit panel with, and the substrate is bent, so that the flexible substrate adjacent to at least some of the cylinder relative to the base portion of microelectronic components move. 在根据本发明该方面的优选方法中,柱体基底的移动有助于末端的移动,允许末端即使在接触焊盘自身彼此不共面的情况下也与接触焊盘配合。 In a preferred method according to this aspect of the present invention, the moving cylinder helps move the end of the substrate, allowing the end even when the contact pads themselves are not coplanar with each other and with the contact pads.

根据本发明该方面的方法可以包括如下额外的步骤:保持柱体末端与所述接触焊盘接触,并在保持步骤期间测试封装,例如通过经配合的接触焊盘和柱体向以及从封装传输信号。 The method according to this aspect of the present invention may comprise the following additional steps: holding the end of the cylinder in contact with the contact pad, and during the step of maintaining the test package, e.g., by mating contact pads and the cylinder and to transfer from the package through signal. 可以使用具有简单接触焊盘的简单电路面板实施该方法。 You can use a simple circuit panel has a simple contact pads of the implementation of the method. 该方法还可以包括,在测试之后将末端从接触焊盘解除配合,且还可以包括在从测试电路面板释放之后,将柱体末端与电路面板的导电元件结合。 The method may further comprise, after the end of the test with the lift from the contact pads, and may also include, after the release of the panel from the test circuit, the conductive member and the cylinder end panel combination circuit.

安装结构可以包括柔性衬底,其可以具有形成于其上的导电迹线,用于使柱体与微电子元件电互连。 Mounting structure may include a flexible substrate, which may have conductive traces formed thereon, for causing the cylinder and electrically interconnecting microelectronic element. 柔性衬底可以是基本沿水平面延伸的大致片状衬底,该衬底具有顶表面和底表面,导电柱从顶表面向上突出。 Flexible substrates can be substantially sheet-like substrate extending substantially along a horizontal plane, the substrate having a top surface and a bottom surface, a conductive pillar protruding upwardly from the top surface. 柔性衬底还可以包括多个延伸通过衬底并界定多个区域的间隙,不同柱体设置 Flexible substrates may also include a plurality of gaps extending through the substrate and defining a plurality of regions, different setting cylinder

于不同区域上,例如如2004年11月10日提交的共同转让的题为"MICRO PIN GRID WITH PIN MOTION ISOLATION"的美国专利申请No. 10/985119所公开的,在此通过引用将其公开并入本文。 On different areas, such as common transfer of November 10, 2004 filed entitled "MICRO PIN GRID WITH PIN MOTION ISOLATION" U.S. Patent Application No. 10/985119 disclosed herein by reference in its public and herein. 该封装可以并入支撑层,例如设置于柔性衬底和微电子元件之间的应力缓冲层。 The package may be incorporated into the support layer, such as a stress buffer layer disposed on the flexible substrate and the microelectronic element. 在其它实施例中,该封装可以包括多个彼此间隔开并设置于柔性衬底和微电子元件之间的支撑元件,柱体的基底与支撑元件水平间隔开,如2004年12月16日提交的共同审查中、共同转让的题为"MICROELECTRONIC PACKAGES AND METHODS THEREFOR"的美国专利申请No. 11/014439中所更详细描述的,在此通过引用将其公开并入本文。 In other embodiments, the package may include a plurality of spaced apart and disposed in the support element and the flexible substrate microelectronic components between the substrate and the support member is spaced from the horizontal cylinder, as submitted by December 16, 2004 The joint review, commonly assigned, entitled "MICROELECTRONIC PACKAGES AND METHODS THEREFOR" U.S. Patent Application No. 11/014439 as described in more detail in this disclosure are incorporated by reference herein.

封装的微电子元件优选具有面和接触,接触与导电柱和/或可熔块电互连。 Microelectronic component package having a face and preferably in contact, contact with the conductive post and / or the frit may be electrically interconnected. 在某些实施例中,接触暴露于微电子元件的第一面,且安装结构覆盖 In some embodiments, the contact is exposed to a first surface of microelectronic components and mounting structure covering

第一面。 The first surface. 在其它实施例中,接触暴露于微电子元件的第一面,安装结构覆盖微电子元件的方向相反的第二面。 In other embodiments, the contact microelectronic components exposed to the first surface, the opposite direction of the mounting structure of microelectronic components covering the second side.

本发明的另一方面提供了制造微电子封装和这种封装的元件的方法。 Another aspect of the invention provides a method of manufacturing a microelectronic device package and this package. 根据本发明该方面的方法期望包括:提供由诸如铜的导电材料制成的坯件, 在压力下向坯件施加流体,最好为液体,以在坯件中形成至少一个导电端子,以及提供通往至少一个导电端子的电互连。 According to this aspect of the present invention, the desired method comprising: providing a conductive material by a blank made of copper, is applied under pressure to the blank, such as a fluid, preferably a liquid, to form at least one conductive terminal member in the blank, and to provide at least one conductive terminal leads electrically interconnected. 至少一个导电端子可以是导电柱。 At least one conductive terminal may be a conductive pillar. 该方法还可以包括加热坯件以使坯件在形成操作期间更有易延展。 The method may further comprise heating the blank to the blank during the forming operation is more ductile.

该组件还期望地包括设置于微电子元件和衬底之间的多个支撑元件。 The assembly also desirably includes a plurality of support elements disposed between the microelectronic components and the substrate. 支撑元件最好支撑微电子元件上方的柔性衬底,同时至少一些导电柱与支撑元件偏移开。 The support element is preferably supported above the flexible substrate microelectronic components, while at least some of the conductive pillar offset from the support element. 可以在柔性衬底和微电子元件之间设置应力缓冲材料。 You can set the stress-buffering material between the flexible substrate and microelectronic components.

在某些优选实施例中,至少一个导电支撑元件包括可熔材料块。 In certain preferred embodiments, the at least one electrically conductive support member comprises a meltable mass of material. 在其它优选实施例中,至少一个导电支撑元件包括电介质内核与电介质内核上的导电外涂层。 In other preferred embodiments, the at least one electrically conductive support member comprises a conductive core and an outer coating of dielectric on the dielectric core. 支撑元件也可以是细长的,具有大于其宽度或直径的长度。 The support member may be elongated, having a diameter greater than its width or length.

微电子元件可以是印刷电路板或用于测试诸如微电子元件和微电子封装的器件的测试板。 Microelectronic element may be a printed circuit board or a device for testing such a test plate microelectronic components and microelectronic packages. 微电子元件的第一面可以是微电子元件的正面,可以在正面触及接触。 The first face microelectronic components can be positive microelectronic components, you can reach contacts in front. 在某些优选实施例中,至少一些支撑元件是导电的。 In certain preferred embodiments, at least some of the support member is electrically conductive. 导电支撑元件按期望将至少一些微电子元件的接触与至少一些导电柱电互连。 The conductive support element as desired at least some contacts with at least some of microelectronic components electrically interconnected conductive pillar. 在某些优选实施例中,支撑元件包括从柔性衬底延伸的多个第二导电柱。 In certain preferred embodiments, the support member comprises a plurality of second conductive studs extending from the flexible substrate. 第二导电柱优选向着微电子元件的第一面突出,至少一些第二导电柱与第一导电柱电互连。 The second conductive studs preferably microelectronic element toward a first side projection, at least some of the second conductive pillar and the first conductive studs electrically interconnected. 在某些优选实施例中,第一导电柱通过与第一导电柱紧邻设置的第二导电柱电互连到接触。 In certain preferred embodiments, the first conductive studs with the first conductive pillars disposed adjacent to the second conductive studs electrically interconnected to the contact.

导电柱可以是细长的,从而使柱体具有显著大于柱体宽度或直径的长度。 Conductive pillars can be elongated, so that the cylinder has significantly greater than the width or diameter of the cylinder length. 可以将支撑元件设置成阵列,使得支撑元件在柔性衬底上界定多个区域,每个区域由界定区域角部的多个支撑元件划界,不同的导电柱设置于不同区域中。 The support member may be arranged in an array, so that the support member defining a plurality of areas on a flexible substrate, each region defined by a plurality of support elements delimitation area corners, different conductive pillars disposed in different areas. 在优选实施例中,在每个区域中仅设置一个导电柱。 In the preferred embodiment, only one conductive pillar provided in each region.

在本发明的另一优选实施例中,微电子组件包括具有面和接触的微电子元件、与微电子元件隔开且覆盖其第一面的柔性衬底,以及从柔性衬底延伸并从微电子元件的第一面突出的多个第一导电柱,至少一些导电柱与微电子元件电互连。 In another preferred embodiment of the present invention, the microelectronic assembly includes a microelectronic element having a surface and in contact with the microelectronic components are separated and cover the flexible substrate first surface and extending from the flexible substrate and the micro a first surface of the first conductive studs protruding plurality of electronic components, at least some of the electrically conductive pillar and interconnecting microelectronic element. 该组件还按期望包括从柔性衬底延伸并向着微电子元件的第一面突出的多个第二导电柱,第二导电柱支撑着微电子元件上的柔 The assembly also includes an extension as expected from a flexible substrate and a plurality of protruding toward the first surface of the second conductive pillar microelectronic components, the second conductive pillar supporting the flexible microelectronic components on

性衬底,至少一些第一导电柱从第二导电柱偏移开。 Of the substrate, at least some of the first conductive pillar opening offset from the second conductive studs.

在优选实施例中,至少一些第二导电柱是导电的,第二导电柱将微电子元件的至少一些接触与至少一些第一导电柱电互连。 In a preferred embodiment, at least some of the second conductive pillar is conductive, at least some of the second conductive pillar contacting the microelectronic device with at least some of the first electrically conductive pillar interconnects. 至少一些第一导电柱可以通过紧邻第一导电柱的第二导电柱连接到至少一些接触。 At least some of the first conductive pillar may be connected to at least some of the contacts by a second column adjacent to the first conductive conductive pillars. 该组件还可以包括设置于柔性衬底上的导电迹线,由此,导电迹线将至少一些第一导电柱与微电子元件上的至少一些接触电互连。 The assembly also may include conductive traces disposed on a flexible substrate, whereby at least some of the conductive traces electrically interconnecting at least some of the first conductive pillar contacting microelectronic element. 在某些优选实施例中,至少一个导电迹线延伸于相邻导电柱之间。 In certain preferred embodiments, the at least one conductive trace extending between adjacent conductive pillars.

根据本发明某些优选实施例的组件有助于具有非平坦接触和接口的微电子元件和封装的测试,并避免了对专用的昂贵测试设备的需求。 Components According to certain preferred embodiments of the present invention has a non-flat contact help and microelectronic components and packaging test interface and avoid the need for expensive special test equipment. 在根据本发明该方面的优选方法中,导电柱基底的移动有助于柱体末端的移动, 即使在接触焊盘自身彼此不共面的情况下也允许末端与相对的接触焊盘配合。 In a preferred method according to this aspect of the present invention, the conductive pillars moving substrate contributes to the end of the moving cylinder, even in the case where the contact pads themselves coplanar with each other and also allows the end opposite the mating contact pads.

如上所述,可以在柔性衬底上提供导电迹线以将至少一些第一导电柱与至少一些第二导电柱电互连。 As described above, the conductive traces may be provided to at least some of the first conductive pillar with at least some of the second electrically conductive pillar interconnected on a flexible substrate. 这些迹线可以非常短;每条迹线的长度按 These traces can be very short; the length of each trace by

期望等于第一导电柱和第二导电柱之间的偏移距离。 Desired offset distance equal to the first conductive pillar and the second conductive pillars. 在优选形式中,可以证明该设置是适于高频信号传输的、柱体和微电子元件之间的低阻抗导电路径。 In preferred form, it can prove that the set is suitable for high-frequency signal transmission, low-impedance conductive path between the cylinder and microelectronic components.

在本发明的另一优选实施例中,微电子组件包括其正面上具有接触的裸芯片或晶片。 In another preferred embodiment of the present invention, the microelectronic assembly includes a bare chip or wafer contact on its front. 裸芯片或晶片与其顶表面上具有导电柱且其底表面上具有导电端子的柔性衬底并置。 Bare chip or wafer and a top surface of the conductive pillar and which has a flexible substrate having conductive terminals on the bottom surface juxtaposed. 至少一些导电柱未与一些导电端子对准。 At least some of the conductive pillar is not aligned with some of the conductive terminals. 导电柱优选与导电端子互连。 Conductive pillar preferably interconnected conductive terminals. 在组装期间,将导电柱的末端抵靠到芯片或晶片的接触上,以将芯片或晶片与柔性衬底上的导电端子电互连。 During assembly, the end of the conductive pillar abutting onto the contactless chip or wafer to electrically conductive terminals on the chip or wafer and the flexible substrate interconnect. 可以在芯片/ 晶片和柔性衬底之间提供密封剂。 It can provide a sealant between the chip / wafer and a flexible substrate. 可以提供诸如焊料或锡/金的导电元件与导电端子接触。 It may be provided such as a solder or a tin / gold conductive member in contact with the conductive terminals. 导电端子与导电柱的非对准为封装提供了顺从性 Conductive terminals and the non-aligned conductive vias for the package provides a compliance

(compliancy),使得导电端子能够相对于芯片/晶片移动。 (Compliancy), such that the conductive terminals with respect to the chip / wafer moving. 在某些优选实施例中,导电柱具有金外层,该金外层被直接压到芯片接触上。 In certain preferred embodiments, the conductive pillar with a gold outer layer, the outer layer of the metal is pressed directly onto the chip contacts. 在其它优选实施例中,利用各向异性导电膜或各向异性导电胶形成导电柱和接触之间的电互连,由此在导电柱和接触之间设置导电颗粒。 In other preferred embodiments, the anisotropic conductive film or anisotropic conductive paste forming electrical interconnects and the contact between the conductive post, whereby the conductive particles disposed between the conductive pillar and the contact. 在本发明的另一优选实施例中,用于将芯片/晶片与柔性衬底保持在一起的密封剂包括不导电膜或胶。 In another preferred embodiment of the present invention, for the chip / wafer held together with the flexible substrate comprises a non-conductive sealant film or adhesive.

下文将详细描述本发明的这些和其它优选实施例。 These and other preferred embodiments of the present invention will be described in detail below. 附图说明 Brief Description

图1A-1E示出了制造微电子组件的现有技术方法。 Figure 1A-1E illustrates a prior art method of manufacturing a microelectronic assembly. 图2A-2B示出了图1A-IB中所示的现有技术的微电子组件的另一视图。 Figures 2A-2B shows another view of the prior art shown in FIG. 1A-IB microelectronic components. 图3示出了根据本发明某些优选实施例的微电子封装的截面图。 Figure 3 shows a cross-sectional view of certain preferred embodiments of the present invention, a microelectronic package. 图4A-4C示出了根据本发明某些优选实施例的制造堆叠微电子组件的方法。 Figures 4A-4C illustrate a method of manufacturing stacked microelectronic assembly embodiment in accordance with certain preferred embodiments of the present invention.

图5A-5C示出了根据本发明另一优选实施例的制造堆叠微电子组件的方法。 Figures 5A-5C illustrate a method of manufacturing stacked microelectronic assembly according to another preferred embodiment of the present invention.

图6A-6B示出了根据本发明又一优选实施例的制造堆叠微电子组件的方法。 Figures 6A-6B illustrate a method of manufacturing stacked microelectronic assembly according to a further embodiment of the preferred embodiment of the present invention.

图7示出了根据本发明某些优选实施例的堆叠微电子组件的截面图。 Figure 7 shows a cross-sectional view of the stacked microelectronic assembly in accordance with certain preferred embodiments of the present invention. 具体实施方式 DETAILED DESCRIPTION

图1A-1C示出了制造可堆叠组件的常规方法,该可堆叠组件包括具有电介质衬底24的第一微电子封装22,电介质衬底24具有第一表面26和第二表面28。 Figures 1A-1C illustrate a conventional method of manufacturing a stacked assembly, the stacked assembly may include a dielectric substrate 24 of a first microelectronic package 22, a dielectric substrate 24 having a first surface 26 and second surface 28. 第一微电子封装22包括可以在衬底24的第二表面28触及的导电焊盘30。 A first microelectronic package 22 may include a second surface 28 of the substrate 24 of the conductive pads 30 touch. 第一微电子封装22还包括附着于衬底24的第二表面28的第一微电子元件32,例如半导体芯片。 22 further includes a first microelectronic package 24 is attached to the second surface of the substrate 28 of the first microelectronic element 32, such as a semiconductor chip. 微电子封装22还包括第一微电子元件32上方的第二微电子元件34。 Microelectronic package 22 further comprising a second microelectronic element 32 at the top of the first microelectronic element 34. 封装材料36覆盖第一和第二微电子元件32、 34。 Packaging material 36 covering the first and second microelectronic elements 32, 34.

参考图1A,该微电子组件还包括具有衬底40的第二微电子元件38, 该衬底40具有第一表面42和第二表面44。 With reference to Figure 1A, the microelectronic assembly further comprises a second microelectronic element 38 having a substrate 40, the substrate 40 having a first surface 42 and second surface 44. 衬底40的第一表面42包括可以在第一表面触及的接触46。 The substrate 40 includes a first surface 42 in contact with a first surface 46 accessible. 在组装期间,第一衬底24的导电焊盘30优选被置于同第二衬底40的接触46对准的位置。 During assembly, the first substrate 30 is preferably conductive pads 24 is placed in contact with the second substrate 40 of 46 aligned position. 为了跨越或桥接密封剂层36的高度以确保可靠的电互连,在第一衬底24的一些导电焊盘30上放置第一焊球48,且在第二衬底40的一些接触46上放置第二焊球50。 In order to bridge or span the height of the sealant layer 36 to ensure reliable electrical interconnection, a first solder ball 48 is placed on a number of conductive pads 30 of the first substrate 24 and second substrate 46 of some contacts 40 on Place the second solder balls 50.

如图1A所示,第一衬底24包括设置在被密封微电子元件32、 34左侧的五个导电焊盘30以及设置在被密封微电子元件右侧的五个导电焊盘。 1A, a first substrate 24 includes a microelectronic element disposed in sealed 32, 34 on the left side and five conductive pads 30 are provided in the sealing member microelectronic five conductive pads on the right side. As

下文将要更详细描述的,由于必须要跨越的第一和第二微电子封装之间的 It will be described in greater detail below, because of the need to cross between the first and second microelectronic package of

高度,且由于跨越间隙所需的焊球尺寸,可以不在每个导电焊盘30或接触46上设置焊球。 Height, and because the gap across the desired ball size, can not each of the conductive pads 30 or 46 solder balls touch. 结果,仅有一些对准的导电焊盘30和接触46可以具有在其间延伸的导电材料。 As a result, only some contact with conductive pads 30 and 46 may be aligned with a conductive material extending therebetween.

参考图1B,在彼此并置第一和第二微电子元件之后,第一微电子封装的第一焊球48靠住第二微电子封装的第二焊球50。 1B, the juxtaposed to each other in the first and second microelectronic element after the first microelectronic package solder balls 48 abut the first second of the second microelectronic package solder balls 50. 如图1B所示,第一和第二组焊球48、 50优选彼此对准,以电互连相对的导电焊盘30和接触46。 1B, the first and second sets of solder balls 48, 50 is preferably aligned with each other, to electrically interconnect opposed conductive pads 30 and the contacts 46. 第一和第二焊球48、 50优选具有足以跨越第一和第二微电子封装22、 38 之间的间隙的尺寸,以形成其间的电互连。 The first and second solder balls 48, 50 preferably has sufficient across the first and second microelectronic package 22, the size of the gap 38 between, to form the electrical interconnection therebetween. 在图1B的实施例中,焊球的高度显著高于密封剂层36的高度。 In the embodiment of FIG. 1B, the height of the solder balls is significantly higher than the height of the sealant layer 36. 然而,对准的第一和第二焊球48、 50的组合高度必须仅足以跨越密封剂层36形成的层之间的间隙。 However, a combination of the first and second solder balls 48 aligned, the height must be sufficient to only 50 across the gap between the layers of sealant layer 36 is formed.

参考图1C,在相对的焊球48、 50彼此接触之后,可以通过例如加热焊料块来使焊料块回流,以形成导电块, 一些导电块延伸于第一衬底24的导电焊盘30和第二衬底40的接触46之间。 With reference to Figure 1C, after a relatively solder balls 48, 50 contact with each other, for example, by heating the solder bumps to make the solder bump reflow to form a conductive block, the block number of the conductive substrate extends in the first conductive pads 30 and 24, 40 between the two substrate contact 46. 在图1C所示的特定实施例中, 微电子组件20包括被密封微电子元件32、 34左侧的三个导电块和其右侧的三个导电块。 In the particular embodiment shown in FIG. 1C, the microelectronic assembly 20 includes a sealed microelectronic three conductive block member 32, three conductive block 34 on the left side and the right side thereof. 由于表面张力,导电块52往往在顶部较薄,在底部较厚。 Due to surface tension, often at the top of the conductive block 52 is thinner, thicker at the bottom. 如图1C所示,导电块52A、 52B、 52D、 52E和52F具有泪滴状形状,其底部比顶部厚。 1C, the conductive blocks 52A, 52B, 52D, 52E, and 52F having teardrop shape, the bottom thicker than the top. 导电块52C塌陷成球形块。 Conductive block 52C collapse into a ball block. 结果,导电块52C不能形成导电焊盘30E和接触46E之间的电互连。 As a result, the conductive block 52C can not form conductive pads 30E and 46E electrical interconnection between contacts.

图1D中示出了一种方案,用于确保导电块52'能够桥接第一衬底24' 的导电焊盘30'和第二衬底40'上的接触46'之间的间隙。 Figure 1D shows a scheme for ensuring conductive block 52 'can bridge the first substrate 24' is conductive pads 30 'and the second substrate 40' contact gap 'between the 46 on. 在图1D所示的组件中,将两个衬底24'和40'置于比图1C实施例所示的间距更近。 In the assembly shown in FIG. 1D, the two substrates 24 'and 40' is placed over the embodiment shown in FIG. 1C closer spacing. 然而, 导电块52'往往会展宽并覆盖相邻的导电焊盘30'和接触46'。 However, the conductive block 52 'is often broadens and cover adjacent conductive pads 30' and the contact 46 '. 结果,不能在所有对准的导电焊盘30和接触46之间放置导电块。 As a result, the conductive block can be placed between the conductive pads 30 and 46 contact aligner. 如果在所有对准的导电焊盘30'和接触46'上放置诸如焊球的导电块, 一个导电焊盘或接触上的导电材料会接触到相邻的导电焊盘或接触或相邻导电焊盘和/或接触上的导电材料。 If all of the alignment of the conductive pads 30 'and the contact 46', such as solder balls placed on the conductive block, a conductive material on the conductive pads or contacts come into contact with adjacent conductive pads or contacts or welding adjacent guide disc and / or conductive material on the contact. 在某些情况下,相邻导电焊盘和/或接触上的导电焊料材料在回流期间会流到一起,这将导致微电子组件短路等。 In some cases, the adjacent conductive pads and / or conductive material in contact on the solder during reflow will flow together, which would lead to short circuits microelectronic assembly.

图1E示出了在试图对图1D实施例导致的问题进行解决的时候发生的额外问题。 Figure 1E shows an additional problem in trying to resolve the problem of the Figure 1D embodiment example caused when occurred. 在图1E中,第一衬底24''和第二衬底40''相互隔开充分的距 In FIG. 1E, a first substrate 24 '' and the second substrate 40 '' spaced a sufficient distance

离,以便避免图1D中所示的横向集束问题。 From, in order to avoid problems in Figure 1D transverse bundle shown. 随着将衬底彼此移开,表面张 As the substrate away from each other, the surface tension

力和重力可能导致诸如焊球的导电材料仅在接触46"上集中,在第一衬底24''的导电焊盘30''和第二衬底40',的接触46''之间为间隙47''。还可 Between force and gravity may cause a conductive material such as solder balls only in contact with 46 "focus on the first substrate 24 'of conductive pads 30' 'and the second substrate 40', the contacts 46 ' the gap 47 'may also be

以在相对的导电焊盘和接触之间形成两个更小的导电块,例如在导电焊盘30J"上形成较小的导电块52F''-l,在接触46J',上形成较大的导电块52F' ,-2。 In two smaller conductive block between the opposing conductive pads and contacts are formed, e.g., small conductive block is formed in the conductive pads 30J "on 52F '' - l, the contact 46J ', the formation of larger conductive block 52F ', -2.

图2A和2B示出了在将焊球置于每个对准的导电焊盘和接触上时发生的一些上述问题。 2A and 2B illustrates some of the above problems occur when the solder balls placed on each of the conductive pads and the contact alignment. 参考图2A,第一微电子封装22包括第一衬底24,第一衬底24具有第一表面26和远离其的第二表面28。 2A, the first microelectronic package 22 includes a first substrate 24, a first substrate 24 having a first surface 26 and away from the second surface 28 thereof. 第一衬底24包括位于已密封微电子元件32、 34左侧的五个导电焊盘30A-30E以及位于已密封第一和第二微电子元件32、 34右侧的五个导电焊盘30F-30J。 The first substrate 24 includes a sealed microelectronic element 32, 34 to the left of the five conductive pads 30A-30E, and located in the sealed first and second microelectronic elements 32, 34 to the right of the five conductive pads 30F -30J. 在相应的导电焊盘30A、 30C和30E上方分别设置焊球48A、 48C和48E。 In the respective conductive pads 30A, 30C and 30E are provided above the solder balls 48A, 48C and 48E. 类似地,在相应的导电焊盘30F、 30H和30J上方分别设置焊球48F、 48H和48J。 Similarly, in the respective conductive pads 30F, 30H and 30J are provided above the solder balls 48F, 48H and 48J. 在导电焊盘30B、 30D、 30G和301上不设置焊球。 Not the solder balls on the conductive pad 30B, 30D, 30G, and 301. 这是因为焊球48太大,以致于不能被放置在每个导电焊盘30上。 This is because the solder ball 48 is too large, so that can not be placed on each of the conductive pad 30. 假想(phantom)的焊球48B表明,在导电焊盘30A-30C上没有足够的空间来在每个导电焊盘上放置焊球。 Phantom (phantom) solder balls 48B show that there is not enough space on the conductive pads 30A-30C to place balls on each of the conductive pads. 如果尝试这种布置,三个焊球48A-48C会在回流操作期间彼此接触,这会导致电子组件短路或形成有缺陷的电互连。 If you try this arrangement, three balls 48A-48C will be in contact with each other during a reflux operation, which will lead to a short circuit or electronic component is formed defective electrical interconnection.

图2A还示出了包括第二衬底40的第二微电子封装38,第二衬底40具有第一表面42和第二表面44。 Figure 2A also illustrates a second substrate 40 includes a second microelectronic package 38, a second substrate 40 having a first surface 42 and second surface 44. 第二衬底40包括接触46A-46J。 The second substrate 40 includes a contact 46A-46J. 焊球50设置于接触46A-46J中一部分的顶部。 Solder ball 50 is provided in contact with the top part of the 46A-46J. 具体而言,焊球50A、 50C和50E分别设置在接触46A、 46C和46E顶部。 Specifically, the bump 50A, 50C and 50E are provided in the contact 46A, 46C and 46E top. 此外,焊球50F、 50H和50J分别设置在接触46F、 46H和46J顶部。 In addition, the solder balls 50F, 50H and 50J are disposed in contact with 46F, 46H and 46J top. 在接触46B顶部不设置焊球,因为在该接触上放置焊料会导致焊球50A-50C彼此接触,这会导致短路或有缺陷的电互连。 46B does not contact the top of the solder balls, as placed on the contact solder balls 50A-50C will lead to contact with each other, which can cause a short circuit or defective electrical interconnection.

参考图2B,在组装期间,使第一微电子封装22与第二微电子封装38 并置,从而使导电焊盘30A-30J与接触46A-46J基本对准。 With reference to Figure 2B, during assembly, the first 22 and second microelectronic packages and microelectronic package 38 is set so that the conductive pads 30A-30J and 46A-46J contacting substantially aligned. 将导电焊盘上的焊球48A、 48C、 48E、 48F、 48H和48J放置成与第二微电子封装38上的第二焊球50A、 50C、 50E、 50F、 50H和50J接触。 The balls of conductive pads 48A, 48C, 48E, 48F, 48H and 48J placed second on 38 second microelectronic packages balls 50A, 50C, 50E, 50F, 50H and 50J touch. 堆叠焊球的高度足以跨越由密封剂层36的高度产生的间隙。 Stacking height sufficient solder balls across the gap generated by the height of the sealant layer 36. 由于空间量不够,并不是在所有的对 Since the amount of space is not enough, not at all to

准导电焊盘和接触之间都设置焊球。 It is set between the quasi conductive pads and solder contacts. 具体而言,至少在导电焊盘30B和接触46B之间不设置焊球,因为在第一和第二衬底24、 40的相对表面上没有足够的空间。 Specifically, at least the solder balls are not provided in the contact between the conductive pads 30B and 46B, because there is not enough space on the opposite surfaces of the first and second substrates 24, 40. 虽然示出了假想的焊球48B、 50B,但这样的焊球实际上并不在相对的导电焊盘30B和接触46B上。 Although the illustrated imaginary balls 48B, 50B, but this is not actually the balls opposite the conductive pads 30B and the contact 46B. 示出假想的焊球仅^l表示如果在每个对准的导电焊盘和接触顶部都设置焊球将会发生的空间问题和短路问题。 Shows an imaginary balls ^ l only said that if the conductive pads are provided in each contact with the top of the alignment and space problems and the short-circuit problem will occur balls.

所以,图1A-1C以及2A-2B示出了与使用焊球或焊料块跨越堆叠微电子组件层之间的间隙相关联的一些问题。 Therefore, Figures 1A-1C and 2A-2B illustrate some of the problems associated with gaps between the layers of stacked microelectronic assembly using solder balls or solder bumps spans. 如上所述,问题之一涉及到相对的接触或导电焊盘之间的距离或间隙空间。 As mentioned above, one of the problems related to the distance or gap or space opposite the contact between the conductive pads. 为了充分跨越层间的高度,焊料块必须要具有足够的直径以跨越该高度。 To fully across the height between the layers, the solder bumps must be of sufficient diameter to span the height. 令人遗憾的是,为了跨越该高度,随着焊料块直径的增加,可以在衬底表面上并排设置的焊球数量下降。 Unfortunately, in order to cross the height of the solder bump diameter increases, the number of balls can be arranged side by side on the substrate surface decreases. 因此,可以在堆体中的层间形成的垂直延伸的电连接的数量减小了。 Thus, the number of electrical connections between the stack body can be a layer formed by vertically extending reduced. 考虑到这些不足,需要提供具有微细间距的堆叠微电子组件。 Taking into account these problems, the need to provide stacked microelectronic assembly having a fine pitch.

图3示出了根据本发明某些优选实施例的微电子封装122 。 Figure 3 shows a microelectronic package 122 in accordance with certain preferred embodiments of the present invention. 微电子封装包括诸如柔性电介质衬底的衬底124,其具有第一表面126和远离其的第二表面128。 Microelectronic package includes a flexible dielectric substrate such as a substrate 124 having a first surface 126 and second surface 128 remote from its. 微电子封装包括从柔性衬底124的第二表面128突出的导电柱130。 Microelectronic package includes a flexible substrate 124 from the second surface 128 of conductive pillars 130 protruding. 导电柱130具有远离衬底124的第二表面128的末端131。 Conductive post 130 away from the substrate 124 having a second end surface 128 of 131. 微电子封装122还包括衬底124的第二表面128上方的第一微电子元件132以及第一微电子元件132上的第二微电子元件134。 Microelectronic package 122 also includes a second surface of the substrate 124, 128 above the first microelectronic element 132 and second microelectronic element 132 on the first microelectronic element 134. 第一和第二微电子元件132、 134被密封在密封剂层136中。 The first and second microelectronic elements 132, 134 is sealed in the sealing layer 136.

微电子封装122还包括可从衬底124第一表面126触及的诸如焊球的可熔块148。 Microelectronic package 122 also includes a first surface of the substrate 123 from 126 balls to reach, such as frit 148. 可熔块148优选与一个或多个导电柱130电接触。 Frit 148 may preferably with one or more electrically conductive stud contact 130. 微电子封装122还优选包括在整个衬底124上延伸的导电迹线149。 Microelectronic package 122 also preferably includes a substrate 124 extending over the entire conductive traces 149. 导电迹线149可以与一个或多个导电柱130和/或一个或多个可熔块148电接触。 149 may be electrically conductive column 130 and / or 148 electrical contact with the conductive traces with one or more of one or more frit. 导电迹线149 可以在衬底124的第一表面126上、第二表面128上和/或第一和第二表面126、 128之间延伸。 149 may be on the first surface 126 of the substrate 124, and / or the first and second surfaces 126, 128 extending between the upper surface 128 of the second conductive traces.

密封剂材料136具有底表面154,该底表面界定了在底表面154和衬底124的第二表面128之间延伸的高度H'。 The sealant material 136 has a bottom surface 154, the bottom surface defining a height H between the bottom surface 154 and the second surface of the substrate 124, 128 extending '. 导电柱130界定在导电柱的末端131和衬底124的第二表面128之间延伸的第二高度H2。 Conductive post 130 defines a second height H2 extending between the end surface 128 of the second conductive studs 131 and the substrate 124. 如下文将要详细描述的,导电柱的高度H2和将要与导电柱130的末端131配合的相对焊料块 As will be described in detail, and the conductive pillar height H2 relative to the solder bumps 131 and the conductive studs 130 of the mating end

的高度必须足以跨越由密封剂层136的高度H,生成的间隙。 The height must be sufficient to span the height of the sealant layer 136 H, the resulting gap. 焊料块148具有顶点151,顶点151界定了在焊料块的顶点151和衬底124的第一表面126之间延伸的高度H3。 Solder block 148 has an apex 151, apex 151 defines the height H3 between the first surface of the substrate 151 and the vertex 124 of solder bumps 126 extending therefrom. 如下文将要详细描述的,当把两个或更多个图3所示的微电子封装彼此堆叠在一起时,衬底124的第一表面126上的导电柱的高度a和焊料块148的高度li通常大于或等于密封剂层136的高度,以便跨越由密封剂层136的高度产生的间隙。 As will be described in detail, when two or more microelectronic shown in Figure 3 package stacking height of a solder bump and the first surface of the conductive pillar together, the substrate 124 126 148 height each other li generally greater than or equal to the height of the sealant layer 136, so that the gap across the height of the sealant layer 136 produced.

图4A示出了与图3中所示的封装类似的两个微电子封装122A、 122B。 Figure 4A shows the package shown in FIG. 3 is similar to two microelectronic packages 122A, 122B. 第一微电子封装122A包括衬底124A、导电柱130A、可熔块148A和被密封的微电子元件132A、 134A。 The first microelectronic package 122A includes a substrate 124A, conductive pillar 130A, 148A and can be sealed frit microelectronic element 132A, 134A. 微电子元件132A、 134A被具有底表面154A的密封剂层136A密封。 Microelectronic element 132A, 134A are having a sealant layer 136A 154A of the bottom surface of the seal. 密封剂层136A的底表面154A界定了在衬底124A的第二表面128A和密封剂层136A的底表面154A之间延伸的第一高度H,。 The bottom surface of the sealant layer 136A 154A defines a first height H between the bottom surface 154A of the substrate surface 128A and 124A of the second sealant layer 136A extending ,. 导电柱130A界定了在其末端131A和衬底124A的第二表面128A之间延伸的第二高度H2。 Conductive stud 130A defines a second height H2 between the second surface of the ends 131A and 128A 124A extending the substrate. 焊料块148A界定了在焊料块的顶点151和衬底124A的第一表面126A之间延伸的第三高度H3。 Solder bumps 148A defines a third height H3 between the first surface 126A of the substrate 151 and the vertex of the solder bumps 124A extending. 第二微电子封装122B包括具有第一表面126B和第二表面128B的衬底124B。 The second microelectronic package 122B includes a substrate having a first surface and a second surface 126B 128B of 124B.

参考图4B,第一微电子封装122A被堆叠在第二微电子封装122B上, 导电柱的末端131A与焊料块148B的顶点配合。 4B, the first microelectronic package 122A is stacked on the second microelectronic package 122B, 131A and solder terminal block 148B of the conductive columns with vertices. 导电柱的高度&和焊料块的高度H3的组合高度优选等于或大于密封剂层136A的高度&。 H3 height and solder bump height & conductive column preferably equal to or greater than the combined height of the sealant layer 136A height &.

参考图4C,在导电柱131的末端131抵靠到可熔块之后,例如通过加热对可熔块进行回流,以使可熔块变成至少部分熔化的状态。 Refer to Figure 4C, the conductive end of the column 131 to 131 against the frit can then, for example by heating to reflux clinker, clinker becomes so can at least partially melted state. 回流的可熔材料优选通过毛细作用被吸附到导电柱外表面周围。 Reflux fusible material preferably is adsorbed by capillary action to the outer peripheral surface of conductive pillars. 在回流状态下,可熔块利用表面张力来对导电柱自定心。 At reflux, can use surface tension frit conductive pillar self-centering. 结果,第一微电子封装122A的导电柱优选与第二微电子封装122B的导电柱基本对准。 As a result, the first microelectronic package 122A and the second conductive pillar is preferably a microelectronic package 122B are substantially aligned conductive pillars. 表面张力还将第一微电子封装122A和第二微电子封装122B相互拉近。 Surface tension will first microelectronic package 122A and 122B of the second microelectronic package closer to each other.

图5A-5C示出了根据本发明另一优选实施例的微电子组件220。 Figures 5A-5C shows a microelectronic assembly 220 according to another preferred embodiment of the present invention. 微电子组件220包括具有衬底224的第一微电子元件222,衬底224具有第一表面226和远离其的第二表面228。 Microelectronic assembly 220 includes a first microelectronic element 224 having a substrate 222, a substrate 224 having a first surface 226 and away from the second surface 228 thereof. 第一衬底224包括可在第二表面228触及的导电焊盘230A-230J。 The first substrate 224 includes a second surface 228 accessible conductive pads 230A-230J in. 第一微电子封装222还具有附着于衬底的一个或多个微电子元件,例如半导体芯片。 A first microelectronic package 222 also has one or more microelectronic elements attached to the substrate, such as a semiconductor chip. 在图5A所示的特定实施例中,第一微电子封装222包括第二表面228上的第一微电子元件232以及第一微电子元件 In the particular embodiment shown in FIG. 5A embodiment, the first microelectronic package 222 includes a second upper surface 228 of the first microelectronic element 232 and a first microelectronic element

上的第二微电子元件234。 On the second microelectronic element 234. 密封剂层236覆盖微电子元件232、 234。 Sealant layer 236 covering the microelectronic element 232, 234. 密封剂层具有底表面254,其界定了密封剂层底表面和衬底224的第二表面228 之间的距离。 A sealant layer having a bottom surface 254, 228 which defines the distance between the second surface and the bottom surface of the sealant layer 224 of the substrate.

导电焊盘230A-230J具有与图1A和2A的实施例所示的间隔类似的间隔。 Conductive pads 230A-230J having FIGS. 1A and 2A, the illustrated embodiment is similar to the spacing interval. 然而,图5A的特定实施例使用了细长的导电柱248A-248J,而不是图1A和2A实施例所示的焊料块。 However, the particular embodiment of Figure 5A uses an elongated conductive pillars 248A-248J, FIG. 1A and 2A instead of the embodiment shown in the solder bumps. 结果,有足够的空间供一个导电柱248从每个导电焊盘230突出而不会使相邻的导电柱彼此接触,如以上图1A和2A 实施例所示,在导电焊盘和接触上都使用焊球时会发生所述接触。 As a result, there is enough space for a conductive stud 248 protruding from each of the conductive pads 230 adjacent conductive column without making contact with each other, as described above in Example 1A and 2A, on the conductive pads and contacts are It occurs when you use the contact balls. 于是, 能够具有来自第一微电子封装222的更多输入/输出并形成更多电互连。 Thus, it is possible to have more microelectronic package 222 from the first input / output and the formation of more electrically interconnected.

微电子组件220还包括具有第二衬底240的第二微电子封装238,第二衬底240具有第一表面242和远离其的第二表面244。 Microelectronic assembly 220 further includes a second substrate having a second microelectronic package 240 238, a second substrate 240 having a first surface 242 and away from the second surface 244 thereof. 第一表面242包括接触246A-246J。 The first surface 242 includes a contact 246A-246J. 焊球250设置于每个接触246A-246J上。 Solder balls 250 provided on each of the contact 246A-246J.

参考图5B,第一衬底224的第一表面228与第二衬底240的第一表面242并置。 5B, a first surface 228 of the first substrate 224 and the first surface of the second substrate 242 and 240 is set. 导电柱248的末端231抵靠在焊球250的顶点。 The end of the conductive pillar 248 231 250 abuts balls vertices. 密封剂层236的底表面254界定了在密封剂层底表面254和衬底224的第二表面228之间延伸的高度H,。 Sealant layer bottom surface 236 of 254 defines the height H in the sealant layer extending between the bottom surface 228 of the second surface of the substrate 254 and 224 ,. 导电柱230界定了在柱末端231和第一衬底224的第二表面228之间延伸的高度H2。 Conductive post 230 defines the height H2 between the end of the column 231 and the second surface 228 of the first substrate 224 extends. 焊球250界定了在焊球顶点和第二衬底240的第一表面242之间延伸的高度H3。 Solder balls 250 defines the height H3 between the balls and the first surface of the second substrate apex 240 242 extends. 导电柱和焊球的组合高度H2和ft等于或大于密封剂层236的高度仏。 Conductive post and ball combination ft height H2 and the sealant layer is equal to or greater than 236 highly 仏. 结果,导电柱230和焊球250的组合足以跨越由密封剂层的高度产生的间隙。 As a result, a combination of conductive pillar 230 and ball 250 is sufficient to span the gap height of the sealant layer is generated.

图5C示出了在已经对焊料材料250进行回流并将其吸附到导电柱230 的侧面之后的微电子组件220。 Figure 5C shows the solder material 250 after having carried out the adsorption to the conductive pillar and the side surface 230 of the microelectronic assembly 220 of its reflux. 随着焊料材料250吸附到导电柱的侧面,表面张力将第一微电子封装222和第二微电子封装238彼此拉向一起。 As the solder material 250 to the side surface of the conductive adsorption column, the surface tension of the first and second microelectronic packages 222 each microelectronic package 238 to pull together. 此外, 回流的焊料材料提供了自定心功能,由此使导电柱230位于第二微电子封装238的接触246的顶部中心。 In addition, solder reflow material provides self-centering function, whereby the conductive pillar 230 is located in the top center of the second microelectronic package contacts 238 246.

图6A和6B示出了本发明的自定心特征。 6A and 6B illustrate a self-centering feature of the present invention. 参考图6A,第一微电子封装322A与第二微电子封装322B并置。 6A, the first and second microelectronic packages 322A and 322B is set microelectronic package. 导电柱330的末端抵靠在第二微电子封装322B上的焊料块348上。 The end of the conductive post 330 abuts against the solder bumps 348 on the second microelectronic package 322B. 在该特定实施例中,导电柱330至少部分地与焊料块348不对准。 In this particular embodiment, the conductive pillar 330 at least partially with the solder bumps 348 are not aligned. 图6A中示出了失准,因此第一微电子封装322A上的导电柱330D沿轴Ai延伸,第二微电子封装322B上的导电柱330D'沿不同于 Figure 6A shows a misalignment, thus 330D conductive pillars along a first axis Ai microelectronic package 322A on the extended conductive studs 330D on the second microelectronic package 322B 'direction different from

轴A,的轴A2延伸。 Axis A, the axis A2 extends. 结果,第一微电子封装上的导电柱未与第二微电子封装322B上的焊料块348基本对准。 As a result, the conductive column is not the first microelectronic packages with solder bumps on microelectronic packaging 322B on the second 348 substantially aligned.

参考图6B,在第二微电子封装322B上的焊料回流期间,回流的焊料吸附到导电柱外表面周围并提供自定心作用,迫使第一微电子封装322A的导电柱与第二微电子封装322B的导电柱基本对准。 With reference to Figure 6B, during solder reflow 322B on the second microelectronic package, solder reflow adsorbed to the outer circumferential surface of the conductive pillar and provide a self-centering effect, forcing the first microelectronic package 322A and the second conductive studs microelectronic package The conductive pillars 322B are substantially aligned. 如图6B所示,第一微电子封装322A的第一导电柱沿轴Al对准,第二微电子封装的第二导电柱沿轴A2 对准,由此轴Al和A2现在位于公共轴上。 As shown in Figure 6B, the first conductive studs first microelectronic package 322A is aligned along the axis Al, the second conductive studs second microelectronic package is aligned along axis A2, whereby Al and A2 axes are in a common axis . 作为自定心作用的结果,第一和第二微电子封装322A、 322B的导电柱现在基本彼此对准。 As a result of self-centering effect, the first and second microelectronic package 322A, 322B of the conductive pillar is now substantially aligned with each other.

图6B示出了方向箭头D,其示出了在焊料块的回流期间第一微电子封装322A相对于第二微电子封装322B的移动。 6B shows a direction of arrow D, which shows the solder bumps during reflux with respect to the first microelectronic package 322A and 322B to move the second microelectronic package. 此外,如上所述,回流的焊料提供表面张力,所述表面张力将第一和第二微电子封装322A、 322B彼此拉向一起。 In addition, as described above, to provide a surface tension of the solder reflow, the surface tension of the first and second microelectronic packages 322A, 322B to pull each other together.

图7示出了包括四个堆叠层的堆叠微电子组件的局部截面图。 Figure 7 shows a partial cross section comprising four stacked layers stacked microelectronic assembly of FIG. 上层的导电柱与下层的可熔导电块电互连。 The upper and lower conductive pillar fusible electrically interconnected conductive block. 在组装期间,将柱体末端置于与相对的可熔导电块接触。 During assembly, the cylinder is placed in contact with the opposite ends of the fusible conductive block. 然后对可熔块进行回流,由此回流的块吸附到导电柱外表面周围。 Then be frit reflux, thus returning to block adsorption columns around the outer conductive surface.

在某些优选实施例中,衬底可以是诸如聚酰亚胺或其它聚合物片的柔性电介质衬底,其包括顶表面和远离其的底表面。 In certain preferred embodiments, the substrate may be a flexible dielectric substrate such as a polyimide or other polymer sheet, comprising a top surface and away from the bottom surface thereof. 虽然电介质衬底的厚度可以随着应用而变化,但电介质衬底最典型的厚度大约为10um-100ym。 Although the thickness of the dielectric substrate may vary with the application, but the most typical thickness of the dielectric substrate is approximately 10um-100ym. 柔性片上优选具有导电迹线。 The flexible sheet is preferably electrically conductive traces. 导电迹线可以在柔性片的顶表面上,在顶表面和底表面二者上或在柔性衬底内部延伸。 Conductive traces may be on the top surface of the flexible sheet on the top surface and a bottom surface extending both or inside a flexible substrate. 于是,如本公开中所使用的, 将第一特征设置于第二特征"上"这种表述不应被理解为要求第一特征位于第二特征的表面上。 Thus, as used in this disclosure, the first feature to the second feature set 'on' This statement should not be understood as requiring characterized located on the first surface of the second feature. 导电迹线可以由任何导电材料形成,但最典型地由铜、铜合金、金或这些材料的组合形成。 Conductive traces may be formed from any conductive material, but most typically formed of copper, copper alloy, gold, or a combination of these materials. 迹线的厚度也将随着应用而变化, 但典型的大约为5um-25um。 Trace thickness will vary with the application, but typically is about 5um-25um. 可以设置导电迹线,使每条迹线具有支撑端以及远离支撑端的柱端。 You can set the conductive traces, so that each trace has a support end and far end of the end of the support column.

如上所述,在某些优选实施例中,导电柱从衬底的表面突出。 As described above, in certain preferred embodiments, the conductive post protrude from the surface of the substrate. 每个柱体可以连接到一条导电迹线的柱端。 Each cylinder can be connected to one end of the column conductive traces. 在某些优选实施例中,导电柱可以从迹线的柱端通过衬底向上延伸。 In certain preferred embodiments, the conductive pillar may extend upwardly from the column ends traces through the substrate. 导电柱的尺度可以在很大范围内变化,但最典型的是柔性片表面上的每个柱高度大约为50-300 um。 Scale conductive vias can vary widely, but the most typical is that each column height on the surface of a flexible sheet of about 50-300 um. 每个柱体优选具 Each column preferably has

有与衬底相邻的基底部和远离衬底的末端。 A terminal base portion of the substrate adjacent to and away from the substrate. 导电柱可以具有截头圆锥形状, Conductive pillars may have a frusto-conical shape,

由此每个柱体的基底部和末端基本为圆形。 Thus the base and the end of each cylinder is substantially circular. 柱体基底部典型为大约100-600 ym的直径,而末端典型为大约40-600um的直径,更优选为大约40-200 Pm的直径。 The base cylinder typically about 100-600 ym in diameter, and typically about 40-600um end diameter, more preferably about 40-200 Pm diameter. 柱体可以由任何导电材料形成,但最好由诸如铜、铜合金、金及其组合的金属材料形成。 Cylinder can be formed of any conductive material, but is preferably formed of a metal material such as copper, copper alloys, gold and combinations thereof. 例如,柱体可以主要由铜形成,在柱体表面具 For example, the column may be primarily formed of copper, the cylindrical surface having

有一层金。 A layer of gold.

可以通过诸如2004年10月6日提交的共同审查、共同转让的美国专利申请No. 10/959465 [TESSERA 3. 0-358]中所公开的工艺那样制造电介质衬底、迹线和柱体,在此通过引用将其公开并入本文。 Such as a joint review by October 6, 2004 filed commonly assigned U.S. Patent Application No. 10/959465 [TESSERA 3. 0-358] disclosed manufacturing process as a dielectric substrate, traces and column, In this disclosure is incorporated by reference herein. 如,465申请所更详细公开的,蚀刻金属板或以其它方式处理金属板以形成很多从板突出的金属柱。 For example, 465 disclosed in more detail herein, the etched metal plate or otherwise treated metal plate to form a lot of metal protruding from the plate cylinder. 向该板施加电介质层,使柱体经过电介质层突出。 The dielectric layer is applied to the plate, so that the cylinder projecting through the dielectric layer. 电介质层的内部或侧面面对金属板,而电介质层的外侧面对柱体的末端。 Or the internal side of the dielectric layer facing the metal plate, and the outer end face of the dielectric layer cylinder. 可以通过将诸如聚酰亚胺的电介质涂布到板上和柱体周围,或者更典型的,通过迫使柱体与电介质片配合使得柱体穿透该片,从而制造电介质层。 Can be obtained by coating such as a polyimide dielectric and the cylinder surrounding the board, or, more typically, by forcing the dielectric sheet with the cylinder such that the cylinder through the sheet, thereby manufacturing the dielectric layer. 一旦片到位,就蚀刻金属板以形成电介质层内侧上的各迹线。 Once the pieces in place, etching the metal plate to form the inner side of each trace dielectric layer. 或者,诸如电镀或蚀刻的常规工艺可以形成迹线,然而可以使用共同转让的美国专利6177636中公开的方法形成柱体(在此通过引用将其公开并入本文)。 Alternatively, a conventional process such as plating or etching traces can be formed, but the method can be used commonly assigned U.S. Patent No. 6,177,636 discloses forming cylinder (herein incorporated by reference in the disclosure herein). 在又一种选择中,可以用任何适当的方式将柱体制造成单个元件并组装到柔性片上,柔性片将柱体连接到迹线。 In yet another alternative, can be used in any suitable manner pillar system will result in a single element and assembled on a flexible film, a flexible sheet connected to the cylinder trace.

在本发明的某些优选实施例中,导电柱可以彼此独立地自由移动。 In certain preferred embodiments of the present invention, the conductive pillar can be free to move independently of each other. 柱体之间彼此独立地位移允许所有柱体末端接触相对微电子元件上的所有接触。 Displacement between the cylinder independently from each other to allow access to all end all contact with the opposing cylinder microelectronic element. 例如,第一导电柱附近的柔性衬底能够比第二导电柱附近的柔性衬底更加显著地弯曲。 For example, flexible substrate a first conductive pillar can be bent near the more remarkable than the flexible substrate near the second conductive studs. 因为可以将所有柱体末端与相对微电子元件的所有接触可靠地配合,所以可以通过经测试电路板和经配合的柱体和接触焊盘施加测试信号、功率和地电势来可靠地测试封装。 Because surely you can fit all cylinder end all contacts with the opposite microelectronic components, it is possible to reliably test the package has been tested by the board and by the mating contact pads applied to the column and test signals, power and ground potential. 此外,利用简单的测试电路板实现了可靠的配合。 In addition, the use of a simple test circuit boards for reliable mating. 例如,测试电路板的接触焊盘是简单的平面焊盘。 For example, the contact pad test circuit board is a simple flat pads. 测试电路板无需包括补偿非平面性的特殊功能部件或复杂的插座构造。 Test boards need to include compensation for non-planarity of the special features or complex socket construction. 可以利用形成普通电路板通用的技术来制造测试电路板。 Ordinary circuit board can be formed common technology to manufacture the test circuit boards. 这本质上降低了测试电路板的成本,还便于构造简单布局、与高频信号兼容的带有迹线(未示出)的测试电路板。 This essentially reduces the cost of test circuit board layout also facilitates simple structure, compatible with the high-frequency signal traces (not shown) of the test board. 而且,根据特定高频信号处理电路的需要,测试电 Furthermore, according to the specific needs of the high-frequency signal processing circuit, Test

路板可以包括与接触焊盘非常靠近的诸如电容器的电子元件。 Circuit board may include electronic components and contact pads are very close, such as capacitors. 这里,再次因为测试电路板无需包括适应非平面性的特殊功能部件,这种电子元件的放置得到简化。 Here, again, because the test circuit board need not include special adaptation of the non-planar features, the placement of electronic components is simplified. 在一些情况下,希望尽可能使测试电路板平面化,以便减小系统的非平面性并从而使对管脚移动的需求最小化。 In some cases it is desirable to make the test board as flat, in order to reduce the system's non-planarity and thus the demand for pin movement is minimized. 例如,在测试电路板为高度平面化的陶瓷电路板(例如抛光的氧化铝陶瓷结构)的情况下, For example, the test circuit board is a highly planarized ceramic circuit boards (e.g., polished alumina ceramic structure) of the case,

仅仅约为20 um的管脚移动就足够了。 Only about 20 um pin movement is sufficient.

在本发明的某些优选实施例中,在测试过微电子封装之后,可以从测试电路板取下封装,并通过用诸如焊料的导电接合材料将柱体末端结合到电路面板的接触焊盘,将所述封装永久地与诸如电路面板的具有接触焊盘的另一衬底互连在一起。 In certain preferred embodiments of the present invention, the microelectronic package after tested, the test board can be removed from the package, and solder the conductive bonding material by binding the ends of the cylinder such as to contact pads of the circuit panel, the permanently with the package, such as a circuit panel having contact pads of another substrate are interconnected. 可以利用表面安装微电子组件的通用常规设备来执行焊料接合过程。 Microelectronic assembly can use a common surface mounted device to perform the conventional solder bonding process. 于是,可以在柱体或接触焊盘上提供焊料块,并在将柱体与接触焊盘配合之后对其进行回流。 Thus, the solder bumps may be provided on the cylinder or contact pads and the contact pads after the cylinder with its reflux. 在回流期间,焊料的表面张力会使柱体在接触焊盘上居中。 During reflow, the solder surface tension causes the cylinder centered on the contact pad. 这种自定心作用在柱体末端小于接触焊盘的情况下尤其显著。 The case of such self-centering in the column is less than the end of the contact pads are particularly significant. 此外,焊料至少在一定程度上润湿柱体侧面,从而形成包围每个柱体末端的过渡曲面(fillet)以及柱体和焊盘相对表面之间的强 In addition, at least to some extent, solder wetting cylinder side, thereby forming a strong surface surrounding the transition at the end of each column (fillet) and the cylinder and the pad between the opposing surfaces

可以在柱体末端周围和接触焊盘周围提供诸如环氧树脂或其它聚合材料的底填材料(未示出),以便加强焊料结合。 It may be provided, such as an epoxy resin or other polymeric materials, underfill material (not shown), in order to enhance solder bonding contact pads around and around the end of the cylinder. 希望该底填材料仅部分地填充封装和电路板之间的间隙。 We hope the underfill material only partially fills the gap the package and the circuit board. 在这种设置中,底填不会将柔性衬底或微电子器件结合到电路板。 In this arrangement, the bottom will not fill a flexible substrate or a microelectronic device coupled to the circuit board. 底填仅在柱体与接触焊盘的连接处加强了柱体。 Underfill only strengthen the cylinder in connection with the contact pads of the column. 然而,在柱体基底部不需要任何加强,因为每个柱体基底部和相关迹线之间的连接特别抗疲劳破坏。 However, at the bottom of the cylinder base without any strengthened, as the bottom of each column base connection between the traces and the associated special anti-fatigue damage.

以上讨论涉及到单个微电子元件。 Discussed above relate to a single microelectronic components. 然而,封装可以包括一个以上的微电子元件或一个以上的衬底。 However, the package may include one or more microelectronic substrate, or more than one element. 此外,可以在芯片为晶片形式期间执行用于将柔性衬底、支撑元件和柱体组装到芯片上的工艺步骤。 In addition, the chip may be in the form of a wafer during execution for a flexible substrate, the supporting member and the cylinder assembly to process step chip. 可以将单个大衬底组装到整个晶片或晶片的一些部分上。 Single large substrate can be assembled into a number of parts of the entire wafer or wafer. 可以切割组件以形成单个单元, 每个单元包括一个或多个芯片以及衬底的相关部分。 It can be cut to form a single assembly unit, each unit comprising one or more of the relevant parts of the chip and the substrate. 上面讨论的测试操作可以在切割步骤之前执行。 Test operations discussed above may be performed before the cutting step. 封装补偿测试板中或晶片本身中的非平面性的能力极大地方便了大单元的测试。 Compensation package test plate or wafer non-planarity itself greatly facilitates the ability to test large unit.

衬底和迹线可能在柱体周围的区域中发生局部形变。 Substrate and traces local deformation may occur in the area around the cylinder. 这些区域往往会 These areas tend to

向上形变,从而在衬底的底表面中留下凹坑。 Upward deformation, leaving the pits on the bottom surface of the substrate. 柱体可以具有头部,这些头部可以部分或完全进入凹坑之内。 May have a cylinder head, the head may partially or completely into the pits. 为了控制衬底的形变,可以将衬底的顶表面抵靠在具有孔的管芯上,该孔与迫使柱体穿过衬底的位置对准。 In order to control the deformation of the substrate may be a top surface of the substrate has a hole abuts against the die on the cylinder through the hole and forces the position of the substrate alignment. 这种管芯也能够防止衬底和迹线分离。 This die can be prevented and traces separate substrate. 在该工艺的变型中,可以在单层衬底的顶表面或底表面上设置迹线。 In this process variant, you can set the trace on the top or bottom surface of a single layer of the substrate. 可以将所得的柱阵列衬底与微电子元件组装到一起以形成上述封装,或者可以将其用在希望具有小的柱阵列的任何其它微电子组件中。 The resulting column array substrate with microelectronic elements can be assembled together to form the package, or it may be used in any other desired microelectronic assembly having a small column array. 该组装工艺允许选择性地设置柱体。 The assembly process allows to selectively cylinder. 在迹线中提供焊接区和孔并不重要。 Provide pads and traces holes is not important. 于是,可以沿着任何迹线在任何位置设置柱体。 Thus, you can set the column at any position along any trace. 此外, 基本可以由任何导电材料形成柱体。 In addition, the basic pillar may be formed of any conductive material. 可以用不同的材料形成不同的柱体。 You can use different materials to form different column. 例如,可以全部或部分地由诸如鸨的坚硬难熔金属形成要经受剧烈机械载荷的柱体,而可以由诸如铜的较软金属形成其它柱体。 For example, all or a portion formed of such hard refractory metal bustard subjected to intense mechanical loading cylinder, but may be formed of a relatively soft metal such as copper forming the other cylinder. 而且,可以全部或部分地由诸如镍、金或铂的耐腐蚀金属形成一些或全部柱体。 Further, in whole or in part by a corrosion resistant metal such as nickel, gold or platinum formed on some or all cylinders.

如以上较早实施例所述,导电柱可以独立于其它导电柱自由移动,从而确保每个导电柱与测试板上每个导电焊盘之间的可靠接触。 As described above the earlier embodiment, the conductive pillars can be independent of other conductive columns to move freely, to ensure reliable contact with each conductive pillar and the test board between each of the conductive pads. 导电柱的末端能够移动以补偿垂直间隔方面潜在的差异,从而仅通过施加适中的垂直力将可测试封装和测试板压到一起就可以使所有末端与所有导电焊盘同时接触。 The end of the conductive vias can be moved in a vertical aspect compensation interval potential difference, so that only by applying a moderate vertical force will be testing and packaging and test panel pressed together at the same time can make all end all contact with the conductive pads. 在该过程中,至少一些导电柱的末端相对于其它柱体末端在垂直或Z 方向上位移。 In this process, at least some of the end of the conductive pillar end of the cylinder relative to the other in the vertical or Z direction displacement. 此外,与不同导电柱相关联的柔性衬底的不同部分可以彼此独立地形变。 In addition, the different parts of the flexible substrate associated with the different conductive pillars can be changed independently from each other terrain. 在实践中,衬底的形变可以包括衬底的弯曲和/或拉伸,从而 In practice, the substrate may comprise a curved deformation and / or stretching of the substrate, thereby

基底部的运动可以包括绕xy平面或水平面中的轴倾斜以及基底部的一些水平位移,且还可以包括其它运动分量。 Movement of the base may include a number of horizontal displacement xy plane about a horizontal or inclined axis and the base portion, and may also include other moving components.

由于诸如微电子器件正面的非平面性、电介质衬底的翘曲和柱体自身的不等高度等因素,柱体末端可能不会精确地彼此共面。 Due to unequal microelectronic device such as a positive non-planarity, and the dielectric substrate warpage own column height and other factors, the cylinder may not end exactly coplanar with each other. 而且,封装相对于电路板可能会稍微倾斜。 Also, the package with respect to the circuit board may be slightly tilted. 由于这些和其它原因,柱体末端和接触焊盘之间的垂直距离可能是不等的。 Because the vertical distance between these and other reasons, the end of the cylinder and between the contact pads may be unequal. 柱体之间彼此独立的位移允许所有柱体末端接触相对微电子封装上的所有接触焊盘。 Separate cylinder displacement between each other to allow all the cylinder end all contact with the opposing contact pads microelectronic package on.

因为可以将所有柱体末端与所有接触焊盘可靠地配合,所以可以借助经测试电路板和经相配合的柱体和接触焊盘施加测试信号、功率和地电势来可靠地对封装进行测试。 Because you can be all end all contact pad cylinder fitted reliable, so you can test the circuit board by means of the cylinder and the contact pads and by applying a test mating signals, power and ground potential to reliably test the package. 此外,利用简 In addition, the use of simple

需包括补偿非平面性的特殊功能部件或复杂的插座构造。 It should include compensation for the non-planarity of the special features or complex socket construction. 可以利用形成普通电路板通用的技术来制造测试电路板。 Ordinary circuit board can be formed common technology to manufacture the test circuit boards. 这本质上降低了测试电路板的成本,并且还便于构造简单布局的、与高频信号兼容的带有迹线(未示出) 的测试电路板。 This essentially reduces the cost of testing a circuit board, and also convenient to construct simple layout that is compatible with high-frequency signal test circuit board with traces (not shown). 而且,根据特定高频信号处理电路的需要,测试电路板可以包括与接触焊盘非常靠近的诸如电容器的电子元件。 Furthermore, according to the specific needs of the high-frequency signal processing circuit, the test circuit board may include electronic components and very close to the contact pads, such as a capacitor. 这里,再次因为测试电路板无需包括适应非平面性的特殊功能部件,这种电子元件的放置得到简化。 Here, again, because the test circuit board need not include special adaptation of the non-planar features, the placement of electronic components is simplified. 在一些情况下,希望尽可能使测试电路板平面化,以便减小系统的非平面性并从而使对管脚移动的需求最小化。 In some cases it is desirable to make the test board as flat, in order to reduce the system's non-planarity and thus the demand for pin movement is minimized. 例如,在测试电路板为高度平面化的陶瓷电路板(例如抛光的氧化铝陶瓷结构)的情况下,仅仅约 For example, in the circuit board under test is highly planarized ceramic circuit boards (e.g., polished alumina ceramic structure), it is only about

为20um的管脚移动就足够了。 As 20um pin move is sufficient.

在本发明的某些优选实施例中,可以在微电子封装的-一个或多个导电部分上提供颗粒涂层,例如美国专利4804132和5083697 (在此通过引用将其公开并入本文)所公开的颗粒涂层,以增强微电子元件之间的电互连的形成并便于微电子封装的测试。 In certain preferred embodiments of the present invention, it may be packaged microelectronic - providing a coating on one or more of the particles of conductive portions, e.g., U.S. Patent No. 4,804,132 and 5,083,697 (herein incorporated by reference in the disclosure herein) as disclosed The particle coating to enhance the electrical interconnection between the microelectronic components and to facilitate the formation of a microelectronic package test. 优选在诸如导电端子或导电柱的末端等导电部分上提供颗粒涂层。 Particle coating is preferably provided on the conductive portion such as the conductive terminal end of the conductive pillars or the like. 在一个特别优选的实施例中,颗粒涂层为金属化金刚石晶体涂层,其是利用标准光刻胶技术选择性电镀到微电子元件的导电部分上的。 In a particularly preferred embodiment, the particles of the coating is a metal coating diamond crystal, which is selectively plated using standard photoresist techniques to the conductive portion of the microelectronic element. 在操作中,可以将具有金刚石晶体涂层的导电部分压到相对的接触焊盘上,以穿透接触焊盘外表面存在的氧化层。 In operation, a conductive part may be pressed into the diamond crystal coating on the opposing contact pads, the contact pads to penetrate the outer oxide layer present on the surface. 除了传统的擦触作用之外,金刚石晶体涂层促进了通过穿透氧化物层来形成可靠的电互连。 In addition to the traditional role of rubbing contact, diamond crystal coating promotes the electrically interconnected by penetrating the oxide layer to form reliable.

如上所述,柱体的运动可以包括倾斜运动。 As described above, the cylinder movement may include a tilting movement. 该倾斜运动导致每个柱体的末端在末端与接触焊盘配合时与接触焊盘擦触。 The campaign led to the end of each column tilt at the end of the contact pad with rubbing contact with the contact pads. 这促进了可靠的电接触。 This promotes a reliable electrical contact. 如在2004年11月10日提交的共同审查、共同转让的题为"MICRO PIN GRID ARRAY WITH WIPING ACTION" [TESSERA 3. 0-375]的申请No. 10/985126 (在此通过引用将其公开并入本文)中更详细描述的,所述柱体可以具有促进这种擦触作用或者有助于柱体和接触配合的特征。 As in common review November 10, 2004 submitted commonly assigned, entitled "MICRO PIN GRID ARRAY WITH WIPING ACTION" [TESSERA 3. 0-375] Application No. 10/985126 (by reference to its public incorporated herein) described in more detail, the column may have the role of promoting such rubbing contact or help cylinder and contact mating features. 如在2004年11月10日提交的共同审査、共同转让的题为"MICRO PIN GRID WITH PIN MOTION ISOLATION" [TESSERA 3. 0-376]的申请No. 10/985119 (在此通过引用将其公开并入本文)中更详细公开的,柔性衬底可以具有增强柱体彼此独立移动的能力并增强倾斜和擦触作用的特征。 As in common review November 10, 2004 submitted commonly assigned, entitled "MICRO PIN GRID WITH PIN MOTION ISOLATION" [TESSERA 3. 0-376] Application No. 10/985119 (herein by reference in its disclosure is incorporated herein) as disclosed in more detail, the flexible substrate may have enhanced ability to move independently of each other cylinder and tilt and enhanced contact wiping action feature.

在本发明的某些优选实施例中,微电子封装、组件或堆体可以包括如下专利申请中所公开的一个或多个实施例的一个或多个特征:2004年10月6日提交的题为"Formation of Circuitry With Modification of Feature Height" [TESSERA 3. 0-358]的美国申请No. 10/959465; 2005年6月24日提交的题为"Structure With Spherical Contact Pins" [TESSERA 3. 0-416] 的美国申请No. 11/166861:2004年12月16日提交的美国申请No. 11/014439[TESSER a. 3. 0-374],其要求2003年12月30日提交的美国临时申请No. 60/533210的优先权;2004年11月10日提交的美国申请No. 10/985126[TESSERA 3.0-375],其要求2003年12月30日提交的美国临时申请No. 60/533393的优先权;2004年11月10日提交的美国申请No. 10/985119[TESSERA 3.0-376],其要求2003年12月30日提交的美国临时申请No. 60/533437的优先权;2005年5月27日提交的美国专利申请No. 11/140312[TESSERA 3.0-415],其要求2004年6月25日提交的美国临时申请No. 60/583066以及2004年10月25日提交的美国临时申请No. 60/621865的优先权;2005年3月16日提交的美国临时申请No. 60/662199 [TESSERA 3.8-429]; 美国专禾U 申请公布No. 2005/0035440 [TESSERA 3. 0-307];以及2005年12月23日提交的题为"MICROELECTRONIC PACKAGES AND METHODS THEREFOR "的序列号为No. 60/753605、转让代理文档号为TESSERA 3.8-482的美国临时申请,在此通过引用将其公开并入本文。 In certain preferred embodiments of the present invention, microelectronic packaging, assembly or stack may include one or more of the following features as disclosed in the patent application to one or more embodiments: title October 6, 2004 filed for the "Formation of Circuitry With Modification of Feature Height" [TESSERA 3. 0-358] US Application No. 10/959465; entitled June 24, 2005 filed "Structure With Spherical Contact Pins" [TESSERA 3. 0 -416] US Application No. 11/166861: United States December 16, 2004 filed an application No. 11/014439 [TESSER a 3. 0-374], which requires the United States December 30, 2003 to submit the interim. Application No. 60/533210 filed; US November 10, 2004 filed No. 10/985126 [TESSERA 3.0-375], which requires the United States December 30, 2003 filed provisional application No. 60/533393 priority; the United States Nov. 10, 2004 filed No. 10/985119 [TESSERA 3.0-376], which requires the United States December 30, 2003 filed provisional application No. 60/533437 filed; 2005 May 27 filed US Patent Application No. 11/140312 [TESSERA 3.0-415], which requires the United States June 25, 2004 Provisional Application No. 60/583066 filed and October 25, 2004 to U.S. Provisional Application No. 60/621865 filed; the United States March 16, 2005 filed provisional application No. 60/662199 [TESSERA 3.8-429]; United States Patent Application Publication Wo U No. 2005/0035440 [TESSERA 3. 0- 307]; and entitled December 23, 2005 filed "MICROELECTRONIC PACKAGES AND METHODS THEREFOR" Serial No. No. 60/753605, transfer agent docket number TESSERA 3.8-482 of US Provisional Application herein by reference the disclosure of which is incorporated herein.

参考具体实施例,应当理解这些实施例仅仅是本发明的原理和应用的例示。 Reference to specific embodiments, it should be understood that these examples are merely illustrative of the principles and applications of the invention. 因此要理解,可以对例示性实施例作出很多修改,并且可以想到其它布置,而不会脱离如所附权利要求定义的本发明的精神和范围。 Therefore to be understood that the exemplary embodiments can be made a lot of changes, and you can think of other arrangements without departing from the spirit and scope of the appended claims define the invention.

工业实用性声明 Industrial Applicability Statement

本发明在半导体封装行业中具有实用性。 The present invention has utility in semiconductor packaging industry.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
CN102403275A *17 Sep 20104 Apr 2012深南电路有限公司Package on package structure and fabricating method for same
CN102403275B17 Sep 201015 Jan 2014深南电路有限公司Package on package structure and fabricating method for same
CN103620772A *18 Apr 20125 Mar 2014泰塞拉公司Multi-chip module with stacked face-down connected dies
CN104885217A *18 Oct 20132 Sep 2015泰塞拉公司Multiple die stacking for two or more die
US948433316 Feb 20151 Nov 2016Tessera, Inc.Multi-chip module with stacked face-down connected dies
Classifications
International ClassificationH01L25/10, H01L25/065, H01L23/498
Cooperative ClassificationH01L2225/1058, H01L25/0657, H01L2225/1023, H01L2924/3511, H01L2924/1532, H01L2924/15331, H01L25/105, H01L25/50, H01L2924/3011, H01L2924/15311, H01L2224/16
European ClassificationH01L25/50, H01L25/10J
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5 Dec 2012C14Granted