CN101345228B - Substrate for mounting device, manufacturing method thereof, semiconductor module and portable equipment - Google Patents
Substrate for mounting device, manufacturing method thereof, semiconductor module and portable equipment Download PDFInfo
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- CN101345228B CN101345228B CN200710185791XA CN200710185791A CN101345228B CN 101345228 B CN101345228 B CN 101345228B CN 200710185791X A CN200710185791X A CN 200710185791XA CN 200710185791 A CN200710185791 A CN 200710185791A CN 101345228 B CN101345228 B CN 101345228B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention relates to a packaging board and manufacture method thereof, semiconductor module and mobile apparatus. An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region. A solder resist is formed in such a manner as to cover part of the gold plating layer and the wiring pattern corresponding to the boundary region and the wiring region, and the solder resist has a predetermined opening through which to connect to the semiconductor device. A conductive member is connected to the gold plating layer in the electrode region, and a molded resin layer seals the entire semiconductor module.
Description
Technical field
The present invention relates to element mounting substrate, particularly have the element mounting substrate of pad electrode.
Background technology
Portable electric appts such as mobile phone, PDA, DVC, DSC are in the process of quickening its multifunction, and this product for realizing this point, needs a kind of high integrated system LSI in order to be accepted just must reach miniaturization, lightweight by market.On the other hand, for this electronic equipment, it is more convenient that people require to use, and for the LSI that uses on equipment, then require multifunction, high performance.For this reason, follow the highly integrated of LSI chip on the one hand, increase its I/O quantity, on the other hand, requirement for the miniaturization of encapsulation itself is stronger, in order to satisfy the requirement of this two aspect, needs to strengthen being adapted at installing to high-density on the substrate exploitation of the semiconductor packages of semiconductor product.In order to adapt to this requirement, developing so-called CSP (Chip Size Package: various encapsulation technologies chip size packages).
As the example of this encapsulation, known BGA (Ball Grid Array: ball grid array).BGA installs semiconductor chip on base plate for packaging, and it is carried out after the resin forming, forms the technology of solder ball with area-shaped as outside terminal on the surface of opposition side.
Figure 13 is the constructed profile of the BGA N-type semiconductor N module of record in patent documentation 1.This semiconductor device is at a side surface semiconductor element mounted thereon 106 of circuit substrate 110, in the solder ball 112 of opposite side surface engagement as external connection terminals.Wiring pattern 103 (103a of pad electrode portion) in that a side surface setting of circuit substrate 110 is electrically connected with semiconductor element 106 is provided with the 103b of island portion (ラ Application De portion) that engages external connection terminals on the opposite side surface of circuit substrate 110.The electrical connection of wiring pattern 103 and the 103b of island portion is, by what carry out in the conductor portion of the internal face setting of the through hole 111 that connects insulated substrate 101.The surface of solder mask 105 protective circuit substrates 110.After the one side surface semiconductor element mounted thereon 106 of circuit substrate 110, seal with sealing resin layer 108.
Figure 14 is the profile of the pad electrode portion (using the section part shown in the X among Figure 13) of amplification semiconductor device shown in Figure 13.The 103a of pad electrode portion with leads such as gold thread 107 and semiconductor element 106 go between and be connected is made of wiring portion and its surperficial Gold plated Layer 104 of covering, and wherein wiring portion is made of copper.Solder mask 105 is arranged to cover the copper wiring portion of the 103a of pad electrode portion, and covers the part of Gold plated Layer 104.The peristome of solder mask 105 with after lead-in wire is connected etc., utilizes sealing resin layer 108 and semiconductor element 106 to be sealed in the lift-launch of carrying out semiconductor element 106.
Patent documentation 1:(Japan) spy opens the 2005-197648 communique
Yet,, can not suppress moisture and immerse via interface separately though solder mask 105 and sealing resin layer 108 suppress to immerse these bodies from the moisture of outside.Particularly, because the surface of Gold plated Layer 104 is level and smooth, therefore constitutes moisture and enter the structure of wiring pattern 103 1 sides easily via the interface of itself and solder mask 105.Therefore, there are a lot of moisture near 103 parts of the wiring pattern Gold plated Layer 104.At the moisture that so enters on the surface of wiring pattern 103 further under the situation of diffusion, the copper ion of the part stripping that applies positive voltage of wiring pattern 103 during from the semiconductor module start, with the interface of insulated substrate 101 and with the Interface Moving of solder mask 105, the part that applies negative voltage at wiring pattern 103 is separated out, and produces so-called problem of moving be short-circuited (insulation breakdown) because of ion.This problem is to hinder the big obstacle that improves conventional semiconductor module reliability.
Summary of the invention
The present invention makes in view of the above problems.Technical problem to be solved by this invention is: the moisture that suppresses to immerse from pad electrode portion is in the wiring pattern diffusion into the surface, and improves the reliability of element mounting substrate.
An embodiment of the invention are element mounting substrates.This element mounting substrate is characterised in that, comprising: wiring layer, and it is made of copper, comprises wiring zone and the electrode zone that is connected with this wiring zone, and has stage portion at the borderline region of wiring zone and electrode zone; Gold plated Layer, its wiring layer surface at electrode zone forms; Insulating barrier, it covers the part of Gold plated Layer and the wiring layer in borderline region and wiring zone, and the peristome that has regulation at electrode zone.Here, the electrode of so-called electrode zone is meant the pad electrode that for example is provided with at circuit substrates such as base plate for packaging or module substrates, perhaps the pad electrode that is provided with at the semiconductor element that with the LSI chip is representative.Utilize kind electrode, or element mounting substrate is carried out wire-bonded with the semiconductor element that with LSI is representative be connected, or element mounting substrate and outside semiconductor device are carried out wire-bonded be connected.
According to this execution mode, the distance that on the wiring layer surface, spreads for the moisture that immerses via the interface of Gold plated Layer and insulating barrier, to compare this diffusion length elongated with the situation that prior art is not provided with stage portion like that.Therefore, can suppress moisture and supply with, between wiring layer, be difficult to take place the ion migration to the wiring layer in wiring zone.As a result, can improve the reliability of element mounting substrate.
In the above-described embodiment, preferred stage portion is more recessed and form than the upper surface of the wiring layer in wiring zone.Like this, owing to accumulate moisture easily at the bottom side of stage portion, and this stage portion works as the obstacle that immerses step moisture, therefore can further suppress moisture from the borderline region of wiring layer to the diffusion of wiring zone.As a result, can further improve the reliability of element mounting substrate.
In the above-described embodiment, preferably matsurface processing is carried out on the surface of the wiring layer that is connected with insulating barrier in the borderline region.In this case, owing to be provided with fine concavo-convexly on the surface of the wiring layer of borderline region, therefore the moisture that immerses is elongated and can limit its diffusion in the lip-deep diffusion length of wiring layer.In addition, if be provided with fine concavo-convexly on the surface of wiring layer, owing to improved cementability with insulating barrier in this part, therefore the moisture that immerses more is difficult to diffusion at the wiring layer of borderline region and the interface of insulating barrier.As a result, can further suppress moisture from the borderline region of wiring layer to the diffusion of wiring zone, can further improve the reliability of element mounting substrate.
In the above-described embodiment, wiring layer and insulating barrier are arranged on the substrate, and wiring layer is along the edge part of a side that is connected with substrate, have the gap between itself and substrate, and insulating barrier can form this gap of landfill.Thus, owing to utilize the anchoring effect of the insulating barrier in landfill gap, improved the cementability of wiring layer and insulating barrier, therefore the moisture that immerses more is difficult to diffusion on the wiring layer surface in wiring zone.As a result, can further improve the reliability of element mounting substrate.
Another embodiment of the present invention is a semiconductor module.This semiconductor module is characterised in that, comprising: the element mounting substrate of above-mentioned any execution mode and the semiconductor element of installing at this element mounting substrate.In this embodiment, semiconductor element can be connected by wire-bonded with element mounting substrate.In addition, semiconductor element can be connected by the upside-down mounting chip with element mounting substrate.
Another embodiment of the invention is a portable set.This portable set is characterised in that, is equipped with the semiconductor module of above-mentioned any execution mode.
Another embodiment of the present invention is the manufacture method of element mounting substrate.The manufacture method of this element mounting substrate is characterised in that, comprising: the operation that forms the first metal layer on substrate; The first metal layer is carried out composition, and formation has electrode zone, the operation of the wiring of the borderline region regional and that be provided with between electrode zone and wiring zone that connects up; Form the operation of second metal level on the surface of wiring and substrate; According to the mode that the part of the zone of the regulation around electrode zone, borderline region and electrode zone and borderline region second metal level is exposed, on substrate, form the operation of first mask; Use first mask, optionally remove electrode zone, borderline region and electrode zone and borderline region around second metal level in regulation zone after, dig out the wiring layer of electrode zone and borderline region and the substrate in regulation zone, make the surperficial low operation in the surface ratio wiring zone of borderline region; Remove the operation of first mask; According to the mode that the substrate in the regulation zone around the wiring of electrode zone and the electrode zone exposes, on substrate, form the operation of second mask; Use second metal level as electroplate lead wire, form the operation of Gold plated Layer at electrode zone; Remove the operation of second mask and second metal level; Operation with the wiring layer in a part, borderline region and the wiring zone in insulating barrier coated electrode zone.
In the element mounting substrate manufacture method of above-mentioned execution mode, the first metal layer can use chemical plating and electroplate and form.In addition, second metal level can use chemical plating to form.In addition, Gold plated Layer can be Au-Ni layer or Au-Pb-Ni layer.
In addition, in the element mounting substrate manufacture method of above-mentioned execution mode, also be included in after the formation wiring, the surface of connecting up carried out the operation of roughening.
In addition, in the element mounting substrate manufacture method of above-mentioned execution mode, can be along the edge part of the bottom of the wiring in the zone that insulating barrier covers, between this wiring and substrate, the gap is set after, form insulating barrier.
According to the present invention, the moisture that can suppress to immerse from pad electrode portion improves the reliability of element mounting substrate in the wiring figure diffusion into the surface.
Description of drawings
Fig. 1 is the constructed profile of the semiconductor module with pad electrode of first execution mode;
Fig. 2 is the amplification profile of the pad electrode portion of semiconductor module shown in Figure 1;
Fig. 3 is the amplification view of the pad electrode portion of semiconductor module shown in Figure 1;
Fig. 4 (A)～(D) is the profile of manufacturing process of pad electrode portion that is used to illustrate the semiconductor module of first execution mode;
Fig. 5 (A)～(D) is the profile of manufacturing process of pad electrode portion that is used to illustrate the semiconductor module of first execution mode;
Fig. 6 (A)～(C) is the profile of manufacturing process of pad electrode portion that is used to illustrate the semiconductor module of first execution mode;
Fig. 7 (A) and Fig. 7 (B) are the wiring pattern profiles partly of the semiconductor module of first execution mode and second execution mode;
Fig. 8 is the profile of pad electrode portion of the semiconductor module of expression the 3rd execution mode;
Fig. 9 is the constructed profile of the semiconductor module block structure with pad electrode of expression the 4th execution mode;
Figure 10 is the amplification profile of the pad electrode portion of semiconductor module shown in Figure 9;
Figure 11 is the figure of the handset structure with semiconductor module of expression the 5th embodiment;
Figure 12 is the fragmentary cross-sectional view (profile of first housing) of mobile phone shown in Figure 11;
Figure 13 is the profile of the schematic section structure of the existing BGA N-type semiconductor N device of expression;
Figure 14 is the profile that amplifies the pad electrode portion of semiconductor device shown in Figure 13.
Description of reference numerals
1 insulated substrate; 2 wiring patterns; The 2b stage portion; 4a connects up regional; The 4b borderline region; The 4c electrode zone; 5 Gold plated Layer; 6 solder masks; 8 conductive components; 12 sealing resin layers.
Embodiment
Below, with reference to description of drawings the specific embodiment of the present invention.In institute's drawings attached, identical structural element is represented with identical mark, and is suitably omitted its explanation.
(first execution mode)
Fig. 1 is the constructed profile of the semiconductor module with pad electrode of first execution mode.Fig. 2 is the amplification profile of the pad electrode portion (the section part of representing with X among Fig. 1) of semiconductor module shown in Figure 1.Fig. 3 is the schematic plan view of the pad electrode portion of the semiconductor module shown in Figure 1 seen from upper face side.In addition, Fig. 2 is the profile of the A-A line in Fig. 3.
The semiconductor module of first execution mode is, at the upper surface semiconductor element mounted thereon 7 of element mounting substrate 20, in the structure of its lower surface engages as the solder ball 11 of external connection terminals.At the upper surface of element mounting substrate 20, wiring pattern 27 that be electrically connected with semiconductor element, that be made of copper is set, at the lower surface of element mounting substrate 20, the wiring pattern 9 joint external connection terminals, that be made of copper is set.The electrical connection of wiring pattern 2 and wiring pattern 9 is to realize by the conductor portion that is provided with on the internal face of the via hole 1a that connects insulated substrate 1.Wiring pattern 2 has electrode zone 4c and the stage portion 2b that is provided with Gold plated Layer 5 in its surface, and is connected with semiconductor element 7 by the conductive component 8 of electrode zone 4c.The surface of solder mask 6 and solder mask 10 difference protecting cloth line patterns 2 and wiring pattern 9.In addition, with the upper surface of sealing resin layer 12 potted component board for mounting electronic 20 and the semiconductor element 7 that carries at element mounting substrate 20.
Specifically, as shown in Figure 2, the wiring pattern 2 that on the insulated substrate 1 that plays the effect of core base material, forms, by carrying out that returning of wiring drawn or wiring zone 4a, electrode zone (pad electrode portion) 4c that is connected with semiconductor element 7 of the connection between wiring etc. up and down, and the borderline region 4b that between regional 4a of wiring and electrode zone 4c, is provided with formation.Surface at the electrode zone 4c of wiring pattern 2 is provided with Gold plated Layer 5.The upper surface of the wiring pattern of borderline region 4b forms more recessed than the upper surface of the wiring pattern of the regional 4a of wiring, is provided with stage portion 2b at borderline region 4b.As shown in Figure 3, this stage portion 2b is arranged to cross-section wiring pattern 2.Solder mask 6 is to cover the wiring pattern of the part of Gold plated Layer 5 and borderline region 4b and the regional 4a of wiring and form, and has the peristome 6a that is used for the regulation that is connected with semiconductor element 7.Gold plated Layer 5 in electrode zone 4c connects conductive component 8, with all these structures of sealing resin layer 12 sealings.
In addition, wiring pattern 2 is that " wiring layer ", the regional 4a of wiring are that " wiring zone ", borderline region 4b are that " borderline region ", electrode zone 4c are that " electrode zone ", Gold plated Layer 5 are that " Gold plated Layer ", solder mask 6 are that " insulating barrier " and stage portion 2b are the examples separately of " stage portion ".
Fig. 4～Fig. 6 is the constructed profile of manufacturing process that is used to illustrate the pad electrode portion of element mounting substrate shown in Figure 2.Below, with reference to the manufacturing process of Fig. 2, Fig. 4～Fig. 6 introduction according to the pad electrode portion of the element mounting substrate of first execution mode.
At first, shown in Fig. 4 (A),, utilize electroless plating method and galvanoplastic to form the thick wiring layer 2z of about 20 μ m that constitutes by copper as on the insulated substrate 1 of core base material.
Shown in Fig. 4 (B), adopt photoetching technique on wiring layer 2z, to form Etching mask PR1 with predetermined pattern.
Shown in Fig. 4 (C), the wet etching technique of employing use ferrous chloride carries out wiring layer 2z utilizing wet treatment to remove Etching mask PR1 after the composition.Afterwards, clean processing, peel off the residue that when ashing (ア Star シ Application グ), produces by utilizing medicament.Thus, form wiring pattern 2 with allocated circuit wiring.
Shown in Fig. 4 (D), utilize electroless plating method to plate the copper film 3z that thickness is about 1 μ m on the whole surface of the insulated substrate 1 that comprises wiring pattern 2.
Secondly, shown in Fig. 5 (A), utilize photoetching technique on copper film 3z, to form Etching mask PR2 with predetermined pattern.At this moment, note avoiding on the copper film 3z of electrode zone 4c and borderline region 4b, forming Etching mask PR2.
Shown in Fig. 5 (B), utilize lithographic technique that copper film 3z is carried out utilizing wet treatment to peel off Etching mask PR2 after the composition.Thus, when forming Gold plated Layer 5 in the operation afterwards, be formed for the copper film 3 that wiring pattern 2 is together powered.Electroplate lead wire when in other words, copper film 3 is as formation Gold plated Layer 5.
Shown in Fig. 5 (C), utilize photoetching technique to be formed on to contain the part of the electrode zone 4c of wiring pattern 2 to have the anti-golden Etching mask PR3 of peristome.At this moment, utilize anti-golden Etching mask PR3 to cover borderline region 4b.
Shown in Fig. 5 (D), utilize lithographic technique that the surface of copper film 3 is carried out about the about 5 μ m of soft etching, form stage portion 2a.Thus, when forming Gold plated Layer 5 in the operation afterwards, can reduce the wiring thickness (highly) of pad electrode portion (electrode zone 4c).
Then, shown in Fig. 6 (A), utilize the plating method of selecting, forming thickness on the surface of the wiring pattern 2 of stipulating zone (electrode zone 4c) is the Gold plated Layer (electrolysis Au-Ni plated film) 5 of about 5.5 μ m (the about 5 μ m of about 0.5 μ m/).Afterwards, utilize wet treatment to peel off anti-golden Etching mask PR3.Thus, form Gold plated Layer 5 on the surface selectivity ground of the electrode zone 4c of wiring pattern 2.And Gold plated Layer 5 is not limited to the Au-Ni layer, for example, can also use the Au-Pb-Ni layer as Gold plated Layer 5.
Shown in Fig. 6 (B), utilize lithographic technique to remove copper film 3 by comprehensive etching.At this moment, wiring pattern 2 surfaces for while etching borderline region 4b, make the upper surface of the wiring pattern 2 among the borderline region 4b more recessed, form the stage portion 2b (shoulder height is about 1 μ m) of corresponding copper film 3 thickness at borderline region 4b than the upper surface of the wiring pattern 2 of the regional 4a of wiring.
Shown in Fig. 6 (C), form the solder mask 6 of the peristome 6a with regulation, this solder mask 6 covers the part of Gold plated Layer 5 and the wiring pattern 2 of borderline region 4b and the regional 4a of wiring.Solder mask 6 can be used as the diaphragm of wiring pattern 2.
At last, as shown in Figure 1, conductive component 8 is connected the Gold plated Layer 5 of the electrode zone 4c of wiring pattern 2 by wire-bonded.Here, conductive component 8 adopts gold thread etc.Afterwards, be formed for sealing the sealing resin layer 12 of total.Sealing resin layer 12 is formed on the solder mask 6, forms the electrode zone 4c (Gold plated Layer 5) of comprehensive covering semiconductor element 7 (with reference to Fig. 1) and wiring pattern 2.Sealing resin bed 12 protection semiconductor elements 7 are not subjected to ectocine.The material of sealing resin layer 12 for example is hot curing insulative resins such as epoxy resin.In addition, in sealing resin layer 12, can add the filler that is used to improve thermal conductivity.
Utilize these operations, can obtain the element mounting substrate (the pad electrode portion of element mounting substrate) of first execution mode.
Element mounting substrate and semiconductor module according to first execution mode of above explanation can obtain following effect.
(1) by stage portion 2b being set at borderline region 4b with Gold plated Layer 5, the distance that on the surface of wiring pattern 2, spreads for the moisture that immerses via the interface of Gold plated Layer 5 and solder mask 6, the situation that stage portion is not set like that with prior art is compared, and its diffusion length is elongated.Therefore, can suppress the supply (diffusion) of moisture, between wiring pattern, be difficult to take place the ion migration to the wiring pattern 2 of the regional 4a of wiring.As a result, can improve the reliability of element mounting substrate and semiconductor module.
(2) by forming stage portion 2b than the recessed mode of upper surface of the wiring pattern 2 of the regional 4a of wiring according to the upper surface of the wiring pattern 2 of borderline region 4b, bottom side at stage portion 2b accumulates moisture easily, because stage portion 2b plays the inhibition of the moisture of immersion, therefore can further suppress moisture from the borderline region 4b of wiring pattern 2 to the regional 4a diffusion of wiring.As a result, can improve the reliability of element mounting substrate and semiconductor module.
(3) by the pit of the stage portion 2b that contains borderline region 4b is set on the surface of wiring pattern 2, between wiring pattern 2 and solder mask 6, produce anchoring effect, improved the cementability between wiring pattern 2 and the solder mask 6.Therefore, the moisture of immersion more is difficult to diffusion on the surface of the wiring pattern 2 of borderline region 4b.As a result, can further improve the reliability of element mounting substrate and semiconductor module.
(4) by stage portion 2b being set at borderline region 4b with Gold plated Layer 5, because the immersion source adjacency of stage portion 2b and moisture, guarantee to suppress the diffusion of moisture, therefore compare with the situation that in the regional 4a of wiring, is provided with stage portion, can more effectively improve the reliability of element mounting substrate and semiconductor module.
(second execution mode)
Fig. 7 is equivalent to the profile of the B-B line in Fig. 3, and Fig. 7 (A) is the profile of the semiconductor module of first execution mode, and Fig. 7 (B) is the profile of the semiconductor module of second execution mode.
Shown in Fig. 7 (A), the wiring pattern 2 in the semiconductor module of first execution mode is the rectangular wiring patterns 2 that form on insulated substrate 1, and this wiring pattern 2 is covered by solder mask 6.Relative therewith, the wiring pattern 2 in the semiconductor module of second execution mode, its bottom becomes horn mouth state (full front of a Chinese gown draws I shape ) 2c expansion, and along this part edge part, has gap 1b between itself and insulated substrate 1.In addition, other structure is identical with first execution mode of front.
In this semiconductor module, etching condition in the operation shown in the control chart 4 (C), the shape of wiring pattern 2 is processed into its bottom is presented on the basis of horn mouth state 2c, handle by the soup in the operation shown in control chart 4 (C), Fig. 5 (B) and Fig. 6 (A), insulated substrate 1 is isotropically carried out etching, can be along the bottom margin portion of wiring pattern 2, between itself and insulated substrate 1, form gap 1b.And, when on wiring pattern 2, forming solder mask 6, easier with solder mask 6 landfills this gap 1b.
According to the semiconductor module of this second execution mode, except the effect of above-mentioned (1)～(4), can also obtain following effect.
(5) at wiring pattern 2, edge part along a side that is connected with insulated substrate 1, between itself and insulated substrate 1, gap 1b is set, solder mask 6 forms in the mode of this gap of landfill 1b, thus, the anchoring effect of the solder mask 6 by landfill gap 1b has improved the cementability of wiring pattern 2 and solder mask 6, and therefore the moisture that immerses more is difficult to diffusion on the surface of the wiring pattern 2 of the regional 4a of wiring.As a result, can improve the reliability of semiconductor module.
(6) present the horn mouth state by the bottom that makes wiring pattern 2, and gap 1b is set in its underpart, because compare with the situation that this structure is not set, longer from the side of wiring pattern 2 to the diffusion length of the moisture of insulated substrate 1 side shifting, therefore can suppress the supply of moisture, corresponding with it, between wiring pattern, be difficult to take place the ion migration.As a result, improved the reliability of semiconductor module.
(the 3rd execution mode)
Fig. 8 is the profile of pad electrode portion of the semiconductor module of the 3rd execution mode.Be with the difference of first execution mode: borderline region 4b has been carried out matsurface processing with the surface of the wiring pattern 2 of the regional 4a of wiring.In addition, first execution mode with previous is identical.
After the operation shown in Fig. 6 (B), by wet treatment etc. roughening is carried out on the surface of the wiring pattern 2 that is made of copper, can easily form this semiconductor module.For example, if utilize the acids soup to carry out surface treatment, its surface just becomes and has small concavo-convex matsurface.Thus, the surface of wiring pattern 2 has small concavo-convex and be roughened.By this roughening, the arithmetic average roughness Ra of wiring pattern 2 is about 0.38 μ m.The Ra on the surface of wiring pattern 2 can measure with contact pin type surface shape measuring device.In addition, in the wet treatment that utilizes this acids soup, the surface of Gold plated Layer 5 is not roughened.The Ra of Gold plated Layer 5 is about 0.11 μ m.
According to the semiconductor module of the 3rd execution mode, except the effect of above-mentioned (1)～(4), can also obtain following effect.
(7) owing to carry out matsurface by the surface of the wiring pattern 2 that is connected with solder mask 6 at borderline region 4b pair and process, can be provided with fine concavo-convex on the surface of the wiring pattern 2 of borderline region 4b, therefore the moisture that immerses is elongated in wiring pattern 2 lip-deep diffusion lengths, can limit its diffusion.In addition, if be provided with fine concavo-convexly on the surface of wiring pattern 2, owing to improved cementability with solder mask 6 in this part, therefore the moisture that immerses more is difficult to diffusion at the wiring pattern 2 of borderline region 4b and the border of solder mask 6.As a result, can further suppress moisture from the borderline region 4b of wiring pattern 2 to the regional 4a diffusion of wiring, can further improve the reliability of semiconductor module.
In addition, in the above-described embodiment, although show the formation that utilizes copper film 3 and remove the example that forms stage portion 2b, but the invention is not restricted to this, for example, utilize photoetching technique at the mask that borderline region 4b is provided for forming the resist of stage portion in addition, also can utilize lithographic technique to form desirable stage portion.Also can obtain above-mentioned effect in this case.
In the above-described embodiment, although show the example that pad electrode portion (electrode zone 4c) is set on element mounting substrate 20, but the invention is not restricted to this, for example, can also be to be the pad electrode portion that is provided with on the semiconductor element of representative with the LSI chip.Also can obtain above-mentioned effect in this case.
In the above-described 3rd embodiment, utilize wet treatment to carry out the example of roughening, the invention is not restricted to this, for example, also can utilize plasma treatment etc. that roughening is carried out on the surface of wiring pattern 2 although show.In this case, for example, if carry out surface treatment by the plasma irradiation that utilizes argon gas, this surface becomes and has small concavo-convex asperities.In addition, in this plasma treatment, the surface of Gold plated Layer 5 is not roughened.
In the above-described embodiment, although show the example that stage portion 2b is set on the surface of the wiring pattern 2 of borderline region 4b,, for example can also stage portion be set on the surface of the wiring pattern 2 of the regional 4a of wiring.In this case, by step, the moisture that immerses from electrode zone 4c is difficult to be diffused into the wiring zone in this stage portion the place ahead, and step can be suppressed between the wiring pattern in stage portion the place ahead the ion migration takes place.
(the 4th embodiment)
Fig. 9 is the constructed profile of the semiconductor module block structure with pad electrode portion of expression the 4th execution mode.Figure 10 is the amplification profile of the pad electrode portion of semiconductor module shown in Figure 9.In the semiconductor module of first execution mode, semiconductor element 7 is connected by conductive component 8 wire-bonded in the Gold plated Layer 5 of the electrode zone 4c of wiring pattern 2.Relative therewith, in the semiconductor module of the 4th execution mode, semiconductor element 7 is connected with the upside-down mounting chip with element mounting substrate 20.Specifically, the electrode forming surface that is formed with the semiconductor element 7 of projection 90 faces down, and projection 90 is connected with the Gold plated Layer 5 of the electrode zone 4c of wiring pattern 2 by scolding tin 92.In addition, between semiconductor element 7 and solder mask 6, be filled with bottom filling 94.
Element mounting substrate and semiconductor module according to the 4th execution mode that as above illustrates can obtain element mounting substrate and the same effect of semiconductor module with first execution mode.
(8) owing to can protect projection 90, scolding tin 92 and Gold plated Layer 5, therefore improved the connection reliability of projection 90 and Gold plated Layer 5 by end filler 94.In addition, utilize end filler 94 can further suppress moisture and supply with (diffusion), between wiring pattern, further be difficult to take place the ion migration to the wiring pattern 2 of the regional 4a of wiring.
(the 5th execution mode)
Below, introduce portable set with above-mentioned semiconductor module.As portable set the example that is equipped on mobile phone is shown, but for example, can also is PDA(Personal Digital Assistant), digital video camera (DVC) and digital still life camera electronic equipments such as (DSC).
Figure 11 is the figure of handset structure that expression has the semiconductor module of the 5th execution mode.Mobile phone 211 constitutes first housing 212 and is connected by movable part 220 with second housing 214.First housing 212 and second housing 214 serve as that axle can rotate with movable part 220.Be provided with display part 218, the speaker portion 224 of information such as display text and image at first housing 212.Be provided with operation with operating portions such as button 222, microphone portion 226 at second housing 214.The semiconductor module that each execution mode provides carries the inside at this mobile phone 211.
Figure 12 is the fragmentary cross-sectional view (profile of first housing 212) of mobile phone shown in Figure 11.The semiconductor module 130 that the embodiments of the present invention provide carries at printed base plate 228 by external connecting electrode 290, and is electrically connected by this printed base plate 228 and display part 218 etc.In addition, in the rear side of semiconductor module 130 (surface of a side opposite) heat-radiating substrates 216 such as metal substrate are set with external connecting electrode 290, for example, it constitutes: the heat that is produced by semiconductor module 130 can not store in first housing, 212 inside, can be effectively to the heat radiation of the outside of first housing 212.
If utilize the portable set with semiconductor module of present embodiment, can obtain following effect.
(10) in pad electrode portion, owing to suppress the supply (diffusion) of moisture to wiring pattern 2, between wiring pattern, be difficult to take place the ion migration, improved the connection reliability of semiconductor module 130, therefore improved the reliability of the portable set that is equipped with this semiconductor module 130.
(11) because (Chip Size Package: chip size packages) semiconductor module 130 of technology manufacturing can reach slimming, miniaturization, so can seek to carry slimming, the miniaturization of the portable set of this semiconductor module 130 by the wafer level chip size package shown in the above-described embodiment.
Claims (20)
1. element mounting substrate comprises:
Wiring layer, it is made of copper, comprises wiring zone and the electrode zone that is connected with this wiring zone, and has stage portion at the borderline region of described wiring zone and described electrode zone;
Gold plated Layer, its wiring layer surface at described electrode zone forms;
Insulating barrier, it covers the wiring layer in the part of described Gold plated Layer and described borderline region and described wiring zone and forms, and has the peristome of regulation at described electrode zone.
2. according to the element mounting substrate of claim 1 record, it is characterized in that described stage portion forms more recessed than the upper surface of the wiring layer in described wiring zone.
3. according to the element mounting substrate of claim 1 record, it is characterized in that, matsurface is carried out on the surface of the wiring layer that is connected with described insulating barrier at described borderline region process.
4. according to the element mounting substrate of claim 2 record, it is characterized in that, matsurface is carried out on the surface of the wiring layer that is connected with described insulating barrier at described borderline region process.
5. according to the element mounting substrate of each record in the claim 1～4, it is characterized in that, described wiring layer and described insulating barrier are arranged on the substrate, described wiring layer is along the edge part of a side that is connected with described substrate, and described substrate between have the gap, described insulating barrier forms this gap of landfill.
6. a semiconductor module is characterized in that, comprising:
According to the element mounting substrate of each record in the claim 1～5 and
Semiconductor element in described element mounting substrate installation.
7. according to the semiconductor module of claim 6 record, it is characterized in that described semiconductor element is connected by wire-bonded with described element mounting substrate.
8. according to the semiconductor module of claim 6 record, it is characterized in that described semiconductor element is connected with the upside-down mounting chip with described element mounting substrate.
9. a portable set is characterized in that, carries the semiconductor module according to each record in the claim 6～8.
10. the manufacture method of an element mounting substrate comprises:
On substrate, form the operation of the first metal layer;
Described the first metal layer is carried out composition, form have electrode zone, the operation of the wiring of wiring zone and the borderline region that between described electrode zone and described wiring zone, is provided with;
Form the operation of second metal level on the surface of described wiring and described substrate;
According to the mode of exposing in the part of described electrode zone, described borderline region and the regulation zone around described electrode zone and described borderline region, described second metal level, on described substrate, form the operation of first mask;
Use described first mask, optionally remove after described second metal level in described electrode zone, described borderline region and described electrode zone and described borderline region regulation zone on every side, dig out the described wiring layer of described electrode zone and described borderline region and the described substrate in described regulation zone, make the surperficial low operation in the described wiring of the surface ratio zone of described borderline region;
Remove the operation of described first mask;
According to the mode that the described substrate in the regulation zone around the described wiring of described electrode zone and the described electrode zone exposes, on described substrate, form the operation of second mask;
Use described second metal level as electroplate lead wire, form the operation of Gold plated Layer at described electrode zone;
Remove the operation of described second mask and described second metal level;
Cover the operation of the wiring layer in the part of described electrode zone, described borderline region and described wiring zone with insulating barrier.
11. the manufacture method according to the element mounting substrate of claim 10 record is characterized in that, utilizes chemical plating and electroplate to form described the first metal layer.
12. the manufacture method according to the element mounting substrate of claim 10 record is characterized in that, utilizes chemical plating to form described second metal level.
13. the manufacture method according to the element mounting substrate of claim 11 record is characterized in that, utilizes chemical plating to form described second metal level.
14. the manufacture method according to the element mounting substrate of each record in the claim 10～13 is characterized in that described Gold plated Layer is Au-Ni layer or Au-Pb-Ni layer.
15. the manufacture method according to the element mounting substrate of each record in the claim 10～13 is characterized in that, also is included in to form after the described wiring, the surface of described wiring is carried out the operation of roughening.
16. the manufacture method according to the element mounting substrate of claim 14 record is characterized in that, also is included in to form after the described wiring, the surface of described wiring is carried out the operation of roughening.
17. manufacture method according to the element mounting substrate of each record in the claim 10～13, it is characterized in that, the edge part of the bottom of the described wiring in the zone that described insulating barrier covers, between described wiring and described substrate, the gap is set after, form described insulating barrier.
18. manufacture method according to the element mounting substrate of claim 14 record, it is characterized in that, the edge part of the bottom of the described wiring in the zone that described insulating barrier covers, between described wiring and described substrate, the gap is set after, form described insulating barrier.
19. manufacture method according to the element mounting substrate of claim 15 record, it is characterized in that, the edge part of the bottom of the described wiring in the zone that described insulating barrier covers, between described wiring and described substrate, the gap is set after, form described insulating barrier.
20. manufacture method according to the element mounting substrate of claim 16 record, it is characterized in that, the edge part of the bottom of the described wiring in the zone that described insulating barrier covers, between described wiring and described substrate, the gap is set after, form described insulating barrier.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006302443 | 2006-11-08 | ||
| JP302443/06 | 2006-11-08 | ||
| JP275739/07 | 2007-10-23 | ||
| JP2007275739 | 2007-10-23 | ||
| JP290839/07 | 2007-11-08 | ||
| JP2007290839A JP4498404B2 (en) | 2006-11-08 | 2007-11-08 | Device mounting substrate, manufacturing method thereof, semiconductor module, and portable device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101345228A CN101345228A (en) | 2009-01-14 |
| CN101345228B true CN101345228B (en) | 2011-02-09 |
Family
ID=39648919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710185791XA Expired - Fee Related CN101345228B (en) | 2006-11-08 | 2007-11-08 | Substrate for mounting device, manufacturing method thereof, semiconductor module and portable equipment |
Country Status (3)
| Country | Link |
|---|---|
| JP (2) | JP4498404B2 (en) |
| KR (1) | KR20080042012A (en) |
| CN (1) | CN101345228B (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101289796B1 (en) * | 2008-07-01 | 2013-07-26 | 삼성테크윈 주식회사 | Curcuit board and method of manufacturing the same |
| TWI373836B (en) | 2008-09-23 | 2012-10-01 | Advanced Semiconductor Eng | Circuit board and process thereof |
| CN101783332B (en) * | 2009-01-16 | 2012-01-25 | 日月光半导体制造股份有限公司 | Circuit board and preparation process thereof |
| JP5607994B2 (en) * | 2010-06-15 | 2014-10-15 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device and manufacturing method thereof |
| KR101774004B1 (en) * | 2011-03-17 | 2017-09-01 | 해성디에스 주식회사 | Manufacturing method of semiconductor package |
| CN104428912A (en) * | 2012-06-26 | 2015-03-18 | 株式会社村田制作所 | Mounting board and light-emitting device |
| JP6623056B2 (en) * | 2015-12-16 | 2019-12-18 | 新光電気工業株式会社 | Wiring board, semiconductor device |
| CN105657976A (en) * | 2016-01-19 | 2016-06-08 | 深圳崇达多层线路板有限公司 | Manufacturing method of entire-board nickel gold plating stepped board |
| JP6485776B2 (en) * | 2016-05-31 | 2019-03-20 | 大口マテリアル株式会社 | Wiring member for multi-row type semiconductor device and manufacturing method thereof |
| JP6485777B2 (en) * | 2016-05-31 | 2019-03-20 | 大口マテリアル株式会社 | Wiring member for multi-row type semiconductor device and manufacturing method thereof |
| DE102017206992A1 (en) * | 2017-04-26 | 2018-10-31 | Infineon Technologies Ag | Substrate and manufacturing process for it |
| JP7064324B2 (en) * | 2017-12-18 | 2022-05-10 | スタンレー電気株式会社 | A semiconductor light emitting device and a method for manufacturing a semiconductor light emitting device using the semiconductor light emitting device. |
| CN108322999B (en) * | 2018-03-30 | 2020-09-04 | 成都奕斯伟芯片设计有限公司 | Circuit board, method for forming solder mask layer of circuit board and chip |
| JP2021125643A (en) * | 2020-02-07 | 2021-08-30 | キオクシア株式会社 | Semiconductor device and manufacturing method thereof |
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| JPH05191021A (en) * | 1992-01-14 | 1993-07-30 | Matsushita Electric Works Ltd | Printed wiring board |
| JP3400535B2 (en) * | 1993-04-28 | 2003-04-28 | 大日本印刷株式会社 | Master for electrodeposition transfer and method for producing the same |
| JP2000114412A (en) * | 1998-10-06 | 2000-04-21 | Shinko Electric Ind Co Ltd | Manufacture of circuit board |
| JP3488888B2 (en) * | 2000-06-19 | 2004-01-19 | アムコー テクノロジー コリア インコーポレーティド | Method of manufacturing circuit board for semiconductor package and circuit board for semiconductor package using the same |
| JP2004165238A (en) * | 2002-11-11 | 2004-06-10 | Sumitomo Metal Electronics Devices Inc | Plastic package and its manufacturing method |
| JP4351129B2 (en) * | 2004-09-01 | 2009-10-28 | 日東電工株式会社 | Printed circuit board |
| JP5066783B2 (en) * | 2004-10-14 | 2012-11-07 | イビデン株式会社 | Multilayer printed wiring board and method for manufacturing multilayer printed wiring board |
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- 2007-11-08 JP JP2007290839A patent/JP4498404B2/en not_active Expired - Fee Related
- 2007-11-08 CN CN200710185791XA patent/CN101345228B/en not_active Expired - Fee Related
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| US6670215B2 (en) * | 1996-03-22 | 2003-12-30 | Renesas Technology Corporation | Semiconductor device and manufacturing method thereof |
| CN1430272A (en) * | 2001-12-26 | 2003-07-16 | 株式会社日立制作所 | Semiconductor device and its manufacturing method |
| US7347949B2 (en) * | 2004-07-23 | 2008-03-25 | Shinko Electric Industries, Co., Ltd. | Method of manufacturing a wiring board by utilizing electro plating |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4498404B2 (en) | 2010-07-07 |
| JP5062600B2 (en) | 2012-10-31 |
| CN101345228A (en) | 2009-01-14 |
| KR20080042012A (en) | 2008-05-14 |
| JP2010157757A (en) | 2010-07-15 |
| JP2009123719A (en) | 2009-06-04 |
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