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Publication numberCN101341593 B
Publication typeGrant
Application numberCN 200680045001
PCT numberPCT/US2006/042450
Publication date22 Aug 2012
Filing date30 Oct 2006
Priority date1 Nov 2005
Also published asCN101341593A, US7511371, US7939920, US8030135, US20070096265, US20080315382, US20090239340
Publication number200680045001.1, CN 101341593 B, CN 101341593B, CN 200680045001, CN-B-101341593, CN101341593 B, CN101341593B, CN200680045001, CN200680045001.1, PCT/2006/42450, PCT/US/2006/042450, PCT/US/2006/42450, PCT/US/6/042450, PCT/US/6/42450, PCT/US2006/042450, PCT/US2006/42450, PCT/US2006042450, PCT/US200642450, PCT/US6/042450, PCT/US6/42450, PCT/US6042450, PCT/US642450
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Multiple die integrated circuit package
CN 101341593 B
A multiple die package for integrated circuits is disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias are formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator layer. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator layer. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator, at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframes may be physically coupled by a welding process within vias in the insulator. A removable storage card package is also described.
Claims(26)  translated from Chinese
1. 一种多晶片半导体封装,其包括: 绝缘体,其具有第一表面、与所述第一表面相対的第二表面及预定位置处的ー个或ー个以上通孔通路; 第一引线框架,其至少部分地上覆于所述第一表面上并具有多个引线,上覆于ー个或ー个以上通孔通路的引线的部分变形到所述ー个或ー个以上通孔通路中; 第一集成电路晶片,其邻近并电耦合到所述第一引线框架的所述多个引线中的至少ー者; 第二引线框架,其至少部分地上覆于所述第二表面上并具有多个引线;及第二集成电路晶片,其邻近并电耦合到所述第二引线框架的所述多个引线中的至少ー者; 其中所述第一引线框架的所述多个引线中的至少ー者穿过所述绝缘体中的所述通孔通路中的一者而电耦合到所述第二引线框架的所述多个引线中的对应ー者。 1. A multi-chip semiconductor package, comprising: an insulator having a first surface, ー ー or more through-holes via the second surface and at a predetermined position relative to the first surface Dui; a first lead frame at least partially overlying the ground on the first surface and having a plurality of leads overlying ー ー or more through-passage of the pin holes to the portion transformation ー ー one or more through-holes or passage; first integrated circuit die, adjacent and electrically coupled to said first plurality of leads of said lead frame at least ー persons; second lead frame at least partially on the ground overlying said second surface and having a plurality a lead wire; and a second integrated circuit die, adjacent and electrically coupled to said second plurality of leads of said lead frame at least ー persons; wherein the plurality of leads of the first lead frame at leastー by passing through the insulator in the through hole via is electrically coupled to one of said second plurality of leads of said lead frame corresponding ー person.
2.如权利要求I所述的封装,其中所述封装进ー步包括囊封剂,其至少部分地囊封所述绝缘体、所述第一及第ニ集成电路晶片及所述第一及第ニ引线框架。 2. The package according to claim I, wherein said encapsulated ー encapsulating agent further comprises, at least partially encapsulating said insulator, said first and second Ni and the first and second integrated circuit die ni leadframe.
3.如权利要求I所述的封装,其中所述第一及第ニ集成电路晶片是相同的。 I A package according to claim, wherein said first and second integrated circuit die ni is identical.
4.如权利要求I所述的封装,其中所述第一及第ニ集成电路晶片分别包括控制器集成电路及存储器阵列集成电路。 4. The package according to claim I, wherein said first and second integrated circuit die ni respectively include a controller integrated circuit and an integrated circuit memory array.
5.如权利要求4所述的封装,其中所述存储器阵列集成电路包括非易失性存储器装置。 5. The package of claim 4, wherein said memory array includes a nonvolatile memory integrated circuit device.
6.如权利要求I所述的封装,其中所述第一及第ニ集成电路晶片通过接合线分别电耦合到所述第一及第ニ引线框架。 6. A package according to claim I, wherein said first and second integrated circuit die ni respectively by the bonding wires electrically coupled to said first and second lead frame ni.
7.如权利要求I所述的封装,其中所述第一及第ニ集成电路晶片通过倒装芯片连接分别电耦合到所述第一及第ニ引线框架。 7. A package as recited in claim I, wherein said first and second integrated circuit die ni respectively electrically coupled to the first and second Ni lead frame by flip chip bonding.
8.如权利要求6所述的封装,其中所述第一与第二集成电路晶片呈背对背关系。 8. A package as claimed in claim 6, wherein said first and second integrated circuit die was back to back relationship.
9.如权利要求7所述的封装,其中所述第一与第二集成电路晶片呈面对面关系。 9. A package according to claim 7, wherein said first and second integrated circuit die was face to face relationship.
10.如权利要求I所述的封装,其中所述通孔通路中填充有导电材料,所述材料物理接触所述第一引线框架的所述至少ー个弓I线。 10. A package as recited in claim I, wherein said through-holes filled with a conductive material in the passageway, the first lead frame of physical contact with said at least one of said material ー I bow line.
11.如权利要求I所述的封装,其中所述绝缘体在所述ー个或ー个以上通孔通路位置处包括各向异性导电材料,且通过致使所述各向异性导电材料在所述ー个或ー个以上通孔通路处变为导电而形成电连接。 11. A package as recited in claim I, wherein said insulator comprises an anisotropic conductive material in the ー ー more or at a via location passage, and by causing the anisotropic conductive material in the ーor ー via at least one through hole is formed into electrically conductive connection.
12.如权利要求I所述的封装,其中所述第一及第ニ引线框架中的每ー者的至少ー个引线在所述绝缘体中的所述通孔通路中的至少ー者内被彼此物理焊接。 12. A package as recited in claim I, wherein in said first and second lead frame each ー ni persons ー at least one lead within the insulator in the through hole in the path to be another person, at least ーPhysical welding.
13.如权利要求I所述的封装,其中上覆于ー个或ー个以上通孔通路的所述第二引线框架的引线的部分变形到所述ー个或ー个以上通孔通路中,所述第一及第ニ引线框架引线中的每ー者的所述至少ー个引线变形并进入所述通孔通路,然后所述引线在所述通孔通路中被彼此焊接。 13. A package as recited in claim I, wherein the one or overlying ー ー more through-hole passage of the second lead of the lead frame portion deformed to the ー ー least one through hole or passage, said first and second leads of said lead frame ni of each of those ー ー deformation of the leads at least one through hole and into the passage, and then the wire passage in the through hole, are welded to each other.
14. 一种用于形成多晶片集成电路封装的方法,其包括以下步骤: 提供具有第一表面及与所述第一表面相対的第二表面的绝缘体层; 在所述绝缘层中在所需位置处形成一个或ー个以上通孔通路;提供具有至少部分地上覆于所述第一表面上的多个引线的第一引线框架; 提供具有至少部分地上覆于所述第二表面上的多个引线的第二引线框架; 将第一集成电路晶片耦合到所述第一引线框架的至少ー个引线; 将第二集成电路晶片耦合到所述第二引线框架的至少ー个引线; 在覆盖一通孔通路的位置,将所述第一引线框架的一引线的一部分变形到所述通孔通路中; 穿过所述绝缘体层中的所述通孔通路将经变形到所述通路中的所述引线的所述部分电连接到所述第二引线框架的ー对应引线; 从而将所述第一与第二集成电路晶片彼此电耦合。 14. A method for forming a multi-chip integrated circuit package, comprising the steps of: providing an insulator layer having a first surface and said first surface to a second surface of the Dui; in the insulating layer in the desired position forming one or more vias ー passage; provided having at least a first portion of the floor overlying the plurality of leadframe leads on said first surface; providing at least part of the floor overlying said second surface having a plurality a second lead frame leads; coupling a first integrated circuit die to the first lead frame at least ー of leads; coupling the second integrated circuit die to the second lead frame ー at least one lead; cover position a through hole passage, the deformation portion of the first lead frame leads to a passage in the through hole; through the insulator layer via the through-hole passage to deform into the path of the wherein said lead portion is electrically connected to the second lead frame ー corresponding lead; whereby said first and second integrated circuit die are electrically coupled.
15.如权利要求14所述的方法,且其进一歩包括以下步骤: 至少部分地囊封所述绝缘体层、所述第一及第ニ集成电路晶片以及所述第一及第ニ引线框架。 15. The method of claim 14, and which carry a 歩 comprising the steps of: at least partially encapsulating said insulator layer, said first and second integrated circuit die and the ni ni first and second lead frame.
16.如权利要求14所述的方法,其进ー步包括以下步骤: 将所述第二引线框架的所述对应引线的一部分形成到所述通孔通路中。 16. The method of claim 14, which further comprises the steps of intake ー: the lead frame of the second part of the lead is formed corresponding to the through-hole passage.
17.如权利要求16所述的方法,其中所述电连接步骤包括在所述通孔通路内的所述第一引线框架的所述引线的所述部分与所述第二引线框架的所述对应引线的所述部分之间形成物理焊接。 Wherein the portion of the lead wire 17. The method of claim 16, wherein said electrically connecting step comprises the passage in the through hole of the first lead frame and the second lead frame is formed between the welded portion corresponding to the physical leads.
18.如权利要求16所述的方法,其中所述电连接步骤包括在所述通孔通路内的所述第一引线框架的所述引线的所述部分与所述第二引线框架的所述对应引线的所述部分之间提供导电粘合剤。 Wherein the portion of the lead wire 18. The method of claim 16, wherein said electrically connecting step comprises the passage in the through hole of the first lead frame and the second lead frame Ji provided between said conductive adhesive portions corresponding leads.
19.如权利要求14所述的方法,其中所述将第一及第ニ集成电路晶片与所述第一及第ニ引线框架耦合的步骤包括耦合相同的集成电路晶片。 19. The method of claim 14, wherein said first and second writing is the first and second integrated circuit die and the lead frame coupling step of writing is the same integrated circuit die includes a coupling.
20.如权利要求14所述的方法,其中所述将第一及第ニ集成电路晶片耦合到所述第一及第ニ引线框架的步骤包括将存储器阵列集成电路晶片耦合到所述第一引线框架并将控制器集成电路晶片耦合到所述第二引线框架。 20. The method of claim 14, wherein said integrated circuit die is coupled to the writing is the first and to the first and second step ni lead frame comprises a memory array coupled to the first integrated circuit die lead frame and the controller is coupled to the second integrated circuit die lead frame.
21.如权利要求20所述的方法,其中所述将所述存储器阵列集成电路晶片耦合到所述第一引线框架的步骤包括耦合非易失性存储器阵列集成电路晶片。 21. The method of claim 20, wherein said coupling the memory array integrated circuit wafer to the step of coupling the first lead frame includes a nonvolatile memory array integrated circuit wafer.
22.如权利要求21所述的方法,且其进一歩包括在所述非易失性存储器阵列集成电路晶片上方堆叠额外的非易失性存储器集成电路晶片的步骤。 22. The method of claim 21, and which carry a 歩 step comprises an integrated circuit wafer above the non-volatile memory array stacking additional non-volatile memory integrated circuit die.
23.如权利要求14所述的方法,其中所述将所述第一及第ニ集成电路晶片耦合到所述第一及第ニ引线框架的步骤包括在所述第一及第ニ集成电路晶片与所述第一及第ニ引线框架之间形成线接合。 23. The method of claim 14, wherein said first and second writing is the integrated circuit die coupled to the first and second step of the writing is included in the lead frame of the first and second integrated circuit die ni between the first and second lead frame and the formation of Ni wire bonding.
24.如权利要求23所述的方法,其中所述耦合所述第一与第二集成电路晶片的步骤进一歩包括将所述集成电路晶片以背对背关系放置的步骤。 24. The method of claim 23, wherein said step of coupling said first and second integrated circuit die into a 歩 comprising the step of the integrated circuit wafer is placed back to back relationship.
25.如权利要求14所述的方法,其中所述将所述第一及第ニ集成电路晶片耦合到所述第一及第ニ引线框架的步骤包括在所述第一及第ニ集成电路晶片与所述第一及第ニ引线框架之间形成倒装芯片连接。 25. The method of claim 14, wherein said first and second writing is the integrated circuit die coupled to the first and second step of the writing is included in the lead frame of the first and second integrated circuit die ni flip-chip bonding to form the lead frame between the first and Ni.
26.如权利要求25所述的方法,其中所述将所述第一及第ニ集成电路晶片耦合到所述第一及第ニ引线框架的步骤进一歩包括将所述第一及第ニ集成电路晶片以面对面关系放置。 26. The method of claim 25, wherein said integrated circuit die is coupled to the writing is the first and second step of the first and second lead frame into a 歩 ni comprises said first and second integrated ni circuit chip is placed face to face relationship.
Description  translated from Chinese

多晶片集成电路封装及形成其的方法 Multi-chip integrated circuit package and method of forming thereof

[0001] 相关_请交叉参考案 [0001] _ Please cross-reference related case

[0002] 本申请案涉及与本申请案同一日期提出申请且标题为“用于多晶片集成电路封装的方法(Methods for a Multiple Die Integrated Circuit Package) ” 的第11/264, 556号(代理人案号为SAND-01109US0)共同待决美国专利申请案。 [0002] The present application relates to the present application, filed on the same date and entitled "Method for multi-chip integrated circuit package (Methods for a Multiple Die Integrated Circuit Package)" section 11/264, No. 556 (Agents Docket No. SAND-01109US0) co-pending US patent application.

[0003] 技术领域 [0003] FIELD

[0004] 本发明及所说明的各实施例大体来说涉及制作包含多于ー个集成电路装置的封装式半导体装置,且更特定来说涉及制作具有“多个”集成装置的封装以形成封装式系统、存储器或存储器卡存储装置。 [0004] The present invention and embodiments described relate generally to the production of integrated circuits containing more than ー device packaged semiconductor device, and more particularly relates to the production having a "multiple" integrated package to form a package device type system, a memory or a memory card storage device.

[0005] 背景技术 [0005] BACKGROUND

[0006] 在电子技术中,将半导体装置提供在保护并提供与集成电路的外部连接的封装中。 [0006] In electronics, the semiconductor device provides protection and provides integrated package of external connections. 对装置的集成性及先进功能性的需求已致使在单个封装中提供多个集成电路,其有时称为芯片或晶片(dies)。 The need for integration and advanced functional apparatus has been provided so that a plurality of integrated circuits in a single package, which is sometimes called a chip or wafer (dies). 可以各种方式及各种材料形成封装,包含用热硬化或热固化材料形成的模制封装,例如“圆顶封装体”或环氧封装、预形成的塑料或陶瓷或者金属主体及类似物。 Can be formed in various ways and various materials are encapsulated with a thermosetting material or thermosetting molding package, such as "glob-top" epoxy encapsulation or pre-formed plastic or ceramic or metallic body, and the like. 所使用的材料保护小且易碎的半导体集成电路或“晶片”免受物理及某程度的湿气损坏,且为用于将外部端子(通常为金属或其它导电触点)耦合到集成电路上的导电接合垫(其为集成电路的外部电连接)的导电引线或电线提供保护。 The material used small and fragile protection semiconductor integrated circuit "wafer" from physical damage and moisture to a certain extent, and is for the external terminal (typically a metal or other conductive contacts) on or coupled to an integrated circuit The conductive bond pad (which is connected to the external power integrated circuit) of the conductive leads or wires to provide protection.

[0007] 经常,在半导体封装技术中使用引线框架,以提供机械支撑并在集成电路与封装式装置的外部电触点或引线之间进行电连接。 [0007] Frequently, the use of a lead frame in semiconductor packaging technology, to provide mechanical support and electrical contact between the external lead wire or an integrated circuit packaged device electrically connected. 引线框架由导电材料(经常为铜或合金,或例如合金42的铁镍合金,经常将其涂布以增加与例如金、钌、钯及类似物等材料的导电性及可软焊性)组成,且额外涂层或镍、铜或其它材料的合金可用于改善连接的可软焊性及可制造性。 Lead frame made of a conductive material (often copper or alloys, or iron-nickel alloy such as Alloy 42, which is often applied to increase the electrical conductivity and for example, solderable of gold, ruthenium, palladium, and the like and other materials) composition and an additional coating or nickel, copper alloys or other materials can be used to improve the connections between solderable and manufacturability. 导电材料上的塑料涂层可用于形成引线框架。 Plastic coated conductive material may be used to form the lead frame. 可将引线加以软焊或镀敷以在装配之前或在完成的封装的装配之后进行软焊。 The leads may be soldered or plated prior to assembly or after assembly of the completed package soldering. 通常以集成带形式提供引线框架,且可将所述引线框架蚀刻或冲压成形,引线框架带是以带形式连接以便于装配及制造的若干引线框架,且然后在稍后的制造阶段将所述弓I线框架分离。 Usually provided in the form of a lead frame integrated with, and may be the etching or stamping the leadframe, the leadframe strip is connected so as to form with a number of assembly and manufacture of the lead frame, and then at a later manufacturing stage of the I bow wire frame separation.

[0008]弓丨线框架通常提供多个弓I线(经常为手指状,但也使用其它形状),其从将成为所需的成品封装的外部边界的区域外部伸延到经布置以接纳集成电路的内部区域。 [0008] Bow 丨 wire frame provides a plurality of generally I bow lines (often a finger shape, but other shapes), which will be required from the area outside of the finished package extend to the outer boundary of the integrated circuit is arranged to receive The interior region. 在现有技术中,已知使用其中引线框架的ー个区域提供中心支撑的布置,所述区域称为“晶片垫”,其用于接纳矩形或正方形半导体晶片,且引线指状元件在所述晶片垫的ー个或ー个以上侧上延伸到接近于所述集成电路晶片的外部边缘的区域。 In the prior art, it is known to use a lead frame which ー regions provide center support arrangement, the area is called "chip pad", which is used to receive a rectangular or square semiconductor wafer, and the lead fingers in theー ー one or more upper side extends to near an outer edge of said integrated circuit die pad region of the wafer. 将引线框架指状元件固定成远离所述晶片并穿过经囊封的封装的计划外部边界而延伸。 The lead frame finger is fixed to and away from the wafer through the via encapsulated package plan outer boundary extends. 在现有技术的其它布置中,所述引线指状元件可在晶片上方(芯片上引线或“L0C”型引线框架)或晶片下方(芯片下引线或“LUC”型引线框架)延伸,其中所述引线提供机械支撑以及电路径。 In other arrangements of the prior art, the lead fingers may be below (under the chip leads or "LUC" type lead frame) extends above the wafer (chip leads or "L0C" type lead frame) or wafer, wherein said lead wire to provide mechanical support and electrical paths.

[0009] 涂层或胶带形式的绝缘体粘合剂可用于将晶片固定到引线,或通过将引线固定在一起并在装配过程期间维持其位置来使引线稳定。 [0009] The coating or adhesive tape may be used to form insulator wafer is fixed to the lead, or the lead fixing by together and maintain their position during the assembly process to stabilize the leads. 可使用晶片附着粘合剂将晶片粘合到晶片垫,所述粘合剂可以是导电或绝缘材料且可以是树脂或热硬化材料。 May be attached using an adhesive wafer wafer to wafer bonding pad, the adhesive may be a conductive or insulating material and may be a resin or a thermosetting material.

[0010] 不管使用何种类型的引线框架,有必要提供耦合机构以将集成电路电耦合到引线框架。 [0010] Regardless of the type of lead frame, it is necessary to provide a coupling mechanism to an integrated circuit electrically coupled to the lead frame. 通常使用接合线。 Commonly used wire bonding. 通过线接合エ艺将这些微型线施加到半导体装置;通常在通过毛细管施加线时将其分配。 By wire bonding Eito art these miniature wire applied to the semiconductor device; typically applied to distribution line by a capillary. 线接合エ艺使用热及压力且有时使用其它能量(例如,超声波能量)以通过将线附着到集成电路接合垫来形成接合,且然后使所述接合线在集成电路上方且远离集成电路而延伸到引线框架的引线指状元件的端上方的区域,然后所述毛细管再次使用热及压力来形成所述接合线到所述引线框架的第二连接。 Eito-art wire bonding using heat and pressure, and sometimes use other energy (e.g., ultrasonic energy) to be attached to the integrated circuit by wire bonding pad to form a bond, and then the joining line at the top of the integrated circuit and extending away from the integrated circuit to leadframe lead fingers like element above the area of the end, and then the capillary to form the joining line to a second connection of said lead frame using heat and pressure again. 另ー选择为,所述接合线可以在相反方向上形成,从而首先附着到所述引线框架指状元件并向上延伸到所述集成电路上方并附着到接合垫。 Another ー selection, the bonding lines may be formed in the opposite direction, so that the lead frame attached to the first finger-like element extending upward to the integrated circuit and attached to the bond pad. 经常加热经切割的线以在所述接合线的端上形成球,然后其用于到所述集成电路晶片的下一接合(“球”接合),所述接合线的附着到所述引线框架的不具有球的端可称为“跳点接合”。 Often heated to form the cut line on the ball end of the bonding wire, and then for the next to the integrated circuit wafer bonding ("ball" engagement), attached to the joining line of said lead frame The client does not have the ball can be called "hops engagement." 如果需要,多个接合线可从集成电路的不同垫延伸到引线框架的单个引线,举例来说,可以此方式进行集成电路的电源或接地连接。 If desired, a plurality of bonding wires may extend from different pads of the integrated circuit to the lead frame of single wire, for example, an integrated circuit can be power or ground connection in this way. 所述接合线可以是金或其它已知的导体材料,其具有充足的延展性及挠性以允许此类型的处置并可用于球接合及跳点接合步骤而不存在有害的中断。 The bonding wire may be gold or other known conductive material having sufficient ductility and flexibility to allow this type of disposal may be used to engage the ball and jumping point bonding step without harmful interruption. 所述线接合エ艺可高度自动化,且通常在非常高的速率下执行。 The wire bonding can be highly automated Eito arts, and is usually performed at a very high rate.

[0011] 在装配过程中,在将集成电路晶片线接合到引线框架之后,可将所述引线框架及晶片放置在模制装备(举例来说,在转移模制机器中)中,其中分配液体或熔化模制化合物材料以将所述引线框架与集成电路囊封在一起,以如上所说明向所述晶片提供机械保护及某程度的湿气抵抗力。 [0011] During assembly, after the wire bonding integrated circuit die to the lead frame, the lead frame can be placed in the mold and the wafer equipment (for example, in a transfer molding machine), in which the distribution of the liquid or melt molding compound to the lead frame material with the integrated circuit encapsulated together to provide mechanical protection as explained above and a certain degree of moisture resistance to the wafer. 其它替代性方案包含使用注模、环氧及树脂(例如,“圆顶封装体”)材料且可使用用于集成电路囊封的其它已知材料。 Other alternatives comprises using injection molding, and an epoxy resin (e.g., "glob") material and may be encapsulated in an integrated circuit used for other known materials. 代替模制的是,可改为将引线框架与晶片组合件安装到陶瓷、金属或塑料主体中,然后可随后使用盖子及粘合剂或其它物品通过囊封剂来将所述主体密封。 Instead of molded, the lead frame can be changed with the mounting wafer assembly to ceramic, metal or plastic body, and can then use the lid and other items by adhesive or encapsulant to seal the main body. 引线框架的引线的外端可自己形成封装式装置(例如,在DIP、四方扁平包装、SOP或其它引线式封装中)的外部触点,或可使用额外连通技术,例如球栅格阵列(“BGA”)或引脚栅格阵列(“PGA”)封装及类似物。 The outer end of the lead frame leads to the formation of their own packaged device (for example, in the DIP, quad flat package, SOP or other leaded package) external contacts, or use the extra connectivity technologies such as ball grid array (" BGA ") or pin grid array (" PGA ") package and the like. 引线框架可结合其它互连插入物技术来使用,例如印刷电路板、基于以膜为基础的材料的挠性电路、用于半导体制造的市售膜(例如,卡普顿(Kapton)、宇部兴产(Upilex)、迈拉(Mylar)及类似物),或可使用陶瓷衬底材料。 Interconnect lead frame can be combined with other techniques used inserts, such as printed circuit boards, flexible circuit-based membrane-based material, a commercially available film for semiconductor manufacturing (e.g., Kapton (Kapton), Ube production (Upilex), Myra (Mylar) and the like), or you can use a ceramic substrate material. 为可在现有技术中使用复杂的衬底布置,经常将多个层插入物与将外部连接器耦合到集成电路的所形成金属层一起使用。 Complex may be used for the substrate is disposed in the prior art, often a plurality of insert layers and coupled to the external connector for use with integrated circuits formed by a metal layer. 举例来说,底表面上的端子可穿过衬底或插入物中的多个层及通路耦合到插入物的上表面上的引线框架或线接合平台端子。 For example, the terminals on the bottom surface of the insert may pass through the substrate or in a plurality of layers and passages is coupled to a lead frame or line on the upper surface of the insert engages a terminal platform. 这些插入物或衬底通常为层压结构,其中绝缘体层形成于各个导电层上。 These inserts or substrate is typically a laminated structure, wherein the insulator layer is formed on the respective conductive layers. 一旦装配完成,那么可将这些层压物进行过模制以提供密封的封装式装置或可将所述组合件放置于被密封的主体中。 Once assembled, it may be these laminates was subjected to over-molded to provide a sealed package type device or the assembly may be placed in the sealed body.

[0012] 随着不断需要在封装式装置中提高集成性,在所属技术中也已知提供MCM或多芯片模块,其中在封装式装置内提供多于ー个集成电路晶片。 [0012] With the constant need to improve integration in the respective technology is also known to provide a multi-chip module MCM, which in the packaged device offers more than ー integrated circuit wafer encapsulated device. 举例来说,可将存储器装置与控制器封装在一起以形成此种模块。 For example, the memory device and the controller may be packaged together to form such a module. 处理器与存储器也可形成模块。 Processor and memory modules can also be formed. 另ー选择为,这些装置可以是相同装置以(举例来说)形成大的存储器集成电路(例如,商品DRAM或非易失性存储器装置),可将多个相同的晶片放置在一个封装中,其中将此类装置的共用端子与封装的外部触点并联地耦合在一起。 Another ー selection, these devices may be the same means (for example) to form large memory integrated circuits (e.g., commodity DRAM or non-volatile memory device), a plurality of the same wafer may be placed in a package, wherein the common terminal of the package of external contacts of such devices coupled together in parallel.

[0013] 为将多个集成电路在系统配置中耦合在一起,使用各种技术。 [0013] The plurality of integrated circuits coupled together in the system configuration, using a variety of techniques. 可形成挠性电路,其具有提供在挠性衬底的一个或两个侧上的金属化图案,这些图案从而用作用于将两个集成电路连接在一起的互连层。 May form a flexible circuit having a flexible substrate provided on one or both sides of the metallization pattern, the patterns used for the two integrated circuits so connected together interconnect layer. 可使用多个金属层及层间通路技术来形成层压物(例如FR-4 或BT树脂卡),这些层压插入物再次用作用于将集成电路连接在一起的微型电路板并提供用于外部连通的迹线(例如,端子)。 To form a laminate (e.g., FR-4 or BT resin card) may use a plurality of metal layers and inter-layer circuit technology, these laminates inserts again used as the integrated circuit are connected together and to provide for micro-circuit board External communication traces (e.g., terminal).

[0014] 当要将相同的装置耦合在一起以提高集成性(举例来说,在DRAM装置的情况下)时,可使用晶片堆叠。 [0014] When the same device to be coupled together in order to improve integration (for example, in the case of DRAM devices), the wafer stack may be used. 接合线可从引线框架的引线延伸到若干晶片,举例来说,DRAM封装的地址引线可接线到堆叠的若干DRAM集成电路。 Bonding wire may extend from the leads of the lead frame to a number of the wafer, for example, DRAM address pins of the package may be wired to the plurality of stacked DRAM integrated circuit. 晶片的堆叠可包含晶片之间的间隔物以使线接合装备能够接近个别堆叠式集成晶片的晶片垫。 The wafer stack may comprise a spacer between the wafer so that the wire bonding equipment can close individual stackable integrated wafer wafer pad.

[0015] 当要将相同的装置耦合在一起以提高集成性(举例来说,在DRAM装置的情况下)时,可采用晶片堆叠。 [0015] When the same device to be coupled together in order to improve integration (for example, in the case of DRAM devices), the wafer stack may be employed. 可使用各种方法,例如在“朝上”布置中提供多个晶片,且可形成线接合以使用接合线将每一晶片耦合到共用引线框架从而将其并联耦合。 Various methods can be used, for example, providing a plurality of wafers in the "up" arrangement, and may be formed using wire bonding to each of the bonding wires coupling the wafer to a common lead frame so as to be coupled in parallel. 已知采用背对背关系将晶片放置在引线框架上,然而,为维持共用的接合垫覆盖区域,在使用背对背关系时,经常需要“镜像晶片”,以便将晶片的朝上的一个侧上的端子定位在与朝下的对应晶片上相同的位置及次序。 Is known to use a wafer on a back to back relationship on the lead frame, however, in order to maintain a common bond pad coverage area, when using back to back relationship, often need "mirror wafer", in order to locate a terminal side of the wafer on the upward On the down position corresponding to the wafer and the same order. 对“镜像晶片”的需求大大增加制造的复杂性、库存控制及成本,并需要每ー封装式装置包含具有相同功能的两个不同晶片。 "Mirror wafer" greatly increased demand for complexity, inventory control and manufacturing costs, and need each ー packaged device comprises two different wafers having the same functions. 另ー选择为,可以使用插入物或层压电路以实现两个相同功能晶片的背对背定位,此层压插入物也对成品装置増加成本及复杂性。 Another ー selection, or the insert can be used to achieve a laminated circuit positioned back to back two wafers of the same function, the laminate for the finished device insert may also add cost and complexity Zeng.

[0016] 近年来増加商业重要性的特定封装式装置类型为可抽换式非易失性存储卡,其允许在各种电子装置之间进行数据传送。 [0016] In recent years, the importance of the particular business Zeng plus packaged device type removable type nonvolatile memory card, which allow communication between various electronic devices for data transfer. 此非易失性存储器或存储卡可用于各种格式,包含小型快闪(Compact FLASH)、安全数字或SD、迷你SD、存储器棒、USB驱动器、多媒体卡或MMC及其它格式。 This non-volatile memory or a memory card can be used for a variety of formats, including CompactFlash (Compact FLASH), Secure Digital, or SD, mini SD, memory stick, USB drive, multimedia card, or MMC, and other formats. 为提供強健、可靠且稳定的数据存储格式,在单个封装式装置中连同智能控制器一起提供非易失性EEPROM或快闪存储器装置。 To provide robust, reliable and stable data storage format, in a single package type device together with intelligent controller provides nonvolatile EEPROM or flash memory device together. 智能控制器提供数据错误校正及检测、测试、高速缓冲存储及冗余支持功能,以便即使非易失性存储器装置内的某些存储位置预期会出现故障且在产品的使用寿命期间的确出现故障,仍正确地存储及检索用户数据且用户或系统不知晓不再使用存储器阵列内的某些位置;智能控制器用冗余存储器位置来取代这些位置并维持可用位置的映射,其用于维持数据的适当存储及一致性。 Intelligent controller to provide error correction and detection data, test, and cache memory redundancy support, so that even if some of the storage location of the expected non-volatile memory within the device will fail during the life of the product and indeed fails, appropriate intelligent controller with redundant memory location to replace these positions and maintain the mapping of available locations, for maintaining data; still correctly store and retrieve user data and the user or the system does not know not to use certain locations within the memory array Storage and consistency. 对于用户系统来说,装置看似大的存储器阵列,控制器及自动错误校正特征及冗余支持为用户提供透明自动存储器控制操作,此不影响装置的使用。 For the user system, the apparatus appears to be a large memory array, controller, and automatic error correction features and redundancy as providing transparent automatic storage control operation, this does not affect the use of the device. 这些可抽换式存储卡已得到使用并将继续用于其中存储数据的许多应用,尤其针对蜂窝式电话、数码相机、数字媒体存储(例如,用于音乐播放器、视频播放器、电子游戏、个人数字助理或PDA装置的MP3音乐及视频),针对病历存储、智能卡、信用卡及类似物。 These removable memory cards have been using and will continue to be used in many applications in which data is stored, particularly for cellular phones, digital cameras, digital media storage (for example, for a music player, video player, video games, MP3 music and video personal digital assistant or PDA device), for medical memory, smart cards, credit cards and the like.

[0017]图I描绘典型的可抽换式存储卡封装的外部表面。 [0017] Figure I depicts a typical removable storage card package exterior surface. 此卡可以是(举例来说)颁发给本申请案的发明者华莱士(Wallace)的第6,410,355号美国专利中所说明的类型,所述专利以引用的方式并入本文中。 This card may be (for example) the type of award to the inventor of the present application Wallace (Wallace) U.S. Patent No. 6,410,355 as described in said patent is incorporated herein by reference . 在图Ia中,描绘卡(举例来说,安全数字或SD格式卡)的接触侧,其中导电端子101经布置以接触封装100内的集成电路。 In Fig. Ia, the contact side depicting card (e.g., a secure digital or SD card format), wherein the conductive terminal 101 is arranged to contact the integrated circuit 100 within the package. 图Ib描绘封装100的相对侧,其不具有电触点,但通常携载具有用于用户的视觉检查及參考的信息、商标名称、媒体大小及类似物的标签。 Figure Ib depicts the opposite side of the package 100, which does not have an electrical contact, but usually has a user carries a visual inspection and the reference information, trade name, size and the like of the label media. 端子的数量及所使用连接的类型随格式而变化,举例来说,对于安全数字或SD,图Ia所示的端子为典型端子,且使用仅几个外部端子。 Number and type of terminal being used to connect with the format change, for example, for the Secure Digital or SD, the terminal shown in FIG. Ia typical terminal, and using only a few external terminal. 对于经常用于数码相机的小型快闪或“CF”卡来说,端子的数量更大,且所述端子为定位在封装的侧的ー个端上的阴插座。 For frequently used in digital cameras compact flash or "CF" card, the greater the number of terminals, and the terminal is positioned on one end of the package ー side of the female receptacle. 相机或读卡器具有插槽,其用于使用插槽内的阳端子或引脚接纳CF封装的同一端,当将小型快闪卡插入所述插槽时,所述阳端子或引脚进入对应的阴插座,从而完成连接。 Camera or card reader has a slot for a male terminal or pin to accept the package the same end use CF slot when the compact flash card into the slot, the male terminal or pin into the corresponding female receptacle, thereby completing the connection. 可使用其它连接,举例来说,可将USB端ロ用作所述连接。 You can use other connections, for example, can be used as the USB connection terminal ro.

[0018] 用于可抽换式存储卡装置的现有技术封装通常包含以多层层压印刷电路板或“ PC板”形式的复杂插入物或衬底,其为控制器集成电路及存储器装置或装置提供物理支撑及装置间的连通。 Prior art package [0018] for the removable storage card device typically comprises a multilayer laminated printed circuit board or "PC board" in the form of complex insert or substrate, which is an integrated circuit and a memory controller means or providing physical support and device connectivity between devices. 可以是BT树脂、FR4或玻璃纤维或类似物的板通常是层压结构,其并入有金属层,所述金属层经图案化以形成导体迹线、耦合各个层以进行电连接的通路及用于线接合以将板表面上的迹线耦合到集成电路晶片或其它组件、安装到所述板的封装式或裸晶片组件的平台。 May be a BT resin, FR4 or glass fibers or the like plate is usually a laminate structure, which is incorporated with a metal layer, the metal layer is patterned to form conductor tracks, electrically coupled to respective layers and the connection path for wire bonding to traces on the board surface of the coupling to the integrated circuit die or other component mounted to the platform of the plate packaged or bare wafer assembly. 举例来说,可并排提供多个存储器装置或将所述多个存储器装置提供为堆叠,或可使用单个存储器装置,但在任何情况下如现有技术封装的存储卡是复杂的封装式装置,其中至少两个装置封装在其内并耦合在一起。 For example, side by side to provide a plurality of memory devices or said plurality of memory means provides for the stack, or can use a single memory device, but in any case as in the prior art memory card package is complex encapsulated device, wherein at least two devices encapsulated therein and coupled together. 图2以截面视图描绘典型的布置。 Figure 2 depicts a cross-sectional view of a typical arrangement. 在图2中,将现有技术的存储卡200图解说明为具有安装在层压衬底208的同一表面上的集成电路晶片204及205。 In Figure 2, the prior art memory card 200 is illustrated as an integrated circuit chip mounted on the same surface of the laminate substrate 208 having a 204 and 205. 接合线203将集成电路晶片的有源表面或正面上的接合垫连接到所述衬底的上表面上的导电区域或平台206。 Conductive regions or platforms bonding wire 203 to the bonding pads of the active surface of the integrated circuit wafer or on the front side is connected to the upper surface of the substrate 206. 将两个此类接合线显示为通过在平台206上连接集成电路的两个晶片垫而将其电耦合,所述集成电路从而被电耦合并可以是(举例来说)存储器及控制器集成电路。 Such joining of the two lines displayed on the platform 206 through the connection pad and the integrated circuit of the two wafers to be electrically coupled, so as to be electrically coupled to the integrated circuit and can be (for example) the memory controller IC and . 使用晶片附着材料209来将晶片204、205固定到衬底208。 Use of the wafer 209 is attached to the wafer material 204, 205 fixed to the substrate 208. 在形成接合线203并将其附着到集成电路晶片204及205以及衬底上的平台206的常规半导体封装装配过程之后,在可以是热硬化或室温模制化合物或其它囊封材料的囊封剂211中囊封所述接合线与集成电路晶片。 After 203 and 204 attached to the ICs and the conventional semiconductor package assembly process, and platform 205 is formed on the substrate 206 bonding wire at room temperature or may be a thermosetting molding compound or other encapsulating material encapsulating agent 211, the bonding wire and encapsulated integrated circuit die. 所述封装可以外壳201 (其可以是塑料)完成,从而覆盖衬底与模制材料。 The package may housing 201 (which may be plastic) is completed, so as to cover the substrate and the molding material. 在另一方法中,颁发给本发明的发明者华莱士(Wallace)的第6,639,309号美国专利(也以引用的方式并入本文中)描绘可抽换式存储卡,其通过线接合连接及过模制囊封而在多层PC板材料的相对表面上并入有存储器装置及控制器装置。 In another method, awarded to the inventors of the present invention, Wallace (Wallace) US Patent No. 6,639,309 (also incorporated herein by reference) depicts removable storage card, which by wire bond connection and encapsulated and overmolded on the opposite surface of the multilayer PC board material incorporates a memory device and a controller means.

[0019] 封装半导体集成电路的其它方法可并入有耦合在一起的多个引线框架或多层引线框架。 [0019] Other methods for encapsulating a semiconductor integrated circuit may incorporate a plurality of lead frames coupled together, or multi-layer lead frame. 举例来说,颁发给卡斯托(Casto)的第5,147,815号美国专利(其以引用的方式并入本文中)描绘两个集成电路晶片及两个引线框架,其装配并提供在单个模制双列直插式塑料或“DIP”封装中。 For instance, issued to Casto (Casto) U.S. Patent No. 5,147,815 (which is incorporated by reference herein) depicts the two ICs and two lead frames, fitted and provided in a single molded plastic dual in-line or "DIP" package. 将集成电路晶片及其相应的引线框架布置为背对背关系且通过使用接合线来将每一晶片耦合到相应的引线框架,另ー选择为,在插入物的相对侧上将集成电路布置为面对面关系且在倒装芯片(Flip Chip)布置中将所述集成电路耦合到其相应的引线框架,将所述两个集成电路独立地耦合到布置在封装式装置的相对侧上的外部引线且所述两个集成电路并非彼此电通信。 The IC chip and the corresponding lead frame and arranged back to back relationship by the use of a bonding wire to each wafer is coupled to a respective lead frame, and the other ー selected to, opposite sides of the insert will be arranged in confronting relationship to the integrated circuit and flip-chip (Flip Chip) is arranged in the integrated circuit will be coupled to its corresponding lead frame, the two integrated circuits disposed independently coupled to the opposite side of the packaged device and the external lead two integrated circuits are not in electrical communication with each other. 颁发给吉田(Yoshida)等人的第6,603,197号美国专利(也以引用的方式并入本文中)提供耦合到至少两个不同集成电路装置的多个引线框架,将所述两个不同集成电路装置耦合到所述引线框架的各引线以形成模块,其中某些共用引线(举例来说,电源引线)在封装的外部物理及电耦合在一起,使得两个集成电路装置可接收信号。 Issued to Yoshida (Yoshida) et al., U.S. Patent No. 6,603,197 (also incorporated by reference herein) provide coupled to at least two of the plurality of lead frames of different integrated circuit device, the said two Different integrated circuit device is coupled to the leads of the lead frame to form a module, some of the common wire (e.g., power leads) electrically coupled to the external physical and packaged together, such that the two integrated circuit device can receive signals . 同样,颁发给帕克(Park)等人的第6,316,825号美国专利(也以引用的方式并入本文中)提供堆叠封装以将两个相同的集成电路装置(例如,存储器装置)堆叠在具有两个在所述封装的外部物理耦合的引线框架的模制封装中,使得耦合到外部引线的每一信号物理及电耦合到以并联方式连接的两个相同存储器装置中的每ー者。 Similarly, issued to Park (Park), et al. U.S. Patent No. 6,316,825 (also incorporated by reference herein) provide two identical stacked package to an integrated circuit device (e.g., memory device) Stacking having two molding package encapsulating said external physical coupling of a lead frame such that the external lead coupled to each signal physically and electrically coupled to two identical memory devices connected in parallel in each of those ー.

[0020] 所属技术中已知的其它布置提供耦合到多层引线框架的单个集成电路,举例来说,颁发给麦克沙恩(McShane)的第5,220,195号美国专利(也以引用的方式并入本文中)提供单个集成电路,其线接合到多层引线框架并包含封装内的多层引线框架的部分之间的物理连接及所形成的通孔通路,其中接合线延伸到所述通路中以物理接触定位在集成电路下面的引线框架层,从而使得能够在所述封装式装置内形成多个电压层。 [0020] relevant to other arrangements known in the art to provide a multi-layer lead frame is coupled to a single integrated circuit, for example, issued to McShane (McShane) U.S. Patent No. 5,220,195 (also referenced incorporated herein) providing a single integrated circuit wire bonded to the multi-layer lead frame and contains the physical connection portion of the multilayer lead frame within the package between the passage and the through hole is formed, wherein the bonding wire extending into the path to physical contact in the integrated circuit positioned below the lead frame layer, so that the layer can be formed in a plurality of voltage within the encapsulated device.

[0021] 虽然存在用于多个集成电路的现有技术封装,但不断需要多晶片封装,其在維持封装的可靠性的同时提供降低的生产成本。 [0021] Although the presence of the prior art package for a plurality of integrated circuits, multi-chip package but is a continuing need, which provide reduced production costs while maintaining the reliability of the package.

[0022] 因此,需要经改善的多集成电路封装及用于封装多个集成电路的方法,所述方法简单且可靠,允许各集成电路装置之间任意连接,不需要昂贵的插入物、印刷电路板或衬底,且制造成本低于现存封装及方法。 [0022] Therefore, a need improved integrated circuit package and method for multi-packaging a plurality of integrated circuits, the method is simple and reliable, allowing any connection between the integrated circuit device, no expensive inserts, a printed circuit board or substrate, and the manufacturing cost is lower than the existing packaging and method.


[0023] 本发明的各优选实施例提供一种用于多半导体集成电路或晶片的封装,其电连接ー个或ー个以上集成电路,提供对所述集成电路的机械支撑,提供设施以在所述集成电路之间进行任意连接,且提供到封装式装置的外部连接的电连通。 [0023] Each preferred embodiment of the present invention to provide a semiconductor integrated circuit or multi-chip package, which is electrically connected ー ー one or more integrated circuits, to provide mechanical support to the integrated circuit, in order to provide facilities arbitrary electrical connection between said integrated circuit, and is supplied to the encapsulated device external connection communication. 本发明的封装不需要现有技术中所使用的类型的插入物或衬底,且材料使用与半导体处理工业中已知的现存装备及自动化工厂机器兼容的常规线接合及引线框架技木;使得使用及构建本发明不需要重组或专门装备。 Package of the present invention does not require use of the prior art type of insert or substrate, and the material used in semiconductor processing equipment known in the industry and the existing automated plant machinery is compatible with conventional wire bonding and lead frame technology of wood; such that the use and construction of the present invention does not require restructuring or specialized equipment.

[0024] 在本发明的第一实施例中,提供第一引线框架且其经定位而上覆于简单的绝缘体层上。 [0024] In a first embodiment of the present invention, there is provided a first lead frame and which is positioned on a simple and overlying insulator layer. 所述绝缘体层具有为在某些位置中形成的开ロ的通路且引线框架的某些引线上覆于所述通路。 The insulator layer having a certain lead to the formation in some locations in the path and open ro lead frame overlying said passageway. 引线框架的其它引线可延伸到所述绝缘体的外部边界或延伸出所述绝缘体的边缘。 Other leads of the lead frame may extend to the outer boundary of the insulator or the insulator extending edge. 引线框架的某些引线可以不延伸到外部连接器。 Some of the leads of the lead frame may not extend to the external connector. 提供第一集成电路晶片且其经定位而接近于引线框架的内部端,在某些实施例中,引线框架可具有提供在内部的开ロ且可将晶片放置在所述内部开口中。 Providing a first integrated circuit die and its inner end positioned rather close to the lead frame, in some embodiments, the lead frame may have provided in the interior of the open ro and may be placed on the inside of the wafer opening. 在其它实施例中,晶片可座落在引线框架的引线上方,或在引线框架的引线下方。 In other embodiments, the wafer can be located above the leads of the lead frame, or below the leads of the lead frame. 在优选实施例中,将晶片线接合到引线框架以将集成电路的所述引线中的一者或一者以上电连接到所述引线框架的所述引线。 In a preferred embodiment, the wafer is wire-bonded to the lead frame to the lead of the integrated circuit in one or more of the lead is electrically connected to the lead frame. 在其它优选实施例中,可使用如所属技术中已知的倒装芯片技术将引线框架的引线连接到晶片。 In other preferred embodiments may be used as one of ordinary skill in the art will be aware of the flip-chip connected to the leads of the lead frame of the wafer.

[0025] 然后,第二引线框架经放置而上覆于绝缘体的第二(相対)表面上。 [0025] Then, after placing second lead frame and overlying the second insulator (phase Dui) surface. 第二引线框架的某些引线经定位而上覆于绝缘体的通孔通路上,以用于且对应于第一引线框架的某些引线。 Some lead of the second lead frame which is positioned on the upper overlying the insulator through hole passage, and for some wire corresponding to the first lead frame. 第二引线框架的其它引线可延伸到绝缘体层的外部以与完成的装置进行外部电连接,并可延伸出绝缘体的外部边界。 Other external lead of the second lead frame may extend into the insulator layer so as to complete the device with the external electrical connection, and the outer boundary extending insulator. 第二集成电路晶片经放置而接近于第二引线框架的内部引线。 The second integrated circuit die and close to the inner lead by placing second lead frame. 第二引线框架可在邻近引线框架的引线的内部端的中心部分中具有用于接纳晶片的空间,或可使用芯片下引线或芯片上引线引线框架布置。 The second leadframe leads of the lead frame adjacent the inner end of the central portion having a space for receiving the wafer, or may use on-chip or wire leads of the lead frame is arranged under the chip. 进行从第二集成电路上的晶片垫端子到第二引线框架的所述引线中的至少ー者的电连接(例如,接合线连接或倒装芯片连接)。 Carried from the wafer terminal pad on the integrated circuit to the second lead of the second lead frame by at least ー electrical connection (e.g., a bonding wire connection or flip chip connection). 在典型的应用中,存在从集成电路延伸到引线框架的若干且有时许多接合线。 In a typical application, there are several and sometimes many bonding wires extending from the integrated circuit to the lead frame. 另ー选择为,可在将任一晶片附着到其对应的引线框架之前将第一及第ニ引线框架彼此附着。 Another ー selected to be prior to 任一晶 sheet attached to its corresponding first and second lead frame Ni lead frame attached to each other.

[0026] 有利地,穿过绝缘体中的通路来电耦合第一及第ニ引线框架的某些引线。 [0026] Advantageously, the passage through the insulator to electrically couple the first and second lead frame ni some leads. 本发明的此方面使得通过穿过所述绝缘体进行所述两个引线框架之间的电连接的设施来将所述第一与第二集成电路晶片电耦合在任意位置中成为可能。 This aspect of the invention enables electrical connection between the two facilities lead frame by passing through the insulator to the first and second integrated circuit die are electrically coupled in any possible position. 在第一优选实施例中,通过使第一及第ニ引线的引线框架引线物理变形到绝缘体中的通路内的空间中,且然后在通路内的两个引线之间进行物理接触,便可实现连接。 In a first preferred embodiment, by making the first and second lead of the lead frame leads ni physical deformation of the insulator into the space within the passage, and then in the passage between the two leads of physical contact, can be realized connection. 在优选实施例中,从而在两个引线框架之间进行导电焊接。 In the preferred embodiment, so that the lead frame between two electrical conductive soldering. 举例来说,可使用通过热施加的能量、电能量、超声波能量、激光能量及类似物进行焊接。 For example, heat may be applied by the use of energy, electrical energy, ultrasound energy, laser energy, and the like welding. 在其它优选实施例中,可通过提供定位在通路内的导电材料(例如,用作电连接的导电膏,且所述连接可使用热或电能量来完成)来在两个引线框架之间进行电连接。 In other preferred embodiments, may be positioned within the passageway by providing a conductive material (e.g., electrically conductive paste used for connection, and the connection can be used to complete the thermal or electrical energy) between the two lead frames to be electrically connected.

[0027] 在其它优选实施例中,绝缘体可由各向异性导电材料形成,所述材料最初在所有方向上用作绝缘体,但当在一区域中施加压カ或热能量或两者时,所述材料在垂直方向上变为选择性导电,同时在平面方向上仍然为绝缘体。 When [0027] In other preferred embodiments, the insulator is formed by the anisotropic conductive material, the material initially used as an insulator in all directions, but when application of the pressure or heat energy or both grades in an area, the material in the vertical direction becomes selective conductive, while still in a planar direction is an insulator. 一般来说,通路是其中在邻近绝缘体的顶表面的导体与邻近绝缘体的底表面的导体之间实现电连通的区域。 In general, the path is an area in which adjacent the top surface of the insulator between conductors adjacent the bottom surface of the insulator and conductor electrically connected.

[0028] 集成电路晶片可经定位而上覆于绝缘体的相对表面上,使得所述集成电路晶片可以是背对背关系。 [0028] on opposite surfaces of an integrated circuit wafer can be positioned and overlying the insulator, so that the ICs can be back to back relationship. 不同于现有技术的背对背布置,当使用本发明时不需要镜像晶片,因为本发明提供的穿过绝缘体形成电连接的方法允许两个装置的端子的任意连接。 Unlike the prior art are arranged back to back, the mirror is not required when using the present invention, the wafer, because the present invention provides a method of forming an electrical connection through the insulator permits any two terminal devices connected. 至于现有技术封装中的某些封装,不需要对准或反射两个集成电路晶片的端子。 As some of the prior art package encapsulation, does not require alignment or reflected two integrated circuit die terminals.

[0029] 此外,在某些实施例中,对于DRAM、EEPR0M、快闪或其它动态或非易失性存储器装置来说,集成电路晶片可以是相同的,其中可通过将多个相同的集成电路晶片耦合在一起而创建较大的封装式装置。 [0029] In addition, in some embodiments, for DRAM, EEPR0M, flash, or other dynamic or non-volatile memory devices, the ICs may be the same, which can be obtained by a plurality of identical integrated circuits chip coupled together to create a larger packaged devices. 在其它优选实施例中,晶片可具有不同的功能(例如存储器控制器与存储器装置、模拟电路与数字装置、感测器与控制器装置及类似物)以在完成的封装式装置中提供集成功能。 In other preferred embodiments, the wafer may have different functions (e.g., memory controller and memory devices, analog circuits and digital devices, sensors and controller means, and the like) in order to provide integrated functionality in the finished encapsulated device .

[0030] 在替代性优选实施例中,本发明可提供:具有形成于所选定位置中的通路的绝缘体、上覆于所述绝缘体层的ー个表面上的第一引线框架、上覆于相对的绝缘体层上的第二引线框架、使用已知的倒装芯片技术耦合到所述第一引线框架的第一集成电路,其中集成电路接合垫经定位而在物理上接近于所需的引线且形成焊料球或焊料垫,然后使用能量来回流所述焊料球或焊料垫以在晶片垫与引线的内部之间形成机械及电连接;如以前完成的装置具有穿过绝缘体中的通路在所述第一与第二集成电路之间进行的电连接一祥,可使用倒装芯片技术同样地将第二集成电路耦合到所述第二引线框架。 [0030] In an alternative preferred embodiment, the present invention provides: an insulator having formed at the position of the selected path, the ー overlying the first lead frame on the one surface of the insulator layer, overlying a second insulator layer on the lead frame opposite, using known flip-chip technology coupled to the first integrated circuit of the first lead frame, wherein the integrated circuit bonding pads positioned near the required lead and physically and forming solder balls or pads, and then use the energy to reflux the solder balls or pads to the interior of the wafer between the pad and the lead of a mechanical and electrical connection; as previously completed device having a through passage in the insulator electrolysis is performed between said first and second integrated circuit connected to a Cheung, similarly to the second integrated circuit coupled to the second lead frame may be used flip-chip technology. 因为第一及第ニ晶片两者在此优选实施例中使用倒装芯片技术耦合到所述引线框架,因此可以面对面关系来布置所述集成电路装置。 Because both the first and second Ni wafer In this preferred embodiment, the use of flip-chip technology coupled to the lead frame, it can be arranged in confronting relationship to said integrated circuit device.

[0031] 涵盖于本发明及随附权利要求书内的替代性实施例包含将倒装芯片连接与线接合连接组合以便(举例来说)可使用倒装芯片技术将ー个晶片耦合到第一引线框架,且可使用线接合将第二晶片耦合到第二引线框架。 [0031] encompassed by the present invention and the appended claims within the claim book alternative embodiment comprises flip-chip connected to the wire bonding for connection combinations (for example) may be flip-chip technique ー wafer coupled to the first lead frame, and wire bonding may be used to couple the second wafer to the second lead frame.

[0032] 在另ー优选实施例中,使用本发明的封装设备及方法形成可抽换式存储卡;提供具有形成于所选定位置中的通路的绝缘体层,第一引线框架经定位而上覆于所述绝缘体上且具有上覆于所述绝缘体中的通路上的某些引线,作为非易失性存储器装置的第一集成电路经定位而接近于所述第一引线框架且在所述非易失性集成电路与所述引线框架之间进行至少ー个电连接,接近于第二引线框架提供第二集成电路,其经定位而上覆于所述绝缘体的相对表面上并具有某些引线,所述引线上覆于所述绝缘体中的通路上,所述第二集成电路是用于操作所述非易失性存储器装置的控制器电路,所述第二集成电路电连接到所述第二引线框架。 [0032] In another preferred embodiment ー using encapsulation equipment and method of the present invention is formed removable memory card of embodiment; position in the insulator layer for the selected path, the first lead frame and positioned on the offers having formed overlying said insulator and having a certain lead overlying the insulator pathway, as a first non-volatile memory device and an integrated circuit positioned proximate to the first lead frame and in the performed between a non-volatile integrated circuit and at least one of said lead frame ー electrically connected, close to the second lead frame providing a second integrated circuit, and its positioned overlying opposite surfaces of said insulator and having a certain lead, the lead wire overlying said insulator passage, said second integrated circuit is a controller circuit for operating the non-volatile memory means, said second integrated circuit electrically connected to the The second lead frame.

[0033] 通过使用本发明的方法穿过所述绝缘体中的通路在所述第一与第二引线框架之间形成电连接来在所述存储器控制器电路与所述非易失性存储器之间进行电连接。 The insulator passage between said first and second lead frame electrically connected to the memory controller circuit and the nonvolatile memory between the [0033] By using the present invention through the method of are electrically connected. 可通过过模制或囊封所述绝缘体、第一及第ニ集成电路及所述第一及第ニ引线框架的部分来完成所述存储卡,所述第一及第ニ引线框架的剰余外部部分用于形成完成的存储卡的外部连接。 By over-molding or encapsulating the insulator, the first integrated circuit and the first and second ni ni portion of the lead frame to complete the memory card, the writing is the first and second external lead frame than 剰part of external memory card connection completion for forming.

[0034] 有利地,用于本发明的优选实施例的绝缘体可包括各种已知材料。 [0034] Advantageously, the insulator used in the preferred embodiment of the present invention may include a variety of known materials. 因为在绝缘体内或绝缘体上不需要电连接、复杂的多层布线或金属化图案,因此绝缘体可用将所述第一与第二引线框架彼此电绝缘的任何材料形成且还可具有在其内形成的通孔通路。 Because there is no electrical connection in an insulator or insulator, complex multi-layer wiring or metallization pattern, the insulator can be used any material so the first and second lead frame electrically insulated from each other and may also be formed having formed therein The through-hole passage. 可使用塑料、玻璃、陶瓷、玻璃纤维、树脂、PC板、胶带、膜、纸及其它绝缘体。 May be used plastic, glass, ceramic, fiberglass, resin, PC board, tape, film, paper, and other insulation. 化学蚀刻、光刻法、激光钻孔或机械钻孔エ艺可形成所述通路。 Chemical etching, photolithography, laser drilling or mechanical drilling of the passageway may be formed Eito art. 可使用塑料或树脂模制来形成其中形成有通路的绝缘体。 Can be used plastic or resin-molded to form a via formed therein insulator. 所述绝缘体可形成为各种厚度并可视需要而为刚性或挠性材料。 The insulator may be formed in various thickness and visual needs of a rigid or flexible material. 可过模制所述绝缘体以完成所述封装式装置,另一选择为,可将所述绝缘体、集成电路及弓I线框架组合件定位在外壳的空腔中或预形成的主体结构内,随后使用盖子或层以粘合剂或密封剂来密封所述结构。 The insulator may be over-molded to complete the packaged device, Alternatively, the insulator may be an integrated circuit, and I bow wire frame assembly positioned within the main structure of the housing cavity or preformed, then used to cap or an adhesive or sealant layer to seal the structure.

[0035] 在另ー优选实施例中,可通过并入有绝缘体的任ー侧上的多个集成电路晶片而在单个封装中提供集成系统,将所述多个晶片线接合到引线框架,所述引线框架穿过所述绝缘体中的通路而耦合以在所述集成电路之间进行任意连接,其中用于系统的封装式组合件包含无源元件,例如电阻器、电容器或感应器。 [0035] In another ー preferred embodiment, by incorporating a plurality of integrated circuit dies on either side of the insulator ー while providing an integrated system in a single package, the plurality of wafer bonding wire to the lead frame, the said lead frame through a passage in the insulator and coupled to the integrated circuit between any connection, wherein the assembly is packaged for systems include passive components such as resistors, capacitors or inductors. 然后可将整个组合件过模制成使用本发明的方法提供的完成封装式系统。 The entire assembly may then be over-molded using the method of the present invention to provide a complete packaged system.

[0036] 本发明的实施例的优点包含提供使用与现存工具兼容的常规线接合或倒装芯片技术及封装模制方法并使用与现存自动化半导体封装基础构造兼容的材料来形成包含彼此电耦合的多集成电路装置的多集成电路模块而无需现有技术的复杂插入物、挠性电路、层压衬底或图案化印刷电路板的设备及方法。 [0036] advantages of embodiments of the present invention comprises providing tools compatible with existing conventional wire bonding or flip-chip technology and encapsulation molding method and compatible with existing automated basic structure of a semiconductor package formed of a material containing electrically coupled to each other multiple integrated circuit module more complex integrated circuit devices without the insert, the flexible circuit, patterned laminated substrate or a printed circuit board apparatus and methods of the prior art.

[0037] 以上说明已相当广泛地概述了本发明的实施例的特征与技术优点,以便可更好地了解以下对本发明的详细说明。 Above [0037] Description has outlined rather broadly the features and technical advantages of the embodiments of the present invention, in order to better understand the following detailed description of the invention. 所属技术中的技术人员应了解,可容易地将所掲示的概念及具体实施例用作修改或设计用于实行本发明的相同目的的其它结构或エ艺的依据。 Ordinary skill in the art will appreciate, the concept can be easily shown by kei and cases used for modifying or designing for carrying out the same purposes of the present invention, or other structures in accordance with embodiments Eito arts. 所属技术中的技术人员还应认识到,此类等效构造并不背离如所附权利要求书论述的本发明的精神及范围。 The spirit and scope of ordinary skill in the art should also realize that such equivalent constructions do not depart from the appended claims as discussed in the present invention.

附图说明 Brief Description

[0038] 为更完全地了解本发明及其优点,现在參考以下结合附图所作的说明,所述附图是出于易于了解的目的而提供的代表性例示且并非按比例绘制,所述附图中: [0038] for a more complete understanding of the invention and the advantages thereof, reference is now made to the following description of the accompanying drawings, the drawings are for representative purposes embodiment provides easily understood and are not shown to scale, the attachment in which:

[0039] 图I以图Ia的俯视图及图Ib的仰视图描绘现有技术可抽换式存储卡封装; [0039] Figure I is a plan view and a bottom view Figure Ia, Ib depicts a prior art removable storage card packaging;

[0040] 图2描绘如图I所图解说明的包含存储器装置及控制器装置的现有技术可抽换式存储卡的截面图; [0040] Figure 2 depicts a sectional view of the prior art includes a memory device and a controller device I the illustrated removable memory card in FIG;

[0041] 图3描绘可并入到本发明的优选实施例中的具有通孔通路的绝缘体层的俯视图; [0041] Figure 3 depicts the present invention may be incorporated into the preferred embodiment in a plan view of an insulator layer having a through hole passage embodiment;

[0042] 图4描绘图3的绝缘体层的截面图; [0042] Figure 4 depicts a sectional view of the insulator layer 3;

[0043] 图5描绘例如图3、4中的具有定位在所述绝缘体上的引线框架及集成电路的绝缘体层的俯视图; [0043] Figure 5 depicts the example in Figures 3, 4 positioned on said insulator having a lead frame and integrated circuit a plan view of the insulator layer;

[0044] 图6以截面图描绘图5的装置,后跟额外的处理步骤; [0044] Figure 6 depicts a sectional view of the apparatus of FIG. 5, followed by additional processing steps;

[0045] 图7a、7b以截面图描绘本发明的绝缘体层的额外优选实施例; [0045] Figures 7a, 7b to the cross-sectional view depicting an additional insulating layer of the present preferred embodiment of the invention;

[0046] 图8描绘作为本发明的优选实施例的完成封装式装置的截面图; [0046] Figure 8 depicts a sectional view of an example of complete packaged device as a preferred embodiment of the present invention;

[0047] 图9描绘作为本发明的另ー优选实施例的另ー完成封装式装置的截面图; [0047] Figure 9 depicts the present invention as a complete packaged device further ー sectional view of another preferred embodiment ー;

[0048] 图10描绘图9的装置的俯视图,及 [0048] Figure 10 depicts a plan view of the apparatus of FIG. 9, and

[0049] 图11描绘作为本发明的另ー优选实施例的另ー完成封装式装置的截面图。 [0049] Figure 11 depicts the present invention further ー ー another preferred embodiment of the apparatus is completed packaged sectional view.

[0050] 不同图式中的对应编号及符号通常指代对应的部件,除非另有指示。 [0050] different schemata corresponding numbers and symbols generally refer to corresponding parts unless otherwise indicated. 绘制所述图式以清楚地图解说明优选实施例的相关方面且所述图式不必按比例绘制。 The drawings are drawn to clearly illustrate the relevant aspects of the preferred embodiments and the drawings are not necessarily drawn to scale.


[0051] 下文详细说明目前优选实施例的操作及制作。 [0051] the following detailed description of the operation and production of cases currently preferred embodiment. 然而,所说明的实施例及实例并非本发明所涵盖的仅有应用或使用。 However, the embodiments and examples described in the present invention are not only covered by the application or use. 所论述的具体实施例仅例示用以制造及使用本发明的具体方式,而不限制本发明的范围。 The specific embodiments discussed are illustrative only and the use of specific methods for the manufacture of the present invention is shown, without limiting the scope of the invention. 所述图式是出于说明的目的而非按比例绘制。 The drawings are for purposes of illustration and not drawn to scale.

[0052] 图3描绘用于本发明的优选实施例中的绝缘体层300的俯视图。 [0052] Figure 3 depicts a preferred embodiment of the present invention, a plan view of the insulator layer 300 of Fig. 绝缘体层300可包括与半导体处理步骤兼容的许多绝缘材料中的任一者,例如迈拉(Mylar)、宇部兴产(Upilex)、卡普顿(Kapton)及其它膜、绝缘纸、树脂、聚酰亚胺、玻璃、玻璃纤维及类似物,其在所属技术中已熟知。 Insulator layer 300 may include compatibility with semiconductor processing steps many insulating materials in any one of, for example, Myra (Mylar), Ube (Upilex), Kapton (Kapton) and other films, insulation paper, resins, poly imide, glass, glass fiber, and the like, which are well known in the art belong. 层300是电绝缘且优选地具有与某些热エ艺(例如,转移模制)兼容的物理特性。 Layer 300 is electrically insulating and preferably has a compatibility with some heat Eito art (e.g., transfer molding) physical characteristics. 所述绝缘层中的通孔通路301在如下文详述的预定位置处形成,并提供形成于绝缘层300中的通孔。 The insulating layer 301 via a through hole at a predetermined position is formed as detailed below, and provided in the insulating layer 300 is formed in the through hole. 通孔通路可以是任何大小但在优选实施例中直径约为3-10密耳且优选地直径约为5密耳。 The through-hole passage can be any size but embodiments of about 3-10 mils in diameter and preferably a diameter of about 5 mils in the preferred embodiment. 在将要说明的第一优选实施例中,所述通路是开放性通孔,在下文所说明的其它实施例中,所述通路可用导电膏或粘合剂加以填充。 In a first preferred embodiment will be described, the path is open through-holes, in other embodiments described hereinafter, the path is not available to be filled with a conductive paste or adhesive.

[0053] 图4以截面图描绘图3的绝缘层。 [0053] Figure 4 depicts a sectional view of the insulating layer 3 of FIG. 在图4中,将通孔通路301显示为延伸穿过绝缘层300。 In Figure 4, the passage 301 is displayed as a through hole extending through the insulating layer 300. 举例来说,可通过激光钻孔、机械钻孔、蚀刻、冲孔或使用其它手段来形成通孔通路301以在材料(例如,模制)中形成孔。 For example, by laser drilling, mechanical drilling, etching, or punching to form through holes 301 to form a passage hole in the material (e.g., molding) using other means. 如在所属技术中所熟知,可使用光刻法来将所述表面上具有用于界定所述孔的位置及尺寸的正或负抗蚀剂的抗腐蚀层图案化,可施加选择性蚀刻来移除所述材料,且然后可剥离所述图案层。 As is well known in ordinary skill may be used photolithography of positive or negative resist having a corrosion-resistant layer is patterned for defining the position and size of the holes of the upper surface, may be applied to selective etching removing the material, and then the pattern layer is peelable.

[0054] 图5描绘本发明的优选实施例在已完成多个装配步骤之后的俯视图。 Example After the assembly step has been completed a plan view of a plurality of [0054] Figure 5 depicts a preferred embodiment of the present invention. 在图5中,绝缘体层300已具有形成于所选定位置中的通孔通路301。 In Figure 5, the insulator layer 300 is formed at a position having a through hole 301 of the selected passage. 引线框架具有引线502并包含上覆于通孔通路位置301上的某些引线。 A lead frame having leads 502 and comprises overlying certain location terminal via path 301. 集成电路晶片303经定位而接近于引线502的内部端。 The integrated circuit die 303 is positioned close to the inner end 502 of the lead. 形成接合线505并将接合垫507电耦合到引线502。 Forming a bonding wire 505 and the bonding pad 507 is electrically coupled to the lead 502. 虽然在图5中所描绘的视图中不可见,但执行对称操作以将第二引线框架及第ニ集成电路晶片定位在绝缘体层300的相对表面上,其中将第二引线框架的某些引线定位在通孔通路301下方。 While depicted in Figure 5 the view is not visible, but the operation to perform symmetric second integrated circuit die lead frame and the second Ni positioned on the opposite surface of the insulator layer 300, wherein some of the leads of the second lead frame positioning 301 through holes in the bottom path.

[0055] 图6描绘本发明的优选实施例在装配的中间阶段的截面图。 Example sectional view at an intermediate stage of assembly [0055] Figure 6 depicts a preferred embodiment of the present invention. 在图6中,将集成电路晶片303显示为定位在绝缘体层300的第一表面上方。 In Figure 6, the integrated circuit die 303 is shown as positioned above the first surface of the insulator layer 300. 以截面图显示引线框架引线502,且将接合线505显示为将集成电路晶片的接合垫连接到引线框架引线502。 In cross section illustrating the lead frame leads 502, and the bonding wire 505 is shown as an integrated circuit wafer bonding pads connected to the lead frame leads 502. 显示通孔通路301在绝缘体层300中的所选定位置处形成。 Displayed via the through hole 301 is formed at a position of the insulating layer 300 selected.

[0056] 将引线框架601显示为定位在绝缘体层300下面并在通孔通路301下面延伸。 [0056] The lead frame 601 is displayed to be positioned in and extending below the insulator layer 300 via the through-hole 301 below. 使用接合线605将集成电路晶片604从接合垫603耦合到引线框架601引线。 Using bonding wires 605 from the integrated circuit die 604 is coupled to a bond pad 603 of the lead frame 601 leads.

[0057] 如图6所图解说明,可将引线框架引线耦合在一起以穿过绝缘体而在通孔通路位置301内形成物理及电连接。 [0057] FIG. 6 illustrates, can be coupled to the lead frame leads are formed through the insulator physically and electrically via the through hole 301 in the position of the connection. 在图6中,使用焊接工具607在通孔通路301中将引线502与602挤压在一起并使其变形,且施加能量以使所述两个引线变为焊接在一起。 In Figure 6, using the welding tool 607 in the through hole 301 in the lead passages 502 and 602 are squeezed together and deformed, and applying energy to cause the two leads become welded together. 可使用超声波、电及/或热能量来形成所述焊接,所涵盖的方法包含使用电阻焊接、电容放电或激光焊接。 May be used to form the ultrasonic welding, electrical and / or thermal energy, the method comprises using covered resistance welding, laser welding or capacitor discharge. 在某些实施例中,可在装配之前用材料涂布所述弓I线框架弓I线以通过点镀敷或其它方法帮助形成所述焊接。 In certain embodiments, the material may be coated with a wire frame of the bow I I bow line through point plating or other methods to help form the weld prior to assembly. 此耦合操作是在每一通孔通路位置301中执行的。 This coupling operation is performed in the position of each through orifice passage 301. 通过适当地设计所述引线框架及绝缘体层300,可在如图5及图6所示的两个集成电路之间的任何所需位置处进行电连接。 By properly designing the lead frame and the insulating layer 300, may be electrically connected at any desired position of two integrated circuits shown in Figs. 5 and 6 between. [0058] 在优选方法中,使用工具(例如,图6中的工具607)在上与下引线框架引线之间形成焊接并同时在绝缘体层300中形成通孔通路301,即所述绝缘体最初并没有形成于其中的孔,将所述引线框架定位在彼此相対的任ー侧上,且定位在需要将来自所述上及下引线框架的引线耦合在一起的位置处。 [0058] In a preferred method, using a tool (e.g., tool 607 in FIG. 6) between the upper and the lead frame leads are welded and formed under the insulator layer 300 while forming a through hole passage 301, i.e. the insulator initially no holes formed therein, said lead frame is positioned on each other in any ー Dui side and positioned at a required position from the upper and lower leads of the lead frame coupled together. 在此优选方法中,焊接工具607用于将能量(例如,热)施加于需要连接的位置处的引线,绝缘体材料响应于所述能量而熔化或蒸发且在移除所述绝缘体材料时形成通孔通路301,使所述引线物理变形到通孔通路301中且然后在单个连续操作中将所述引线焊接在一起。 In this preferred method, the bonding tool 607 is used to lead the energy (e.g., heat) is applied at a position to be connected, the insulator material in response to melt or vaporize upon removal of the energy and the insulator material is formed through orifice passage 301, so that the physical deformation of the lead passage 301 into the through hole in a single continuous operation, and then the lead will be welded together. 在此方法中,因为绝缘体不需要图案化或设计,因此可在大大地降低绝缘体层的成本。 In this method, because the insulator does not require patterning or design, and therefore can significantly reduce the cost of the insulator layer.

[0059] 图7a及7b描绘用于在绝缘体层300中的通孔通路位置301处连接上与下引线框架引线的替代性方法。 [0059] Figures 7a and 7b depict the connection to the next lead frame leads alternative methods through hole 301 for passage position in the insulator layer 300. 在图7a中,描绘用于本发明的封装的具有填充有导电材料705的通孔通路301的绝缘体层300的一部分。 A portion of the insulator layer 300 is filled with a conductive material having a through-hole 705 of passage 301 in Figure 7a, the present invention is depicted for enclosing the. 将导电材料(例如,导电膏)沉积在通孔通路301中且随后随着装配过程的继续而将所述导电材料定位在引线框架引线之间。 The conductive material (e.g., conductive paste) is deposited in the through hole via 301 and then continues with the assembling process and the conductive material is positioned between the lead frame leads. 所述导电材料完成如图6的两个集成电路装置之间的电连接。 As shown the conductive material to complete an electrical connection between two integrated circuit device 6. 如所属技术中所熟知,所述导电材料可以是筛分于所述通路中的导电膏或导电油墨,举例来说,可从新泽西州(New Jersey)的落基山(Rocky Hill)的派利克(Parelec)购得的商品名为帕莫德VLT(Parmod VLT)的导电油墨材料;且可通过丝网印刷、激光研磨及填充或喷墨印刷工艺来施加此材料。 Owned technology known as the conductive material can be screened in the path of the conductive paste or conductive ink, for example, from New Jersey (New Jersey) in Rocky Mount (Rocky Hill) faction Lick ( Parelec) under the tradename Pa Mode VLT (Parmod VLT) of conductive ink material; and may be by screen printing, laser or ink-jet printing and filling grinding process is applied to this material. 可施加热或其它能量来完成导电路径并将引线物理接合到所述导电材料。 Heat or other energy may be applied to complete a conductive path and physically bonded to the electrically conductive wire material.

[0060] 图7b描绘用作绝缘体层300的各向异性导电材料。 [0060] FIG 7b depicts an anisotropic conductive material is used as the insulator layer 300. 此材料最初在平面水平及垂直方向上绝缘。 The insulating material is initially in a plane horizontal and vertical directions. 所述材料包含导电丝,其在经受压力及/或热或其它能量时在选择性区域中在垂直方向上变为导电。 The material comprises a conductive filament which is in selective regions in the vertical direction becomes conductive when subjected to pressure and / or heat or other energy. 因此,在图7b中,导电路径707在位于两个引线框架引线之间的位置处形成,一个引线来自上引线框架且ー个引线来自下引线框架,此引线路径用于代替图5及6的通孔通路301而在任意选定位置处连接所述弓I线框架引线。 Thus, in Figure 7b, the conductive path 707 at a position between the two leads of the lead frame is formed, a lead from the lead frame and ー of leads from the lower lead frame, this path is used in place of the lead 5 and 6 of FIG. through orifice passage 301 is connected at any selected position of the bow line I frame lead. 明尼苏达州(Minnesota)的圣保罗(St. Paul)的3M公司提供作为各向异性导体的压敏粘合剂转移胶带,3M胶带9703是可使用的实例性产品。 Minnesota (Minnesota) St. Paul (St. Paul) 3M Company provided as a pressure sensitive adhesive transfer tape anisotropic conductor, 3M tape 9703 is an example of the use of the product. 用于实施例的各向异性膜及导电膏(例如图7b(膜)或图7a(膏))也可从其它商业卖主(例如,德国杜塞尔多夫(Diisseldorf)的汉高(Henkel)技木)购得。 Anisotropic conductive paste for film embodiment (eg Figure 7b (film) or Figure 7a (paste)) is also available from other commercial vendors (for example, in Dusseldorf, Germany (Diisseldorf) Henkel (Henkel) Wood Technology) purchased. 这些材料可与其它膜一起使用或単独使来提供绝缘体层300。 These materials may be used in combination with other films or radiolabeling alone make the insulator layer 300 is provided.

[0061]图8描绘使用倒装芯片技术以将集成电路晶片耦合到引线框架的替代性优选实施例。 [0061] Figure 8 depicts the use of flip-chip technology to couple integrated circuit die to the lead frame an alternative preferred embodiment. 在图8中,使用上覆于绝缘体层300的任一侧上并保护其内的装置及引线框架的囊封剂803来形成封装801。 In Figure 8, the use of overlying on either side of the insulator layer 300 and protective encapsulant 803 and lead frame means therein to form the package 801. 通孔通路301在绝缘体层300中形成并耦合如上所说明的来自上及下引线框架的引线502。 Through orifice passage 301 is formed and coupled to the above described upper and lower lead 502 from the lead frame 300 in the insulator layer. 通过以下步骤将可以是存储器控制器装置的集成电路晶片303倒装芯片接合到上引线框架:首先执行熟知的晶片或晶圆凸点エ艺,其在集成电路的晶片垫上形成焊料块、球或柱,然后将焊料凸点的晶片与引线框架引线的内部端对准且将所述晶片固定为“朝下”以将晶片垫耦合到所述引线框架引线,使用热能来回流所述焊料并完成到所述引线框架的连接。 By the following steps may be a memory controller integrated circuit die flip-chip bonding apparatus 303 to the lead frame: first performs well-known wafer or wafer bumping Eito art, which solder bump pads are formed in an integrated circuit wafer, the ball or column, and then the inside of the solder bumps of the wafer and the lead end of the lead frame aligned and the wafer is fixed to the "down" to the wafer pad coupled to said lead frame leads, the use of thermal energy to the solder and complete the reflux connection to the lead frame. 同样,也将可以是(举例来说)非易失性存储器(例如,快闪存储器装置)的集成电路809倒装芯片安装到下引线框架,且形成焊接(例如,807)以在通孔通路301中将上与下引线框架耦合在一起。 Similarly, it will be (for example) a non-volatile memory (e.g., flash memory devices) flip-chip integrated circuit 809 is mounted to the lower lead frame, and forming a weld (e.g., 807) to the through-hole passage 301 will be coupled with the lower lead frame. 图8还描绘本发明在封装内的两个或更多个集成电路之间进行任意定位连接的能力,晶片不必相同或甚至几乎大小相同。 Figure 8 also depicts the ability to locate the connection between any two of the present invention in a package or more integrated circuits, wafers do not have the same or even almost the same size.

[0062]图9描绘使用线接合连接的替代性优选实施例的完成封装901,其将芯片下引线或“LUC”引线框架用于所述上及下引线框架。 [0062] Figure 9 depicts the use of wire bonding to connect alternative preferred embodiment 901 to complete the package, under which the chip leads or "LUC" lead frame for the upper and lower lead frame. 同样地在图9中,引线延伸穿过囊封剂边界并提供到封装的外部连接。 Similarly in Figure 9, the leads extending through the encapsulant boundary and provides an external connection to the package. 以截面图描绘如以前在绝缘体层300的任ー侧上提供有囊封剂903的封装901,再次说明,所述囊封剂保护集成电路晶片、引线框架及线接合免受损坏及湿气。 As previously depicts a cross-section provides a package encapsulant 903 901 300 on either side of the insulator layer ー, again, the encapsulant to protect ICs, lead frame and wire bonds from damage and moisture. 集成电路晶片303经提供而上覆于上引线框架的引线502上且可使用胶带或环氧晶片附着物609而有利地安装到所述引线框架。 Provided by the integrated circuit die 303 and overlying the upper wire 502 and the lead frame or tape may be used advantageously epoxy wafer 609 attachments mounted to the lead frame. 使用如以前的线接合将上及下集成电路的接合垫606线接合连接到引线框架引线502,接合线505延伸并耦合到所述引线框架引线。 As in previous wire bonding using the upper and lower integrated circuit wire bond pad 606 connected to the lead frame the bonding wire 502, the bonding wire 505 extends and is coupled to said lead frame leads. 显示焊接807在通孔通路301中将上与下引线框架引线耦合。 Display welded through holes 807 in the passage 301 in the upper and lower lead frame lead is coupled. 引线502延伸穿过囊封剂边界以形成外部端子并(举例来说)通过使用插槽装置来启用到封装901的外部连接。 Lead 502 extends through the encapsulant to form an external terminal boundary and (for example) by using a socket to enable external devices connected to the package 901. 在此实施例中,来自上引线框架的引线出现在封装的一个侧上且来自下引线框架的引线出现在封装的另ー侧上。 In this embodiment, the leads from the lead frame is present on a side of the package and the leads from the lead frame under the package appears on the other side ー.

[0063] 图10以俯视图描绘图9的封装901。 [0063] Figure 10 depicts a plan view of the package 901 of FIG. 将绝缘体层300显示为具有形成于其上的囊封剂903。 The insulator layer 300 is shown as having formed thereon encapsulant 903. 将引线502显示为上覆于绝缘体层300上。 The lead 502 is shown as overlying the insulator layer 300. 将焊接807显示为位于在某些引线502下面形成的通路中。 The weld 807 is displayed via the lead 502 to be located in some of the following form. 将集成电路晶片303定位在引线502上方,使得引线框架为LUC或芯片下引线布置,可通过胶带或环氧附着所述晶片以提供支撑。 The integrated circuit die 303 is positioned above the lead wires 502, such that the lead frame is arranged at LUC or chip leads, may be attached by adhesive tape or an epoxy wafer to provide the support. 通过线接合505将所述集成电路上的接合垫耦合到引线框架引线502。 505 will engage the pads on the integrated circuit 502 is coupled to the lead frame leads by wire bonding. 在此视图中不可见的是位于绝缘体层300下面并通过焊接807耦合到上引线框架的第二集成电路与引线框架组合件。 Not visible in this view is located beneath the insulator layer 300 and 807 is coupled by welding to the lead frame of the second integrated circuit and the lead frame assembly.

[0064] 图11显示另一优选实施例,其中在封装的一个侧上将引线502中的某些形成为向下且囊封剂903包围整个组合件,但允许选定引线502的底表面101上的区域暴露以进行外部电连接。 [0064] Figure 11 shows another preferred embodiment in which one side of the package will lead 502 is formed downwardly and some of encapsulant 903 surrounds the entire assembly, but allows the bottom surface of the lead 502 of the 101 selected on the exposed region to be electrically connected externally. 可如图I所示或以所属技术中的技术人员将明了的其它类似图案来定位这些外部连接区域。 Figure I shows may or ordinary skill in the art will understand other similar pattern to locate these external connection areas.

[0065] 可改变用于实践本发明的方法且将这些变更涵盖于本发明及随附权利要求书的范围内。 [0065] The method may be varied for the practice of the present invention and those changes encompassed within the scope of the present invention and the scope of the claims appended claims. 举例来说,可将引线框架与绝缘体层300装配在一起作为预形成的组合件并将集成电路晶片定位位邻近对应的引线框架,使用线接合或倒装芯片耦合来完成到所述晶片的连接,且然后可执行过模制或圆顶封装体囊封。 For example, the lead frame may be assembled together with the insulator layer 300 as an integrated circuit die assembly and positioned adjacent to the corresponding bit of the pre-formed lead frame using a wire bonding or flip-chip coupling to completion of said wafer is connected to and then perform the over-molded or dome encapsulated package. 另ー选择为,可以带形式提供引线框架,可定位集成电路晶片并执行线接合或倒装芯片处理以在使用或不使用粘合剂或胶带的情况下将所述集成电路耦合到所述引线框架;然后将引线框架组合件定位在绝缘体层300的相应相对表面上方,已通过提前将绝缘体层300图案化而提供通孔通路301,且然后通过焊接,使用如以上所说明的导电膏或焊料或各向异性导体连接来将所述引线框架耦合在一起。 Another ー selection, can take the form of a lead frame, an integrated circuit wafer can be positioned and perform wire bonding or flip-chip processing to the case of using or without using an adhesive tape or the integrated circuit is coupled to said lead a frame; then the lead frame assembly is positioned above the respective opposite surface of the insulator layer 300, has passed in advance of the insulator layer 300 is patterned to provide vias passage 301, and then by soldering, using a conductive paste or solder as described above or anisotropic conductor is connected to said lead frame coupled together. 最后,可对完成的组合件进行过模制或圆顶封装体囊封,从而完成所述封装。 Finally, the assembly can be accomplished through molding or glob-top encapsulation, thereby completing the package. 可在另ー替代性方法中提供不具有形成于其内的通孔通路301的如上说明的绝缘体层300,且可使用工具焊接并同时在绝缘体层300中形成通孔通路301。 In another ー can be provided in alternative methods do not have an insulator layer 300 is formed above the through-hole of the passage 301 described therein, and may be formed while a through hole 301 in the passage 300 in the insulator layer using the welding tool.

[0066] 虽然在本文中详细说明本发明的某些优选实施例及其优点,但应了解,可在不背离如随附权利要求书所界定的本发明的精神及范围的情况下对所说明的实施例做出各种改变、替换及变更。 [0066] Although the detailed description of certain preferred embodiments and advantages of the embodiment of the present invention, it is to be understood, may be made without departing from the spirit herein and scope as defined by the appended claims of the present invention described Examples that various changes, substitutions and alterations. 此外,本申请案的范围并非既定限定为本说明书中所说明的电路、结构、方法及步骤的特定实施例。 Moreover, the scope of the present application is not intended as limited to the circuit described in the present specification, the particular structure, methods and steps described. 因此,随附权利要求书既定在其范围内包含利用本发明的那些エ艺,机器,制造、事件的组成、构件、方法或步骤以及利用本发明的所属技术中的技术人员所明了的变动与解决方案。 Accordingly, the appended claims are intended to include the use of those Eito art, machine, manufacture, composition of events, means, methods, or steps, and the present invention is the use of ordinary skill in the art of the present invention are apparent and variations within its scope solution.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2002/0121690 Title not available
US428884120 Sep 19798 Sep 1981Bell Telephone Laboratories, IncorporatedDouble cavity semiconductor chip carrier
US44234684 May 198227 Dec 1983Motorola, Inc.Dual electronic component assembly
US631682510 May 199913 Nov 2001Hyundai Electronics Industries Co., Ltd.Chip stack package utilizing a connecting hole to improve electrical connection between leadframes
Non-Patent Citations
1JP昭57-63850A 1982.04.17
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