CN101330084A - 半导体元件 - Google Patents

半导体元件 Download PDF

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CN101330084A
CN101330084A CNA2007103071418A CN200710307141A CN101330084A CN 101330084 A CN101330084 A CN 101330084A CN A2007103071418 A CNA2007103071418 A CN A2007103071418A CN 200710307141 A CN200710307141 A CN 200710307141A CN 101330084 A CN101330084 A CN 101330084A
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semiconductor element
silicon
core
trap
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郑钧隆
锺昇镇
郑光茗
庄学理
梁孟松
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体元件，具有包含高介电常数栅介电层的核心元件，和包含二氧化硅或其他非高介电常数栅介电层的输入/输出元件。首先，在半导体基材上形成由隔离结构所分隔的核心阱和输入/输出阱。在输入/输出阱上形成包含二氧化硅或其他非高介电常数栅介电层的输入/输出元件。电阻形成在邻接核心阱的隔离结构上。在核心阱上形成包含有高介电常数栅介电层的核心元件，例如电晶体。在一些实施例中，同时形成有p型和n型输入/输出阱。输入/输出元件和其他元件较佳形成于核心元件之前，并且受到牺牲层保护直至核心元件形成。

Description

半导体元件
技术领域
本发明涉及一种半导体元件，特别是涉及一种具有输入/输出元件及核心元件且较可靠的半导体元件。
背景技术
一般而言，半导体元件是一种于半导体晶圆上所制备而得，且非常微小的电子构件。使用不同的制备技术可将这些元件制造并连接在一起而形成集成电路。特定数目的集成电路可建构在单一个晶片上，特定数目的集成电路可用来在电子运用的操作中，以执行一系列有用的功能。而上述的电子运用可以为，例如行动电话、个人电脑和个人游戏装置。由于上述大众化装置对尺寸的需求，使得这些形成在晶片上的构件也必须非常地微小。
其中包含许多种类的半导体构件，例如电晶体，是一种用来控制电子讯号的开关；二极管则执行相似但不同的功能；而电阻器以及电容器也被以半导体元件的形式形成。超过百万个此类构件形成在单一晶片上，并且连结在一起以形成集成电路。
这些半导体元件使用一连串工艺操作而形成于晶圆基材(也称作衬底)上。一般而言，使用离子植入来赋予基材半导体特性或在基材上形成结构。接着选择性地加入或移除隔离层及导电材料以创造出每一个个别元件的一部分。光刻胶材料形成于一个或多个下层材质层之上。然后将光刻胶选择性地暴露于光线之中，其中此光线穿过一个称为光掩模的屏幕。受曝光的部分会产生与未曝光部分不同的物理特性。根据光刻胶的特性，借由一种选择性溶剂可将光刻胶的曝光与未曝光两部分其中之一移除，而形成一组保护结构。
当此一保护结构被使用时，下方材质层未被保护的部分会被，例如蚀刻工艺，减损或完全移除。也可能进行离子植入处理。在任何情形下，当选择性的处理或移除工艺完成之后，移除遗留下来的光刻胶结构都会在不伤害下方材质层的前提下，采用一种用来移除光刻胶的溶液来进行移除。以下将以典型的电晶体作为本发明的背景。
请参照图1，图1绘示一种传统半导体元件10的结构剖面图。半导体元件10是一种包含有形成在基材20上的栅极结构12的电晶体。栅极结构12包括一个借由栅氧化硅13与基材20隔离的栅极14。栅极14由例如金属或结晶多晶硅所构成。栅氧化硅13只是一部分被氧化的硅基材20。金属接触15来提供多晶硅栅极一个与外部导体的终端进行接触的可靠区域。间隙壁位于栅极14的其中一个侧壁，在此一案例中间隙壁16和间隙壁17具有此一功能。一般而言源极区21和漏极区23借由离子植入形成在基材20之中，借以在栅极结构12下方的源极区21和漏极区23之间定义出一条通道22。操作上，当施予栅极14一特定电压，可使电流通过通道22。
有时，半导体元件例如图1所绘示的电晶体可能被用于不同但具有互补性质的功能。在一个案例中所使用的两个电晶体，其中一个作为核心元件；另一个则做为输入/输出元件。图2绘示此种半导体元件30的结构剖面图。图中，半导体元件30之中的核心阱18和输入/输出阱19彼此相邻的形成，并且借由一浅勾隔离结构26彼此分隔(亦可参见图1)。核心阱18和输入/输出阱19借由不同的离子掺杂分别地形成于基材20之中，以提供两者预设的电子特性。其中图1所绘示的电晶体形成在半导体元件30的核心阱18上。
第二电晶体，一种输入/输出元件40则形成在输入/输出阱19上。输入/输出元件40具有包含一栅极34的栅极结构45，其中栅极34借由栅介电层33与输入/输出阱19隔离。接触35直接设于栅极34上。间隙壁36和37则设在栅极结构45的其中一侧源极区41和漏极区43则是在栅极结构45下方积材20的输入/输出阱19部分定出通道42。
很明显的，半导体元件10和输入/输出元件40的构成组件相似。但其中仍不同点，此不同点影响了这两种元件在同一晶圆上的制作。在一些应用上，当核心元件具有比输入/输出元件还要薄的栅氧化系层时，会使其因而展现了较佳的性能。而另一方面，由于输入/输出元件则必须处理较高的电压，因此不能同时以适合核心元件的最佳标准来进行制造输入/输出元件。
因此有需要提供一种可靠的半导体元件制造方法，以有效率的方式，同时因应制造上述两种不同元件所需的功能标准。而本发明的实施例正可提供上述问题的解决方案。
由此可见，上述现有的半导体元件在结构与使用上，显然仍存在有不便与缺陷，而亟待加以进一步改进。为了解决上述存在的问题，相关厂商莫不费尽心思来谋求解决之道，但长久以来一直未见适用的设计被发展完成，而一般产品又没有适切的结构能够解决上述问题，此显然是相关业者急欲解决的问题。因此如何能创设一种新型结构的半导体元件，实属当前重要研发课题之一，亦成为当前业界极需改进的目标。
有鉴于上述现有的半导体元件存在的缺陷，本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识，并配合学理的运用，积极加以研究创新，以期创设一种新型结构的半导体元件，能够改进一般现有的半导体元件，使其更具有实用性。经过不断的研究、设计，并经过反复试作样品及改进后，终于创设出确具实用价值的本发明。
发明内容
本发明的主要目的在于，克服现有的半导体元件存在的缺陷，而提供一种新型结构的半导体元件，所要解决的技术问题是使其同时具有核心构件和输入/输出构件，从而更加适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种半导体元件，其包括：一核心元件，包括一高介电常数栅介电层形成于一应变硅通道区之上；以及一输入/输出元件，其中该输入/输出元件包括一非高介电常数栅介电层。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的半导体元件，其中所述的高介电常数栅介电层具有大于8的一介电常数。
前述的半导体元件，更包括一电晶体。
前述的半导体元件，其中所述的应变硅通道区包括一硅层形成在一硅-锗层之上。
本发明的目的及解决其技术问题还可采用以下技术方案来实现。依据本发明提出的一种半导体元件，其包括：一第一构件，包括一高介电常数栅介电层形成于一应变硅通道区之上，其中该应变硅通道区包括硅-锗；以及一第二构件，其中该输入/输出元件包括一非高介电常数介电层。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的半导体元件，其中所述的第一构件是一电晶体，具有一漏极区和一源极区，其中该漏极区和该源极区的每一者都具有一上方边界延伸高过该高介电常数栅介电层。
前述的半导体元件，其中所述的第二构件包括一栅极结构，该栅极结构包含二氧化硅栅介电层。
前述的半导体元件，更包一金属栅极沉积于该高介电常数栅介电层上。
本发明与现有技术相比具有明显的优点和有益效果。由以上可知，为了达到上述目的，本发明一实施例提供了一种半导体元件，使此一半导体元件可同时具有核心元件以及输入/输出元件所提供的两种不同但性质互补的功能。此一种半导体元件包括一核心元件以及一输入/输出元件。其中核心元件具有设于应变硅(Strained-Silicon)通道区上的高介电常数的栅介电层。其中，输入/输出元件包含有非高介电常数的栅介电层。高介电常数的栅介电层较佳具有大于8的介电常数。虽然上述电子构件，例如金氧半导体场效应电晶体，可能具有金属、多晶硅或金属硅化物栅极其中之一，但本发明的半导体元件还包括电阻。应变硅通道区较佳是借由在邻接于核心元件的凹室中的硅-锗上方，原位磊晶成长硅所形成。
根据本发明的另一实施例，提供一种半导体元件，可使此一半导体元件可同时具有两种不同但具有互补性质的功能。此一半导体元件包括第一构件，此第一构件具有高介电系数栅介电层并且设在包含有硅者的应变硅通道区上方。半导体元件还包括包含有非高介电系数栅介电层的第二构件。半导体元件的第一构件可以是例如，具有源极区和漏极区的电晶体，其中源极区和漏极区皆各自具有一个延伸高过高介电系数栅介电层的阻障层。第一构件也同时包括设于高介电系数栅介电层上的栅极。半导体元件的第二构件包括，例如一个二氧化硅栅介电层。
本发明的又一实施例，提供一种半导体元件的制造方法，可以在无须额外工艺的前提下，即同时制备一个具有结构不同但性质互补的核心元件和输入/输出元件。此方法包括在基材中形成至少一隔离结构。形成一个借由此一隔离结构隔离的核心阱和输入/输出阱。在输入/输出阱上形成氧化硅层。在输入/输出阱的氧化硅层形成多晶硅层。由多晶硅层和氧化硅层中形成输入/输出元件栅极结构。在输入/输出阱中轻掺杂漏极(Lightly-Doped Drain；LDD)。形成虚拟间隙壁以保护输入/输出元件。定义核心元件通道，并借由离子植入来调整核心元件通道的临界电压(Threshold Voltage；Vt)。进行一个快速热退火工艺。形成一个核心元件的高介电系数栅介电层。形成一个核心元件的栅极。形成核心元件的源极区和核心元件的漏极区。移除虚拟间隙壁。形成核心元件和输入/输出元件的间隙壁。借由离子植入来形成源极区和漏极区。
根据本发明的再一实施例，提供一种半导体元件的制造方法，可以在无须额外工艺的前提下，即同时制备一个具有结构不同但性质互补的核心元件和输入/输出元件。此一制造方法包括在基材中形成一个核心阱和输入/输出阱，且核心阱和输入/输出阱硅借由隔离结构彼此隔离。在一些情形下，对核心阱进行离子植入以调整其临界电压。此一方法同时包括在输入/输出阱上形成一输入/输出元件的栅极结构。输入/输出元件的栅极结构包括设于一介电层上的一电极。此介电层为输入/输出元件的介电层，例如由二氧化硅所组成，且具有数大约小于5的介电常。此一方法也包括在核心阱中形成应变硅通道，并在核心阱上形成核心元件的栅极结构。核心元件的栅极结构包括设于一介电层上的一电极。此核心元件的介电层具有数大约大于8的介电常。在一实施例之中，形成应变硅通道的步骤包括：在核心阱中形成通道凹室。借由磊晶成长在通道凹室中形成硅-锗层。借由磊晶成长在硅-锗层上形成硅层。
此一方法还包括进行一轻掺杂漏极工艺将离子植入输入/输出阱中，并在轻掺杂漏极离子植入之后，对此半导体元件进行热退火。例如，此一半导体元件包括n型输入/输出阱和p型输入/输出阱，此轻掺杂漏极离子植入包括p型轻掺杂漏极离子植入和n型轻掺杂漏极离子植入。在定义输入/输出多晶硅栅极和多晶硅电阻之后，形成一个虚拟间隙壁以隔离输入/输出元件与由高介电常数元件工艺所形成的核心元件。移除虚拟间隙壁。此一方法也包括形成一个设在隔离结构上的电阻，此隔离结构邻接于核心元件。在形成核心元件的应变硅通道之前，先在输入/输出元件的栅极结构和电阻上形成氮化硅层。此一方法更包括形成核心元件的变动硅源极区和变动硅漏极区。例如，在邻接核心阱栅极结构的核心阱中形成源极区和漏极区凹室。借由磊晶成长在源极区凹室和漏极区凹室中形成硅-锗层。借由磊晶成长在硅-锗层上形成硅-碳层。
本发明的又另一实施例，提供一种在基材上制备半导体元件的方法，可以在无须额外工艺的前提下，即同时制备一个具有结构不同但性质互补的核心元件和输入/输出元件。此一方法包括提供一半导体基材。在基材之中形成至少一个隔离结构，形成一个由隔离结构所分隔的核心阱和输入/输出阱。在输入/输出阱上形成氧化硅层。在输入/输出阱的氧化硅层上形成多晶硅层。从多晶硅层和氧化硅层形成输入/输出栅极结构。在输入/输出阱中形成轻掺杂漏极。形成虚拟间隙壁以保护输入/输出元件。定义一核心元件通道。借由离子植入来调整核心元件通道的临界电压。进行快速热退火。形成核心元件的高介电常数栅介电层。形成核心元件的栅极。形成核心元件的源极区和核心元件的漏极区。移除虚拟间隙壁，并形成核心元件和输入/输出元件的间隙壁。借由离子植入来形成源极区和漏极区。
借由上述技术方案，本发明半导体元件至少具有下列优点：
根据上述实施例，本发明的技术特征与优势，是在无须调整用来制造核心元件的高介电常数工艺的前提下，即制备一个具有预设电子特性的输入/输出元件。其中当核心元件使用高介电常数介电层和多晶硅栅极或金属栅极形成时，其所形成的输入/输出元件并不具有高介电常数介电层。在本发明的较佳实施例之中，并不需要额外的光掩模对输入/输出元件进行整合，也可避免输入/输出元件进行穿过氧化硅层的离子植入。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
附图说明
图1是一种传统电晶体的结构剖面图。
图2是一种传统半导体元件的结构剖面图。
图3是根据本发明的实施例所绘示的一种半导体元件结构剖面图。
图4是根据本发明的实施例所绘示用来制造半导体元件的方法流程图。
图5a至图5g是根据制造半导体元件的选定步骤，所绘示的一系列工艺结构剖面图。
10：半导体元件       12：栅极结构
13：栅氧化硅         14：栅极
15：金属接触         16：间隙壁
17：间隙壁           18：核心阱
19：输入/输出阱      20：基材
21：源极区           22：通道
23：漏极区           30：半导体元件
33：栅介电层         34：栅极
35：接触             36：间隙壁
37：间隙壁           40：输入/输出元件
41：源极区           42：通道
43：漏极区           45：栅极结构
100：半导体元件      101：基材
102：核心阱          103：输入/输出阱
104：隔离结构        105：隔离结构
106：隔离结构        110：输入/输出元件
112：栅极结构        113：栅氧化硅
114：栅极            115：间隙壁
116：间隙壁          117：源极区
118：通道            119：漏极区
120：核心元件        122：栅极结构
123：栅介电层        124：栅极
125：间隙壁          126：间隙壁
127：源极区          128：通道
129：漏极区          130：电阻
200：方法            205：提供基材。
207：在基材之中形成浅沟隔离结构。
209：进行核心阱离子植入工艺。
211：进行输入/输出阱离子植入工艺
213：进行快速热退火。
215：移除牺牲氧化硅层。
217：在输入/输出阱上形成氧化硅层。
219：形成多晶硅层。
221：在多晶硅层上形成硬式罩幕层。
223：图案化硬式罩幕层。
225：形成输入/输出元件的多晶硅栅极结构。
227：进行轻掺杂漏极离子植入工艺。
229：进行热退火步骤。
231：进行一个p型轻掺杂漏极离子植入工艺。
233：在整个元件之上沉积氧化硅层。
235：沉积氮化硅层。
237：蚀刻氮化硅层。
239：于核心阱中形成凹室。
241：在凹室中进行原位磊晶成长，以形成通道区。
243：形成低温氧化硅层。
245：进行选择性离子植入以调整核心元件的临界电压。
247：进行尖峰快速热退火工艺。
249：移除低温氧化硅层。
251：形成核心元件的高介电常数栅介电层。
253：形成栅极材质层。
255：形成并图案化硬质罩幕层。
257：进行蚀刻工艺以定义出核心元件的栅极结构。
259：形成氮化硅膜薄层。
260：形成保护核心元件栅极的间隙壁。
261：形成薄层氧化硅层。
263：于核心元件之上形成氮化硅层。
265：进行蚀刻以形成虚拟或牺牲间隙壁。
267：形成核心元件的源极和漏极区。
269：移除虚拟间隙壁。
271：沉积永久间隙壁材质。
273：蚀刻永久间隙壁材质。
275：对输入/输出元件和核心元件的源极和漏极区进行离子植入。
300：半导体元件            301：基材
302：核心阱                303：输入/输出阱
304：隔离结构              305：隔离结构
331：电阻堆叠              332：栅极堆叠
333：氧化硅                333a：氧化硅层
333’：氧化硅材质部        334：多晶硅层
334’：多晶硅部分          335：硬质罩幕层
335’：硬质罩幕部分        336：氧化硅层
336’：氧化硅材质部        337：氮化硅层
337’：氮化硅材质部        347：源极区
348：应变硅通道            349：漏极区
350：氧化硅层              353：氧化硅层
355：氮化硅层              360：栅极结构
363：栅介电层              364：栅极
372：间隙壁                373：间隙壁
374：间隙壁                375：间隙壁
376：间隙壁                377：间隙壁
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明提出的半导体元件其具体实施方式、结构、特征及其功效，详细说明如后。
以下将以在定条件下的较佳实施例来描述本发明。也就是说，以下采用一种具有电阻，并且具有分别都以金氧半导体电晶体作为核心元件和输入/输出元件的半导体元件来说明本发明的技术特征。但本发明的技术概念仍适用其他半导体元件。
请参照图3，图3是根据本发明的实施例所绘示的半导体元件100的结构剖面图。半导体元件100包括具有被隔离结构105分隔的核心阱102和输入/输出阱103的基材101。而每一个阱的边界，又分别被隔离结构104和106所界定，使其与邻接的元件部份(未图示)隔离。输入/输出元件110形成在输入/输出阱103上，并且包括有一个栅极结构112。此一栅极结构112包含一个栅极114，例如借由栅氧化硅113使其与基材101分离的多晶栅极。栅氧化硅113较佳是氧化基材101的表面所形成的二氧化硅层，介电常数大约为4。间隙壁115和116位于栅极结构112的一侧。源极区117和漏极区119分别形成于栅极结构112的一侧的基材101之中，以定义出通道118。
在一些实施例之中，核心元件120形成在核心阱102上。核心元件120包括有一个栅极结构122。源极区127和漏极区129分别形成于栅极结构122的一侧的基材101之中。在一个较佳实施例中，源极区127和漏极区129都具有一个隆起的外型，如图3所绘示。也就是说源极区127和漏极区129的上方边界，在某个程度上都高过栅极结构112的下方边界。另外在一个较佳实施例之中，源极区127和漏极区129包含一个硅-锗材质部和一个硅-碳材质部(并未在图3中分别地绘示出来)，其借由磊晶成长来填满基材101中的凹室而形成。位于源极区127和漏极区129之间的通道128包括设在硅-锗层上的(应变)硅层。
栅极结构122包括栅极124，其中栅极124借由栅介电层123使其与基材101的核心阱102分离。在本实施例之中，栅介电层123由高介电常数材质所形成，其介电常数大于8，较佳实质介于8到40之间。栅极124则可由多晶硅、金属或两者的组合所形成。间隙壁125和126则分别位于栅极结构122的一侧。在图3中，半导体元件100还包括电阻130，形成在邻接核心阱102的隔离结构104上。
以下将说明制备上述半导体元件的工艺步骤，请参照图4，图4根据本发明的实施例所绘示用来制造半导体元件的方法200的流程图。首先，假设进行此一方法所需的机器极材料皆已完备。请参照步骤205：方法200由提供基材开始。此一基材可以由硅或其他合适的材质所组成。在本发明的较佳实施例之中，基材是一个硅晶圆。由于本发明的半导体元件包含了不只一个构件，因此接着请参照步骤207：在基材之中形成一个或多个浅沟隔离结构。
步骤207中所形成的浅沟隔离结构可有效地将基材区隔成多个个别区域或阱。同时牺牲氧化硅层也伴随浅沟隔离层产生。接着请参照步骤209：进行离子植入工艺，使掺质进入核心元件下方的阱中，并进行另一个离子植入工艺借以在输入/输出元件下方形成一个阱(请参照步骤211)。在进行快速热退火(请参照步骤213)，例如以温度约980℃至1100℃持续约0秒至30秒。然后请参照步骤215：移除伴随浅沟隔离层所形成(或在不同工艺中形成)的牺牲氧化硅层。
之后在输入/输出阱上形成氧化硅层(请参照步骤217)，较佳是借由成长工艺来形成。此氧化硅层用来形成输入/输出元件的栅氧化硅层。此氧化硅层也可以同时形成在核心阱上，但是形成在此的氧化硅层最终还是会被移除。接着请参照步骤219：形成多晶硅层，并且在多晶硅层上形成硬式罩幕层(请参照步骤221)。其中硬式罩幕层可以是单层结构，但较佳包括一个位于氮化硅层下方的氧化硅层。请再参照步骤223：例如使用微影工艺，图案化硬式罩幕层，其中设于输入/输出阱上的一部分多晶硅层受到图案化罩幕层的保护。接着请参照步骤225：使用，例如蚀刻工艺形成输入/输出元件的多晶硅栅极结构。
接着，针对轻掺杂漏极部分或一部分的输入/输出元件进行离子植入工艺。在一个实施例之中，例如采用大约5KeV至80KeV的能量，进行一个n型轻掺杂漏极离子植入工艺(请再参照步骤227)，借以在n型金氧半导体电晶体上创造出狭窄的源极和漏极延伸。然后进行一热退火步骤(请参照步骤229)。热退火可以为，例如以温度约600℃至900℃持续约20分钟至120分钟。然后请再参照步骤231：采用大约5KeV至80KeV的能量，进行一个p型轻掺杂漏极离子植入工艺，借以在p型金氧半导体电晶体上创造出狭窄的源极和漏极延伸。值得注意的是，虽然在图示中并未个别地绘示保护层或保护区的形成或移除，不过在上述步骤之中，半导体元件未被掺杂的部分，在工艺中自然地会受到应有的保护。
之后，请参照步骤233：在整个元件之上沉积氧化硅层，然后沉积氮化硅层(步骤235)。然后蚀刻氮化硅层(步骤237)，以使位于输入/输出构件的一侧或上方的虚拟(牺牲)间隙壁分离。
在本实施例中，请参照步骤239：于核心阱中形成凹室，并进行氢氟酸溶液清洗(HF-Dip)工艺。要再次说明的是，对于任何为了保护参与上述工艺的元件区域所进行的必要步骤皆已完备，因此未在此赘述或加以绘示。接着请参照步骤241：在凹室中进行原位(In-Situ)磊晶成长，以形成一个通道区。其中此通道区具有一个覆盖有硅材质部的硅-锗材质部，两者构成核心元件的应变硅通道。之后形成低温氧化硅层(请参照步骤243)，并且进行选择性离子植入(请参照步骤245)以调整核心元件的临界电压。再进行一个，例如温度范围大约在980℃至102℃之间的尖峰快速热退火工艺(请参照步骤247)。然后移除低温氧化硅层(请参照步骤249)。
在本实施例之中，接着形成核心元件的高介电常数栅介电层(请参照步骤251)然后形成一层栅极材质层(请参照步骤253)。然后形成并图案化一个硬质罩幕层(请参照步骤255)，再进行一个蚀刻工艺，以定义出核心元件的栅极结构(请参照步骤257)。之后形成一个薄层(请参照步骤259)，其中此一薄层是一种氮化硅膜或一种氮化硅与氧化硅所构成的薄膜。进行一个全面性的蚀刻(Blanket Etching)工艺，以形成保护核心元件栅极的间隙壁(请参照步骤260)。然后请参照本实施例图4步骤261：形成一薄层氧化硅层。在于核心元件之上形成氮化硅层(请参照步骤263)，再进行蚀刻以形成虚拟或牺牲间隙壁(请参照步骤265)。例如借由蚀刻位于核心元件栅极结构的一侧的凹室，并且在凹室沉积一层硅-锗层之后再沉积一层硅层(此一步骤并未分开绘示)，来形成核心元件的源及和漏极区(请参照步骤267)。
当形成源极和漏极区之后，将虚拟间隙壁自核心元件以及输入/输出元件上移除(请参照步骤269)。接着，沉积永久间隙壁材质(请参照步骤271)，并加以蚀刻(请参照步骤273)以形成永久间隙壁。值得注意的是永久间隙壁可以包括不只一层材质，虽然此处并未分开绘示，但永久间隙壁可以是一种多层材质结构。最后(请参照步骤275)，对输入/输出元件和核心元件的源极和漏极区进行离子植入，其中当然还有包括其他个别的步骤(并未个别地加以绘示)。上述工艺将会继续以进行其他元件制备步骤，最后进行封装以形成最后的半导体元件。
值得注意的是，上述的方法200只是本发明的实施例之一，还可能包括其他的变化。在其他实施例之中，以上所述的步骤有可能会被忽略或额外地增加。另外上述的工艺顺序也可以加以变更，且除非有特别的次序要求或很显然的条件限制，否则其所叙述步骤应可以在任何逻辑性前后一至的情形下进行操作。
本发明的另一种实施例绘示于图5a至图5g，图5a至图5g根据制造半导体元件300的选定步骤，所绘示的的一系列工艺结构剖面图。在本实施例之中，首先提供一晶圆基材301，较佳可为硅或其他合适材质。图中可以明显地看出，半导体元件仅占基材301的极小部分。在典型的运用中，可在同一时间进行多个元件的制作。其中基材301中形成有一定数目的隔离结构，请参照图5a中所绘示的隔离结构304和305。
使用选择性离子植入，在本实施例中建构出被隔离结构所隔离的核心阱302和输入/输出阱303。而值得注意的是，上述的特征与图3所绘示的内容相似或相同。因此将这些相似或相同的特征以相同的图号标示于图5a至图5g之中是可行的。但这并不表示类似的图号之间没有差异。如同图3所示，图5a至图5g中的特征也不需要依照比例绘示。在此同时进行一个快速热退火工艺，并且移除任何在离子植入工艺中的牺牲氧化硅层。
在本实施例之中，形成栅极堆叠层。其中氧化硅层333成长于输入/输出阱303上。虽然后续将会被移除，但在图5b中也可看到一层氧化硅层(编号333a)形成在核心阱302上方。接着在氧化硅层333上形成多晶硅层334，并在多晶硅层334上形成硬质罩幕层335。在本实施例之中，硬质罩幕层335包括氧化硅层336和氮化硅层337。在其他实施例之中(未图示)，硬质罩幕层包括一个或多个双层结构。然后图案化硬质罩幕层335，用来在输入/输出阱303上形成包括氧化硅材质部333’、多晶硅部分334’和(由氧化硅材质部336’和氮化硅材质部337’组成的)硬质罩幕部分335’的栅极堆叠332。在本实施例之中，同时也在隔离结构上沉积电阻堆叠331，用来形成电阻。此处的电阻堆叠331包括多晶硅部分334”和由氧化硅材质部336”和氮化硅材质部337”组成的的硬质罩幕部分335”。当于输入/输出阱303上形成栅极堆叠332的同时，先前形成在核心阱302上的氧化硅层333a会被移除。其中输入/输出元件的栅极堆叠332和电阻堆叠331绘示于第5c图。
在本实施例之中，接着对输入/输出元件进行轻掺杂漏极工艺。明显的，当对输入/输出元件进行轻掺杂漏极植入时，核心阱以及元件中其他非输入/输出的部分都会受到，例如光刻胶，的保护。值得注意的是，虽然图中仅绘示一个核心元件和一个输入/输出元件。然而这些元件可以是形成于晶圆上的n型金氧半导体电晶体元件及p型金氧半导体电晶体元件。在这种实施例之中，会依序进行n型的轻掺杂漏极工艺和p型的轻掺杂漏极工艺。然后再进行热退火工艺，例如在温度范围大约980℃至102℃之间环境之下持续2-120分钟。
在图5a至图5g的实施例之中，接着形成氮化硅层355并加以蚀刻，借以在既存的结构上形成牺牲间隙壁，例如氮化硅间隙壁。如图5d所绘示，在形成氮化硅层355之前，会先形成氧化硅层350。借由上述结构恰当的保护，而定义出核心元件通道。再于核心阱302之中蚀刻出一个凹室，保护其他非蚀刻的相关区域，并使用氢氟酸浸泡以移除其余的材质。借由磊晶成长，在凹室中形成核心元件通道区，先成长硅-锗，再成长硅以形成应变硅通道348。如图5e所绘示，接着在新形成的通道348上沉积氧化硅层353。接着对核心区302进行一个用来调整临界电压的离子植入工艺，后进行尖峰快速热退火。
在本实施例之中，接着移除氧化硅层350和353，并制备核心元件的栅极结构360。制备一个高介电常数栅介电层363，借以将栅极364与通道348隔离。其中栅介电层可以是由包括氧化铪、氮氧化铪或氮氧化硅，介电常数大约介于8-40之间的材质所组成。栅极364可以是由多晶硅或金属所形成。如第5f图形成源极区347和漏极区349。在图5a至图5g的实施例之中，源极区347和漏极区349的形成借由形成凹室，然后磊晶成长硅-锗，再成长硅-碳。源极区347和漏极区349都具有较高的外观，也就是说至少有一部分沿着其上方边界的点，高于栅极结构360的下方边界。最后移除剩余的虚拟间隙壁和氧化层，并且形成永久间隙壁372、373、374、375、376和377，而形成如图5g所示的结构。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (8)

1.一种半导体元件，其特征在于包括：
一核心元件，包括一高介电常数栅介电层形成于一应变硅通道区之上；以及
一输入/输出元件，其中该输入/输出元件包括一非高介电常数栅介电层。
2.根据权利要求1所述的半导体元件，其特征在于其中所述的高介电常数栅介电层具有大于8的一介电常数。
3.根据权利要求1所述的半导体元件，更包括一电晶体。
4.根据权利要求1所述的半导体元件，其特征在于其中所述的应变硅通道区包括一硅层形成在一硅-锗层之上。
5.一种半导体元件，其特征在于包括：
一第一构件，包括一高介电常数栅介电层形成于一应变硅通道区之上，其中该应变硅通道区包括硅-锗；以及
一第二构件，其中该输入/输出元件包括一非高介电常数介电层。
6.根据权利要求5所述的半导体元件，其特征在于其中所述的第一构件是一电晶体，具有一漏极区和一源极区，其中该漏极区和该源极区的每一者都具有一上方边界延伸高过该高介电常数栅介电层。
7.根据权利要求5所述的半导体元件，其特征在于其中所述的第二构件包括一栅极结构，该栅极结构包含二氧化硅栅介电层。
8.根据权利要求5所述的半导体元件，更包一金属栅极沉积于该高介电常数栅介电层上。
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