CN101295710B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN101295710B CN101295710B CN2008101097899A CN200810109789A CN101295710B CN 101295710 B CN101295710 B CN 101295710B CN 2008101097899 A CN2008101097899 A CN 2008101097899A CN 200810109789 A CN200810109789 A CN 200810109789A CN 101295710 B CN101295710 B CN 101295710B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor device, which is characterized by including a substrate with an electrode section; a first semiconductor component, which has a first electrode solder pad connected on the electrode section by a first bonding lead, and is adhered onto the substrate; and a second semiconductor component, which has a second electrode solder pad connected on the electrode section by a second bonding lead, and is adhered onto the first semiconductor component by an adhesive agent layer which has a two-layer structured formed by the same material and having different elastic rates.
Description
Technical field
The present invention relates to the semiconductor device that lamination carries a plurality of semiconductor elements.
Background technology
In recent years, be the miniaturization that realizes semiconductor device or High Density Packagingization etc., the lamination-type multi-chip encapsulation body of a plurality of semiconductor elements of stacked package (semiconductor chip) in 1 packaging body, beginning practicability.In such lamination-type multi-chip encapsulation body, a plurality of semiconductor elements, by bonding agents such as small plate adhering materials, be stacked in successively on the installation base plates such as circuit substrate, and be electrically connected the electrode part of the electrode pad of each semiconductor element and circuit substrate etc. by bonding wire.In addition, by with the such laminated structure of sealing resin encapsulation, constitute the lamination-type multi-chip encapsulation body.
, in above-mentioned lamination-type multi-chip encapsulation body, the semiconductor element of epimere side than the little situation of the semiconductor element of hypomere side under, the semiconductor element of epimere side is not interfered the bonding wire of the semiconductor element of hypomere side.But, in such formation, owing to limit spendable semiconductor element significantly, therefore advance range of application is expanded to the semiconductor element of shape to each other or the epimere side semiconductor element bigger than hypomere side.At this moment, when stacked to each other with the semiconductor element of shape or under the situation of epimere side superimposed layer semiconductor element of big shape than hypomere side, the bonding wire of the semiconductor element of hypomere side contacts with the semiconductor element of epimere side, its result, preventing defective insulation or short circuit etc. becomes subject matter.
In addition, advance range of application with the lamination-type multi-chip encapsulation body to expand to each other with the semiconductor element of shape, and the epimere side semiconductor element (for example, with reference to patent documentation 1,2) bigger than hypomere side.
Therefore, between semiconductor element up and down, configuration is so that the height of the lower surface of the semiconductor element of epimere side is set the liner (for example, with reference to patent documentation 3,4) of thickness greater than the mode of the height of the bonding wire on the semiconductor element that is connected the hypomere side.But, use thick like this liner, hinder the slimming of packaging body (semiconductor device).In addition, also studied the bond layer between semiconductor element itself has been paid padding function (for example, with reference to patent documentation 5), but in the slimming that also hinders packaging body in such cases.
In addition, when under the situation of epimere side superimposed layer big semiconductor element, because the semiconductor element of epimere side disposes highlightedly from the semiconductor element of hypomere side, so the below of this ledge forms hollow state than hypomere side.In addition, even in the identical shaped semiconductor element semiconductor device to each other of lamination, under the situation of the offset of the semiconductor element that makes the epimere side, the part of the semiconductor element of epimere side is outstanding from the semiconductor element of hypomere side, and the below of this ledge forms hollow state.Like this, if the part of the semiconductor element of epimere side is outstanding from the semiconductor element of hypomere side, ultrasonic wave output when then connecting bonding wire on the semiconductor element of epimere side is propagated to the hollow bulb of protuberance below, and the problem of the bad connection that produces bonding wire etc. is arranged.
For this point, proposition is passed through to form insulating barrier in the lower face side of the semiconductor element of epimere side, the generation (for example, with reference to patent documentation 6) of the defective insulation the when bonding wire that suppresses the semiconductor element of hypomere side contacts with the semiconductor element of epimere side or short circuit etc.Though utilize insulating barrier that effect is showed in the inhibition of defective insulation or short circuit etc., exist based on the difference of the coefficient of thermal expansion of insulating barrier and bond layer etc., be easy to generate the problem of splitting.In addition, because except that the bonding process of semiconductor element, need the formation operation of insulating barrier, when therefore having the worker of lamination-type multi-chip encapsulation body, the problem that increases of manufacturing cost.
In addition, the load when going between bonding because of semiconductor element in the epimere side, semiconductor element produces deflection.Such deflection becomes the reason that semiconductor element cracks etc., also becomes the reason of bonding wire bad connection simultaneously.In addition, because of the semiconductor element deflection of epimere side, exist the bonding wire that makes on the semiconductor element that is connected the hypomere side to produce the problem of distortion or bad connection etc.In addition, the configuration profile is than its little liner or adhesive linkage between semiconductor element up and down, even under the situation that the size of the semiconductor element that makes the epimere side is stretched out from the semiconductor element of hypomere side, also make the part of the semiconductor element of epimere side, its below forms hollow state.Same problem is also appearring in such cases.
In addition, when under the situation of carrying the big semiconductor element than hypomere side on the epimere side, because the semiconductor element of epimere side disposes highlightedly from the semiconductor element of hypomere side, therefore because of the load when the epimere side lead-in wire bonding, semiconductor element produces deflection.Such deflection becomes the reason that semiconductor element cracks etc., and exists the bonding wire that makes on the semiconductor element that is connected the hypomere side to produce the problem of distortion or bad connection etc.Such problem is not limited on the epimere side when carrying than the big semiconductor element of hypomere side, even identical shaped semiconductor element, under with situation about disposing in the mode that produces hollow bulb below the semiconductor element of epimere side, same problem also appears.
In addition, in patent documentation 1, put down in writing in the formation of epimere side lamination big semiconductor element than hypomere side, with the mounting semiconductor element of hypomere side after on the substrate, carry out resin-sealed, the stacked-type semiconductor device of on this resin-sealed, carrying the semiconductor element of epimere side.According to such formation, because there is resin-sealed portion in the bottom at the semiconductor element of epimere side, therefore can prevent the crackle of the bad or semiconductor element of bonding etc., on the contrary, because after carrying each semiconductor element, therefore need carry out resin-sealed operation, when having worker, the problem that increases of manufacturing cost.In addition, owing to need be used for the space of resin-sealed each semiconductor element, therefore hinder the slimming or the miniaturization of lamination-type multi-chip encapsulation body (semiconductor device).
Patent documentation 1: the spy opens the 2001-217384 communique
Patent documentation 2: the spy opens the 2002-270760 communique
Patent documentation 3: the spy opens the 2003-261233 communique
Patent documentation 4: the spy opens the 2003-218316 communique
Patent documentation 5: the spy opens the 2003-100953 communique
Patent documentation 6: the spy opens the 2002-222913 communique
As mentioned above, in the semiconductor device that adopts lamination-type multi-chip encapsulation body structure in the past, the generation of defective insulation that causes because of contacting of the semiconductor element of the bonding wire of the semiconductor element of hypomere side and epimere side or short circuit etc. becomes the main cause of the slimming that hinders packaging body.In addition, be located at the insulating barrier of lower face side of the semiconductor element of epimere side, though effect is showed in the inhibition to above-mentioned defective insulation or short circuit etc., cause resulting from the splitting of coefficient of thermal expansion difference etc. of insulating barrier and bond layer or increase of manufacturing cost etc.And then, below the semiconductor element of epimere side, produce in the laminated construction of hollow bulb, because of the deflection that produces when the lead-in wire bonding of epimere side semiconductor element, there is the problem of the distortion, bad connection etc. of the bonding wire of the crackle that produces semiconductor element or hypomere side semiconductor element.
In addition, in the semiconductor device of in the past lamination-type multi-chip encapsulation body structure, when at the epimere side lamination semiconductor element bigger than hypomere side, or under the situation of the semiconductor element of biasing ground lamination epimere side, the part of the semiconductor element of epimere side is outstanding from the semiconductor element of hypomere side, and unavoidably the below of this protuberance forms hollow state.If the below of protuberance forms hollow state, will cause bad connection occurring to the bonding wire that the semiconductor element of epimere side connects, or the semiconductor element of the epimere side problem that deflection cracks etc. during because of the lead-in wire bonding.
Summary of the invention
The present invention proposes for solving such problem, its purpose is to provide a kind of semiconductor device, it can also suppress that bad between semiconductor element peels off or the increase of manufacturing cost etc. except that the generation of the defective insulation that contacts of the semiconductor element of the bonding wire of the semiconductor element that can prevent to result from the hypomere side and epimere side or short circuit etc.In addition, purpose is to provide a kind of semiconductor device, produces in the laminated construction of hollow bulb below the semiconductor element of epimere side, the generation of the deflection in the time of can preventing on the semiconductor element of epimere side bonding.
In addition, purpose is to provide a kind of semiconductor device, it disposes on the epimere side in the laminated construction or the laminated construction with respect to the semiconductor element of the semiconductor element of hypomere side biasing ground configuration epimere side of the semiconductor element bigger than hypomere side, can suppress to result from the bonding wire bad connection of protuberance of semiconductor element of epimere side or the crackle generation of semiconductor element etc.
The semiconductor device of a mode of the present invention is characterized in that, possesses: the substrate with electrode part; The 1st semiconductor element has by the 1st bonding wire and is connected the 1st electrode pad on the described electrode part, and is bonded on the described substrate; And the 2nd semiconductor element, have by the 2nd bonding wire and be connected the 2nd electrode pad on the described electrode part, and use by same material and form and the bond layer of 2 layers of structure that spring rate is different carries out bonding on described the 1st semiconductor element.
The semiconductor device of another way of the present invention, it is characterized in that: further in the semiconductor device of bond layer with 2 layers of above-mentioned structure, described the 2nd semiconductor element has from the outstanding laterally part of the periphery of described the 1st semiconductor element, and between the ledge of described the 2nd semiconductor element and described substrate, the 1st layer on the bond layer of the softening or described 2 layers of structure of fusion of the temperature by with described the 2nd semiconductor element bonding the time is come filling.
The semiconductor device of another way of the present invention is characterized in that, possesses: the substrate with electrode part; The 1st semiconductor element has by the 1st bonding wire and is connected the 1st electrode pad on the described electrode part, and is bonded on the described substrate; And the 2nd semiconductor element, have by the 2nd bonding wire and be connected the 2nd electrode pad on the described electrode part, and by comprising that temperature when bonding can keep the bond layer of the insulating properties filler of solid-state state and bond on described the 1st semiconductor element, and have by the outstanding laterally part of the periphery of described the 1st semiconductor element; Between the ledge of described the 2nd semiconductor element and described substrate, the softening or described bond layer of fusion of the temperature by with described the 2nd semiconductor element bonding the time comes filling.
The semiconductor device of another way of the present invention is characterized in that, possesses: the substrate with electrode part; The 1st semiconductor element has by the 1st bonding wire and is connected the 1st electrode pad on the described electrode part, and is overlapped on the described substrate; And the 2nd semiconductor element, have by the 2nd bonding wire and be connected the 2nd electrode pad on the described electrode part, and be overlapped on described the 1st semiconductor element, have simultaneously by the outstanding laterally part of the periphery of described the 1st semiconductor element; The ledge of described the 2nd semiconductor element is by the insulating properties column support that is located on the described substrate.
Semiconductor device according to a mode of the present invention, because with respect to the 1st semiconductor element, bonding the 2nd semiconductor element of bond layer with 2 layers of different structure of same material and spring rate, therefore except that the distortion that can prevent the 1st bonding wire or bad connection, the 1st bonding wire and contacting of the 2nd semiconductor element etc., can also be good and the bonding at low cost the 1st and the 2nd semiconductor element between, can suppress that interelement behind the bonding process peels off simultaneously etc.In addition, semiconductor device according to alternate manner of the present invention, because at the filling bond layer below the outstanding part of the periphery of the 1st semiconductor element of the 2nd semiconductor element, so it is bad etc. to suppress to result from the crackle of the 2nd semiconductor element of hollow bulb of protuberance below or bonding.
In addition, semiconductor device according to alternate manner of the present invention, owing to utilize the insulating properties column that is located on the substrate, support the 2nd semiconductor element from the outstanding part of the periphery of the 1st semiconductor element, so can suppress to result from the bad connection of bonding wire of ledge of the 2nd semiconductor element or the crackle of semiconductor element etc.Thus, can provide stacked-type semiconductor device slim and that reliability is excellent.
Description of drawings
Fig. 1 is the profile of expression according to the concise and to the point formation of the semiconductor device of the 1st execution mode of the present invention.
Fig. 2 is the profile of formation of bond layer of 2 layers of bonding used structure of the 1st semiconductor element of expression semiconductor device shown in Figure 1 and the 2nd semiconductor element.
Fig. 3 is the profile of a routine manufacturing process of the bond layer of expression 2 layers of structure shown in Figure 2.
Fig. 4 represents diagram according to the main position of the manufacturing process of the semiconductor device of the 1st execution mode of the present invention with section.
Fig. 5 is the profile that is illustrated in according to using the configuration example of columnar projections on the semiconductor device of the 1st execution mode.
Fig. 6 is other routine profile that the semiconductor device of columnar projections is used in expression.
Fig. 7 is the vertical view of expression according to the concise and to the point formation of the semiconductor device of the 2nd execution mode of the present invention.
Fig. 8 is the profile of expression according to the concise and to the point formation of the semiconductor device of the 2nd execution mode of the present invention.
Fig. 9 represents diagram according to the main position of the manufacturing process of the semiconductor device of the 2nd execution mode of the present invention with section.
Figure 10 is the diagram of size (hollow amount) of protuberance that is used for illustrating the 2nd semiconductor element of semiconductor device shown in Figure 7.
Figure 11 is the diagram that an example of the thickness of the required bond layer of the filling of the size (hollow amount) of protuberance of expression the 2nd semiconductor element and hollow bulb concerns.
Figure 12 is the vertical view of expression according to the variation of the semiconductor device of the 2nd execution mode of the present invention.
Figure 13 is the profile of expression according to the variation of the semiconductor device of the 2nd execution mode of the present invention.
Figure 14 is the vertical view of expression according to the concise and to the point formation of the semiconductor device of the 3rd execution mode of the present invention.
Figure 15 is the profile of expression according to the concise and to the point formation of the semiconductor device of the 3rd execution mode of the present invention.
Figure 16 is the vertical view of expression according to the concise and to the point formation of the semiconductor device of the 4th execution mode of the present invention.
Figure 17 is the profile of semiconductor device shown in Figure 16.
Figure 18 is the profile of other configuration example that expression is used for the insulating properties column of semiconductor device shown in Figure 16.
Figure 19 is the profile of another other configuration example that expression is used for the insulating properties column of semiconductor device shown in Figure 16.
Figure 20 is the profile of other configuration example again that expression is used for the insulating properties column of semiconductor device shown in Figure 16.
Figure 21 represents diagram according to the main position of the manufacturing process of the semiconductor device of the 4th execution mode of the present invention with section.
Figure 22 is the vertical view of expression according to the concise and to the point formation of the semiconductor device of the 5th execution mode of the present invention.
Figure 23 is the profile of seeing from the frontal of semiconductor device shown in Figure 16.
Figure 24 is the profile of seeing from the side surface direction of semiconductor device shown in Figure 16.
Symbol description
1,30, the 40-semiconductor device, 2-circuit substrate, 4-electrode part, 5-the 1st semiconductor element, 6-the 1st bond layer, 7-the 1st bonding wire, 8-the 2nd semiconductor element, 9-the 2nd bond layer (bond layers of 2 layers of structure), the 1st layer of 10-, the 2nd layer of 11-, 23-columnar projections, 31-protuberance, 41-the 2nd bond layer, 42-insulating properties filler, 101, the 120-semiconductor device, the 102-circuit substrate, the 104-electrode part, 105,121-the 1st semiconductor element, 106,122-the 1st bond layer, 107,123-the 1st bonding wire, 108,124-the 2nd semiconductor element, 109,125-the 2nd bond layer, 110, the 130-protuberance, 111-insulating properties column, the 112-resin column, the 113-reinforcement material, 114, the 115-resin bed, 116-stops frame, 117,126-the 2nd bonding wire, 127-the 3rd semiconductor element, 128-the 3rd bond layer, 129-the 3rd bonding wire.
Embodiment
Below, implement mode of the present invention with reference to description of drawings.In addition, below, based on the description of drawings embodiments of the present invention, but these accompanying drawings provide for diagram, and the present invention is not limited to these accompanying drawings.
Fig. 1 is the profile of expression according to the concise and to the point formation of the semiconductor device of the 1st execution mode of the present invention.Semiconductor device shown in this figure (semiconductor package body) 1 as component mounting substrate, has circuit substrate 2.Circuit substrate 2, the substrate that can adopt resin substrate, ceramic substrate, glass substrate etc. to constitute by various materials.As resin substrate, use general multilayer copper plating film laminated plate (multilayer printed-wiring board) etc.In the lower face side of circuit substrate 2, form external connection terminals 3 such as slicken solder projection.In addition, in the upper surface side of the element installed surface that becomes circuit substrate 2, the electrode part 4 that for example is electrically connected with external connection terminals 3 by internal layer wiring (not shown) is set.This electrode part 4 becomes the lead-in wire bonding part.
The installed surface of above-mentioned circuit substrate 2 (above) on, by the 1st bond layer 6 bonding the 1st semiconductor elements 5.The 1st bond layer 6 adopts the general bonding material of small pieces (small pieces adhering film etc.).Be located at the 1st electrode pad of the upper surface side of the 1st semiconductor element 5, be electrically connected with the electrode part 4 of circuit substrate 2 via the 1st bonding wire 7.On the 1st semiconductor element 5, for example adopt the 2nd bond layer 9 bonding and its 2nd semiconductor elements 8 with shape.
The 2nd bond layer 9 that is used for bonding the 1st semiconductor element 5 and the 2nd semiconductor element 8 as shown in Figure 2, has by being configured in the 1st layer 10 of the 1st semiconductor element 5 sides and be configured in the 2nd layer of 11 2 layers of structure that form of the 2nd semiconductor element side.The above-mentioned the 1st layer 10 and the 2nd layers 11, except that with same material being same bonding agent forms with resin material, has different spring rates.The 1st layer 10 and the 2nd layers 11,, softening or melt temperature is different based on such spring rate.Specifically be the softening or fusion of the temperature during the 1st layer of 10 usefulness the 2nd semiconductor element 8 bonding, the 2nd layer of 11 temperature maintenance layer shape when bonding.
That is, on the 2nd bond layer 9 the 1st layer 10, the effect as bonding agent is played in the softening or fusion of temperature during with the 2nd semiconductor element 8 bonding.In addition, the 2nd layer 11, the temperature maintenance layer shape during with respect to the 2nd semiconductor element 8 bonding plays the effect as insulating barrier, prevents the defective insulation that contacts of following the 2nd semiconductor element 8 and the 1st bonding wire 7 or short circuit etc.The formation material of the 2nd bond layer 9 of 2 layers of structure like this adopts identical bonding agent resin material, for example the so thermosetting dielectric resin material of epoxy resin.The 2nd bond layer 9 of 2 layers of structure, for example can by make form the 1st layer 10 with the baking temperature of the 2nd layer of 11 o'clock thermosetting resin varnish or drying time different the acquisition.
The bond layer 9 of 2 layers of structure is for example by following making.At first, shown in Fig. 3 (a), epoxy resin varnish (A step) is coated in become on the film matrix of the support material 12 after, for example make this overlay drying at 150 ℃, form the 2nd layer 11 of semi-harden state (B step).Then, on the 2nd layer 11, apply identical epoxy resin varnish (A step) once more, for example make this overlay drying, form the 1st layer 10 of semi-harden state (B step) at 130 ℃.The bond layer 9 of 2 layers of structure like this is used as the adhesive film when being bonded in the 2nd semiconductor element 8 on the 1st semiconductor element 5.In addition, the bond layer 9 of 2 layers of structure also can be formed directly on the back side of the 2nd semiconductor element 8.
As mentioned above, by with different temperature drying epoxy resin varnishes, can form spring rate so that softening or melt temperature is different the 1st layer 10 and the 2nd layers 11.Specifically be, when using more than or equal to the 1st layer 10 baking temperature (more than or equal to 130 ℃) and being lower than the 2nd layer 11 the temperature heating of baking temperature (being lower than 150 ℃), the 2nd layer of 11 sustaining layer shape, and have only the 1st layer of 10 softening or fusion.Thereby, temperature by with the 2nd semiconductor element 8 bonding the time is set in above-mentioned temperature range (for example more than or equal to 130 ℃ and less than 150 ℃), remove and to keep the 2nd layer 11 layer shape, play outside the effect as insulating barrier, can also make the 1st layer of 10 softening or fusion, make it play well effect as bonding agent.
In addition, replace the control of the baking temperature of above-mentioned epoxy resin varnish,, also can access the bond layer 9 of 2 layers of structure with the 1st layer 10 and the 2nd layers 11 by making difference drying time of coating behind the epoxy resin varnish.In such cases, for example epoxy resin varnish (A step) be coated in become on the film matrix of the support material 12 after, for example make this overlay drying with predetermined temperature, form the 2nd layer 11 of semi-harden state (B step).Then, on the 2nd layer 11, apply epoxy resin varnish (A step) once more, use with the 2nd layer of 11 identical temperature and use time chien shih this overlay drying than the 2nd layer of 11 weak point.So also can access spring rate so that softening or melt temperature is different the 1st layer 10 and the 2nd layers 11.
The bond layer 9 of 2 layers of structure of employing is bonded in the 2nd semiconductor element 8 on the 1st semiconductor element 5, be located at connection the 2nd bonding wire 13 on the 2nd electrode pad of its upper surface side, and then, be electrically connected with the electrode part 4 of circuit substrate 2 by the 2nd bonding wire 13.In addition, the such sealing resin 14 of epoxy resin seals laminations, is configured in the 1st semiconductor element 5 and the 2nd semiconductor element 8 on the circuit substrate 2 by for example adopting, and constitutes the semiconductor device 1 of lamination-type multi-chip encapsulation body structure.
In addition, in Fig. 1, the structure of 2 semiconductor elements of lamination 5,8 has been described, but the lamination number of semiconductor element is not limited thereto, and can certainly be more than 3 or 3.At the semiconductor element of lamination more than 3 or 3, constitute under the situation of semiconductor device, bonding between semiconductor element adopts the bond layer of 2 layers of structure, promptly adopts the 1st layer and the 2nd layer bond layer of sustaining layer shape of the softening or fusion of temperature when having with semiconductor element bonding.
The semiconductor device 1 of the 1st above-mentioned execution mode for example can be by following making.About the manufacturing process of semiconductor device 1, with reference to Fig. 4 explanation.Shown in Fig. 4 (a), on circuit substrate 2, adopt the 1st bond layer 6 bonding the 1st semiconductor elements 5.Then, implement the lead-in wire bond sequence, be electrically connected the electrode part 4 of circuit substrate 2 and the electrode pad of the 1st semiconductor element 5 with the 1st bonding wire 7.Then, shown in Fig. 4 (b), the bonding circuit substrate 2 that is equipped with the 1st semiconductor element 5 is positioned on the heating station 21.
In addition, in the lower face side of the 2nd semiconductor element 8, adhere to bond layer (adhesive films of 2 layers of structure) 9 based on 2 layers of structure of making such as manufacturing process shown in Figure 3.At this moment, the bond layer 9 of 2 layers of structure, with the 2nd layer 11 promptly the 2nd layer of 11 mode that is configured in the 2nd semiconductor element 8 sides of the temperature maintenance layer shape when bonding adhere to.Dispose in the mode of joining with the 1st semiconductor element 5 for the 1st layer 10.The 2nd semiconductor element 8 that keeps adhering to like this bond layer 9 of 2 layers of structure with erecting tools 22.Erecting tools 22 for example has the absorption holding unit and the heating arrangements of semiconductor element 8.In addition, the bond layer 9 of 2 layers of structure also can apply ground formation such as thermosetting resin varnish successively below the 2nd semiconductor element 8.
Then, shown in Fig. 4 (c), with the 1st semiconductor element 5 position alignment after, the 2nd semiconductor element 8 that remains on the erecting tools 22 is descended, the 2nd bond layer 9 is contacted with the 1st semiconductor element 5, adopt at least one side in heating station 21 and the erecting tools 22 simultaneously, heat the 2nd bond layer 9.The heating-up temperature of this moment is made as more than or equal to the 1st layer 10 baking temperature and less than the 2nd layer 11 baking temperature.Using the 2nd layer 11 of 150 ℃ of drying as mentioned above, under the situation with the 1st layer 10 of 130 ℃ of drying,, be made as for example 140 ± 5 ℃ the heating-up temperature of the 2nd bond layer 9 (temperature during the 2nd semiconductor element 8 bonding).
Heating with above-mentioned temperature under the situation of the 2nd bond layer 9, the effect as the bonding agent of bonding the 1st semiconductor element 5 and the 2nd semiconductor element 8 is played in the 1st layer of 10 softening or fusion.In addition, because the 1st layer of 10 softening or fusion when heating, therefore the 1st bonding wire 7 enters in the 1st layer 10.Thus, can prevent that the 1st bonding wire 7 from producing distortion or bad connection etc. because of damaging by pressure.In addition, because the 2nd layer 11 with respect to above-mentioned heating-up temperature sustaining layer shape, play the effect as insulating barrier, the 1st bonding wire 7 in therefore can preventing to enter into the 1st layer 10 contacts with the 2nd semiconductor element 8.Thus, can prevent the defective insulation that contacts of following the 1st bonding wire 7 and the 2nd semiconductor element 8 or short circuit etc. effectively.
In the bond layer 9 of 2 layers of structure, the 1st layer 10 thickness is set according to the height of the 1st bonding wire 7 is suitable.For example, be under the situation of 60 ± 15 μ m at the height (maximum height on the 1st semiconductor element 5) of the 1st bonding wire 7, the 1st layer 10 thickness preferably softening with heating-up temperature or fusion is for example 75 ± 15 μ m.In addition, with respect to the 2nd layer 11 thickness of heating-up temperature sustaining layer shape,, for example preferably set about 10 μ m as long as can access as the function of insulating barrier just passablely.If the 2nd layer 11 thickness is too thick, then hinder the slimming of semiconductor device 1.
After adopting the bond layer 9 of 2 layers of structure, being bonded in the 2nd semiconductor element 8 on the 1st semiconductor element 5, implement the lead-in wire bond sequence, with the electrode part 4 of the 2nd bonding wire 13 electrical connection circuit substrates 2 and the electrode pad of the 2nd semiconductor element 8., formation operation by implement external connection terminals 3, utilize the resin-sealed operation of sealing resin 14 etc., obtain the semiconductor device 1 of lamination-type multi-chip encapsulation body structure thereafter.
As mentioned above, by adopting the bond layer 9 of 2 layers of different structure of spring rate, remove the distortion or the bad connection that can prevent the 1st bonding wire 7, and the 1st outside bonding wire 7 and contacting of the 2nd semiconductor element 8 etc., can also be on the 1st semiconductor element 5 good and bonding at low cost the 2nd semiconductor element 8.In addition,, therefore behind the bonding process of the 2nd semiconductor element 8, can not produce splitting etc. owing to form the bond layer 9 of 2 layers of structure with same material, and then can suppress bonding required worker the time or the increase of manufacturing cost.
Promptly, in the laminated construction of in the past employing insulating barrier and bond layer,, cause splitting etc. because of coefficient of thermal expansion difference of insulating barrier and bond layer etc., but in the bond layer 9 of 2 layers of structure that form with same material, can not produce splitting because of coefficient of thermal expansion difference etc.And then, by the bond layer 9 that adopts 2 layers of structure, bonding the 1st semiconductor element 5 and the 2nd semiconductor element 8, because it is identical with the bonding process of the small pieces adhering film of in the past 1 layer of structure of employing that bonding process itself can be taken as, so can not cause bonding required worker the time or the increase of manufacturing cost.That is, can cut down in the past required man-hour or the cost of formation insulating barrier.
In addition, because usefulness has the 2nd layer 11 as the function of insulating barrier, prevent contacting of the 1st bonding wire 7 and the 2nd semiconductor element 8, therefore can be with the thickness of the 2nd bond layer 9, be set in the 1st bonding wire 7 shifting grounds are taken in the 1st layer 10 the scope.Thereby, compare with the stacked-type semiconductor device in the past of setting the interval between the 1st semiconductor element and the 2nd semiconductor element by liner, can seek the slimming of semiconductor device 1.That is, can realize the semiconductor device 1 of the lamination-type multi-chip encapsulation body structure that the raising two of slimming and reliability is upright.
In the above-described embodiment, by the 1st layer 10 the thickness that has as the function of bonding agent, be scheduled to from the 1st semiconductor element 5 to the 2nd layer 11 the distance that has as the function of insulating barrier, in other words, be the part height of configuration the 1st bonding wire 7, still, for example, as shown in Figure 5, also formation columnar projections 23 on the electrode pad that connects the 1st semiconductor element 5, the distance that predetermined the 1st semiconductor element 5 and the 2nd semiconductor element are 8 can be not used in.Thus, can prevent the 2nd layer of 11 damage that causes with contacting of the 1st bonding wire 7 or distortion etc. more reliably.
Then, with reference to the semiconductor device of Fig. 7 and Fig. 8 explanation according to the 2nd execution mode of the present invention.Fig. 7 is the vertical view of expression according to the concise and to the point formation of the semiconductor device of the 2nd execution mode, and Fig. 8 is its profile.In addition, for the identical part of described the 1st execution mode, additional prosign, and part is omitted its explanation.
Fig. 7 and semiconductor device 30 shown in Figure 8, same with described the 1st execution mode, by the 1st bond layer 6 the 1st semiconductor element 5 is bonded on the circuit substrate 2.The electrode pad of the 1st semiconductor element 5 is electrically connected with the electrode part 4 of circuit substrate 2 by the 1st bonding wire 7.On the 1st semiconductor element 5, adopt the bond layer 9 of 2 layers of structure, bonding the 2nd semiconductor element 8 with the 1st layer 10 and the 2nd layers 11.The electrode pad of the 2nd semiconductor element 8 is electrically connected with the electrode part 4 of circuit substrate 2 by the 2nd bonding wire 13.
The 2nd semiconductor element 8 is with respect to the 5 biasing ground configurations of the 1st semiconductor element.Thereby, be equivalent to the both ends of the lead-in wire bonding part of the 2nd semiconductor element 8, outstanding laterally from the periphery of the 1st semiconductor element 5.Owing to do not have the 1st semiconductor element 5 at the downside of these protuberances 31, thus former state unchangeably the 2nd semiconductor do not have part 8 below, specifically be that the below of protuberance 31 forms hollow bulb.If the electrode pad of the 2nd semiconductor element 8 with such protuberance 31 is implemented the lead-in wire bonding, because the load deflection of the 2nd semiconductor element 8 during because of bonding, therefore exist in and crack on the 2nd semiconductor element 8 etc., or produce bad etc. the problem of bonding.
Therefore, in the semiconductor device 30 of present embodiment, in the protuberance 31 and the space between the circuit substrate 2 of the 2nd semiconductor element 8, fill for the 1st layer 10 on the bond layer 9 of the softening or 2 layers of structure of fusion of the heating-up temperature by with bonding the 2nd semiconductor element 8 time when bonding (temperature).That is, in order below protuberance 31, not produce hollow bulb, will a part of the 1st layer 10 softening with heating-up temperature or fusion be filled to the below of the protuberance 31 of the 2nd semiconductor element 8.Thus, owing to below the protuberance 31 of the 2nd semiconductor element 8, exist to constitute the 1st layer 10 adhesive resin, so the 2nd semiconductor element 8 not deflections when the lead-in wire bonding, it is bad etc. to prevent that the 2nd semiconductor element 8 from crackles or bonding taking place.
The semiconductor device 30 of the 2nd above-mentioned execution mode for example can be by following making.In addition, for the identical part of manufacturing process of the semiconductor device 1 that forms according to the 1st execution mode, clipped explanation.At first, shown in Fig. 9 (a),, be placed on the heating station 21 the bonding circuit substrate 2 that is equipped with the 1st semiconductor element 5.In addition, remain on the 2nd semiconductor element 8 that lower face side is stained with the bond layer 9 of 2 layers of structure with erecting tools 22.In addition, the bond layer 9 of 2 layers of structure also can form by apply thermosetting resin varnish successively below the 2nd semiconductor element 8.
On the bond layer 9 of 2 layers of structure below sticking to the 2nd semiconductor element 8, but the 2nd layer 11 thickness with respect to heating-up temperature sustaining layer shape, same with the 1st execution mode, so long as the thickness (for example 10 μ m) that can access as the function of insulating barrier is just passable.In addition, the 1st layer 10 is not bonding the 1st semiconductor element 5 and the 2nd semiconductor element 8, need set for and can supply with the fully thickness of the insulating resin of the below of the protuberance 31 of filling the 2nd semiconductor element 8.But if it is too much to constitute the 1st layer 10 the amount of adhesive resin (insulating resin), the 1st layer 10 will be outstanding from the peripheral part of the 2nd semiconductor element 8, occurs imappropriate.
Therefore, on the bond layer 9 of 2 layers of structure the 1st layer 10, the thickness of the adhesive resin layer 10 of promptly softening or fusion with heating-up temperature, consider the bonding required amount of the 1st semiconductor element 5 and the 2nd semiconductor element 8 and the 2nd semiconductor element 8 protuberance 31 below (hollow bulb) the required amount of filling and set.For example, as shown in figure 10, width W 2 at the 2nd semiconductor element 8 is that (global shape is 10 * 10mm) to 10mm, the width of protuberance 31 (hollow amount) is xmm, the width W 1 of the 1st semiconductor element 5 is (10-2x) mm, and step difference (height above 1 semiconductor element 5 of substrate 2 surfaces to the) is under the situation of 0.2mm, and filling hollow amount is the 1st layer 10 required thickness of hollow bulb of protuberance 31 belows of xmm, for example, as shown in figure 11.
Below, shown in Fig. 9 (b), with the 1st semiconductor element 5 position alignment after, fall the 2nd semiconductor element 8 that remains on the erecting tools 22, pressure with appropriateness, the 2nd bond layer 9 is contacted with the 1st semiconductor element 5, adopt at least one side in heating station 21 and the erecting tools 22 simultaneously, heat the 2nd bond layer 9.The heating-up temperature of this moment, same with the 1st execution mode, be made as more than or equal to the 1st layer 10 baking temperature and less than the 2nd layer 11 baking temperature.In this pressurization, heating process, because by the 1st layer 10 thickness on the bond layer 9 of controlling 2 layers of structure as mentioned above, therefore can not make the 1st layer of 10 peripheral part outstanding by the 2nd semiconductor element 8, the adhesive resin (insulating resin) that the enough formations of energy are the 1st layer 10, the hollow bulb of protuberance 31 belows of the 2nd semiconductor element 8 of filling well.
The 2nd semiconductor element 8 is being bonded on the 1st semiconductor element 5, after using the hollow bulb of protuberance 31 belows of adhesive resin (insulating resin) filling the 2nd semiconductor element 8 simultaneously, with the 2nd bonding wire 13, be electrically connected the electrode part 4 of circuit substrate 2 and the electrode pad of the 2nd semiconductor element 8.At this moment, because below the protuberance 31 of the lead-in wire bonding part that is equivalent to the 2nd semiconductor element 8, imbed adhesive resin, so the deflection of the 2nd semiconductor element 8 can prevent to go between bonding the time.Thereby crackle that the load in the time of can suppressing because of bonding significantly produces at the 2nd semiconductor element 8 or bonding are bad etc.Then, same with the 1st execution mode, the formation operation by implementing external connection terminals, utilize the sealing process of sealing resin etc., obtain the semiconductor device 30 of lamination-type multi-chip encapsulation body structure.
Figure 12 and semiconductor device 30 shown in Figure 13, on the 1st semiconductor element 5, the bond layer 9 bonding shapes that adopt 2 layers of structure are than its 2nd big semiconductor element 8.Thereby, be equivalent to the peripheral part of the lead-in wire bonding part of the 2nd semiconductor element 8, outstanding laterally by the periphery of the 1st semiconductor element 5.The hollow bulb of these protuberance 31 belows, the 1st layer 10 on the bond layer 9 of the softening or 2 layers of structure of fusion of the heating-up temperature by with bonding the 2nd semiconductor element 8 time when bonding (temperature) is filled with respectively.Thereby owing to below the protuberance 31 of the 2nd semiconductor element 8, exist to constitute the 1st layer 10 adhesive resin, so the 2nd semiconductor element 8 not deflections when the lead-in wire bonding, it is bad etc. to prevent that the 2nd semiconductor element 8 from crackles or bonding taking place.
Then, with reference to the semiconductor device of Figure 14 and Figure 15 explanation according to the 3rd execution mode of the present invention.Figure 14 is the vertical view of expression according to the concise and to the point formation of the semiconductor device of the 3rd execution mode, and Figure 15 is its profile.In addition, for the described the 1st and the 2nd identical part of execution mode, additional prosign, and part is omitted its explanation.
Figure 14 and semiconductor device 40 shown in Figure 15, same with the described the 1st and the 2nd execution mode, by the 1st bond layer 6, the 1st semiconductor element 5 is bonded on the circuit substrate 2.The electrode pad of the 1st semiconductor element 5 is electrically connected with the electrode part 4 of circuit substrate 2 by the 1st bonding wire 7.On the 1st semiconductor element 5, by the 2nd bond layer 41 bonding the 2nd semiconductor elements 8.The electrode pad of the 2nd semiconductor element 8 is electrically connected with the electrode part 4 of circuit substrate 2 by the 2nd bonding wire 13.
The 2nd semiconductor element 8 is bonded in the 2nd bond layer 41 on the 1st semiconductor element 5, and have temperature (heating-up temperature) when bonding can keep the insulating properties filler 42 of solid-state state, this insulating properties filler 42 has the function as the liner of the distance that keeps 8 of the 1st semiconductor element 5 and the 2nd semiconductor elements.Thereby, except that the distortion that can prevent the 1st bonding wire 7 or bad connection and the 1st bonding wire 7 and contacting of the 2nd semiconductor element 8 etc., can also be well and bonding the 2nd semiconductor element 8 on the 1st semiconductor element 5 at low cost.
Be configured in the insulating properties filler 42 in the 2nd bond layer 41, for example the temperature (heating-up temperature) by with respect to bonding the 2nd semiconductor element 8 time can be kept insulative resin thermal endurance and shape, that have intensity (shape maintains function) and constitutes, and its concrete material does not limit especially.As the concrete constituent material of insulating properties filler 42, can enumerate thermosetting resins such as polyimide resin, silicones, acrylic resin, urethane resin.Employing has the adhesive resin (epoxy resin etc.) of the insulating properties filler 42 that is made of such insulative resin, and the 2nd semiconductor element 8 is bonded on the 1st semiconductor element 5.
And then, with respect to the 1st semiconductor element 5 biasing ground configurations the 2nd semiconductor element 8.Thereby, be equivalent to the both ends of the lead-in wire bonding part of the 2nd semiconductor element 8, outstanding laterally from the periphery of the 1st semiconductor element 5.Below these protuberances 31, softening or fusion the 2nd bond layer 41 of the heating-up temperature by with bonding the 2nd semiconductor element 8 time when bonding (temperature) is filled.That is, so that do not produce hollow bulb ground below protuberance 31, to the below of the protuberance 31 of the 2nd semiconductor element 8, filling is softened with heating-up temperature or the part of the 2nd bond layer 41 of fusion.The thickness of the 2nd bond layer 41, same with the 2nd execution mode, preferably set according to the charging quantity of hollow bulb is suitable.
Figure 16, the 17th, expression is according to the overlooking of the concise and to the point formation of the semiconductor device of the 4th execution mode of the present invention, profile.Semiconductor device shown in this figure (semiconductor package body) 101 as component mounting substrate, has circuit substrate 102.Circuit substrate 102, the substrate that can adopt resin substrate, ceramic substrate, glass substrate etc. to constitute by various materials.As resin substrate, use general multilayer copper plating film laminated plate (multilayer printed-wiring board) etc.In the lower face side of circuit substrate 102, form external connection terminals 103 such as slicken solder projection.In addition, in the upper surface side of the element installed surface that becomes circuit substrate 102, the electrode part 104 that for example is electrically connected with external connection terminals 103 by internal layer wiring (not shown) is set.This electrode part 104 becomes the lead-in wire bonding part.
The installed surface of circuit substrate 102 (above) on, by the 1st bond layer 106 bonding the 1st semiconductor elements 105.The 1st bond layer 106 adopts general small plate adhering material (small pieces adhering film etc.).Be located at the 1st electrode pad of the upper surface side of the 1st semiconductor element 105, be electrically connected with the electrode part 104 of circuit substrate 102 via the 1st bonding wire 107.On the 1st semiconductor element 105, by the 2nd bond layer 109 bonding 2nd semiconductor elements 108 bigger than its shape.The 2nd bond layer 109, same with the 1st bond layer 106, adopt general small plate adhering material (small pieces adhering film etc.).
As mentioned above,, therefore be equivalent to the peripheral part of the lead-in wire bonding part of the 2nd semiconductor element 108 because the 2nd semiconductor element 108 has the shape bigger than the 1st semiconductor element 105, outstanding laterally by the periphery of the 1st semiconductor element 105.Because there is not the 1st semiconductor element 105 in the downside at the protuberance 110 of the peripheral part that is equivalent to the 2nd semiconductor element 108, the protuberance 110 that therefore forms the 2nd semiconductor element 108 same as before is to the outstanding state of hollow bulb.If the electrode pad of the 2nd semiconductor element 108 with such protuberance 110 is implemented the lead-in wire bonding, because the load deflection of the 2nd semiconductor element 108 during because of bonding, therefore exist in and crack on the 2nd semiconductor element 108 etc., or produce bad etc. the problem of bonding.
Therefore, in the semiconductor device 101 of present embodiment, below the protuberance 110 of the 2nd semiconductor element 108, set in advance insulating properties column 111.That is, the protuberance 110 of the 2nd semiconductor element 108 is supported by the insulating properties column on the precalculated position that is located at circuit substrate 102 111.In the semiconductor device 101 of this execution mode, each protuberance 110 is supported on each limit of the 2nd semiconductor element 108 by a plurality of for example 3 insulating properties columns 111.The quantity that is provided in the insulating properties column 111 on each limit on each limit of the 2nd semiconductor element 108 also can be 1, but from improving rigidity, and when making lamination or the angle of the load dispersing when connecting consider, preferably, be supported on every limit of the 2nd semiconductor element 108 by a plurality of insulating properties columns 111.
Support the insulating properties column 111 of protuberance 110, constitute clinch with the 2nd semiconductor element 108 by insulating material such as insulative resins at least.Insulating properties column 111 in the semiconductor device 101 shown in Figure 16, for example applying by column, thermosetting resins such as epoxy resin, polyimide resin, silicones, acrylic resin form.In addition, also can for example, as shown in figure 18, overlap to form a plurality of resin columns 112 according to the height of insulating properties column 111.Thus, can reduce the deviation etc. of the height of insulating properties column 111.The number of overlapping resin column 112 can and become the suitable settings such as viscosity of resin combination of the formation material of resin column 112 according to the height of insulating properties column 111.Figure 18 represents to apply successively the state that forms 3 resin columns 112.
In addition, at aspects such as mouldability of seeking to improve insulating properties column 111 or intensity, for example, and as shown in figure 19, also can be at the internal configurations reinforcement material 113 of insulating properties column 111.Reinforcement material 113 can adopt for example insulative resin formed body or insulating properties inorganic matter (glass or pottery etc.) or metal parts etc.Insulating properties column 111 with such reinforcement material 113, at first on circuit substrate 2, form lower resin 114, dispose reinforcement material 113 thereon, become the upper resin layer 115 with the clinch of the 2nd semiconductor element 108 then, make like this.By internal configurations reinforcement material 113, can reduce the deviation etc. of the height of insulating properties column 111, and, further be easy to the bonding that goes between by improving intensity or hardness at insulating properties column 111.
In addition, as shown in figure 20, also can adopt full-bodied resin combination in advance, setting stops frame 116, and portion forms insulating properties column 111 within it.Stop frame 116 by periphery setting at insulating properties column 111, even, also can form well than higher insulating properties column 111, collapsing etc. in the time of can suppressing the lamination of insulating properties column 111 in addition or when connecting.In addition, because therefore the resin material can suppress to form insulating properties column 111 time, can prevent that the electrode part 104 that resin is attached on circuit substrate 102 is first-class to the expansion of in-plane.
Then,, seal lamination, be configured in the 1st semiconductor element 105 and the 2nd semiconductor element 108 on the circuit substrate 102, constitute the semiconductor device 101 of lamination-type multi-chip encapsulation body structure by adopting for example such sealing resin 118 of epoxy resin.In addition, in Figure 16, the structure of 2 semiconductor elements of lamination 105,108 has been described, but the lamination number of semiconductor element is not limited thereto, and can certainly be more than 3 or 3.Even constitute under the situation of semiconductor device at the semiconductor element of lamination more than 3 or 3, by supported the protuberance of the semiconductor element more than the 2nd section or the 2nd section respectively by the insulating properties column, it is bad etc. also can to prevent element crackle or bonding effectively.
The semiconductor device 101 of the 4th above-mentioned execution mode for example can be by following making.About the manufacturing process of semiconductor device 101, with reference to Figure 21 explanation.At first, shown in Figure 21 (a), on circuit substrate 102, adopt the 1st bond layer 106 bonding the 1st semiconductor elements 105.Then, implement the lead-in wire bond sequence, be electrically connected the electrode part 104 of circuit substrate 102 and the electrode pad of the 1st semiconductor element 105 with the 1st bonding wire 107.
Then, shown in Figure 21 (b), on the preposition of the bonding circuit substrate 102 that is equipped with the 1st semiconductor element 105, form insulating properties column 111.Insulating properties column 111 as mentioned above, forms by thermosetting resins such as column coating epoxy resin.Insulating properties column 111 as shown in figure 18, also can form in the mode of overlapping a plurality of resin columns.In addition, also can adopt insulating properties column 111 with Figure 19 or structure shown in Figure 20.No matter adopt which kind of structure, all form clinch with the 2nd semiconductor element 108 by insulative resin at least.And then on the 1st semiconductor element 105, mounting becomes the small plate adhering material of the 2nd bond layer 109 etc.
Then, shown in Figure 21 (c), behind configuration the 2nd semiconductor element 108 in position alignment ground on the 1st semiconductor element 105, plus-pressure with appropriateness makes the 2nd semiconductor element 108 contact with the 1st semiconductor element 105, heat the 2nd bond layer 109 simultaneously, the 2nd semiconductor element 108 is bonded on the 1st semiconductor element 105.At this moment, the protuberance 110 of the 2nd semiconductor element 108 contacts with insulating properties column 111, bonding protuberance 110 and insulating properties column 111.Like this, support the protuberance 110 of the 2nd semiconductor element 108 with insulating properties column 111.
Then, shown in Figure 21 (d), the 2nd semiconductor element 108 is implemented the lead-in wire bond sequence, be electrically connected the electrode part 104 of circuit substrate 102 and the electrode pad of the 2nd semiconductor element 108 with the 2nd bonding wire 117.At this moment, the protuberance 110 of the 2nd semiconductor element 108, support by insulating properties column 111, because the deflection of the 2nd semiconductor element 108 that the load in the time of can suppressing to go between bonding causes, therefore can prevent effectively that the crackle of the 2nd semiconductor element 108 or bonding are bad, or the distortion of the 1st bonding wire 107 or bad connection etc.In addition, the formation operation by implementing external connection terminals 103, utilize the resin-sealed operation of sealing resin 118 etc., can obtain the semiconductor device 101 of lamination-type multi-chip encapsulation body structure.
As mentioned above, by support the protuberance 110 of the 2nd semiconductor element 108 by insulating properties column 111, can prevent to result from the element crackle of protuberance 110 or the bad connection of bonding wire etc. effectively.In addition, condition of contact is promptly loaded or the range of choice of ultrasonic wave output owing to enlarge, and therefore can implement the lead-in wire bonding to the 2nd semiconductor element 108 better.And then, because insulating properties column 111 does not hinder the slimming of semiconductor device 101 or miniaturization etc. yet, therefore under the situation of the epimere side superimposed layer semiconductor element 108 bigger, can realize semiconductor device 1 small-sized, slim and the lamination-type multi-chip encapsulation body structure that reliability is excellent than the semiconductor element 105 of hypomere side.
Then, about semiconductor device, describe with reference to Figure 22, Figure 23 and Figure 24 according to the 5th execution mode of the present invention.Figure 22 is the vertical view of expression according to the concise and to the point formation of the semiconductor device of the 5th execution mode, and Figure 23 is the profile of seeing from its frontal, and Figure 24 is the profile seen of direction from the side.In addition, for the identical part of aforementioned the 4th execution mode, additional prosign, and part is omitted its explanation.
Figure 22, Figure 23 and semiconductor device 120 shown in Figure 24, same with aforementioned the 1st execution mode, by the 1st bond layer 122, the 1st semiconductor element 121 is bonded on the circuit substrate 102.The electrode pad of the 1st semiconductor element 121 by the 1st bonding wire 123, is electrically connected with the electrode part 104 of circuit substrate 102.On the 1st semiconductor element 121, by the 2nd bond layer 125, bonding shape is than its 2nd little semiconductor element 124.The electrode pad of the 2nd semiconductor element 124 by the 2nd bonding wire 126, is electrically connected with the electrode part 104 of circuit substrate 102.
On the 2nd semiconductor element 124, by the 3rd bond layer 128, bonding the 3rd semiconductor element 127.The electrode pad of the 3rd semiconductor element 127 by the 3rd bonding wire 129, is electrically connected with the electrode part 104 of circuit substrate 102.On the 1st bond layer the 122, the 2nd bond layer 125 and the 3rd bond layer 128, same with the 4th above-mentioned execution mode, adopt common small plate adhering material.Herein, with respect to the 2nd semiconductor element 121 biasing ground configurations the 3rd semiconductor element 127.Thereby, be equivalent to the end of the lead-in wire bonding part of the 3rd semiconductor element 127, outstanding laterally by the periphery of the 2nd semiconductor element 124.
The protuberance 130 of the 3rd semiconductor element 127, same with the 1st above-mentioned execution mode, support by the insulating properties column 111 that is located on the circuit substrate 102.In this embodiment, support protuberance 130 by 3 insulating properties columns 111.About insulating properties column 111, same with the 4th above-mentioned execution mode, can adopt that thermmohardening type resin such as column coating epoxy resin forms, form in the mode of overlapping a plurality of resin columns and have Figure 19 or structure shown in Figure 20 etc. variform.In addition, though omitted diagram, but lamination, be configured in the 1st semiconductor element the 121, the 2nd semiconductor element 124 and the 3rd semiconductor element 127 on the circuit substrate 102,, constitute the semiconductor device 120 of lamination-type multi-chip encapsulation body structure thus with the sealing of sealing resins such as epoxy resin.
In the semiconductor device 120 of the 5th above-mentioned execution mode, because with insulating properties column 111, support is configured in the 3rd semiconductor element 127 on the 2nd semiconductor element 124, promptly with respect to the protuberance 130 of the 3rd semiconductor element 127 of the 2nd semiconductor element 124 biasing, so can prevent to result from the element crackle of protuberance 130 or the bad connection of bonding wire etc. effectively.Thereby, even setover ground under the situation of epimere side superimposed layer semiconductor element 127, also can realize semiconductor device 120 small-sized, slim and the lamination-type multi-chip encapsulation body structure that reliability is excellent at semiconductor element 124 with respect to the hypomere side.
Herein, in the semiconductor device 120 of Figure 22～shown in Figure 24, expression is by the 2nd semiconductor element 124, on the 1st semiconductor element 121, be equipped with the formation of the 3rd semiconductor element 127, but replacing the 2nd semiconductor element 124, under the situation of configuration liner chip, also can adopt identical formation.In addition, be not limited to 3 sections laminated semiconductor elements situation of (comprising the liner chip), even at 2 sections laminated semiconductor elements or more than 4 sections or 4 sections under the situation of laminated semiconductor element, by support the protuberance of the semiconductor element more than the 2nd section or the 2nd section with the insulated type column, also can prevent the generation that element crackle or bonding are bad etc. effectively.
In addition, the present invention is not limited to above-mentioned execution mode, can be used in the various semiconductor device that lamination carries a plurality of semiconductor elements.Semiconductor device for such is also included within the present invention.In addition, embodiments of the present invention in the scope of technological thought of the present invention, can be expanded or be changed, and this expansion or execution mode after changing are also included within the technical scope of the present invention.
Claims (7)
1. semiconductor device is characterized in that possessing:
Substrate with electrode part;
The 1st semiconductor element has by the 1st bonding wire and is connected the 1st electrode pad on the described electrode part and is bonded on the described substrate; And
The 2nd semiconductor element has by the 2nd bonding wire and is connected the 2nd electrode pad on the described electrode part and bonds on described the 1st semiconductor element by bond layer, and has from the outstanding laterally part of the periphery of described the 1st semiconductor element;
Described bond layer has contained the insulating properties filler of the liner effect that keeps the distance between described the 1st semiconductor element and described the 2nd semiconductor element, and between the ledge of described the 2nd semiconductor element and the described substrate, the temperature described bond layer softening or fusion by with described the 2nd semiconductor element bonding the time is filled.
2. semiconductor device as claimed in claim 1 is characterized in that:
The temperature maintenance solid-state state of described insulating properties filler when bonding.
3. semiconductor device is characterized in that possessing:
Substrate with electrode part;
The 1st semiconductor element has by the 1st bonding wire and is connected the 1st electrode pad on the described electrode part and carries on described substrate; And
The 2nd semiconductor element has by the 2nd bonding wire and is connected the 2nd electrode pad on the described electrode part and carries on described the 1st semiconductor element, and has from the outstanding laterally part of the periphery of described the 1st semiconductor element;
The ledge of described the 2nd semiconductor element is by insulating properties column support below the ledge that is positioned at described the 2nd semiconductor element on the described substrate, that be provided with in the mode of separating with described the 1st semiconductor element.
4. semiconductor device as claimed in claim 3 is characterized in that:
Described insulating properties column, the contact site with described the 2nd semiconductor element is made of insulative resin at least.
5. semiconductor device as claimed in claim 3 is characterized in that:
Described insulating properties column portion within it disposes reinforcement material.
6. semiconductor device as claimed in claim 3 is characterized in that:
Be provided with at the peripheral part of described insulating properties column and stop frame.
7. semiconductor device as claimed in claim 3 is characterized in that:
Described the 2nd semiconductor element is bigger than described the 1st semiconductor element, and perhaps biasing is carried on described the 1st semiconductor element.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004150046 | 2004-05-20 | ||
| JP2004150047 | 2004-05-20 | ||
| JP150046/2004 | 2004-05-20 | ||
| JP150047/2004 | 2004-05-20 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA200510070829XA Division CN1700467A (en) | 2004-05-20 | 2005-05-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101295710A CN101295710A (en) | 2008-10-29 |
| CN101295710B true CN101295710B (en) | 2011-04-06 |
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Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA200510070829XA Pending CN1700467A (en) | 2004-05-20 | 2005-05-19 | Semiconductor device |
| CN2008101097899A Active CN101295710B (en) | 2004-05-20 | 2005-05-19 | Semiconductor device |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA200510070829XA Pending CN1700467A (en) | 2004-05-20 | 2005-05-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN1700467A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103923573A (en) * | 2013-01-10 | 2014-07-16 | 日东电工株式会社 | Adhesive thin film, cutting/chip bonding thin film, manufacturing method for semiconductor device and semiconductor device |
| CN104726032A (en) * | 2013-12-24 | 2015-06-24 | 日东电工株式会社 | Adhesive film, dicing/die-bonding film, method for manufacturing semiconductor device, and semiconductor device |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4719042B2 (en) | 2006-03-16 | 2011-07-06 | 株式会社東芝 | Manufacturing method of semiconductor device |
| JP5437111B2 (en) * | 2010-03-01 | 2014-03-12 | 日東電工株式会社 | Die bond film, dicing die bond film and semiconductor device |
| JP5840479B2 (en) * | 2011-12-20 | 2016-01-06 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| US9418971B2 (en) * | 2012-11-08 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure including a thermal isolation material and method of forming the same |
| JP6373811B2 (en) * | 2015-09-08 | 2018-08-15 | 東芝メモリ株式会社 | Semiconductor device manufacturing method and manufacturing apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1270417A (en) * | 1999-04-14 | 2000-10-18 | 夏普公司 | Semiconductor device and manufacture thereof |
| US6157080A (en) * | 1997-11-06 | 2000-12-05 | Sharp Kabushiki Kaisha | Semiconductor device using a chip scale package |
-
2005
- 2005-05-19 CN CNA200510070829XA patent/CN1700467A/en active Pending
- 2005-05-19 CN CN2008101097899A patent/CN101295710B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6157080A (en) * | 1997-11-06 | 2000-12-05 | Sharp Kabushiki Kaisha | Semiconductor device using a chip scale package |
| CN1270417A (en) * | 1999-04-14 | 2000-10-18 | 夏普公司 | Semiconductor device and manufacture thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103923573A (en) * | 2013-01-10 | 2014-07-16 | 日东电工株式会社 | Adhesive thin film, cutting/chip bonding thin film, manufacturing method for semiconductor device and semiconductor device |
| CN103923573B (en) * | 2013-01-10 | 2019-07-12 | 日东电工株式会社 | Adhesive foil, dicing/die bonding film, the manufacturing method of semiconductor device and semiconductor device |
| CN104726032A (en) * | 2013-12-24 | 2015-06-24 | 日东电工株式会社 | Adhesive film, dicing/die-bonding film, method for manufacturing semiconductor device, and semiconductor device |
| CN104726032B (en) * | 2013-12-24 | 2020-08-11 | 日东电工株式会社 | Adhesive film, dicing die-bonding film, method for manufacturing semiconductor device, and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101295710A (en) | 2008-10-29 |
| CN1700467A (en) | 2005-11-23 |
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