CN101276798A - 隔离焊料垫 - Google Patents
隔离焊料垫 Download PDFInfo
- Publication number
- CN101276798A CN101276798A CNA2007101417267A CN200710141726A CN101276798A CN 101276798 A CN101276798 A CN 101276798A CN A2007101417267 A CNA2007101417267 A CN A2007101417267A CN 200710141726 A CN200710141726 A CN 200710141726A CN 101276798 A CN101276798 A CN 101276798A
- Authority
- CN
- China
- Prior art keywords
- lead
- solder pads
- solder
- wire
- relevant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/10175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
本发明描述了一种集成电路封装包,包括小片和引线框,该引线框包括用于防止在回流期间焊料不必要散布的凹陷区域。该小片包括形成在小片的活性表面上的多个焊料垫。该引线框包括多个引线,多个引线均具有相关的焊料垫。每个焊料垫定位成靠近且电连接小片上的相关焊料凸块。每个引线还包括在靠近焊料垫的区域中的凹陷区域。该凹陷区域用于将焊料垫的表面隔离于引线的其他表面。通过这种方式,接触该引线的该焊料凸块的焊料被限制到相关的焊料垫的表面。
Description
技术领域
本发明大致涉及集成电路(IC)的封装。更具体而言,公开了一种适用于封装焊料凸块的引线框,其限制焊料不必要地散布。
背景技术
有许多用于封装集成电路的传统技术。许多封装技术采用由金属(通常为铜)片压制或蚀刻的引线框,用于电互连到外部装置。采用引线框的一种封装类型是引线倒装晶片(FCOL)封装。
下面参照图1A-B来描述两种示例性FCOL封装100和100’。适用于FCOL封装的引线框通常包括多个引线108。在电连接到单个小片116期间,引线108上的接触区112焊接到相关小片的活性表面上的输入输出垫。该输入输出垫可以是小片116的表面上的垫,或者是利用传统再分配技术从焊接垫再分配出的接触垫。为了便于电连接,在该输入输出垫上形成下凸块金属化处理(UBM)。通常,在输入输出垫118或下凸块金属化处理上形成焊接凸块122。下凸块金属化处理以及焊接凸块可以以及优选为在单个小片一体化之前以晶片级执行。
助熔剂通常施加到焊接凸块122和/或引线框108的接触区112。助熔剂通常化学清除所连接到的金属而有助于焊接。更具体而言,当施加助熔剂时,该助熔剂会去除以及防止金属进一步氧化。然后,助熔剂用作润湿剂,有助于在焊接过程中散布焊料。在施加助熔剂之后,小片116和引线框通常设置在回流炉中。在回流期间,焊料凸块122熔化。该液体焊料沿接触区112和下凸块金属化处理堆栈(或焊接垫)流动,然后通过冷却、固化,将引线108连接到小片116。通常,小片和引线框的一部分然后被密封,只留下曝露的引线框的相反端(相对于接触区112),有助于电连接到外部装置。
在FCOL封装中碰到的挑战之一是,防止在回流期间因焊料沿引线108散布过远而导致过量焊球消耗。焊料的不必要散布会导致可靠性问题。更具体而言,当焊料散布时,焊料接接点的形状会因不期望的形状而扭曲。因此,焊料连接点的结构整体性会受损。而且,该扭曲还会导致引线108和小片116之间的支座高度不均匀和/或支座高度减小。支座高度通常是在封装FCOL封装包中非常关心的因素。通常,焊接垫和接触区112之间的支座高度是焊料凸块122的焊料用量以及相关焊接垫(或UBM)和接触区112的表面面积和几何形状的函数。因此,希望将焊料限制到引线108上的限定接触区中。
发明内容
在一个实施例中,公开了一种集成电路封装包,包括小片、引线框和密封材料。该小片包括形成在小片的活性表面上的多个输入输出垫。该引线框包括多个引线。多个引线均具有至少一个相关的焊料垫。每个焊料垫定位成和小片的相关的输入输出垫镜面对称。该引线还包括在靠近焊料垫的区域中的凹陷区域。该凹陷区域用于将焊料垫的表面隔离于引线的其他表面。该封装包还包括多个焊料凸块。每个焊料凸块电连接小片上的相关的输入输出垫到引线框上的相关的焊料垫。通过这种方式,接触该引线的该焊料凸块的焊料被限制到相关的焊料垫的表面。此外,密封材料密封该焊料凸块和小片及引线的至少一部分。
在另一个实施例中,公开了一种适用于半导体封装的引线框面板。该引线框面板包括连杆矩阵,这些连杆矩阵限定多个装置区域,每个装置区域适用于支持相关的焊料凸块小片。引线框面板的每个装置区域包括多个引线。多个引线均具有至少一个相关的焊料垫。每个焊料垫适当地定位成重叠小片上的对应输入输出垫。该引线还包括靠近焊料垫的区域中的凹陷区域。该凹陷区域用于将焊料垫的表面隔离于引线的其他表面。通过这种方式,当在回流期间熔化该焊料时,接触该引线的输入输出垫上的焊料凸块的焊料被限制到相关的焊料垫的表面。
附图说明
为了更好的理解本发明,结合下面的附图,参照下面的具体实施方式部分,其中:
图1A-B示出示例性FCOL封装包;
图2A-D示出根据本发明的实施例适用于封装块的引线框面板的示意性顶视图;以及
图3A-3D示出根据本发明的实施例采用具有凹陷区域的引线框的小片封装包的示意性侧视图。
图4是采用图2C和3A所示的引线框的引线上倒装晶片(FCOL)封装包的示意性侧视图。
在所有附图中,相同的参考标记表示对应部件。
具体实施方式
本发明大致涉及集成电路(IC)的封装。更具体而言,公开了一种适用于封装焊料凸块的引线框,其限制焊料不必要地散布。
在下面的描述中,提出许多个具体细节,以便于完全理解本发明。然而,对于本领域技术人员而言,显然本发明可以不利用这些具体细节来实现。在其他情况下,没有详细描述公知的过程步骤,以便避免不必要地混淆本发明的内容。
下面的描述的重点在于封装采用引线框的倒装晶片型切片。然而,在将多个切片封装成多个封装结构时,本发明能够有利地实现,其中切片上的凸块直接电连接到基底上的金属触点。
参照图2-4,下面将描述本发明的多个实施例,它们提供具有隔离的焊料垫的引线的引线框。将每个焊料垫隔离于引线表面的其余部分限制焊料沿引线不必要地散布。而且,控制焊料的用量以及焊料垫的表面面积和几何形状可以控制小片和引线框的引线之间获得的支座高度。
图2A-D示出根据本发明的多个实施例的适用于封装集成电路的引线框面板200。图2A示出设置成带状的引线框面板200的示意性顶视图。引线框面板200能够构造成具有多个两维装置区域阵列202的金属结构。如更为详细的视图2B-C所示,每个两维阵列202包括多个装置区域204,每个装置区域构造成适用于单个集成电路封装包,以及每个装置区域由精细连杆206来连接。在封装期间,一个或多个半导体切片附着到每个区域204,然后它们在这些区域经过电连接、密封和一体化过程,产生单个的集成电路封装包。
为了便于进行这些过程,每个装置区域204包括多个引线208,每个引线在一端由连杆206支承。如图2D所示,引线208包括导电焊料垫212,以便提供导电接触区,以将引线电连接到小片320上的相关输入输出垫318。虽然描述和示出了具体的引线框面板200的结构,但是所示本发明可以应用于极其宽泛的其他引线框面板或者带状结构中。
图3A-D示出根据本发明的实施例的采用多个引线框装置区域204的多个装置封装包的一部分。虽然如图2A-2D和3A-3D所示在引线框面板200的顶表面上设置有焊料垫212,但是应当理解的是,这仅仅是为了简化便于相对参照。通过示例的方式,在另一个实施例中,焊料垫212可以认为是位于引线框面板200的底表面上。
在一些实施例中,至少部分通过限制在回流之前施加的助熔剂的散布来控制焊料的散布。通常,焊料将不会散布到没有利用助熔剂制备的区域中。在一个实施例中,通过引入靠近焊料垫212形成的凹陷区域214来限制助熔剂的流动。图3A示出采用具有凹陷区域214的引线框的小片封装包的一部分。具体而言,图3A示出具有导电焊料垫212的引线208。焊料垫212经焊料凸块316电连接到小片320上的输入输出垫318。凹陷区域214将焊料垫212隔离于引线208的其他表面。凹陷区域214可以通过任何合适的方式来形成。通过示例的方式,凹陷区域214可以通过蚀刻引线框面板200的顶表面来形成。凹陷区域214实质上形成环绕每个焊料垫212的沟槽,用于将焊料垫隔离于其余的相关引线表面。图4示出在利用模制材料一体成形和密封之后图3A的整个封装包。
如上所述,通常在电连接之前将助熔剂施加到焊料凸块316和/或焊料垫212。每个凹陷区域214从相关引线208的焊料垫表面充分凹陷,从而基本上防止助熔剂和焊料散布到引线的不期望表面。更具体而言,凹陷区域214优选被蚀刻足够深,以使得通过助熔剂的表面张力将助熔剂的散布限制到焊料垫212。通过示例的方式,在典型引线框设计中,凹陷区域214优选凹陷到大约50至100微米范围内的深度,但是也可以设置更深或更浅的凹陷区域。通常,采用深度为引线框厚度的三分之一至一半的凹陷区域是合适的。对于多种焊料垫几何形状和尺寸而言,这些凹陷深度是合适的。
应当理解的是,产生的“升高的”焊料垫有助于限制焊料的散布,这是因为(a)它们会倾向于限定由助熔剂清理的区域,以及(b)焊料的表面张力会倾向于进一步协助防止焊料超过焊料垫212的边缘。
在一个实施例中,引线框面板200的凹陷区域214被蚀刻,以使得焊料垫212基本上是圆形的,如图2D所示。在可选实施例中,焊料垫212可以是基本椭圆形、矩形或正方形(具有或不具有圆角)。然而,在许多应用场合,优选采用基本圆形的焊料垫而非矩形焊料垫或者具有尖锐角部形状的其他焊料垫。更具体而言,尖锐角部具有抵销将助熔剂和焊料限制到焊料垫212的表面的表面张力的效果。此外,在一些应用场合中,希望形成的焊料垫212宽于相关的引线208。
凹陷区域214还优选沿引线208延伸足够长度,以使得助熔剂不会桥接焊料垫212和引线208其余部分之间的凹陷区域。通过示例的方式,对于许多焊料垫形状和尺寸而言,距离焊料垫212的外缘达大约75至150微米的凹陷长度范围是合适的。此外,在一些实施例中,希望凹陷区域214延伸到更大长度。通过示例的方式,希望凹陷区域214延伸到封装包边缘或者引线的整个长度以下,如图3B所示。
在其他实施例中,焊料垫212和输入输出垫318可以在其他结合或通过其他方式来连接。通过示例的方式,焊料凸块316可以首先形成在焊料垫212上,而非输入输出垫318上。而且,可以利用包含焊料和助熔剂的合适混合物的预混合焊料糊来形成焊料凸块316。不管焊接方式如何,凹陷区域214都能够基本上防止助熔剂和焊料散布到除了焊料垫212的表面之外的其他区域。
应当理解的是,本发明有利地用于控制引线208和小片320之间的支座高度。如上所述,引线框(例如,焊料垫212)和小片(例如,输入输出垫318)之间的支座高度通常是焊料凸块316中焊料用量以及相关的UBM(或输入输出垫318)和焊料垫212的表面面积和几何形状的函数。因此,通过控制焊料的用量和焊料垫212和UBM的表面面积和几何形状,可以实现期望的支座高度。而且,由于相同的过程可以应用于每个焊料接点,所以可以在整个小片320上实现均匀的支座高度。在一个实施例中,焊料垫212的表面面积基本上等于UBM的表面面积。在其他实施例中,希望焊料垫212的表面面积大于UBM的表面面积,反之亦然。
此外,对于包括具有多个焊料垫212的引线208的封装包,本发明的方面尤其有利。如果该引线焊接到两个或更多个等电位输入输出垫318,希望引线208具有两个或更多个212。通过示例的方式,单个引线208可以焊接到多个电源或接地垫。图3C示出具有三个焊料垫212的引线208。每个焊料垫212都通过一个或多个凹陷区域214而隔离于其他焊料垫以及隔离于其余引线表面。以及,助熔剂的表面张力保持该助熔剂,因此焊料限制到隔离的焊料垫212。通过这种方式,焊料接点316沿引线208保持相对均匀的形状。此外,小片320和引线208的隔离沿引线的长度方向保持基本上均匀。因此,应当预期到在小片320和引线框之间的支座高度会更加均匀。
最后,希望在一些实施例中将引线208的相反表面凹陷到对应于焊料垫212的引线的部分,如图3D所示。
可以有利地采用上述引线框的FCOL封装包的示例包括SOT-23,SC70和MSOP封装包。
为了清楚说明,上述描述中采用具体术语来提供本发明的完全理解。然而,对于本领域技术人员而言显而易见的是,这些具体细节不是实现本发明必需的。因此,本发明的具体实施例的上述描述仅仅用于阐述和描述。它们不用作排他性说明或者将本发明限制到所公开的具体形式。对于本领域技术人员显而易见的是,可以通过上述教义作出许多变型和变化。
选择上述实施例并加以描述是为了最佳说明本发明的原理及其实际应用,从而使得本领域技术人员能够最佳采用具有多种变型的本发明和多个实施例来适用于特定应用场合。本发明的范围由下面的权利要求及其等同物来限定。
Claims (16)
1. 一种集成电路封装包,包括:
小片,该小片包括形成在小片的活性表面上的多个输入输出垫;
引线框,该引线框包括多个引线,其中多个引线均具有至少一个相关的焊料垫和不同于该焊料垫的接触表面,该焊料垫适当地定位成重叠小片上的对应输入输出垫,该引线还包括在靠近焊料垫的区域中的凹陷区域,以使得该焊料垫的表面隔离于引线的其他表面;
多个焊料凸块,每个焊料凸块电连接相关的输入输出垫到引线框上的相关的焊料垫,从而接触相关的引线的每个焊料凸块的焊料被限制到相关的焊料垫的表面;以及
密封材料,该密封材料密封该焊料凸块和小片及引线的至少一部分。
2. 根据权利要求1所述的封装包,其中至少一个引线包括通过相关的凹陷区域隔离于这些引线本身以及引线的其他表面的至少两个焊料垫。
3. 根据权利要求1或2所述的封装包,其中焊料垫的宽度宽于它们的相关引线。
4. 根据前述任一权利要求所述的封装包,其中每个凹陷区域从相关的焊料垫的表面开始凹陷到大约50至100微米范围内的深度。
5. 根据前述任一权利要求所述的封装包,其中每个凹陷区域延伸到相关的引线长度以下大约75至150微米范围内的长度。
6. 根据权利要求1-4之一所述的封装包,其中凹陷区域从焊料垫开始延伸的深度始终都在相关的引线长度以下。
7. 根据前述任一权利要求所述的封装包,其中引线的一部分曝露到封装包的侧表面上。
8. 根据前述任一权利要求所述的封装包,其中引线的一部分曝露到封装包的底表面上。
9. 一种适用于半导体封装的引线框面板,该引线框面板包括连杆矩阵,这些连杆矩阵限定多个装置区域,每个装置区域适用于支持相关的焊料凸块小片以及包括:
多个引线,其中该多个引线均具有至少一个相关的焊料垫和不同于焊料垫的接触表面,当该小片适当地定位成靠近该装置区域时该焊料垫适当地定位成重叠小片上的对应输入输出垫,该引线还包括靠近焊料垫的区域中的凹陷区域,以使得焊料垫的表面隔离于引线的其他表面,从而当该焊料熔化时接触该引线的小片上的输入输出垫上的焊料凸块的焊料被限制到相关的焊料垫的表面。
10. 根据权利要求9所述的引线框面板,其中至少一个引线包括通过相关的凹陷区域隔离于这些引线本身以及引线的其他表面的至少两个焊料垫。
11. 根据权利要求9或10所述的引线框面板,其中焊料垫的宽度宽于它们的相关引线。
12. 根据权利要求9-11之一所述的引线框面板,其中每个凹陷区域从相关的焊料垫的表面开始凹陷到大约50至100微米范围内的深度。
13. 根据权利要求9-12之一所述的引线框面板,其中每个凹陷区域延伸到相关的引线长度以下大约75至150微米范围内的长度。
14. 根据权利要求9-12之一所述的引线框面板,其中凹陷区域从焊料垫开始延伸的深度始终都在相关的引线长度以下。
15. 根据权利要求9-14之一所述的引线框面板,其中该焊料垫基本上是圆形的。
16. 根据权利要求9-14之一所述的引线框面板,其中该焊料垫基本上是矩形的。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/691429 | 2007-03-26 | ||
US11/691,429 US20080237814A1 (en) | 2007-03-26 | 2007-03-26 | Isolated solder pads |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101276798A true CN101276798A (zh) | 2008-10-01 |
Family
ID=39792801
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2007101417267A Pending CN101276798A (zh) | 2007-03-26 | 2007-08-21 | 隔离焊料垫 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20080237814A1 (zh) |
KR (1) | KR20080087625A (zh) |
CN (1) | CN101276798A (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102214895A (zh) * | 2010-04-07 | 2011-10-12 | 三菱电机株式会社 | 半导体装置及其制造方法 |
CN103441115A (zh) * | 2011-11-29 | 2013-12-11 | 矽力杰半导体技术(杭州)有限公司 | 一种引线框架及应用其的芯片倒装封装装置 |
CN109285932A (zh) * | 2017-07-21 | 2019-01-29 | Lg 伊诺特有限公司 | 发光器件封装 |
CN109817597A (zh) * | 2017-11-21 | 2019-05-28 | 比亚迪股份有限公司 | 一种电池保护芯片封装结构 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090160039A1 (en) * | 2007-12-20 | 2009-06-25 | National Semiconductor Corporation | Method and leadframe for packaging integrated circuits |
US8604624B2 (en) * | 2008-03-19 | 2013-12-10 | Stats Chippac Ltd. | Flip chip interconnection system having solder position control mechanism |
US8252634B2 (en) * | 2009-06-19 | 2012-08-28 | Stats Chippac Ltd. | Integrated circuit packaging system with a leadframe having radial-segments and method of manufacture thereof |
DE102012107876A1 (de) * | 2012-08-27 | 2014-02-27 | Epcos Ag | Trägerplatte, Vorrichtung mit Trägerplatte sowie Verfahren zur Herstellung einer Trägerplatte |
US10032699B1 (en) * | 2014-04-28 | 2018-07-24 | Amkor Technology, Inc. | Flip chip self-alignment features for substrate and leadframe applications |
JP2019079891A (ja) * | 2017-10-23 | 2019-05-23 | トヨタ自動車株式会社 | 半導体装置 |
CN115220175A (zh) * | 2022-07-20 | 2022-10-21 | 中国科学院上海光学精密机械研究所 | 高面形精度的光学组件及其封接方法 |
Family Cites Families (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996013855A1 (en) * | 1994-10-27 | 1996-05-09 | National Semiconductor Corporation | A leadframe for an integrated circuit package which electrically interconnects multiple integrated circuit die |
US5917242A (en) * | 1996-05-20 | 1999-06-29 | Micron Technology, Inc. | Combination of semiconductor interconnect |
US5677567A (en) * | 1996-06-17 | 1997-10-14 | Micron Technology, Inc. | Leads between chips assembly |
US5902959A (en) * | 1996-09-05 | 1999-05-11 | International Rectifier Corporation | Lead frame with waffled front and rear surfaces |
US5817540A (en) * | 1996-09-20 | 1998-10-06 | Micron Technology, Inc. | Method of fabricating flip-chip on leads devices and resulting assemblies |
US6378758B1 (en) * | 1999-01-19 | 2002-04-30 | Tessera, Inc. | Conductive leads with non-wettable surfaces |
JP3871486B2 (ja) * | 1999-02-17 | 2007-01-24 | 株式会社ルネサステクノロジ | 半導体装置 |
US6184573B1 (en) * | 1999-05-13 | 2001-02-06 | Siliconware Precision Industries Co., Ltd. | Chip packaging |
US6388336B1 (en) * | 1999-09-15 | 2002-05-14 | Texas Instruments Incorporated | Multichip semiconductor assembly |
KR100787678B1 (ko) * | 2000-03-10 | 2007-12-21 | 스태츠 칩팩, 엘티디. | 플립칩 내장형 리드프레임 패키지 및 그 처리과정 |
KR100583494B1 (ko) * | 2000-03-25 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
US6353257B1 (en) * | 2000-05-19 | 2002-03-05 | Siliconware Precision Industries Co., Ltd. | Semiconductor package configuration based on lead frame having recessed and shouldered portions for flash prevention |
US6580165B1 (en) * | 2000-11-16 | 2003-06-17 | Fairchild Semiconductor Corporation | Flip chip with solder pre-plated leadframe including locating holes |
US6798044B2 (en) * | 2000-12-04 | 2004-09-28 | Fairchild Semiconductor Corporation | Flip chip in leaded molded package with two dies |
US6507120B2 (en) * | 2000-12-22 | 2003-01-14 | Siliconware Precision Industries Co., Ltd. | Flip chip type quad flat non-leaded package |
KR100394030B1 (ko) * | 2001-01-15 | 2003-08-06 | 앰코 테크놀로지 코리아 주식회사 | 적층형 반도체 패키지 |
US6424024B1 (en) * | 2001-01-23 | 2002-07-23 | Siliconware Precision Industries Co., Ltd. | Leadframe of quad flat non-leaded package |
US6518161B1 (en) * | 2001-03-07 | 2003-02-11 | Lsi Logic Corporation | Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die |
KR100393448B1 (ko) * | 2001-03-27 | 2003-08-02 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
US6597059B1 (en) * | 2001-04-04 | 2003-07-22 | Amkor Technology, Inc. | Thermally enhanced chip scale lead on chip semiconductor package |
US6482680B1 (en) * | 2001-07-20 | 2002-11-19 | Carsem Semiconductor Sdn, Bhd. | Flip-chip on lead frame |
JP3879452B2 (ja) * | 2001-07-23 | 2007-02-14 | 松下電器産業株式会社 | 樹脂封止型半導体装置およびその製造方法 |
US6577012B1 (en) * | 2001-08-13 | 2003-06-10 | Amkor Technology, Inc. | Laser defined pads for flip chip on leadframe package |
US6593545B1 (en) * | 2001-08-13 | 2003-07-15 | Amkor Technology, Inc. | Laser defined pads for flip chip on leadframe package fabrication method |
US6661087B2 (en) * | 2001-10-09 | 2003-12-09 | Siliconware Precision Industries Co., Ltd. | Lead frame and flip chip semiconductor package with the same |
JP2003124420A (ja) * | 2001-10-16 | 2003-04-25 | Shinko Electric Ind Co Ltd | リードフレーム及び該リードフレームを用いた半導体装置の製造方法 |
US6750546B1 (en) * | 2001-11-05 | 2004-06-15 | Skyworks Solutions, Inc. | Flip-chip leadframe package |
JP3606837B2 (ja) * | 2001-12-19 | 2005-01-05 | 株式会社三井ハイテック | リードフレームおよびこれを用いた半導体装置 |
US6943434B2 (en) * | 2002-10-03 | 2005-09-13 | Fairchild Semiconductor Corporation | Method for maintaining solder thickness in flipchip attach packaging processes |
US6927483B1 (en) * | 2003-03-07 | 2005-08-09 | Amkor Technology, Inc. | Semiconductor package exhibiting efficient lead placement |
US6953711B2 (en) * | 2003-08-11 | 2005-10-11 | Carsem (M) Sdn. Bhd. | Flip chip on lead frame |
TWI225700B (en) * | 2003-10-31 | 2004-12-21 | Advanced Semiconductor Eng | Quad flat flip chip package and lead frame |
TWI317991B (en) * | 2003-12-19 | 2009-12-01 | Advanced Semiconductor Eng | Semiconductor package with flip chip on leadframe |
TWI224849B (en) * | 2004-01-02 | 2004-12-01 | Advanced Semiconductor Eng | Quad flat flip chip package and lead frame |
JP2005302951A (ja) * | 2004-04-09 | 2005-10-27 | Toshiba Corp | 電力用半導体装置パッケージ |
US20050248041A1 (en) * | 2004-05-05 | 2005-11-10 | Atm Technology Singapore Pte Ltd | Electronic device with high lead density |
US7250685B2 (en) * | 2005-08-09 | 2007-07-31 | Stats Chippac Ltd. | Etched leadframe flipchip package system |
US7569920B2 (en) * | 2006-05-10 | 2009-08-04 | Infineon Technologies Ag | Electronic component having at least one vertical semiconductor power transistor |
DE102006026023A1 (de) * | 2006-06-01 | 2007-12-06 | Infineon Technologies Ag | Halbleiterbauteil mit Halbleiterchipstapel und Kunststoffgehäuse sowie Verfahren zur Herstellung des Halbleiterbauteils |
US20080135990A1 (en) * | 2006-12-07 | 2008-06-12 | Texas Instruments Incorporated | Stress-improved flip-chip semiconductor device having half-etched leadframe |
-
2007
- 2007-03-26 US US11/691,429 patent/US20080237814A1/en not_active Abandoned
- 2007-08-21 CN CNA2007101417267A patent/CN101276798A/zh active Pending
- 2007-09-11 KR KR1020070091935A patent/KR20080087625A/ko not_active Application Discontinuation
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102214895A (zh) * | 2010-04-07 | 2011-10-12 | 三菱电机株式会社 | 半导体装置及其制造方法 |
US8625646B2 (en) | 2010-04-07 | 2014-01-07 | Mitsubishi Electric Corporation | Semiconductor device |
CN103441115A (zh) * | 2011-11-29 | 2013-12-11 | 矽力杰半导体技术(杭州)有限公司 | 一种引线框架及应用其的芯片倒装封装装置 |
CN109285932A (zh) * | 2017-07-21 | 2019-01-29 | Lg 伊诺特有限公司 | 发光器件封装 |
CN109285932B (zh) * | 2017-07-21 | 2023-10-20 | 苏州立琻半导体有限公司 | 发光器件封装 |
CN109817597A (zh) * | 2017-11-21 | 2019-05-28 | 比亚迪股份有限公司 | 一种电池保护芯片封装结构 |
Also Published As
Publication number | Publication date |
---|---|
US20080237814A1 (en) | 2008-10-02 |
KR20080087625A (ko) | 2008-10-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101276798A (zh) | 隔离焊料垫 | |
US7619303B2 (en) | Integrated circuit package | |
US7880313B2 (en) | Semiconductor flip chip package having substantially non-collapsible spacer | |
US8298871B2 (en) | Method and leadframe for packaging integrated circuits | |
KR100944472B1 (ko) | 금속 범프를 갖는 반도체 다이 패키지용 캐리어 | |
US7619305B2 (en) | Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking | |
KR100246366B1 (ko) | 에리어 어레이형 반도체 패키지 및 그 제조방법 | |
US8237273B2 (en) | Metal post chip connecting device and method free to use soldering material | |
US20060125113A1 (en) | Flip chip package with anti-floating structure | |
US8133759B2 (en) | Leadframe | |
TWI311352B (en) | Fabricating process of leadframe-based bga packages and leadless leadframe utilized in the process | |
CN104956782A (zh) | 集成电路模块 | |
CN103887292B (zh) | 堆叠式双芯片封装结构及其制备方法 | |
CN101355070A (zh) | 多柱体的可堆叠半导体封装构造 | |
CN201725791U (zh) | 小外形集成电路封装结构的引线框及封装器件 | |
TW200605304A (en) | Flip-chip semiconductor package with lead frame and method for fabricating the same | |
CN100481407C (zh) | 晶片上引脚球格阵列封装构造 | |
CN102832190B (zh) | 一种倒装芯片的半导体器件及制造方法 | |
KR100507131B1 (ko) | 엠씨엠 볼 그리드 어레이 패키지 형성 방법 | |
CN217444382U (zh) | 半导体封装框架及结构 | |
CN219269207U (zh) | 一种焊点高度可控触点阵列封装结构 | |
TWI394247B (zh) | 免用焊料之金屬柱晶片連接構造與方法 | |
JP2004111695A (ja) | 半導体装置及びその製造方法 | |
JP2006041224A (ja) | 電子装置および電子装置の実装構造 | |
KR20060133800A (ko) | 칩 스택 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20081001 |