CN101276768A - 用于倒装芯片封装的组合倒置 - Google Patents

用于倒装芯片封装的组合倒置 Download PDF

Info

Publication number
CN101276768A
CN101276768A CNA2007101422513A CN200710142251A CN101276768A CN 101276768 A CN101276768 A CN 101276768A CN A2007101422513 A CNA2007101422513 A CN A2007101422513A CN 200710142251 A CN200710142251 A CN 200710142251A CN 101276768 A CN101276768 A CN 101276768A
Authority
CN
China
Prior art keywords
carrier
tube core
leadframe panel
panel
relevant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007101422513A
Other languages
English (en)
Inventor
A·波达
J·A·巴扬
A·S·普拉布
W·K·王
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of CN101276768A publication Critical patent/CN101276768A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

本发明涉及用于倒装芯片封装的组合倒置。本发明描述了用于封装集成电路的改进的方法和装置。更具体而言，描述了用于固定多个集成电路管芯到引线框面板的方法和装置。每个集成电路管芯包括具有多个焊料凸点的有源表面。所述引线框面板包括器件区域阵列，每个器件区域包括多个引线。所述方法包括将多个管芯放置到载体上指定的位置使得管芯的有源表面朝上。所述载体包括托架，该托架包括载体器件区域的相关阵列。引线框面板可以被放置在所述载体之上，使得所述管芯的有源表面上的焊料凸点与相关器件区域的相关引线相邻并接触。

Description

用于倒装芯片封装的组合倒置
技术领域
本发明一般涉及集成电路(IC)封装。更具体而言，描述了用于将管芯贴装到衬底的方法和装置。
背景技术
存在很多用于将集成电路(IC)管芯贴装到印刷电路板(PCB)或其他所需衬底上的常规方法。通常，管芯被封装成塑料或陶瓷封装。这种封装通常使用金属引线框。每个引线框一般包括与管芯上的相关I/O焊盘电连接的多个引线。所述引线框一般还包括相关的金属接触，用于将所述封装电连接到PCB上的接触。备选地，管芯本身可以直接连接到PCB上的接触。
可以被封装或直接连接到PCB的一种类型的管芯已知为倒装芯片类型的管芯。倒装芯片管芯一般具有在管芯有源表面上的接触焊盘上形成的焊料凸点。在从晶片切割之后，在封装或贴装到合适的衬底之前，管芯可以倒置也可以不倒置。在贴装过程中，焊料凸点直接连接到衬底上的接触焊盘。合适的衬底包括引线框、球栅阵列(BGA)和PCB。
尽管现有的倒装芯片封装方法和系统工作良好，但仍在继续努力以研发更有效的方法和系统。
发明内容
描述了一种将多个集成电路管芯固定到引线框面板的方法。每个集成电路管芯包括有源表面和背面。管芯的有源表面包括多个接触焊盘，所述接触焊盘具有其上形成的焊料凸点。所述方法包括放置多个管芯到载体上指定的位置，使得管芯的有源表面朝上避开所述载体。包括多个器件区域的引线框面板被放置在填充了管芯的载体上。使用这种布置，管芯有源表面上的焊料凸点邻近相关器件区域的相关引线放置并与之接触。在引线框面板被放置之后，焊料凸点被回流，以将管芯贴装到该引线框面板。使用这种布置，管芯上的接触焊盘可以机械地并电学地耦合到所述引线框面板的相关器件区域的引线。在回流之后，引线框面板和贴装的管芯可以从所述载体上分离。在一个优选实施例中，所述载体可以在贴装其他管芯中被再利用。
在另一实施例中，描述了适于在贴装集成电路管芯到引线框面板中使用的载体。所述引线框面板包括器件区域阵列，每个器件区域包括多个引线。所述载体包括托架，该托架包括相关载体器件区域的相关阵列。每个载体器件区域的尺寸被适当地设计以接收相关的集成电路管芯。更具体而言，当管芯被合适地放置在每个载体器件区域中且当引线框面板邻近所述载体被合适地放置时，引线框器件区域的引线与相关管芯上接触焊盘顶部的相关焊料凸点相邻并接触。
附图说明
为更好地理解本发明，在下面将结合附图进行详细描述，附图中：
图1示出了根据本发明一个实施例，用于贴装焊料凸点管芯的工艺的流程图；
图2A-2C示出了根据本发明一个实施例，适于在贴装倒装芯片管芯中使用的引线框面板的示意性顶视图。
图3A-3C示出了根据本发明一个实施例，适于在贴装倒装芯片管芯中使用的载体的示意性顶视图。
图4A-4D示出了根据本发明一个实施例，图1中工艺过程的不同阶段的示意性侧视图。
图5A-5B示出了根据本发明另一实施例，适于在贴装倒装芯片管芯中使用的载体的示意性顶视图和侧视图。
图6A-6D示出了根据本发明另一实施例，图1中工艺过程的不同阶段的示意性侧视图。
贯穿附图，相同的参考数字表示相应的部分。
具体实施方式
本发明一般涉及集成电路(IC)封装。更具体而言，描述了用于贴装多个管芯到衬底的方法和装置。
在下面的描述中，提出了很多特定细节以提供对本发明的彻底理解。然而对于本领域技术人员来说，很明显，可以在不具备这些部分或全部特定细节的条件下实行本发明。在其他实例中，并没有具体地描述已知的工艺步骤以避免混淆本发明。
下面的描述集中于使用引线框以引线上倒装芯片(FCOL)封装形式来封装倒装芯片形式的管芯。然而，可以预期，本发明可以有利地在将各种管芯封装成各种封装配置中实行，在所述封装配置中，管芯上的焊料凸点直接电连接到衬底上的金属接触。
将参考图1-6描述本发明的各个实施例。本发明的方案提供了使用常规贴片机封装倒装芯片管芯的方法和装置。更具体而言，描述了使用并不配置为用作倒装芯片贴片机的贴片机，用于拾取和放置倒装芯片管芯到合适衬底上的方法和装置。
一般而言，倒装芯片贴片机明显比常规(非倒装芯片)贴片机更昂贵。举例来说，倒装芯片贴片机目前可能花费约高达$500,000，而相比而言，常规贴片机大体为$150,000～$200,000。而且，常规贴片机一般比倒装芯片贴片机明显更快。举例来说，常规贴片机可以每小时贴装高达10,000～15,000个管芯。相反，倒装芯片贴片机每小时能够贴装小于4,000个管芯。不过，倒装芯片贴片机确实提供诸如处理高管脚数器件的能力之类的优点。然而，这些高管脚数能力对于很多应用并不需要。更具体而言，很多应用，例如适合用在微型表面安装器件(SMD)中的使用管芯的那些应用需要很少的管脚数。由此希望调整封装工艺，使得高速常规贴片机可用于贴装倒装芯片管芯到衬底。
首先参考图1，然后进一步参考图2-4的视图，将描述根据本发明的一个实施例，贴装倒装芯片集成电路管芯到衬底的工艺100。所述方法有助于多个管芯到衬底的相关器件区域的同时大批量放置，用于后续的贴装。具体而言，多个管芯首先被放置到暂时的载体上。然后衬底被放置到该载体和管芯上，使得每个管芯与衬底的相关器件区域相邻。
在一个优选实施例中，所述衬底是引线框面板。在所述实施例中，所述引线框面板是引线框条的形式。图2A示出了以条形形式布置的引线框面板200的示意性顶视图。引线框面板200被配置为具有器件区域的很多二维阵列202的金属结构。如接下来更详细的图2B-C所示，每个二维阵列202包括多个器件区域204，每个器件区域都被配置用于单个IC封装，且每个器件区域都通过精细连接杆(fine tie bar)206相连。每个器件区域204包括多个引线208，每个引线都在一端被连接杆206支撑。每个引线208包括在引线末端处的接触区域210。
在其他实施例中，衬底可以是适于用在球栅阵列(BGA)或平面栅格阵列(LGA)封装中的衬底。
工艺100从102以放置单独的焊料凸点管芯402到载体300上开始。图4A示出填充了管芯402的载体300的剖面的侧视图。在一个优选实施例中，使用常规贴片机，每个管芯402被放置到载体300上。更具体而言，在管芯被放置到载体300上之前，并不像倒装芯片贴片机所做的那样，该贴片机不倒置每个管芯402。在所示实施例中，管芯402被放置到载体300上，使得管芯的有源表面向上而避开载体。在所示实施例中，每一个管芯还包括管芯有源表面上的多个焊球、接触或焊料凸点404，所述管芯意在被直接安装到引线框面板200的接触区域210上。焊料凸点404可以直接在管芯的I/O焊盘上形成，或者使用常规再分布技术再分布到备选接触焊盘。此外，可以在使焊料凸起以产生焊料凸点404之前，在管芯402的接触焊盘上形成凸点下金属化堆栈(UBM)。
假设载体300具有各式各样的结构形式和配置。优选地，载体300由金属框构造。举例来说，载体300可以由类似于用在构造金属引线框中使用的铜或铜合金制成。图3A示出了以条形形式布置的载体300的一个实施例。图3B-3C随后示出了图3A中所示的载体300更详细的视图。
在所示实施例中，载体300包括很多二维阵列302。每个阵列302包括多个管芯保持腔304。每个管芯保持腔304被配置以接收单个管芯402。举例来说，每个保持腔可以是载体中的凹陷区域。备选地，每个腔304可以是完全穿透所述载体延伸的通孔。优选地，二维阵列302对应于相关引线框面板200的相关二维阵列202。此外，每个管芯保持腔304优选地对应于相关引线框面板200上的相关器件区域204。更具体而言，配置载体300使得当相关引线框面板200被反转并放置到填充的载体顶部时，引线框面板上的器件区域204与载体上的管芯402直接相邻放置。
在一些实施例中，每个管芯402通过放置到腔的底面306上的液体薄膜被“保持”在其相关腔304中。液体薄膜的表面张力帮助管芯402保持在腔304中适当的位置。所述薄膜可以由任意合适的液体形成。优选的液体将具有低的粘性且将在回流过程中蒸发而没有任何残留物。举例来说，水溶助焊剂工作良好。在一个备选实施例中，每个腔304可以包括腔底面上的入口。每个入口可以经由真空线耦合到真空源。这样，管芯402可以通过真空被固定在腔304中。
在一些实施例中，胶带被固定到载体300的背面。该胶带在其中每个腔304包括足够大的通孔以接收相关管芯的实施例中极其有用。这样，在载体中该胶带支撑了管芯403。附加地，管芯402的背面可以粘合到该胶带，以在引线框面板被放置在载体300上时保持所述管芯在适当的位置。
一般地，在104，助焊剂被应用到衬底上的接触区域210和/或焊料凸点404。在某些实施例中，载体300和贴装的管芯402被倒置并浸润在助焊剂的容器中以将助焊剂施加到管芯上的焊料凸点404。在另一实施例中，引线框面板200上的接触区域210使用助焊剂制备。助熔接触区域210可以使用压印传递(stamp transfer)法完成，该方法类似于很多常规贴片机在常规贴片过程中应用环氧树脂所使用的方法。在该实施例中，包括单个管脚或多个管脚的装置可以用于输送助焊剂到引线框面板200上的每个接触区域210。更具体而言，管脚或多个管脚的端头可以浸润到助焊剂容器中。然后，管脚或多个管脚可以被压印到引线框面板200的接触区域210上，由此传递了助焊剂到(多个)接触区域。在优选实施例中，管脚“床”可用于同时输送助焊剂到每个引线框接触区域210。在该“组合助熔”方法中，管脚床被浸润到助焊剂容器中。布置所述管脚床，使得当被压印到引线框面板200上时，每个管脚向相关的接触区域210同时施加助焊剂。
接着，在106，引线框面板200放置在载体300上，如图4B所示。在某些实施例中，这可能需要反转引线框面板200。在所示实施例中，引线框面板200包括贴装到引线框面板的背部底面与载体300相对的胶带406。举例来说，胶带406一般是高温带，例如聚酰亚胺带，适于在引线框面板的封装过程中使用。引线框面板200被直接放置在管芯402上。更具体而言，引线框面板200被直接设置在载体300支撑的管芯402有源表面上的焊料凸点404上。尽管在图4B中所示的特定剖面中没有明显地示出，但应当理解引线框面板200的器件区域204中的引线被连接杆206支撑。
如本领域中公知的，引线框面板条200通常包括位于面板侧面上的支撑轨中的对准孔212。对准孔212一般用于在封装引线框面板和管芯402的过程中使引线框面板200对准于具有相关对准管脚的模具。在一个优选实施例中，载体300还包括对应于引线框面板200中相关对准孔212的对准管脚306。以这种方式，引线框面板200可以相对于载体300精确地放置。
在引线框面板200处于载体300上之后，在步骤108，载体、管芯402和引线框面板一般被放置在回流炉中用于焊料凸点404的回流。在所示实施例中，在将引线框面板200设置在载体300上之前，在管脚306上放置垫片。举例来说，所述垫片可以是放置在管脚306之上或环绕管脚306的环形垫片。所述垫片可以有利地用于回流过程当焊料凸点熔化时控制焊料凸点404的塌陷。更具体而言，焊料凸点404回流过程中，焊料凸点将熔化并在引线框面板200的重力下倒塌。然而，当在载体300和引线框面板200之间使用垫片时，引线框面板将塌向所述垫片。这样，可以选择垫片的厚度以获得管芯402和引线框面板200之间的精确受控的平衡高度。而且，应当意识到垫片有利于跨越每个单独器件区域204以及跨越整个引线框面板200的均匀生成的平衡高度。
在回流工艺中，在其中液体用于将管芯402保持在腔304中适当位置的实施例中，液体薄膜蒸发。在其中真空用于固定管芯402的实施例中，在回流之前所述真空可以从载体300去耦。在将引线框面板200放置到管芯402上以后，引线框面板本身的重量足以保持管芯在适当的位置。
在回流之后，如图4C所示，管芯402经由焊料凸点404机械地并电连接到引线框面板200。应当意识到放置在管脚306上的垫片可用于控制回流过程中焊料凸点404的塌陷，这样允许控制生成的平衡高度。在110，如图4D所示，引线框面板200和贴装的管芯402从载体300分离。在一个优选实施例中，载体300然后可以在贴装另外很多管芯到另一引线框面板中再利用。在其中胶带被粘合到载体300背面的实施例中，所述胶带被去除并替代。在112，在从载体分裂之后，使用塑封材料，填充的引线框面板200可以放置在模具中用于封装。优选地，整个填充的引线框面板200被基本同时封装。接着，在114，封装的引线框面板然后可以被切割，以提供多个单独的IC封装。一般而言，在116，单独的IC封装然后被测试。
在一个备选实施例中，参考图5-6，描述了同样由金属框构造的载体500。图5A示出了载体500的顶视图，而图5B示出了载体的侧视图。然而，并不包括多个腔304，载体500包括多个大的剪切区域502。在一个优选实施例中，载体500包括用于相关引线框面板200的器件区域的每个二维阵列202的剪切区域502。每个剪切区域502优选地在几何上类似并可以稍大于相关二维阵列202。一层带504被粘合到载体500的背面以至少覆盖每个剪切区域502。在该实施例中，不是将管芯402放置在相关腔304中，管芯被直接放置在带504上，如图6A所示。以这种方式，管芯402的背面变得粘合到带504，消除用于固定管芯到载体500的真空或液体的需要。接着，如前所述，引线框面板200被放置在管芯402和载体500上，如图6B所示。同样，载体500可以包括对应于引线框面板200中相关对准孔212的管脚506。载体500、管芯402以及引线框面板200然后可以被放置在回流炉中。应当注意，带504优选地是能够承受回流过程中经历的高温的高温带。举例来说，可以使用高温聚酰亚胺带。
在一个实施例中，在回流过程中管芯402保持粘合到带504。在回流过后，如图6C所示，管芯402经由焊料凸点404被机械地和电连接到引线框面板200。同样，应当意识到，放置在管脚506上的垫片可用于控制回流过程中焊料凸点404的塌陷，由此允许控制生成的平衡高度。如图6D所示，引线框面板200和贴装的管芯402可以从载体500分离。一旦分离，新的一层带504可以粘合到载体500的背面。接着，载体500可以在贴装很多新的管芯402到新引线框面板200中使用。应当意识到，由于载体500的开放属性和带504的使用，载体500可用于贴装管芯402到各种引线框配置。
应当意识到，使用常规贴片机，所述方法以及载体300和500可以用在贴装焊料凸点管芯到各种衬底中。而且，应当意识到，所述方法允许与常规贴片机基本完全的集成。
用于解释目的，前面的描述使用了特定的术语以彻底理解本发明。然而，对于本领域技术人员而言，很明显，并不需要这些特定细节也可实施本发明。这样，本发明特定实施例的前述描述用于说明和描述目的。它们并不是穷举地，或它们并不意在将本发明限制为所公开的精确形式。对于本领域技术人员而言，很明显，考虑到上面的教导，可以进行很多修改和变化。
选择和描述了实施例以最好地理解本发明原理和它的实际应用，从而使本领域技术人员能够最好地利用本发明以及针对预期的特定用途而做出各种改进的实施例。意图在于，本发明的范围由下面的权利要求和它们的等效表述限定。

Claims (20)

1.一种固定多个集成电路管芯到引线框面板的方法，每个集成电路管芯包括有源表面和背面，所述有源表面具有多个接触焊盘，所述接触焊盘具有其上形成的焊料凸点，所述方法包括：
a)将多个管芯放置到载体上指定的位置，其中所述管芯的有源表面避开所述载体；
b)使引线框面板与所述载体邻近放置，该引线框面板包括多个器件区域，每个器件区域包括多个引线且每个器件区域对应于位于所述载体上的相关管芯，其中所述管芯的有源表面上的焊料凸点与相关器件区域的相关引线相邻并接触；和
c)回流所述焊料以固定所述管芯到所述引线框面板。
2.如权利要求1中所述的方法，进一步包括：d)在焊料固化之后，从所述载体分离所述引线框面板和贴装的管芯。
3.如权利要求2中所述的方法，进一步包括：
当使用新的管芯和引线框面板重复步骤(a)-(d)时，再利用所述载体以使用集成电路器件填充附加的引线框面板。
4.如权利要求2或3中所述的方法，进一步包括封装所述引线框面板部分和贴装的管芯以及切割封装的引线框面板部分以产生多个单独的集成电路封装。
5.如前面权利要求中任一项所述的方法，其中所述载体上每个指定的位置包括尺寸经过适当设计的凹陷的腔，以接收相关的管芯，每个腔的底面具有布置在其上的液体薄膜，所述方法进一步包括使用来自于液体薄膜的表面张力来保持所述管芯在它们相关腔中合适的位置。
6.如权利要求1-4中任一项所述的方法，其中所述载体上每个指定的位置包括与每个指定的位置相连的真空源，所述方法进一步包括使用所述真空源来适当地保持所述管芯在它们相关的位置。
7.如权利要求1-4中任一项所述的方法，其中所述载体上每个指定的位置包括粘合到所述载体的胶带，所述方法进一步包括粘合管芯的背面到所述胶带。
8.如前面权利要求中任一项所述的方法，其中在回流之前，所述引线框面板的器件区域并不物理地接触所述载体。
9.一种适于在贴装集成电路管芯到引线框面板中使用的载体，该引线框面板包括器件区域阵列，每个器件区域包括多个引线，该载体包括：
托架，该托架包括相关载体器件区域的相关阵列，每个载体器件区域的尺寸被合适地设计以接收相关的集成电路管芯，
其中当管芯被合适地放置在每个载体器件区域中且当引线框面板邻近载体被合适地放置时，引线框器件区域的引线与相关管芯上的接触焊盘的顶部上的相关焊料凸点相邻并接触。
10.如权利要求9中所述的载体，进一步包括多个对准管脚，所述对准管脚外围环绕所述托架放置并对应于相关引线框面板中的对准孔，其中当所述引线框面板被放置在所述载体上时，载体的管脚穿过引线框面板的孔，由此使所述引线框面板对准于所述载体。
11.如权利要求10中所述的载体，进一步包括放置在所述载体管脚之上并环绕所述载体管脚的多个垫片。
12.如权利要求9-11中任一项所述的载体，其中每个载体器件区域包括尺寸经过适当设计的凹陷的腔以接收相关的管芯。
13.如权利要求12中所述的载体，进一步包括与每个腔互连的真空源，以助于保持所述管芯在它们相关的腔中合适的位置。
14.如权利要求12中所述的载体，进一步包括沉积在所述腔的底面上的液体薄膜，其中每个管芯通过来自于所述液体薄膜的表面张力被保持在每个腔中合适的位置。
15.如权利要求12中所述的载体，其中每个载体器件区域包括尺寸经过适当设计的通孔以接收相关的管芯，所述载体进一步包括粘合到用作管芯支撑表面的托架背面的胶带。
16.如权利要求9-15中任一项所述的载体，其中所述托架的印迹基本与相关引线框面板的印迹相同，且其中所述托架基本由金属或金属合金形成。
17.一种适于在贴装集成电路管芯到引线框面板中使用的载体，该引线框面板包括器件区域阵列，引线框面板中的每个器件区域包括多个引线，该载体包括：
具有通孔的托架，所述通孔的尺寸经过合适地设计以接收多个管芯；
胶带，粘合到用作多个管芯支撑表面的托架背面，
其中多个管芯可以被放置在阵列形式的通孔中，使得管芯的背面粘合到所述带，以使用管芯填充所述载体；以及
其中当引线框面板邻近填充的载体被合适地放置时，所述引线框器件区域的引线与它们相关管芯上的相关焊料凸点相邻并接触。
18.如权利要求17中所述的载体，其中所述托架的印迹基本与相关引线框面板的印迹相同，且其中所述托架基本由金属或金属合金形成。
19.如权利要求17或18中所述的载体，进一步包括多个对准管脚，所述对准管脚外围环绕所述托架放置并对应于相关引线框面板中的对准孔，其中当所述引线框面板被放置在所述载体上时，所述载体的管脚穿过所述引线框面板的孔，由此使所述引线框面板对准于所述载体。
20.权利要求19中所述的载体，进一步包括放置在所述载体管脚上并环绕所述载体管脚的多个垫片。
CNA2007101422513A 2007-03-26 2007-08-31 用于倒装芯片封装的组合倒置 Pending CN101276768A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/691428 2007-03-26
US11/691,428 US20080241991A1 (en) 2007-03-26 2007-03-26 Gang flipping for flip-chip packaging

Publications (1)

Publication Number Publication Date
CN101276768A true CN101276768A (zh) 2008-10-01

Family

ID=39795124

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007101422513A Pending CN101276768A (zh) 2007-03-26 2007-08-31 用于倒装芯片封装的组合倒置

Country Status (3)

Country Link
US (1) US20080241991A1 (zh)
KR (1) KR20080087627A (zh)
CN (1) CN101276768A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102800600A (zh) * 2011-05-27 2012-11-28 台湾积体电路制造股份有限公司 用于半导体封装的封装夹具及工艺
CN101964335B (zh) * 2009-07-23 2013-04-24 日月光半导体制造股份有限公司 封装件及其制造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7749809B2 (en) * 2007-12-17 2010-07-06 National Semiconductor Corporation Methods and systems for packaging integrated circuits
US8048781B2 (en) * 2008-01-24 2011-11-01 National Semiconductor Corporation Methods and systems for packaging integrated circuits
KR101131351B1 (ko) 2009-10-06 2012-04-04 삼성전기주식회사 기판 스트립
US8541886B2 (en) * 2010-03-09 2013-09-24 Stats Chippac Ltd. Integrated circuit packaging system with via and method of manufacture thereof
CN111696928B (zh) 2019-03-15 2022-10-28 富泰华工业（深圳）有限公司 半导体封装结构及其制造方法
TWI689052B (zh) * 2019-03-15 2020-03-21 鴻海精密工業股份有限公司 半導體封裝結構及其製造方法

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3739463A (en) * 1971-10-18 1973-06-19 Gen Electric Method for lead attachment to pellets mounted in wafer alignment
US3722072A (en) * 1971-11-15 1973-03-27 Signetics Corp Alignment and bonding method for semiconductor components
US3859723A (en) * 1973-11-05 1975-01-14 Microsystems Int Ltd Bonding method for multiple chip arrays
US3937386A (en) * 1973-11-09 1976-02-10 General Motors Corporation Flip chip cartridge loader
US3887996A (en) * 1974-05-01 1975-06-10 Gen Motors Corp iconductor loading apparatus for bonding
US3918146A (en) * 1974-08-30 1975-11-11 Gen Motors Corp Magnetic semiconductor device bonding apparatus with vacuum-biased probes
US4551912A (en) * 1983-06-30 1985-11-12 International Business Machines Corporation Highly integrated universal tape bonding
US4607779A (en) * 1983-08-11 1986-08-26 National Semiconductor Corporation Non-impact thermocompression gang bonding method
JPH0793517B2 (ja) * 1986-11-20 1995-10-09 松下電器産業株式会社 電子部品の装着方法
US4980219A (en) * 1988-04-06 1990-12-25 Casio Computer Co., Ltd. Carrier tape for bonding IC devices and method of using the same
US4891817A (en) * 1988-06-13 1990-01-02 Eastman Kodak Company Pulsed dye laser apparatus for high PRF operation
US4941255A (en) * 1989-11-15 1990-07-17 Eastman Kodak Company Method for precision multichip assembly
IT1242420B (it) * 1990-09-03 1994-03-04 Ri Co Srl Metodo di montaggio per l'applicazione di componenti elettronici su circuiti stampati flessibili.
US5297333A (en) * 1991-09-24 1994-03-29 Nec Corporation Packaging method for flip-chip type semiconductor device
US6165819A (en) * 1992-10-20 2000-12-26 Fujitsu Limited Semiconductor device, method of producing semiconductor device and semiconductor device mounting structure
US5817540A (en) * 1996-09-20 1998-10-06 Micron Technology, Inc. Method of fabricating flip-chip on leads devices and resulting assemblies
KR100272737B1 (ko) * 1998-01-09 2001-01-15 윤종용 릴인쇄회로기판및그를이용한칩온보드패키지
US7169643B1 (en) * 1998-12-28 2007-01-30 Seiko Epson Corporation Semiconductor device, method of fabricating the same, circuit board, and electronic apparatus
US6378758B1 (en) * 1999-01-19 2002-04-30 Tessera, Inc. Conductive leads with non-wettable surfaces
JP3828673B2 (ja) * 1999-02-23 2006-10-04 ローム株式会社 半導体装置
US6204092B1 (en) * 1999-04-13 2001-03-20 Lucent Technologies, Inc. Apparatus and method for transferring semiconductor die to a carrier
WO2001068304A2 (en) * 2000-03-10 2001-09-20 Chippac, Inc. Flip chip-in-leadframe package and process
KR100583494B1 (ko) * 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지
JP4239352B2 (ja) * 2000-03-28 2009-03-18 株式会社日立製作所 電子装置の製造方法
US6461881B1 (en) * 2000-06-08 2002-10-08 Micron Technology, Inc. Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
US6872596B2 (en) * 2000-09-21 2005-03-29 Rohwedder Microtech Gmbh & Co. Kg Method of transferring semiconductor chips
JP2002096974A (ja) * 2000-09-22 2002-04-02 Oki Electric Ind Co Ltd 搬送用リールとそれを用いた搬送方法、及び電子装置の製造方法
GB2368386A (en) * 2000-10-23 2002-05-01 Alstom Power Nv Gas turbine engine combustion system
US6689640B1 (en) * 2000-10-26 2004-02-10 National Semiconductor Corporation Chip scale pin array
US6580165B1 (en) * 2000-11-16 2003-06-17 Fairchild Semiconductor Corporation Flip chip with solder pre-plated leadframe including locating holes
US6507120B2 (en) * 2000-12-22 2003-01-14 Siliconware Precision Industries Co., Ltd. Flip chip type quad flat non-leaded package
KR100393448B1 (ko) * 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US6597059B1 (en) * 2001-04-04 2003-07-22 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package
US6482680B1 (en) * 2001-07-20 2002-11-19 Carsem Semiconductor Sdn, Bhd. Flip-chip on lead frame
US6577012B1 (en) * 2001-08-13 2003-06-10 Amkor Technology, Inc. Laser defined pads for flip chip on leadframe package
US6593545B1 (en) * 2001-08-13 2003-07-15 Amkor Technology, Inc. Laser defined pads for flip chip on leadframe package fabrication method
US6661087B2 (en) * 2001-10-09 2003-12-09 Siliconware Precision Industries Co., Ltd. Lead frame and flip chip semiconductor package with the same
US6628000B1 (en) * 2001-11-19 2003-09-30 National Semiconductor Corporation Techniques for maintaining parallelism between optical and chip sub-assemblies
KR100476591B1 (ko) * 2002-08-26 2005-03-18 삼성전자주식회사 웨이퍼 테이블과, 이를 이용한 웨이퍼 쏘잉/소자 접착장치와, 웨이퍼 쏘잉/소자 분류 장치
US6943434B2 (en) * 2002-10-03 2005-09-13 Fairchild Semiconductor Corporation Method for maintaining solder thickness in flipchip attach packaging processes
US6982190B2 (en) * 2003-03-25 2006-01-03 Id Solutions, Inc. Chip attachment in an RFID tag
JP4057589B2 (ja) * 2003-03-25 2008-03-05 富士通株式会社 電子部品搭載基板の製造方法
US6953711B2 (en) * 2003-08-11 2005-10-11 Carsem (M) Sdn. Bhd. Flip chip on lead frame
US6867072B1 (en) * 2004-01-07 2005-03-15 Freescale Semiconductor, Inc. Flipchip QFN package and method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101964335B (zh) * 2009-07-23 2013-04-24 日月光半导体制造股份有限公司 封装件及其制造方法
CN102800600A (zh) * 2011-05-27 2012-11-28 台湾积体电路制造股份有限公司 用于半导体封装的封装夹具及工艺
CN102800600B (zh) * 2011-05-27 2015-12-09 台湾积体电路制造股份有限公司 用于半导体封装的封装夹具及工艺

Also Published As

Publication number Publication date
KR20080087627A (ko) 2008-10-01
US20080241991A1 (en) 2008-10-02

Similar Documents

Publication Publication Date Title
US7087460B2 (en) Methods for assembly and packaging of flip chip configured dice with interposer
CN101276768A (zh) 用于倒装芯片封装的组合倒置
US7091592B2 (en) Stacked package for electronic elements and packaging method thereof
JP5383024B2 (ja) 多層半導体パッケージ
US7161237B2 (en) Flip chip packaging using recessed interposer terminals
CN101276781B (zh) 用于ic封装的组合倒置
KR20100133920A (ko) 재배치된 집적회로 패키지 스태킹 시스템 및 그 제조 방법
KR20130115073A (ko) 역 스터드 범프 관통 비아 상호 연결부를 갖는 패키지 온 패키지 디바이스를 위한 방법 및 장치
CN102456677A (zh) 球栅阵列封装结构及其制造方法
US8106496B2 (en) Semiconductor packaging system with stacking and method of manufacturing thereof
US8766453B2 (en) Packaged integrated circuit having large solder pads and method for forming
US8389330B2 (en) Integrated circuit package system with package stand-off and method of manufacture thereof
US8434664B2 (en) Micro-ball loading device and loading method
US6455941B1 (en) Chip scale package
JP2010010269A (ja) 半導体装置、半導体装置製造用中間体およびそれらの製造方法
EP1732127B1 (en) Method for bonding and device manufactured according to such method
US20080290509A1 (en) Chip Scale Package and Method of Assembling the Same
KR100800140B1 (ko) 패키지 스택
TWI236748B (en) Flip chip on lead package and process thereof
CN114843249A (zh) 一种晶圆级封装多芯片模组及其形成方法
TW409380B (en) Integrated circuit package with uncut chip and its manufacture method
WO2008097964A1 (en) Micro-ball loading device and loading method
JP2002016093A (ja) 半導体装置の製造方法
KR20060136157A (ko) 패키지 스택
JP2011044478A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
AD01 Patent right deemed abandoned

Effective date of abandoning: 20081001

C20 Patent right or utility model deemed to be abandoned or is abandoned