CN101261945A - 半导体结构的制造方法 - Google Patents

半导体结构的制造方法 Download PDF

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CN101261945A
CN101261945A CNA200710181638XA CN200710181638A CN101261945A CN 101261945 A CN101261945 A CN 101261945A CN A200710181638X A CNA200710181638X A CN A200710181638XA CN 200710181638 A CN200710181638 A CN 200710181638A CN 101261945 A CN101261945 A CN 101261945A
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semiconductor chip
identification circuit
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许昭顺
刘潮权
赵智杰
彭迈杉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明揭示一种半导体结构的制造方法。形成第一半导体芯片及与其相同的第二半导体芯片，其中第一及第二半导体芯片各包括：识别电路以及多个输入/输出导电路径。输入/输出导电路径连接至第一及第二半导体芯片单独的存储器电路，其中输入/输出导电路径包括硅沟道。将第二半导体芯片的识别电路编程为不同于第一半导体芯片的识别电路的状态。将第二半导体芯片接合至第一半导体芯片上，其中第一及第二半导体芯片垂直对准，且第一半导体芯片中的每一输入/输出导电路径连接至第二半导体芯片中对应的输入/输出导电路径。无须制造超过一组具有不同设计的存储器芯片。制造设备及工艺以及测试皆得以简化。不仅降低成本，还可改善存货及周期时间。

Description

半导体结构的制造方法
技术领域
本发明涉及一种集成电路，特别是涉及一种用以形成叠层存储器芯片的制造及封装技术。
背景技术
由于集成电路的发明创作，使半导体工业因不同的电子部件(即，晶体管、二极管、电阻器、电容器等等)持续改善其集成度而不断地快速发展。大体而言，集成度的改善来自于不断地降低元件最小尺寸而容许更多的部件可以被整合至所提供的芯片面积中。
这些集成度的改善实质上是二维(2D)空间的改善，因为集成部件所占据的是半导体晶片的表面。虽然光刻工艺的显著进步对于2D集成电路的制作有着重要的改善，然而从2D空间所能获取的密度还是有其物理限制。而限制之一在于制作部件所需的最小尺寸。同样地，当更多的部件被放置于芯片时，需要更复杂的设计。
另一限制来自于当装置数量增加时，装置之间内连线(interconnection)的数量及长度也明显增加。当内连线的数量及长度增加时，电路的RC延迟及功率消耗也会增加。
为了解决上述限制因素，一般常使用三维集成电路(three-dimensionalintegrated circuit，3DIC)及叠层芯片(stacked dies)。而硅沟道(through-siliconvia，TSV)技术常使用于3DIC及叠层芯片中。图1示出公知具有叠层芯片的半导体封装，其中硅沟道4形成于芯片中。芯片10及12各包括半导体基底2，其上形成有集成电路(未示出)。硅沟道4穿过半导体基底2并连接至个别芯片中的集成电路以及接焊盘6。芯片10及12通过接焊盘6而接合在一起。再者，芯片10的接焊盘6用于将芯片10连接至凸块8，而进一步连接至封装基板14。
相较于公知的打线接合(wire bonding)技术，硅沟道技术对于多重芯片的连接更为有效。然而，当使用于叠层存储器芯片，硅沟道技术存在一些缺点。通常在形成存储器芯片的过程中，较佳为存货低、周期时间(cycle time)短、制造成本低(其意指最好只需一个掩模组)以及完全共用输入/输出焊盘(full sharing ofI/O pads)。因此，芯片10及12较佳为具有相同设计且可使用相同的掩模组来制造。
由于存储器芯片需要独一的地址以便于彼此辨别，因此相同的存储器芯片无法单纯地将一个芯片叠加于另一个芯片上。传统上，叠加芯片形成有重配线(redistribution line)。然而，此种方式仍需不同的掩模组来形成存储器芯片的重配线。另外，也有中介层(interposer)的设计方式。此种方式将不同的中介层装贴于芯片上来分辨相同的芯片，使存储器芯片与中介层的组合得以辨别。显然地，此种方式须有额外的成本来形成及装贴中介层。
因此，有必要寻求一种半导体结构及其制造方法，其具备叠层芯片的优势，同时尽可能地降低成本。
发明内容
有鉴于此，本发明的目的在于提供一种半导体结构及其制造方法，其无需采用重配线及中介层而具有叠加相同芯片的能力，进而显著地减少设计及制造成本、存货及周期时间。
本发明的一个方案提供一种半导体结构，包括：第一半导体芯片及相同于第一半导体芯片的第二半导体芯片。第一半导体芯片包括：第一识别电路及位于第一半导体芯片表面的多个第一输入/输出焊盘。第二半导体芯片包括：第二识别电路及位于第二半导体芯片表面的多个第二输入/输出焊盘。其中，第一及第二识别电路经编程而彼此不同。每一第一输入/输出焊盘垂直对准且连接于对应的第二输入/输出焊盘。第二半导体芯片垂直对准于第一半导体芯片且接合于其上。
又根据本发明另一个方案，提供一种半导体结构，包括：第一存储器芯片及第二存储器芯片。第一存储器芯片包括：第一识别电路，其包括至少一第一可编程元件；至少一第一芯片选择焊盘，位于第一存储器芯片的第一侧，其中第一芯片选择焊盘连接于第一可编程元件；至少一第二芯片选择焊盘，位于第一存储器芯片的第二侧，其相对于第一存储器芯片的第一侧，其中第二芯片选择焊盘垂直对准于第一芯片选择焊盘且通过硅沟道而与其电性连接；多个第一输入/输出焊盘，位于第一存储器芯片的第一侧；以及多个第二输入/输出焊盘，位于第一存储器芯片的第二侧，其中每一第二输入/输出焊盘垂直对准第一输入/输出焊盘且通过硅沟道而与其电性连接。第二存储器芯片相同于第一存储器芯片。第二存储器芯片包括：第二识别电路，其包括至少一第二可编程元件且与第一可编程元件具有不同的编程；至少一第三芯片选择焊盘，位于第二存储器芯片的第一侧，其中第三芯片选择焊盘连接于第二可编程元件；至少一第四芯片选择焊盘，位于第二存储器芯片的第二侧，其相对于第二存储器芯片的第一侧，其中第四芯片选择焊盘垂直对准于第三芯片选择焊盘且通过硅沟道而与其电性连接；多个第三输入/输出焊盘，位于第二存储器芯片的第一侧；以及多个第四输入/输出焊盘，位于第二存储器芯片的第二侧，其中每一第四输入/输出焊盘垂直对准第三输入/输出焊盘且通过硅沟道而与其电性连接，每一第四输入/输出焊盘物理接合于对应的第一输入/输出焊盘。
又根据本发明另一个方案，提供一种半导体结构的制造方法。形成第一半导体芯片及相同于第一半导体芯片的第二半导体芯片。第一及第二半导体芯片各包括：识别电路以及多个输入/输出导电路径。输入/输出导电路径连接至第一及第二半导体芯片单独的存储器电路，其中该多个输入/输出导电路径包括硅沟道。此方法还包括：将第二半导体芯片的识别电路编程为不同于第一半导体芯片的识别电路的状态以及将第二半导体芯片接合至第一半导体芯片上，其中第一及第二半导体芯片垂直对准，且第一半导体芯片中的每一输入/输出导电路径连接至该第二半导体芯片中对应的输入/输出导电路径。
如上所述的半导体结构的制造方法，其中每一输入/输出导电路径还包括第一及第二输入/输出焊盘，分别位于该第一及该第二半导体芯片的相对侧，且该第一及该第二输入/输出焊盘垂直对准。
如上所述的半导体结构的制造方法，还包括在同一晶片切割出该第一及该第二半导体芯片。
如上所述的半导体结构的制造方法，还包括对该第一及该第二半导体芯片的其中一个进行薄化。
如上所述的半导体结构的制造方法，还包括：提供相同于该第一及该第二半导体芯片的第三半导体芯片；将该第三半导体芯片的识别电路编程为不同于该第一及该第二半导体芯片的识别电路的状态；以及将该第三半导体芯片接合至该第二半导体芯片上。
如上所述的半导体结构的制造方法，其中该第二半导体芯片的该识别电路编程包括熔丝烧断。
如上所述的半导体装置的制造方法，还包括对该第一半导体的该识别电路进行编程。
又根据本发明另一个方案，提供一种半导体结构的制造方法。形成第一存储器芯片及相同于第一存储器芯片的第二存储器芯片，其中第一及第二存储器芯片各包括：识别电路以及多个导电路径。导电路径连接至存储器电路及识别电路，其中每一导电路径包括第一输入/输出焊盘及第二输入/输出焊盘，分别位于第一及第二存储器芯片的相对侧，且第一及第二输入/输出焊盘垂直对准。此方法还包括：对第一存储器芯片的识别电路进行编程、将第二存储器芯片的识别电路编程为不同于第一存储器芯片的识别电路的状态、以及通过将第二存储器芯片的第二输入/输出焊盘物理接合至第一存储器芯片的第一输入/输出焊盘，而将第二存储器芯片叠加于第一存储器芯片上，其中第一及第二存储器芯片垂直对准。
如上所述的半导体结构的制造方法，还包括施加芯片选择信号，以选择该第一及该第二存储器芯片的其中一个，其中该芯片选择信号施加于部分的该多个导电路径，其连接至该第一及该第二存储器芯片的识别电路。
如上所述的半导体结构的制造方法，还包括在施加该芯片选择信号时，读取或写入该第一及该第二存储器芯片的其中一个。
如上所述的半导体结构的制造方法，其中该第一及该第二存储器芯片的识别电路包括作为编程元件的熔丝，且该第一及该第二存储器芯片的识别电路的编程包括烧断所选择的熔丝。
如上所述的半导体结构的制造方法，其中该第一及该第二存储器芯片的识别电路包括作为编程元件的闪存单元，且该第一及该第二存储器芯片的识别电路的编程包括将数据写入所选择的闪存单元。
本发明的实施例具有许多特点。由于所叠加的芯片均相同，故无须制造超过一组具有不同设计的存储器芯片。制造的设备及工艺以及测试皆得以简化。此不仅仅降低成本，还可改善存货及周期时间。另外，不需在叠层芯片中形成不同的重配线。也不需要中介层。
附图说明
图1示出公知具有叠加芯片的结构示意图；
图2示出四个相同存储器芯片示意图；
图3示出用以辨别芯片的解码电路，其中解码电路包括与门(AND gate)；
图4示出具有不同编程的识别电路的四个相同的存储器芯片；以及
图5示出叠加相同存储器芯片的示意图。
其中，附图标记说明如下：
公知
2～半导体基底；              4～硅沟道；
6～接合焊盘；                8～凸块；
10、12～芯片；               14～封装基底。
实施例
100～基底；                  102～与门；
CE～芯片启动信号(芯片启动线)；
CS0、CS0_B、CS1、CS1_B～信号；
D1、D2、D3、D4～芯片；F1、F2、F3、F4～熔丝(可编程元件)；
ID～识别电路；        I1、I2、I3、I4～节点输入；
P1、P2、P3、P4、P1_B、P2_B、P3_B、P4_B～芯片选择焊盘；
PIO1、PIOn、PIO1_B、PIOn_B～输入/输出焊盘。
具体实施方式
以下提供许多不同的实施例用以说明本发明的制作及使用。然而，本发明提供许多可应用的发明概念，其可实施于广泛多样化的特定背景中。特定的实施例仅表示以特定的方式制作及使用本发明，并非用以局限本发明的范围。
以下的说明提供一种叠加四个存储器芯片的实施例，用以解释本发明的概念。请参照图2，其示出四个相同的芯片，标示为D1、D2、D3、及D4，其为一般所使用的存储器，例如静态随机存取存储器(static random accessmemory，SRAM)、动态随机存取存储器(dynamic random access memory，DRAM)、磁阻随机存取存储器(magnetoresitive random access memory，MRAM)等等。芯片D1、D2、D3、及D4可从包括多个相同的存储器芯片的同一半导体晶片所切割出，或是从不同半导体晶片所切割出。在本文中，虽然芯片D1、D2、D3、及D4等同于存储器芯片D1、D2、D3、及D4，然其也可为非存储器芯片。因此，本发明所揭示的可使用于叠加相同的非存储器芯片。
每一芯片D1、D2、D3、及D4包括基底100，其上具有集成电路(未示出)。多个输入/输出(I/O)焊盘PIO1至PIOn连接至集成电路。在实施例中，集成电路包括存储器电路。因此，I/O焊盘PIO1至PIOn中有一部分连接至地址线(未示出)而有一部分连接至数据线。较佳的是每一I/O焊盘PIO1至PIOn通过硅沟道(TSV)对应连接至位于具有I/O焊盘PIO1至PIOn的芯片的相对侧的I/O焊盘PIO1_B至PIOn_B。再者，每一I/O焊盘PIO1至PIOn垂直对准于所对应的I/O焊盘PIO1_B至PIOn_B。
每一芯片D1、D2、D3、及D4包括可编程(programmable)的识别(identification，ID)电路(标示为ID)，其包括一个或一个以上的可编程元件。在实施例中，可编程元件为熔丝(fuse)，例如为电子式熔丝或激光式熔丝，并标示为F1、F2、F3、及F4，如图2所示。在本文中，可编程元件等同于熔丝F1、F2、F3、及F4。然而，可以理解的是可编程元件也可为其他非挥发装置，例如闪存，用以在完成芯片制作后进行编程。通常闪存的制作成本高于电子式熔丝或激光式熔丝。然而，若芯片D1、D2、D3、及D4以闪存作为部分的存储器电路时，可编程元件则拥有不需额外制造成本的优势。每一可编程元件具有第一端连接至芯片选择焊盘，其位于芯片的一侧，其中连接至可编程元件F1、F2、F3、及F4的芯片选择焊盘分别标示为P1、P2、P3、及P4。而在芯片的相对侧，形成有芯片选择焊盘P1_B、P2_B、P3_B、及P4_B且分别通过硅沟道而与芯片选择焊盘P1、P2、P3、及P4连接。较佳的是芯片选择焊盘P1_B、P2_B、P3_B、及P4_B分别垂直对准于所连接的芯片选择焊盘P1、P2、P3、及P4。
可编程元件F1、F2、F3、及F4的第二端连接至解码电路，其中解码电路的范例示出于图3中。解码电路包括与门(AND gate)102，其中解码电路的输入I1、I2、I3、及I4连接至可编程元件且与门102的输出连接至芯片启动(chip-enable)线CE，用以启动及辨识每芯片。
在每一芯片的辨识电路中的可编程元件的编程不同于其他芯片的辨识电路中的可编程元件。表1列出芯片D1、D2、D3、及D4中每一芯片的可编程元件的状态，其中可编程元件为熔丝。字母“S”表示所对应的熔丝为短路或未烧断，而字母“O”表示所对应的熔丝为开路或是烧断。在芯片选择焊盘P1、P2、P3、及P4分别施加信号CS0、CS0_B、CS1、及CS1_B，其中字母“H”表示高电位，而字母“L”表示低电位。信号CS0_B与信号CS0具有相反的相位，而信号CS1与信号CS1_B具有相反的相位。因此，熔丝F1、F2、F3、及F4的状态组合成为对应的芯片的独一地址。信号CS0及CS1的状态为芯片启动信号CE输出高电位所需的电位。
表1
芯片1 芯片2 芯片3 芯片4
    F1 S S O O
    F2 O O S S
    F3 S O O S
    F4 O S S O
    CS0 H H L L
    CS1 H L L H
请参照图3，在施加不同的信号CS0、CS0_B、CS1、及CS1_B时，芯片D1、D2、D3、及D4的与门102的输出CE具有不同的状态。以芯片1中的识别电路作为范例说明，若熔丝F1为开路，则在节点输入I1为输入高电位，若熔丝F1为短路，则输入电位相同于信号CS0，然后当信号CS0及CS1的状态为高电位时，芯片1的芯片起动线CE处于高电位。芯片2、3、及4的芯片起动信号CE的状态也可通过输入的信号CS0及CS1来决定。在一个时间点，至多一个芯片通过输入的信号CS0及CS1而启动。
在可编程元件为闪存或其他类型时，解码电路被设计成依据储存于闪存的状态来输出芯片启动信号。
请参照图4，其示出在芯片D1、D2、D3、及D4中的可编程元件F1、F2、F3、及F4的状态，其中可编程元件F1、F2、F3、及F4依据表1进行编程。较佳为完成芯片制作之后进行芯片的编程，其中可在单独的芯片切割出芯片之前或之后进行该编程。在可编程元件为激光式熔丝或电子式熔丝时，通过激光或电流来烧断可编程元件。在可编程元件为闪存时，可编程元件所需的状态写入于闪存中。
请参照图5，芯片D1、D2、D3、及D4叠加在一起，对应的芯片选择焊盘P1_B、P2_B、P3_B、及P4_B分别接合至下方芯片的芯片选择焊盘P1、P2、P3、及P4。再者，I/O焊盘PIO1_B至PIOn_B分别接合至下方芯片的I/O焊盘PIO1至PIOn。在较佳的实施例为进行铜对铜的接合。因此单一芯片上的芯片选择焊盘P1、P2、P3、及P4的每一个连接至其他芯片所对应的芯片选择焊盘，且单一芯片上的I/O焊盘PIO1至PIOn的每一个连接至其他芯片所对应的I/O焊盘。
在此叠层结构中，即使芯片D1、D2、D3、及D4全都内连在一起，还是可通过芯片选择焊盘P1、P2、P3、及P4中施加不同的信号CS0、CS0_B、CS1、及CS1_B组合来进行区分。因此，每一芯片能够辨别I/O焊盘PIO1至PIOn上信号变换是否所指就是它本身。同样地，连接至叠层结构的外部电路也能够辨别施加于I/O焊盘的信号读取自哪一芯片的存储器。因此，通过施加芯片选择信号，任何的芯片D1、D2、D3、及D4可被读取或写入。
在上述实施例中，每一识别电路ID包括四个可编程元件，其具有叠加至16个芯片而无须变更设计的能力。本领域普通技术人员可以了解在辨识四个或以下的芯片时，每一芯片仅需两个可编程元件，其中(0，0)、(0，1)、(1，0)、(1，1)状态组合可使用于辨识四个芯片。若需叠加更多的芯片，可加入更多的可编程元件。若仅仅叠加两个芯片，可使用一个可编程元件，其中0及1状态(或熔丝的开路及短路状态)可用来辨识一个芯片。在上述情形中，编程操作可在叠加两个芯片之后进行，其中将上方芯片编程为不同于下方芯片的状态。
图5所示的堆叠结构为背靠前式(back-to-front)叠层，其中一个芯片的背侧贴附于另一个芯片的前侧。在其他的实施例中，也可使用背靠背式或前靠前式的设计。然而，此种设计中，芯片需具备对称结构，当芯片翻转时，相同I/O焊盘及芯片选择焊盘会位于相同的位置，使一个接合焊盘(例如：芯片选择焊盘及I/O焊盘)可连接至另一芯片相同种类的接焊盘。另外，一个或一个以上的叠层芯片可予以薄化。举例而言，芯片4的厚度可大于芯片1、2、及3。在此情形中，芯片4与芯片1、2、及3不同之处仅在于基底1 00的厚度(硅沟道的长度)及可编程元件的编程状态。因此，芯片4仍认定为相同于芯片1、2、及3。
在上述的实施例中，属芯片对芯片式的叠层。在其他实施例中，也可以是晶片对晶片式的叠层或是芯片对晶片式的叠层。在此情形中，晶片上方的芯片可先进行编程，之后再将芯片接合至其他晶片上。芯片D1、D2、D3、及D4的接合可使用焊锡凸块(solder bump)或是一般常用的手段。
本发明的实施例具有许多特点。由于所叠加的芯片均相同，故无须制造超过一组具有不同设计的存储器芯片。制造的设备及工艺以及测试皆得以简化。此不仅仅降低成本，还可改善存货及周期时间。另外，不需在叠层芯片中形成不同的重配线。也不需要中介层。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (12)

1.一种半导体结构的制造方法，包括：
形成第一半导体芯片及相同于该第一半导体芯片的第二半导体芯片，其中该第一及该第二半导体芯片各包括：
识别电路；以及
多个输入/输出导电路径，连接至该第一及该第二半导体芯片单独的存储器电路，其中该多个输入/输出导电路径包括硅沟道；
将该第二半导体芯片的该识别电路编程为不同于该第一半导体芯片的该识别电路的状态；以及
将该第二半导体芯片接合至该第一半导体芯片上，其中该第一及该第二半导体芯片垂直对准，且该第一半导体芯片中的每一输入/输出导电路径连接至该第二半导体芯片中对应的输入/输出导电路径。
2.如权利要求1所述的半导体结构的制造方法，其中每一输入/输出导电路径还包括第一及第二输入/输出焊盘，分别位于该第一及该第二半导体芯片的相对侧，且该第一及该第二输入/输出焊盘垂直对准。
3.如权利要求1所述的半导体结构的制造方法，还包括在同一晶片切割出该第一及该第二半导体芯片。
4.如权利要求1所述的半导体结构的制造方法，还包括对该第一及该第二半导体芯片的其中一个进行薄化。
5.如权利要求1所述的半导体结构的制造方法，还包括：
提供相同于该第一及该第二半导体芯片的第三半导体芯片；
将该第三半导体芯片的识别电路编程为不同于该第一及该第二半导体芯片的识别电路的状态；以及
将该第三半导体芯片接合至该第二半导体芯片上。
6.如权利要求1所述的半导体结构的制造方法，其中该第二半导体芯片的该识别电路编程包括熔丝烧断。
7.如权利要求1所述的半导体装置的制造方法，还包括对该第一半导体的该识别电路进行编程。
8.一种半导体结构的制造方法，包括：
形成第一存储器芯片及相同于该第一存储器芯片的第二存储器芯片，其中该第一及该第二存储器芯片各包括：
识别电路；以及
多个导电路径，连接至存储器电路及该识别电路，其中每一导电路径包括第一输入/输出焊盘及第二输入/输出焊盘，分别位于该第一及该第二存储器芯片的相对侧，且该第一及该第二输入/输出焊盘垂直对准；
对该第一存储器芯片的该识别电路进行编程；
将该第二存储器芯片的该识别电路编程为不同于该第一存储器芯片的该识别电路的状态；以及
通过将该第二存储器芯片的该第二输入/输出焊盘物理接合至该第一存储器芯片的该第一输入/输出焊盘，而将该第二存储器芯片叠加于该第一存储器芯片上，其中该第一及该第二存储器芯片垂直对准。
9.如权利要求8所述的半导体结构的制造方法，还包括施加芯片选择信号，以选择该第一及该第二存储器芯片的其中一个，其中该芯片选择信号施加于部分的该多个导电路径，其连接至该第一及该第二存储器芯片的该识别电路。
10.如权利要求9所述的半导体结构的制造方法，还包括在施加该芯片选择信号时，读取或写入该第一及该第二存储器芯片的其中一个。
11.如权利要求8所述的半导体结构的制造方法，其中该第一及该第二存储器芯片的识别电路包括作为编程元件的熔丝，且该第一及该第二存储器芯片的识别电路的编程包括烧断所选择的熔丝。
12.如权利要求8所述的半导体结构的制造方法，其中该第一及该第二存储器芯片的识别电路包括作为编程元件的闪存单元，且该第一及该第二存储器芯片的识别电路的编程包括将数据写入所选择的闪存单元。
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