CN101253628B - Two-terminal nanotube devices and systems and methods of making same - Google Patents

Two-terminal nanotube devices and systems and methods of making same Download PDF

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CN101253628B
CN101253628B CN2006800249395A CN200680024939A CN101253628B CN 101253628 B CN101253628 B CN 101253628B CN 2006800249395 A CN2006800249395 A CN 2006800249395A CN 200680024939 A CN200680024939 A CN 200680024939A CN 101253628 B CN101253628 B CN 101253628B
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nanotube
conducting
terminal
nanotube articles
articles
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CN101253628A (en
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F·郭
M·梅恩霍德
S·L·孔瑟科
T·鲁克斯
X·M·H·黄
R·斯瓦拉贾
M·斯特拉斯伯格
C·L·伯廷
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Nantero Inc
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Nantero Inc
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Abstract

A two terminal switching device includes first and second conductive terminals and a nanotube article. The nanotube article has at least a plurality of nanotubes, and is in a permanently direct physical contact with the first and second conductive terminals. The two terminal switching device also includes a stimulus circuit in electrical communication with at least one of the first and second terminals. The stimulus circuit is configured to form a first voltage difference between the first and the second conductive terminals, thereby changing a relative resistance of the nanotube article between the first and second terminals between a relatively high resistance and a relatively low resistance. The stimulus circuit is configured to form a second voltage difference between the first and the second conductive terminals, thereby changing the relative resistance of the nanotube article between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the two terminal switching device, and the relatively low resistance between the first and second terminals corresponds to a second state of the two terminal switching device. The first and the second states of the two terminal switching device are non-volatile.

Description

Two-terminal nanotube devices and system and preparation method thereof
The cross reference of related application
The present invention requires following priority of applying for according to 35 U.S.C. § 119 (e), and the content of these applications integral body by reference is incorporated into this:
The U.S. Provisional Patent Application No.60/679 that is entitled as " Reversible Nanoswitch (reversible nanotube switch) " that on May 9th, 2005 submitted to, 029;
The U.S. Provisional Patent Application No.60/692 that is entitled as " Reversible Nanoswitch (reversible nanotube switch) " that on June 22nd, 2005 submitted to, 891;
The U.S. Provisional Patent Application No.60/692 that is entitled as " NRAM Nonsuspended Reversible NanoswitchNanotube Array (the non-reversible nanotube switch nano-tube array that suspends of NRAM) " that on June 22nd, 2005 submitted to, 918; And
The U.S. Provisional Patent Application No.60/692 that is entitled as " Embedded CNT Switch Applications For Logic (embedding of the application of CNT switch) " that on June 22nd, 2005 submitted to logic, 765.
The application relates to following application, and the content of these applications integral body by reference is incorporated into this:
The U.S. Patent application No. (waiting to deliver (TBA)) that is entitled as " Memory Arrays Using Nanotube Articles WithReprogrammable Resistance (use has the memory array of the nanotube articles of re-programmable resistance) " that submits on the same day with the application; And
U.S. Patent application No. (waiting to deliver) with the application's being entitled as of submitting on the same day " Non-Volatile Shadow Latch Using A Nanotube Switch (using the non-volatile shadow latch of nanotube switch) ".
Background
Technical field
The present invention relates generally to the switching device field, relate in particular to and can be used for making non-volatile and two-terminal nanotube device other memory circuitry.
Association area is described
Digital Logical Circuits can be used for personal computer, the portable electric appts such as personal organizers and calculator, electronic amusement apparatus, and the control circuit that is used for household electrical appliance, telephone switching system, automobile, aircraft and other manufacturing commodity.Early stage Digital Logic is made up by the discrete switch element, and this switch element is made of independent bipolar transistor.By the invention of bipolar integrated circuit, a large amount of switch elements separately can be combined on the single silicon substrate to create complete Digital Logical Circuits, such as converter, NAND door, NOR door, trigger, adder etc.Yet, the capabilities limits of the heat that the density of bipolar digital integrated circuit produces when being subjected to its high power consumption and encapsulation technology dissipation circuit working.Make metal-oxide semiconductor (MOS) (" the MOS ") integrated circuit of field-effect transistors (" FET ") switch element greatly reduce the power consumption of Digital Logic, can be formed in the highdensity complex digital circuitry of using in the current techniques.The restriction of the heat that the density of MOS digital circuit and service speed produce when still being subjected to need to dissipate this device work.
Under the condition of high heat or extreme environment, can not correctly bring into play function by Digital Logic integrated circuit bipolar or that the MOS device makes up.Current digital integrated circuit is designed to work under less than 100 degrees centigrade temperature usually, and the circuit of working under 200 degrees centigrade the temperature surpassing is seldom arranged.In custom integrated circuit, the leakage current of the independent switch element in " pass " state increases fast with temperature.Along with leakage current increases, the working temperature of device rises, and increased by the power of circuitry consumes, and difference off status and the difficulty of opening state has reduced the reliability of circuit.Internal short-circuit also takes place in conventional Digital Logical Circuits in extreme environment, because they can be at the inner electric current that produces of semi-conducting material.Might make integrated circuit by particular device and insulation technology, make them when exposing to the open air in extreme environment, keep operating, but the expensive availability and the practicality that has limited them of these devices.In addition, this digital circuit presents timing difference with respect to their conventional homologue, thereby needs additional design verification to come to add protection to existing design.
Be bipolar or the integrated circuit that makes up of FET switch element all is a volatibility.They are only keeping its internal logic states when this device applies power.When power was removed, internal state was lost, unless will add this device to keep this logic state such as the Nonvolatile memory circuit inside or the outside of some type of EEPROM (EEPROM (Electrically Erasable Programmable Read Only Memo)).Even use nonvolatile memory to keep logic state, need adjunct circuit before losing power, logic state to be delivered to memory, and when the power of this device recovers, recover the state of indivedual logical circuits.The replacement solution that prevents information dropout in the volatibility digital circuit such as reserve battery also increases cost and complexity to digital Design.
The key character of logical circuit is low cost, high density, low-power and high-speed in the electronic equipment.Conventional logic solution is subject to silicon substrate, but the logical circuit that makes up on other substrate may allow logical device directly to be integrated in many manufacturing a product in single step, thereby further reduces cost.
Proposed to use nanoscale wire to form the intersection knot to serve as the device of memory cell such as Single Walled Carbon Nanotube.(with reference to WO 01/03208, " Nanoscopic Wire-Based Devices, Arrays, andMethods of Their Manufacture (based on device, array and the manufacture method thereof of nanoscale wire) "; And people such as Thomas Rueckes " Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing (the nonvolatile RAM that is used for molecular computing) " based on carbon nano-tube, Science (science), 289 volumes, the 94-97 page or leaf, on July 7th, 2000.) hereinafter these devices be called nanometer pipeline interleaved storage (NTWCM).In these were proposed, the independent single wall nano pipeline that is suspended on other line had defined memory cell.In a line or two lines, write the signal of telecommunication, make their physical attraction or repulsions each other.Each physical state (promptly attracting or the repulsion line) is corresponding to an electricity condition.Repelling line is the open circuit knot.Attracting line is the closure state that forms rectifying junction.When with electrical power when this knot is removed, these lines keep their physical states (and electrical state therefore), thereby form Nonvolatile memery unit.
The U.S. Patent No. 6 that is entitled as " Electromechanical Memory Array Using Nanotube Ribbons and Method forMaking Same (using electromechanical memory array of nanometer pipe racks and preparation method thereof) ", 919,592 disclose the electromechanical circuits such as memory cell, and wherein circuit comprises structure with conductive trace and the supporting of extending from substrate surface.Nanometer pipe racks or switch that can dynamo-electric distortion be suspended by the supporting of crossing over conductive trace.Each band comprises one or more nanotubes.These bands usually form from the tangled structure selective removal material of one deck nanotube or nanotube.
For example, as U.S. Patent No. 6,919, disclosed in 592, nanostructure (nanofabric) can be patterned to band, and these bands can be used as parts and create non-volatile dynamo-electric memory cell.Band can the dynamo-electric ground deflection in response to the electrostimulation of control trace and/or band.The deflection physical state of band can be represented corresponding information state.The physical state of deflection has nonvolatile features, means that this band remains on its physical state (and information state therefore), even remove power from memory cell.As be entitled as the U.S. Patent No. 6 of " Electromechanical Three-TraceJunction Devices (dynamo-electric three trace junction devices) ", 911, disclosed in 682, three trace frameworks can be used for dynamo-electric memory cell, and wherein two in the trace are the electrodes of control belt deflector.
Also proposed dynamo-electric bistable device is used for the digital information storage (with reference to the U.S. Patent No. 4 that is entitled as " NonvolatileMemory Device Including a Micro-Mechanical Storage Element (nonvolatile semiconductor memory member that comprises the micromechanics memory element) ", 979,149).
Based on the establishment of the bistable state of carbon nano-tube (comprise its individual layer make up) and metal electrode, nano-electromechanical switch and operation have with the common assignee of the present invention more describe U.S. Patent No. 6,784 in detail in patent application morning, 028,6,835,591,6,574,130,6,643,165,6,706,402,6,919,592,6,911,682 and 6,924,538; U.S. Patent application No.2005-0062035,2005-0035367,2005-0036365,2004-0181630; And U.S. Patent application No.10/341005,10/341055,10/341054,10/341130, the content of these patents integral body by reference is incorporated into this (hereinafter and above " references of institute's combination ").
General introduction
The invention provides and make the two-terminal nanotube switch, based on the memory cell array of these switches, based on the fuse/anti-fuse device of these switches and based on the structure and the method for the re-programmable distribution of these switches.
In one aspect, the two-terminal switch device comprise first conducting terminal and with isolated second conducting terminal of first conducting terminal.This device also comprises the nanotube articles with at least one nanotube.This nanotube articles be configured to described first and second conducting terminals all permanently direct physical contact.This device also comprise with first and second conducting terminals in the stimulation circuit of at least one electric connection.This stimulation circuit is configured to form first voltage difference between described first conducting terminal and second conducting terminal, thereby makes the resistance of the nanotube articles between described first and second conducting terminals change to relative high electrical resistance from relatively low resistance.This described stimulation circuit is configured to form second voltage difference between described first conducting terminal and second conducting terminal, thereby makes the resistance of the nanotube articles between described first and second conducting terminals change to relatively low resistance from relative high electrical resistance.Relative high electrical resistance between first and second conducting terminals is corresponding to first state of this device, and the relatively low resistance between first and second conducting terminals is corresponding to second state of this device.First and second states of this device can be non-volatile.The resistance of first state can be about ten times of resistance of second state at least.
In another aspect, nanotube articles is overlapping with at least a portion of controlled geometrical relationship and the first terminal.Controlled geometrical relationship can allow that electric current is relative between the first terminal and nanotube articles to flow preferably, and allows that heat is relative between the first terminal and nanotube articles to flow relatively poorly.Controlled geometrical relationship can be the overlapping of predetermined extent.In another aspect, at least one of first and second terminals has vertical orientated feature, and nanotube articles is complied with at least a portion of this vertical orientated feature basically.In another aspect, nanotube articles comprises the zone of the nano tube structure thing of definition orientation.
In another aspect, first electrostimulation is an erase operation.In another aspect, second electrostimulation is a programming operation.In another aspect, stimulation circuit can at least one apply the 3rd electrostimulation to determine the state of this device in first and second conducting terminals.The 3rd electrostimulation can be nondestructive read operation.
In another aspect, double-end storage spare comprise first conducting terminal and with first conducting terminal, second conducting terminal at interval.This device also comprises the nanotube articles with at least one nanotube.This nanotube articles be configured to first and second conducting terminals permanently direct physical contact.This device also comprise with first and second conducting terminals in the stimulation circuit of at least one electric connection.This stimulation circuit is configured between first and second conducting terminals to form first voltage difference, thereby makes and open one or more gaps between the one or more nanotubes and one or more conductor in the described device.The resistance of opening the nanotube articles between described first and second conducting terminals in one or more gaps becomes relative high electrical resistance from relatively low resistance.This stimulation circuit is configured to form second voltage difference between described first conducting terminal and second conducting terminal, thereby the one or more gaps in the closed described device between one or more nanotubes and the one or more conductor, and the closure in described one or more gaps makes the resistance of the nanotube articles between described first and second conducting terminals become relatively low resistance from relative high electrical resistance.Conductor in the device comprises one or more in first conducting terminal, second conducting terminal, nanotube and the nanotube fragment.Relative high electrical resistance between first and second conducting terminals is corresponding to first state of this device, and the relatively low resistance between first and second conducting terminals is corresponding to second state of this device.First and second states of this device can be non-volatile.
In another aspect, first electrostimulation was carried out heating to open one or more gaps at least a portion of nanotube articles.In another aspect, the one or more hot feature of this device is selected to the hot-fluid that flows out the nanotube element is minimized.The hot-fluid that flows out the nanotube element can be by minimizing with the controlled geometrical relationship aligned nanotubes goods and first conducting terminal, and wherein this geometrical relationship caloric restriction flows out and flows to first conducting terminal from nanotube articles.Controlled geometrical relationship can be the overlapping of predetermined extent.The hot-fluid that flows out the nanotube element can be by selecting conductive phase to good and the first conducting terminal material that heat conduction is relatively poor relatively minimizes.This material has higher relatively conductivity and relatively low thermal conductivity.
In another aspect, first electrostimulation is opened one or more gaps by forming the gap between one or more in the one or more nanotubes and first and second conducting terminals.In another aspect, first electrostimulation is opened one or more gaps by the one or more nanotubes in the electric network of nanotube are separated with one or more other nanotubes.In another aspect, first electrostimulation is opened one or more gaps by one or more nanotubes being broken into two or more nanotube fragments.In another aspect, first electrostimulation is opened one or more gaps by one or more phonon modes of one or more nanotubes in the excitation nano tubing products.One or more phonon modes can show as hot bottleneck.One or more phonon modes can be the optical phonon patterns.One or more nanotubes in the nanotube articles can be chosen to has specific radially breathing pattern (breathingmode) or defect mode by force.In another aspect, second electrostimulation is by attracting closed one or more gaps with one or more nanotubes to one or more conductors.Second electrostimulation can attract one or more nanotubes by generating electrostatic attraction to one or more conductors.
In another aspect, optional memory cell comprise have grid, the unit selecting transistor of source electrode and drain electrode, wherein one of grid and word line and bit line electrically contact, and another electrically contacts in drain electrode and word line and the bit line.This unit also comprises the two-terminal switch device, comprising first conducting terminal, second conducting terminal and have at least one nanotube and with first and second conducting terminals in each nanotube articles of contacting of direct physical for good and all.The source electrode of first conducting terminal and unit selecting transistor electrically contacts, and second conducting terminal and program/erase/read line electrically contact.This unit also comprises with word line, bit line and is used to carry out the storage operation circuit of the line electric connection of programing function, erase feature or read functions.The storage operation circuit can select signal to apply erase signal so that the device resistance between first and second conducting terminals is become relative high electrical resistance from relatively low resistance to select this unit and to be used to carry out on the line of programing function, erase feature or read functions applying on the word line.The storage operation circuit can also select signal to apply programming signal so that the device resistance between first and second conducting terminals is become relatively low resistance from relative high electrical resistance to select this unit and to be used to carry out on the line of programing function, erase feature or read functions applying on the word line.Relative high electrical resistance between first and second conducting terminals is corresponding to the first information state of memory cell, and the relative high electrical resistance between first and second conducting elements is corresponding to second information state of memory cell.First and second information states can be non-volatile.
In another aspect, the storage operation circuit selects signal to read signal to determine the information state of memory cell to select this unit and to apply on program/erase/read line applying on the word line.Determine that the information state of memory cell can not change the state of memory cell.In another aspect, a plurality of optional memory cells can be connected to the line that is used to carry out programing function, erase feature or read functions.
In another aspect, re-programmable both-end fuse-anti-fuse (fuse/antifuse) device comprise first conductor, second conductor opened with first conductor separation and have a plurality of nanotubes and with first and second conductors in each equal nanotube element of contacting of direct physical permanently.The nanotube density that this nanotube element comprises be selected as can in response to be connected across on first and second conductors first threshold voltage and and the high resistance state of opening the electrical connection between described first and second conductors and producing described nanotube articles, to form first device state.The nanotube element can also be in response to being connected across second threshold voltage on first and second conductors and electrical connection between closed first and second conductors and produce the low resistance state of described nanotube articles, to form second device state.This device can be a cross point switches.First and second device states can be non-volatile.
In another aspect, the Reprogrammable interconnection between a plurality of wiring layers comprises first conducting terminal and a plurality of wiring layer, and each wiring layer comprises the wiring layer conducting terminal.This interconnection also comprises the stimulation circuit with first conducting terminal and each wiring layer conducting terminal electric connection.This interconnection also comprises the nanotube articles with a plurality of nanotubes.This nanotube articles be aligned to first conducting terminal permanently direct physical contact and with each wiring layer conducting terminal permanently direct physical contact.This stimulation circuit is configured to form between the wiring layer conducting terminal in first conducting terminal and a plurality of wiring layer conducting terminal first voltage difference, thereby make nanotube articles form interconnection between two wiring layers in described a plurality of wiring layers, nanotube articles has relatively low resistance states.This stimulation circuit is configured to form between the wiring layer conducting terminal in first conducting terminal and a plurality of wiring layer conducting terminal second voltage difference, thereby make nanotube articles disconnect in described a plurality of wiring layer the interconnection between two wiring layers, nanotube articles has higher relatively resistance states.In another aspect, stimulation circuit disconnects all interconnection in response to security consideration.
In another aspect, the method for making double-end storage spare comprises and first conducting terminal is set and is provided with and isolated second conducting terminal of first conducting terminal.This method also comprises the stimulation circuit of at least one electric connection of the setting and first and second conducting terminals.This method comprises that also setting comprises the nanotube articles of at least one nanotube.Nanotube articles is overlapping with at least a portion of at least one in the predetermined extent and first and second conducting terminals.Predetermined overlapping degree in response device and the nanotube articles and first and second conducting terminals between at least one is relevant.
The overlapping of predetermined extent can be determined by isotropic etching process regularly.The overlapping of predetermined extent can be determined by the directional etch process.The overlapping of predetermined extent can be determined by the thickness of expendable film.The overlapping of predetermined extent can be determined by the thickness of at least one in first and second conducting terminals.
In another aspect, this method comprises makes second memory spare, and its structure is the mirror image of double-end storage spare structure.
The accompanying drawing summary
In the accompanying drawings,
Figure 1A illustrates the cross-sectional view of exemplary embodiment of the invention;
Figure 1B illustrates the cross-sectional view of exemplary embodiment of the invention;
Fig. 2 A-I is the SEM microphoto of the structure of some execution mode according to the present invention;
Fig. 3 A-E illustrates the cross-sectional view of the structure of some execution mode according to the present invention;
Fig. 4 is the cross-sectional view of the structure of some execution mode according to the present invention;
Fig. 5 is the cross-sectional view of the structure of some execution mode according to the present invention;
Fig. 6 is the cross-sectional view of the structure of some execution mode according to the present invention;
Fig. 7 is the flow chart that the general manufacture craft of some execution mode according to the present invention is shown;
Fig. 8 A-F illustrates the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Fig. 9 A-C illustrates the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Figure 10 A-I illustrates the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Figure 11 A-C illustrates the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Figure 12 A, B and Figure 13 illustrate the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Figure 14 A-J illustrates the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Figure 15 A-N illustrates the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Figure 16 A-L illustrates the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Figure 17 A-M illustrates the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Figure 18 is that the flow chart of verifying with the switch operability of program cycles is read, wipes in the use that some execution mode according to the present invention is shown;
Figure 19 is the flow chart that the erase cycles of some execution mode according to the present invention is shown;
Figure 20 illustrates the electric current of the device of some execution mode according to the present invention and the curve chart of voltage erasing characteristic;
Figure 21 is the flow chart that the program cycles of some execution mode according to the present invention is shown;
Figure 22 A and 22B be the reading of device that some execution mode according to the present invention is shown respectively, wipe the curve chart with program current and voltage characteristic and resistance characteristic;
Figure 23 A-E, 24A-E and 25A-E illustrate the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Figure 26 is the cross-sectional view of the structure of some execution mode according to the present invention;
Figure 27 is the cross-sectional view of the structure of some execution mode according to the present invention;
Figure 28 is the cross-sectional view of the structure of some execution mode according to the present invention;
Figure 29 is the cross-sectional view according to the structure of one aspect of the invention;
Figure 30 A and 30B illustrate the schematic diagram of prior art structure;
Figure 31 illustrates the cross section of the device of some execution mode according to the present invention;
Figure 32 A and 32B illustrate the schematic diagram of some execution mode according to the present invention;
Figure 33 A-G illustrates the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Figure 34 A-E illustrates the cross-sectional view of the structure of creating in the making step of some execution mode according to the present invention;
Figure 35 and 36 is plane graphs of the structure of some execution mode according to the present invention.
Describe in detail
A plurality of devices that better embodiment of the present invention provides the two-terminal nanotube switch and uses these switches.Generally speaking, nanotube element or goods and overlapping such as at least a portion of each in two terminals of conducting element.The stimulation circuit that is connected in the terminal one or both applies suitable electrostimulation, and the nanotube element comes in response to this stimulation by the state that changes this switch.For example, the state of this switch of resistance characterization of power path between two terminals.Higher relatively resistor path is corresponding to " opening " or the OFF state of switch, and relatively low resistor path is corresponding to " closure " or the ON state of switch.Two states are non-volatile.Stimulation circuit can be read to non-destructive the state of (NDRO) switch, and changes on off state (for example resistance) repeatedly.
The inventor believes that the ability that changes switch between two states is relevant with the relation between the electrical characteristics with the heat of this switch.Particularly, the inventor believes, this switch performances and electric current by the nanotube element are relevant with the relation that heat is dispersed out between the nanotube element.Desirably, for this switch being become " opening " state, stimulation circuit applies the inventor in the nanotube element thinks and is enough to cause the stimulation of heating, and this switch has the design feature that restriction can be flowed out the heat that the electric current of nanotube element causes simultaneously.The inventor believes that this has realized the nanotube element was carried out heating, has disconnected the conductive path in the switch and " opening " state of establishment.In other words, the inventor believes that the heat of this switch and fulgurite reason have strengthened the heat history in the nanotube element, and " opening " state is formed.In some embodiments, heat and fulgurite reason can be by the controlled way be scheduled to nanotube articles and two such as at least one overlapping realization in the terminal of conducting element.For example, in some embodiments, the nanotube element is by such as at least one is overlapping in the appointment geometry of the controlled overlap length of preferred length and two terminals.Then, heat is difficult to flow to the terminal from the nanotube element, but the contact length long enough makes electric current to flow into the nanotube element from this terminal well.In some embodiments, heat and fulgurite are managed by selecting for use and are dispersed the very poor material switch of heat and realize.For example, this switch can come passivation with the layer than lower thermal conductivity, and this helps heat is blocked in the nanotube element.Perhaps, terminal can be made with the better relatively relative relatively poor material with thermal conductivity of conductivity.Other design and the material of the heat of switch and fulgurite reason can be expected.Though should be noted that the switch resistance variation that is caused by electrostimulation is observed repeatedly, still consider the reason of these resistance variations from theoretical and test angle.When the submission date, the inventor believes, the behavior that thermal effect as herein described can cause or help to be observed.The behavior that other effect also can cause or help to be observed.
This switch can be made following detailed description by the method that use is easy to be integrated in the existing semiconductor making method.Describe now and allow between nanotube articles or element and terminal, to make the overlapping several method of specifying geometry.
Because this switch can controllably switch between two non volatile states, and the making of switch can be integrated in the existing semiconductor making method, so this switch can be used for many purposes.For example, this switch can be realized in nonvolatile RAM (NRAM) array, Reprogrammable fuse/anti-fuse device and Reprogrammable distribution are used.
At first, the execution mode based on the nonvolatile memory device/switch of nanotube is shown, and describes its various parts.Then, the method for making switch element is shown.Method of testing when making switch element is described.At last, the non-volatile elements of use based on nanostructure is shown, such as memory array, fuse/anti-fuse device and Reprogrammable distribution, and preparation method thereof execution mode.
2-terminal nanotube switch
Figure 1A illustrates the cross-sectional view of 2-terminal nanotube switch (2-TNS) 10.Nanotube element 25 is placed on the substrate 35 that comprises insulator layer 30.Nanotube element 25 is overlapping at least in part with for example conducting element 15 and 20 two terminals that directly are deposited on the nanotube element 25.
In the present embodiment, can in the zone that is limiting before or after depositing electrically conductive element 15 and 20, make nanotube element 25 form figure.
Conducting element 15 contacts with stimulation circuit 100 with 20.At least one carries out electrostimulation in 100 pairs of conducting elements 15 of stimulation circuit and 20, and this has changed the state of switch 10.Particularly, nanotube element 25 responds this stimulation by the resistance that changes the switch 10 between the conducting element 15 and 20; The relative value of resistance is corresponding on off state.For example, if stimulation circuit 100 cross-over connection conducting elements 15 and 20 apply relative higher voltage and relative higher electric current, then nanotube element 25 responds by the switch resistance between conducting element 15 and 20 is become relative high electrical resistance.This is corresponding to " wiping " state of device, and wherein the conductive phase between the conducting element 15 and 20 is to relatively poor.For example, if stimulation circuit 100 cross-over connection conducting elements 15 and 20 apply relatively low voltage and relatively low electric current, then nanotube element 25 responds by the switch resistance between conducting element 15 and 20 is become relatively low resistance.This is corresponding to " programming " state of device, and wherein the conductive phase between the conducting element 15 and 20 is to better, even near ohmic properties.Usually, the high resistance and low resistance value is preferably at a distance of at least one magnitude.Example voltages, electric current and the resistance of " programming " and " wiping " on off state of some execution mode of two-terminal nanotube switch below will be described in further detail.
Conducting element 15 and 20 is preferably made by electric conducting material, and can be made from the same material or a different material according to the performance characteristics of required switch 10.For example, conducting element 15 and 20 can be by making such as the metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and other suitable metal and combination thereof.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, Duo Bi and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xConductive nitride, oxide or silicide.Also can use the conductor or the semi-conducting material of other type.Conducting element 15 and 20 has for example thickness of 5-500nm scope usually.In the present embodiment, conducting element 15 and 20 about 160nm at interval preferably.This interval can be little or big as technological design allows according to the desirable characteristics of switch 10, for example from 5nm to 1 micron.Preferably, this is at interval less than about 250nm.
Be produced between nanotube element and terminal or the conducting element overlapping preferred approach fully follow above list and award jointly in the assignee's who gives the application patent disclosure and the granted patent describe, or in current electronics industry practice employed known technology.Below describe the partly overlapping preferred approach of making controlled overlap length between nanotube element and terminal or the conducting element in detail.
Insulator 30 can be by SiO 2, SiN, Al 2O 3, BeO, polyimides or other suitable insulative materials constitute, and have for example thickness of 2-500nm scope.Substrate 35 supportings that insulator 30 is made by for example silicon.Substrate 35 can also be by semiconductor, insulator and/or be connected to conducting element 15 and 20 so that the complex of the metal of the signal of telecommunication to be provided to non-volatile 2-terminal nanotube switch (2-NTS) 10.In some embodiments, substrate 35 can be and insulator 30 identical materials, and is for example quartzy.Generally speaking, substrate 35 can be any material of accepting by the nanotube deposition of spin coating, but be preferably the material of from the group that following formation is arranged, selecting: thermal oxide or nitride, the aluminium oxide on silicon dioxide, silicon nitride, the silicon; Or the combination in any of following material on silicon or silicon dioxide: aluminium, molybdenum, iron, titanium, platinum and aluminium oxide; Or any other substrate that uses in the semi-conductor industry.
In some embodiments, nanotube element 25 is works (being also referred to as nanostructure) of the carbon nano-tube of entanglement.The method of making nanotube element and nanostructure is known, and in the references of institute's combination description is arranged.In some embodiments, nanotube element or works are porous, and have filled at least some holes in the nanotube element from the material of conducting element 15 and/or 20.In some embodiments, nanotube element 25 comprises single-walled nanotube (SWNT) and/or many walls nanotube (MWNT).In some better embodiment, nanotube element 25 comprises double-walled nanotubes (DWNT).In some better embodiment, nanotube element 25 comprises one or more nanotube bundles.In some better embodiment, nanotube element 25 comprises one or more DWNT bundles.In some embodiments, nanotube element 25 comprises SWNT, MWNT, nanotube bundle and most of DWNT.In some embodiments, nanotube element 25 comprises single nanotube.
Some nanotube of being made by some method is preferable to being used for 2-TNS 10.For example, the nanotube of being made by CVD technology is preferable, and they present switch behavior as herein described with reaching unanimity.
Fig. 2 A illustrates by revolving the system method and makes the SEM figure of the example SWNT nanostructure 50 of individual layer entanglement nanotube basically.Though Fig. 2 A illustrates the single layer nanometer structure thing, can use other proper technology to make the multi-layer nano works.That is, not need nanostructure must be monolayer nanotube to better embodiment.For example, nanostructure can comprise nanotube bundle and/or single nanotube.Though Fig. 2 A illustrates the nanostructure with random orientation nanotube, also can use the nanotube of alignment or approaching alignment.And nanotube can be metal and/or semiconductor, as institute in conjunction with described in the references.Generally speaking, nanostructure need not to comprise carbon nano-tube fully, but is made by a kind of material simply and have a form that presents non-volatile switch behavior as described herein, for example based on works, other nano wire or the quantum dot of silicon nanowires.
Nanostructure shown in Fig. 2 A is preferably made on horizontal surface.Generally speaking, works is conformal or can be orientated in all angles under hard-core situation.Fig. 2 C is the SEM figure with structure 90 of the nanostructure 95 of following bottoming step (underlying step) after deposition.These conformal nature of nanostructure can be used for making the more vertical orientated 2-TNS of small size (for example can with bigger density making) of size Control with enhancing and needs, following further describing.
In some embodiments, the nanotube element 25 among Figure 1A is thickness SWNT nanostructures between 0.5-5nm.In other embodiments, the nanotube element 25 among Figure 1A is that thickness is at the MWNT of 5-20 nm nanostructure.The SWNT diameter can be in 0.5-1.5nm scope for example.Therefore single nanotube can have the length of 0.3-4 μ m, and can look is enough to cross over spacing between conducting element 15 and 20.Nanotube can also still contact (or " formation network ") to cross over the spacing between these elements less than the distance between conducting element 15 and 20 with other nanotube.Details for conductive articles that is formed by nanotube and network can be with reference to the U.S. Patent No. 6,706,402 that is entitled as " Nanotube Films and Articles (nanotube films and goods) ".Generally speaking, nanotube density should be enough high to guarantee the whole distance between at least one nanotube or the nanotube network leap conducting element 15 and 20.Other preferable feature of nanotube is described herein.
Two-terminal nanotube switch 10 shown in Figure 1A has the path that can be in one of two states between conducting element 15 and 20.A state can be characterized by by the path has higher relatively resistance, R between conducting element 15 and 20 HIGHThis " open ", in " wiping " or the OFF state, electric current is difficult usually to flow between conducting element 15 and 20.Another state can be characterized by by the path has relatively low resistance, R between conducting element 15 and 20 LOWIn this " closure ", " programming " or ON state, electric current flows between conducting element 15 and 20 usually easily.
Switch 10 is made with low resistance state usually.The resistance of this state depends on the characteristic of nanotube element 25 and the characteristic of conducting element 15 and 20.Generally speaking, the intrinsic resistance of nanotube element 25 and nanostructure can be controlled at every square of 100-100, in 000 ohm the scope, for example measured by the four-point probe mensuration.Resistance is every square 1, and 000-10,000 ohm film have the density of every square micron 250-500 nanotube usually.In some embodiments, nanotube element 25 preferably has for example 1-30 nanotube.In some embodiments, the nanotube element preferably has 5-20 nanotube.
The all-in resistance that is in the switch 10 between the conducting element 15 and 20 of " closure " state comprises that the contact resistance of each overlapping region of series connection adds that the intrinsic series resistance of nanotube is divided by the nanotube path number between element 15 and 20 (can be single nanotube and/or nanotube network).In some better embodiment, total making resistance of 2-TNS 10 is usually in 10k Ω-40k Ω scope.In other better embodiment, this switch can be designed to resistance less than 100 Ω or greater than 100k Ω.The explanation of nanotube resistance can be found in following citing document: " A Comparative Scaling Analysis of Metallic andCarbon Nanotube Interconnections for Nanometer Scale VL SI Technologies (being used for the metal of VLSI technology of nanoscale and the comparison convergent-divergent analysis of carbon nanotube interconnect) " of N.Srivastava and K.Banerjee, Proceedings of the 21stInternational VLSI Multilevel Interconnect Conference (VMIC) (the 21st the multistage interconnected proceedings of international VLSI), 29-October 2 September, 1004, Wikoloa, HI, the 393-398 page or leaf.
Generally speaking, the performance of device is not with the nanotube density strong variations in the nanotube element.For example, the sheet resistance of nanostructure can change at least 10 times, and this device work is still good.In better embodiment, the sheet resistance of nanostructure is low to moderate the Ω near 1k.In some embodiments, after making, the resistance of nanostructure is estimated, and if find resistance greater than about 1k Ω, then enough resistance is reduced to the additional nanostructure of density deposition below about 1k Ω.
At least one applies suitable electrostimulation to stimulation circuit 100 in conducting element 15 and 20, so that switch 2-TNS 10 is switched between low resistance and high resistance state.Generally speaking, the specific implementations that the suitable electrostimulation of 2-TNS 10 is depended on this switch.For example, in some embodiments, stimulation circuit 100 can apply relative high voltage biasing by using not limited electric current to cross over conducting element 15 and 20, switch 10 is become high resistance " open " state.In some embodiments, this voltage is about 8-10V, perhaps about 5-8V or 3-5V or lower.Sometimes, electrostimulation is a potential pulse, and sometimes a series of pulses is used for 2-TNS 10 being switched to " opening " state, for example a series of one or more pulses between 1-5V.The duration that also can change one or more pulses switches to " opening " state with 2-TNS 10.Find in some embodiments, for example allow relative high current greater than 5 μ A to flow through this switch and can strengthen the ability that it switches to " opening " state.In some embodiments, stimulation circuit 100 must apply the stimulation above critical voltage and/or electric current, and 2-TNS 10 is switched to " opening " state.Generally speaking, can use any electrostimulation that enough makes 2-TNS 10 switch to relative higher-resistivity state.In some embodiments, this state can be characterized by the resistance R of 1G Ω or above magnitude HIGHGenerally speaking, this state also is regarded as being characterized by relatively low impedance.
In some embodiments, stimulation circuit 100 can apply relative voltage and setovers switch 10 is become low-resistance " closure " state by crossing over conducting element 15 and 20.In some embodiments, about 3-5V or about 1-3V or littler voltage switch to low resistance state with switch 2-TNS.In some embodiments, 2-TNS 10 is switched to the required electrically stimulating parts of " closure " state and depend on the electrostimulation that is used for 2-TNS 10 is switched to " opening " state.For example, if relative higher voltage biasing is used for " opening " this switch, then need relative higher voltage biasing to come " closure " this switch.For example, if the pulse of 8-10V is used for " opening " this switch, then need the pulse of 3-5V to come " closure " this switch.If the pulse of 3-5V is used for " opening " this switch, then need the pulse of 1-2V to come " closure " this switch.Generally speaking, the stimulation that is used for " opening " and " closure " this switch can all change at every turn, depends in part on " opening " stimulation although " closure " stimulates.In other words,, use the pulse " closure " of 3-5V then, but this switch of pulse " closure " of also using 1-2V " is opened " in the pulse that can reuse 3-5V subsequently even for example use the pulse of 8-10V " to open " this switch.Will bigger voltage be used to open this switch will cause need be bigger voltage come closed this switch.Though the example that this paper enumerates uses " opening " voltage that is higher than " closure " voltage, in some embodiments, " closure " voltage can be higher than " opening " voltage.With respect to voltage amplitude, the difference between closure and the opening operation more depends on Current Control.As example, the 6V erasing pulse of no current restriction can be used to open this switch, the 8V programming pulse that will have the current capacity (cap) of 1 μ A subsequently is used for closed this switch.
Sometimes, electrostimulation is a potential pulse, and sometimes a series of pulses is used for 2-TNS 10 being switched to " closure " state, the one or more pulses between for example a series of 1-5V.The duration of one or more pulses also can change so that 2-TNS 10 switches to " closure " state.In some embodiments, identical voltage level can be used for " closure " and " opening " this switch, but the waveform difference of two stimulations.For example, a series of pulses of given voltage can be used for " opening " this switch, and the individual pulse of same or similar voltage can be used for " closure " this switch.Perhaps for example, the long pulse of given voltage can be used for " opening " this switch, and the short pulse of same or similar voltage can be used for " closure " this switch.Use the waveform of these types can simplify the design of 2-TNS 10, apply a plurality of voltages to this switch because no longer need.In specific implementations of the present invention, this phenomenon is limited and do not occur when limited between erasing period during electric current is being programmed.
Find also that in some cases limiting the electric current that flows through switch can strengthen the ability that it switches to " closure " state.For example, add 1M Ω and connect (inline) resistor so that the electric current in the switch is limited in less than 1000nA between stimulation circuit 100 and conducting element 15 and 20 one, the ability that 2-TNS 10 can be switched to " closure " state strengthens about 40%.Another example is to limit the active circuit of electric current during program cycles.Generally speaking, can use and be enough to make 2-TNS 10 to switch to any electrostimulation of relatively low resistance states.In some embodiments, this state is characterized as being the resistance R of about 100k Ω or lower magnitude LOWIn some better embodiment, relatively the resistance of higher-resistivity state is 10 times of resistance of relatively low resistance states at least.Generally speaking, this state also can be regarded as being characterized by relatively low impedance.In some better embodiment, the impedance of higher relatively impedance state is 10 times of impedance of relatively low impedance state at least.
Two states are non-volatile, and promptly they do not change, and at least one applies another suitable electrostimulation in conducting element 15 and 20 up to stimulation circuit 100, although and hold mode power is removed from this circuit.Stimulation circuit 100 also can be determined the state of 2-TNS 10 by nondestructive read operation (NDRO).For example, stimulation circuit 100 can be connected across lower measuring voltage between conducting element 15 and 20, and measures the resistance R between the conducting element.This resistance can be by measuring the electric current flow through and measuring from its calculated resistance R between conducting element 15 and 20.This makes it not change the state of device a little less than stimulating enough, for example is the voltage bias of about 1-2V in some embodiments.Generally speaking, R HIGHPreferably be R at least LOW10 times, make that stimulation circuit 100 can this state of easier detection.
The inventor believes that when switch changes state the conductive path experience in the switch changes it and transports the variation of the ability of electric current.In other words, the inventor believes that the electrical relation along conductive path between one or more conductors changes because of the physical relation between the conductor changes.In the higher state of the resistance of 2-TNS 10, the inventor believes that existing fully between enough a plurality of conductors, the electricity that transports current capacity in restriction path separates or be discontinuous.This can derive from the physical clearance that forms in response to the electrostimulation of stimulation circuit 100 between these elements.In the lower state of the resistance of 2-TNS 10, the inventor believes, exists between enough a plurality of conductors to allow the path to transport electrically contacting of electric current or continuity relatively preferably.This can derive from the gap that closes in response to the electrostimulation of stimulation circuit 100 between one or more conductors.
Different conductor on the switch path comprises one or more independent nanotube in the nano-component 25 or nanometer fragment and two terminals 15 and 20.Because the one or more nanotubes in the nanotube element provide between two terminals and receive the path, thus between nanotube and the terminal and/or between the nanotube and/or in each independent nanotube self or the variation of the physical relation between the fragment might cause the variation of on off state.For example, nanotube can be under low resistance state with terminal in one or more the contact, contact and under high resistance state, lose with one or more physics in the terminal.Perhaps for example, the nanotube electric network in the nanotube element can contact with each other under low resistance state, and separates a gap under high resistance state.Perhaps for example, nanotube can be continuous at physics under the low resistance state separately, and form physical clearance under high resistance state in the middle of this nanotube.Two gained nanotube sheets or fragment can be regarded as (shorter) nanotube separately.Generally speaking, nanotube in the two-terminal nanotube switch and the physical relation between one or more conductor can change.The inventor believes, depends on specific implementations, for example the switch behavior of the variation controllable switch of the physical relation of the one or more particular types in nanotube and terminal, network nanotube and network nanotube or the nanotube.For different switch designs rules, this phenomenon can change.
The inventor believes that between " opening " stimulation period of stimulation circuit 100, the physical change of the conductive path among the 2-TNS 10 can come from the thermal effect in the conductor.Particularly, the inventor believes, what caused by threshold of appearance threshold voltage and/or current density at least a portion of the nanotube of nanotube element 25 crosses heating and can cause nanotube in this element and the one or more conductor physical separation in the path to form the gap.For example, observe about 20 microamperes threshold current and independent nanotube physics can be broken into separately two different fragments in a gap.In some embodiments, this gap is about 1-2nm, and in other embodiments, this gap is less than about 1nm or greater than about 2nm.This physical clearance prevents that electric current from flowing through nanotube, and " opening " path that is characterized by high resistance is provided.If nanotube element 25 is nano tube structure things, then the function of total current and number of nanotubes or density normally of the electric current in each independent nanotube has illustrated that many in some cases nanotubes can be combined in together to form the fact of power path.The inventor believes, in some embodiments, surpasses about 20 microamperes total current by applying the electric current that is enough to make in one or more independent nanotubes, and these nanotubes can overheated and fracture.Because these nanotubes no longer transport electric current, thus the electric current in the nanotube that do not rupture increase, thereby make one or more overheated and fracture in these nanotubes.Therefore, transport great majority or all overheated and fracture in the nanotube of electric current very soon, in 2-TNS 10, created " opening " path or " wiping " state of characterizing by relative high electrical resistance.Whole or most of nanostructure switch (for example referring to arrow) microphotos that rupture in the electrical-conductive nanometer canal path appear illustrating in Fig. 2 B.
Similarly, the inventor believes that the heating excessively that is caused by threshold voltage that applies to nanotube and/or current density can physically disconnect the contact between one or more nanotubes in the nanotube electric network.Though current not identifying with two nanotubes required particular threshold voltage separated from one another and/or current density in the 2-TNS 10, this voltage and/or current density might with disconnect required close or lower of independent nanotube.And, cross heating and can physically disconnect in the nanotube element 25 contacting between one or more in the one or more nanotubes and conductor element 15 and 20 by what threshold voltage and/or current density caused.
The inventor believes, generally speaking, 2-TNS 10 can suffer physical rupture being easy to overheated position, for example along weak hot link or the hot bottleneck of nanotube element 25 on the path that is provided with between conducting element 15 and 20.The inventor believes that if rupture at given position in the path, then current density can all raise in the residual paths, and this can cause the overheated of other position and fracture.Therefore, transport very soon in the path of current great majority or all can be overheated and fracture, in 2-TNS 10, create " opening " path or " wiping " state that characterizes by relative high electrical resistance.
The inventor believes that " closure " stimulation of stimulation circuit 100 causes electrostatic attraction, thereby can create conductive path in 2-TNS 10.This attraction can or move to nanotube and conductor pulling and contact with each other.As mentioned above, have been found that 2-TNS 10 is switched to the required electrostimulation of " closure " state is relevant to the electrostimulation that before had been used for 2-TNS 10 is switched to " opening " state at least in part.The inventor believes, this effect can be relevant to and cause the single gap that specific " opening " stimulate or the size in a plurality of gaps between the nanotube and conductor in the path.For example, relatively low " opening " voltage can cause less relatively overheated, thereby creates relative less clearance between nanotube and conductor.Then, needing relatively low " closure " voltage to make nanotube and conductor cross over these little gaps fully attracts and they is contacted with each other.Perhaps for example, higher relatively " opening " voltage can cause relatively large overheated, thereby between nanotube and conductor, create relatively large gap, then, needing higher relatively " closure " voltage to make nanotube and conductor cross over these big gaps fully attracts so that they contact with each other.Not high enough " closure " voltage can not make nanotube attract so that they contact with enough intensity with conductor.
The inventor believes, the height of not expecting " closure " voltage, and for example 8-10V in some embodiments may attract nanotube high must being enough to conductor.Yet in case nanotube contacts with conductor, the electric current that begins to flow through this connection can cause that in the junction local temperature rises to.This can make this connection overheated and cause nanotube to separate once more with conductor.This connection and disconnection process constantly repeat up to removing " closure " voltage.In this case, switch failure is because it can not be programmed or " closure ".Yet switch can be by low slightly " closure " voltage closure.The height of not expecting " is opened " voltage, and for example about 15-16V in some embodiments can cause heating, thereby causes the very big gap between nanotube and the conductor, for example 30-40nm.This excesssive gap, making does not have sufficiently high " closure " voltage that nanotube and conductor are fully attracted and they is contacted with each other.In this case, switch failure is because it no longer is programmable.This switch may suffer expendable infringement, because be not enough to make nanotube and conductor to attract the stimulation that consequently contacts.
The inventor believes, can be owing to can cross over the electric arc that gap (being operated the gap that forms by previous " opening ") takes place by the replaceable mechanism in stimulation circuit 100 closed circuits footpath.Electronics and/or the high temperature that causes can be drawn to material (near the gap) in the gap to rebuild continuous power path.
The inventor finds that if 2-TNS 10 is not passivated and is excited, then the required stimulus intensity of " closure " this switch is relevant to the used stimulation of " opening " this switch in inert gas.In other words, the big I in gap is relevant to " closure " stimulation in inert gas.The inventor finds that also if 2-TNS 10 is not passivated and is excited in a vacuum, then the required stimulus intensity of " closure " this switch keeps constant in about 10%, regardless of the stimulation that is used for " opening " this switch.In other words, the size in gap is irrelevant or weak relevant with the stimulation in the vacuum.The inventor believes that vacuum can be accumulated heat more apace than it in gas in the nanotube element, may be because heat leaks into the gas from the nanotube element.
The inventor believes, cause by threshold of appearance threshold voltage and/or electric current among the 2-TNS 10 cross heating (can disconnect the contact between nanotube and the conductor) may be relevant with lattice vibration or the phonon that heat in the nanotube causes.Particularly, the inventor believes, but crosses the one or more specific phonon modes in the heating excitation nano pipe, and this phonon modes can disconnect contacting between nanotube and the conductor.Generally speaking, heat can excite the frequency spectrum such as acoustics and optical phonon in the material of nanotube.The acoustical phonon pattern can be transmitted heat, and the optical phonon pattern can not be used to transmit heat usually.Some optical phonon pattern can be coupled in the acoustical phonon pattern, thereby allows heat to flow to the acoustic mode from optical mode, and this moment, its transmitted heat.If yet heat be not easy to flow to the acoustic mode from optical mode, for example can not transmit by nanotube, heat accumulation or hot bottleneck fast can take place in this nanotube.This can cause being enough to disconnecting the heating of crossing that contacts between nanotube and the conductor.
The inventor has obtained Raman (Raman) spectrum of different types of nanotube of test in 2-TNS 10, and the preferable nanotube that has observed the nanotube that for example as one man presents switch behavior as herein described has usually corresponding to the nanotube obvious optical phonon pattern of breathing pattern radially.The inventor believes that this breathing pattern can be relevant with the switch behavior of 2-TNS 10.For example, this pattern can show as hot bottleneck, thereby heat is blocked in the nanotube.This pattern can make the contact gear ratio between nanotube or nanotube and the conductor not manifest that the nanotube of other kind of this pattern is easier to be destroyed by threshold voltage and/or current density.This breathing pattern also can be coupled in the fracture of nanotube or nanotube and conductor between the relevant pattern of fracture that contacts.In other words, this breathing pattern self can be directly with switch in possible gap form relevant, but can be relevant with the phenomenon in formation gap in switch.
Preferable nanotube also can have other the relevant common phonon modes of ability that contacts with conductor with its disconnection.For example, in some nanotube, but can there be one or more patterns of one or more defect modes or the binding pattern of close coupling between nanotube and conductor.Generally speaking, one or more optics or acoustical phonon pattern can help to disconnect the path among the 2-TNS 10, and for example " opening " switch can be that phonon causes.Different types of nanotube for example by distinct methods or use nanotube that different technology conditions makes and/or the nanotube with wall of different numbers, can have different phonon spectras.Some kind can have the phonon modes or the further feature that can cause or strengthen the easily broken fragility that contacts between nanotube and the conductor.For example, have more than one wall and can strengthen the easily broken fragility that contacts between nanotube and the conductor.
The inventor believes, the switch behavior of 2-TNS 10 can obtain from the heat of the parts of this switch and the key relation of electrical characteristics.The inventor believes that the two-terminal nanotube switch preferably can provide sufficiently high voltage and/or electric current to the nanotube element, and sufficient amount of heat is accumulated so that disconnect contacting between one or more nanotubes and the conductor in the nanotube element.Preferably, this disconnection is enough little, makes it can Reprogrammable ground closed.By managing this relation, can design and make and have the better embodiment of strengthening the property.These purposes can design or manage and realize by electricity and/or the thermal technology's journey to this device.
Provide the purpose of sufficient electrostimulation to realize to the nanotube element by techniques well known in the art.Particularly, conducting element preferably conducts the current in the nano-component relatively preferably.Conducting element can be preferably electric conductor relatively preferably.For example, conducting element can be the electric conducting material of metal or other type.Preferably, conducting element can be made by the technology and the material that are easy to be integrated into existing manufacture method or used therein.Under " closure " state at least, in the conducting element one or both preferably with the nearly ohmic properties of nanotube element contact.The contact of making nearly ohmic properties is known.
Allowing sufficient amount of heat to accumulate in the nanotube element so that stimulate in response to " opening " potentially disconnects nanotube and more is added with challenge with the purpose that contacts between the conductor.The for example also heat conduction well of the many materials that can be used for conducting element of good conductive.For example, metal can conduct electricity usually well, and is applicable to many execution modes of making 2-TNS, and also heat conduction is good usually.For example, the good material of the heat conduction of good conductor of heat can draw enough heats from the nanotube element and make that this element can be not overheated in response to " opening " stimulates.Perhaps, the nanotube element is only overheated in response to big " opening " of not expecting stimulates.To stimulate the 2-TNS that heat can be accumulated in order making in the nanotube element, to have conceived plurality of embodiments in response to enough (but being not what do not expect) " opening ".
In some better embodiment, can be easy to the feature that ruptures especially by nanotube being chosen to have stimulate in response to " opening ", nanotube self is carried out the calorifics engineering design.For example, as mentioned above, some nanotube can be selected to have the accumulation heat or is coupled to some pattern that disconnects other pattern that contacts between nanotube and the conductor.Nanotube can have the defective that is easy to be crossed thermal cutoff.In some embodiments, can before deposition, carry out preliminary treatment to introduce defective to nanotube.
In some better embodiment, can be by a kind of material (or multiple material) manufacturing better but that heat conduction is relatively poor relatively being carried out the calorifics engineering design to conducting element from conductive phase.For example, this material can have relatively low thermal conductivity, higher relatively thermal capacitance and/or relatively low thermal-diffusion constant.For example, in some embodiments, doped semiconductor can provide sufficiently high " opening " to stimulate to the nanotube element, and absorbs relatively low heat from the nanotube element.Other types of material with this feature can expect, for example conducting polymer.Preferably, conducting element provides enough electrostimulation with " opening " this switch, does not significantly hinder the heat history in the nanotube element simultaneously.
In addition, in some better embodiment, the distance between two conducting elements is less relatively, for example less than 250nm.Observe, have relative isolated conductor element far away and therefore have the switch of crossing over the relative longer nanotube element of distance between them, need to tend to relatively large " wiping " stimulation so that this device is become " opening " state.Tend between conducting element, to have higher resistance at the switch that has relatively large spacing between the conducting element, and therefore in the nanotube element, have lower current density for given erasing voltage.
Generally speaking, the nanotube element also can contact with other Material Physics except conductor among the 2-TNS, for example lower floor's insulator and upper strata passivation layer.These materials can draw heat from the nanotube element.In some better embodiment, one or more materials with the contact of nanotube element can be chosen to relative relatively poor heat carrier, for example have sufficiently high thermal capacitance and/or enough low thermal conductivity.In other words, these material poor heat conductivity, and can be good heat guard.This is useful, because if these materials that contact with element draw small amount of thermal from this element, then the nanotube element is easier to be overheated.For example, the inventor finds, except other benefit is provided, preferably covers passivation layer and can significantly reduce the required stimulus levels of " opening " 2-TNS on the nanotube element.By preferably comprise passivation layer on switch, in one embodiment, the required stimulation of " opening " switch reduces half.Generally speaking, the inventor believes, preferably heat conduction is relative relatively poor with one or more materials of nanotube element contact, and this helps heat to accumulate in the nanotube element.
The inventor believes that preferable passivation layer also is useful to the 2-TNS parts and the environment isolation of for example nanotube element and/or conducting element.For example, airborne aqueous vapor or be attached at high temperature corrodible this element of water on the nanotube element.Stimulate if apply " opening ", then in the nanotube element, heating can take place under the sufficiently high temperature, make that any water on the element all is enough to damage this element, make its conduction current well to exposed 2-TNS.Though this " has opened " 2-TNS, switch can not " closure " subsequently, because the conductive path that the nanotube element provides has irretrievably been destroyed.If as an alternative, use preferable passivation layer that 2-TNS is carried out passivation, then switch and destructive water are isolated and can be repeated " opening " and " closure ".Preferably, before the deposit passivation layer water on any 2-TNS of being attached to is being removed; Otherwise this layer is easy to catch near the water of switch.Passivation layer does not preferably remove aqueous vapor yet and is fluid-tight.Also preferably do not use the high power plasma that can destroy the nanotube element to make passivation layer.Passivation layer can be made by known any suitable material in the CMOS industry, including, but not limited to: PVDF (polyvinylidene fluoride), PSG (phosphorosilicate glass) oxide, Orion oxide (Orion oxide), LTO (planarization low temperature oxide) oxide, sputter oxide or nitride, Flowfill oxide, ALD (ald) oxide, CVD (chemical vapour deposition (CVD)) nitride.The use that can be bonded to each other of these materials can place the mixture of PVDF layer or PVDF and other copolymer on the CNT top, and can use ALD AL 2O 3Layer covers on this compound, but any oxygen-free high temperature polymer all can be used as passivation layer.In some better embodiment, can mix and form copolymer with other organic material or dielectric material such as the passivating material of PVDF, to generate special passive behavior such as life-span with prolongation and reliability such as PC7.
The passivation of NRAM device can be convenient to this device and at room temperature operate in the air, and combines as protective layer with the material laminate of NRAM top device.The operation of the NRAM device of passivation can not carried out under the inert gas background such as argon, nitrogen or helium usually, perhaps operates to remove the water that is absorbed from exposed nanotubes under (the being higher than 125C) sample temperature that raises.Therefore, the requirement of passivating film is normally dual.The first, passivation should form effective moisture barrier, is exposed in the aqueous vapor to prevent nanotube.The second, passivating film should not disturb the switching mechanism of NRAM device.
A kind of method of passivation relates to around the chamber of NRAM element manufacturing with switch region that sealing is provided.Be implemented around the chamber of independent device (device level passivation) with around the chamber both of the tube core (die-level passivation) of whole 22 devices.Yet the manufacture craft flow process is very complicated, needs at least 2 extra lithography steps and at least 2 additional etch step.
The another kind of method of passivation relates to the suitable dielectric layer of deposition on the NRAM device.The example of this method is to use the spin coating polyvinylidene fluoride (PVDF) that directly contacts with the NRAM device.PVDF is patterned to die-level (on the active region of whole tube core) or device level sheet (covering the independent sheet of independent device).Then, the second suitable dielectric passivating film such as aluminium oxide or silicon dioxide is used to seal PVDF and provides firm passivation to the NRAM operation.The NRAM operation is considered to meeting thermal decomposition upper strata PVDF, therefore needs second passivation layer seal this device.Because the die-level passivation sheet of square micron normally～100, second passivation is broken so this exploded can cause, the NRAM device is exposed in the air, with and lost efficacy subsequently.For fear of this inefficacy of second passivating film, come pulse modulation this device with the 0.5V step-length to the 500ns pulse of 8V by using usually from 4V, come device to the die-level passivation to carry out electricity and " wear out ".This is considered to the controlled decomposition to PVDF, and prevents breaking of upper strata second passivating film.After ageing process, die-level passivation NRAM device operate as normal.Do not need this aging step and at room temperature directly under operating voltage, operate in the air with the device of the device level PVDF coating and the second passivating film passivation.By the device level passivation, PVDF is changed into accurate CNT works shape by image, common 0.5 micron wide long with the 1-2 micron.This small pieces are considered to usually to decompose and second passivating film was lost efficacy.For the given defect concentration in second passivation, on average, compare and on the overlay area of littler device level PVDF sheet, not have defective with bigger die-level sheet.
The inventor believes, in some better embodiment, can stimulate " the opening " that is applied by stimulation circuit and carry out engineering design so that the heat history in the enhancing nanotube element.In one embodiment, applying relatively large voltage to switch is that " opening " stimulated an example of carrying out engineering design.In other embodiments, can apply a series of pulses, and these pulses can be opened by the timed separation that spreads out of the time scale of nanotube element faster than heat to this switch.The inventor believes that in this case, pulse self need not to have bigger amplitude, but the total amount of heat that pulse deposits in the nanotube element may be enough to heating and disconnect this element.
The inventor believes, in some better embodiment, can carry out the calorifics engineering design to the two-terminal nanotube switch by they being designed to have " focus " or hot bottleneck, and one or more nanotubes are overheated especially easily at focus or hot bottleneck.For example, as described in detail below, the nanotube element can be made with controlled geometrical relationship (for example controlled overlap length) and at least one conductor part overlapping.For example, by overlap length being controlled at less than 100nm or less than 50nm, conductor can fully be reduced from the heat that the nanotube element draws, so that might allow the nanotube element overheated rapidly on one or more positions.On the contrary, increase overlap length can by disperse from the nanotube element heat prevent overheated.
For example, observe, and compare more than the 100nm, can by overlap length is limited in less than 50nm come " opening " at least many 10% make switch.And for having less than for the execution mode of the overlap length of 50nm, the required time of " opening " switch can be reduced, this hint or to have illustrated that this nanotube element can stimulate in response to " opening " overheated more quickly.For example, have less than " opening " time of making switch of 50nm overlap length can be on the magnitude of 100ns, and have greater than " opening " time of the switch of 100nm overlap length can be on 1 millisecond or above magnitude.Engineering design can provide switching speed faster, for example lns or faster.Generally speaking, arrange nanotube element and one or more conducting element of great use with the geometrical relationship of appointment to the relation of the heat between management nanotube and the conducting element.This arrangement or other arrangement can be created hot bottleneck or " focus " in 2-NTS, this can strengthen the operation of switch.
In a word, in one or more execution modes, heat and/or electrical engineering design or management can be used for strengthening the two-terminal nanotube switch performances.Heat as herein described and/or electrical engineering designing technique can be simultaneously used in the design of preferable two-terminal nanotube switch with in making more than one.For example, switch can be made and have controlled overlap length reducing the heat that conducting element draws from the nanotube element, and can be further with comprising that in some cases the preferable passivation layer that copolymer mixes come this switch is carried out passivation.
Though should be noted that the switch resistance variation that causes because of electrostimulation is observed repeatedly, still consider the cause of these resistance variations from theoretical and both angles of test.When submitting to, the inventor believes the behavior that thermal effect as described herein can cause or help to be observed.The behavior that other effect also can cause or help to be observed.
Figure 1B illustrates the cross-sectional view of non-volatile 2-terminal nanotube switch (2-TNS) 10 ', wherein by the overlapping heat management of realizing between restriction nanotube element 25 ' and the conducting element 20 '.Nanotube element 25 ' is arranged on the substrate 35 ' that comprises insulator layer 30 '.Nanotube element 25 ' be arranged to for example conducting element 15 ' and 20 ' terminal at least one is overlapping at least in part on predetermined extent, these terminals directly are deposited on the nanotube element 25 '.
In the present embodiment, in a zone nanotube element 25 ' is carried out graphically, this zone can limit before or after the deposition of conducting element 15 ' and/or 20 '.Conducting element 15 ' is overlapping with a whole terminal area of nanotube element 25 ', forms nearly ohmic properties contact.At the opposite end of nanotube element 25 ', 45 ' locates in the overlapping region, conducting element 20 ' and nanotube element 25 ' the overlapping controlled overlap length 40 '.Controlled overlap length 40 ' can be in 1-150nm scope for example, perhaps in the 15-50nm scope.In a better embodiment, controlled overlap length 40 ' is about 45nm.Can split to close and carry out heat and fulgurite reason to make heat difficult from nanotube element inflow conducting element by restriction overlapping nanotube element 25 ' and conducting element 20 ', strengthen the heat history in the nanotube element, wherein the contact length long enough makes that electric current is easy to flow into the nanotube element from conducting element.
In one or more execution modes, one or more electrical characteristics of switch 10 ' are relevant with controlled overlap length 40 '.For example, as described in more detail below, wipe and/or time that program switch 10 ' is required relevant with controlled overlap length 40 '.
The SEM that overlooks that Fig. 2 D to 2I illustrates several different execution modes of function two-terminal nanotube switch schemes, and wherein this switch is made according to material, nanotube element and the method for some execution mode as herein described by using.In the execution mode shown in Fig. 2 D, make 2-TNS 60D on the insulator layer 62D on being deposited on silicon substrate (invisible in the vertical view).Insulator 62D is the SiO of about 20nm 2, and as the end (back of the body) grid.The conducting element 70D and the 75D that correspond respectively to conducting element 15 ' and 20 ' in Figure 1B are palladiums, and thickness is about 100nm.Conducting element 70D and 75D have the width of about 400nm separately, and have the interval 85D of about 150nm.
In image, nanotube element 65D comprises some nanotubes, appears at the right half of of image as bright gray line in the background of the insulator 62D of grey.The major part of conducting element 70D and nanotube element 65D is overlapping, cause in image conducting element 70D to compare and have relative coarse texture with the texture of conducting element 75D, the finite part of conducting element 75D and nanotube element 65C is overlapping, as more detailed description hereinafter.Conducting element 70D has the striped by regional 55D indication, and this zone is that this element is owing to lower floor has the zone that nanotube lifts.Can find out that also nanotube element 65D extends beyond the periphery of conducting element 70D.This structure does not influence the performance of device, but can allow easily the expose portion of nanotube element 65D is carried out imaging and/or sign.
Can see some nanotubes among the nanotube element 65D cross between conducting element 70D and the 75D apart from 85D.Conducting element 75D controlled overlap length and nanotube element 65D with about 17.4nm in regional 80D is overlapping, and this length is corresponding to the controlled overlap length 40 ' among Figure 1B.Can see that conducting element 70D and 75D have white border, this is the charged pseudomorphism in the imaging process.This pseudomorphism has been covered has littler than pseudomorphism length in fact controlled overlapping region 80D.Yet as further described, some execution mode has enough greatly with visible overlapping region in the SEM microphoto.
Execution mode shown in Fig. 2 E has the structure similar to the execution mode of Fig. 2 D, wherein conducting element 70E and 75E have to Fig. 2 D in the similar size of element, but separating by about 250nm apart from 85E.This image has rotated 90 degree with respect to Fig. 2 D.At this, conducting element 75E is at regional 80E and the overlapping about 38.6nm of nanotube element 65E.Though the difference apart from 80D and 80E and 65D and 65E is bigger, the execution mode shown in Fig. 2 D and the 2E can be operated with comparing.Execution mode shown in Fig. 2 F is similar with the execution mode shown in the 2E to Fig. 2 D, but conducting element 70F and 75F are separated by the distance of about 250nm.At this, the overlapping about 84.9nm of conducting element 75F and nanotube element 65F.Execution mode shown in Fig. 2 G is similar to the execution mode shown in Fig. 2 D-2F, but conducting element 70G and 75G are separated by the distance of about 150nm.At this, the overlapping about 90.5nm of conducting element 75G and nanotube element 65G.
Execution mode shown in Fig. 2 G is similar to the execution mode shown in Fig. 2 D-2G, except conducting element 70H and 75H by the distance of about 150nm separately.At this, the overlapping about 104nm of conducting element 75G and nanotube element 65H.In this accompanying drawing, can see that conducting element 75H has the texture of suitable roughening in element 75H and nanotube element 65H overlapping areas 80H.The major part overlapping areas with nanotube element 65H of this texture and conducting element 70H can be compared, but regional 80H is subject to 104nm.Execution mode shown in Fig. 2 I has the structure similar to Fig. 2 H, but conducting element 75I in regional 80I with the overlapping about 136nm of nanotube element 65I.At this, can see once more that conducting element 75I has with element not compare remarkable roughening texture in regional 80I with the remainder that nanotube element 65I overlaps.This roughening texture is that the nanotube of element material 75I below causes.
All execution modes shown in Fig. 2 D-2I are functional switches, wherein realize heat management by the appointment geometrical relationship that nanotube element and conducting element are arranged to such as controlled overlap length.In some embodiments, find the rate of finished products of the operating switch that controlled overlap length influence is made, for example the percentage of making switch that correctly plays a role in the specific implementations.For example, find to compare with the switch of making that has less than the execution mode of the overlap length of 50nm, having will about less 10-20% greater than the switch of making that can correctly play a role of the execution mode of the overlap length of 100nm.Below describe the method for test 2-NTS in detail.
Be intended to example at this voltage of listing, electric current and resistance as the appropriate value of specific implementations; For one or more other execution modes, appropriate value can be different.
In application-specific, expectation makes nanotube element and conducting element overlapping with the geometry different with the execution mode shown in Figure 1A-1B or the 2D-2I, carries out the design of thermal technology's journey so that split to close.For example, expectation is positioned at the nanotube element the upper and lower even vertical side of contact element.Generally speaking, can use any configuration that the appointment geometry that is enough in device to realize described switch behavior is provided.Particularly, conducting element should be arranged to provide enough electrostimulation to the nanotube element, simultaneously switch integral body have enough heat managements with realize in the nanotube element on the cut-off switch path between the nanotube and conductor contact cross heating.
Should be appreciated that the remainder of execution mode as herein described comprises the stimulation circuit that contacts with conducting element, the stimulation circuit 100 of Figure 1A and 1B for example is not though it is illustrated.Though be also to be understood that a plurality of two-terminal nanotube switches that illustrate in the illustrated embodiment, wherein, can use other thermal management algorithm by the overlapping heat management of realizing between the conducting element of restriction nanotube element and for example terminal.For example, in some embodiments, the nanotube element can be partly or entirely overlapping with one or two conducting element, and the material in the switch can be selected to the abundant heat history of guaranteeing in nanotube element at least a portion.
Fig. 3 A illustrates switch 900A, and it is the modification of 2-TNS10 ' shown in Figure 1B and by using preferred approach to make.In the present embodiment, conducting element 905 is overlapping with the top and the side of nanotube element 920, forms nearly ohmic properties contact, and fills the through hole 910 in the insulator 915.This is connected to electrode (not shown) under the insulator 915 with nanotube element 920.Conducting element 970 is with overlapping with the top and the side of nanotube element 920 on controlled overlap length 901.
Fig. 3 B illustrates switch 900B, and it is another modification of the 2-TNS10 ' shown in Figure 1B, and uses preferred approach to make.In the present embodiment, conducting element 935 is overlapping with the bottom of nanotube element 945, forms nearly ohmic properties contact, and fills the through hole 940 in the insulator 915.This is connected in electrode (not shown) under the insulator 915 with nanotube element 945.Conducting element 975 is overlapping with the top and the side of nanotube element 920 on controlled overlap length.
Fig. 3 C illustrates switch 900C, and it is another modification of the 2-TNS10 ' of Figure 1B, and uses preferred approach to make.In the present embodiment, last conducting element 950 and following conducting element 955 contact with each other, and overlapping with upper surface, lower surface and the side surface of nanotube element 965, form nearly ohmic properties contact.The through hole 960 that following contact element 955 is filled in the insulator 915.This is connected in electrode (not shown) under the insulator 915 with nanotube element 965.Conducting element 980 is overlapping with the top and the side of nanotube element 965 on controlled overlap length 907.
Upper and lower conducting element 950 and 955 is illustrated as extending beyond an end of nanotube element 965.Upper and lower conducting element 950 and 955 contacts with each other, and contacts with nanotube element 965 nearly ohmic properties in a zone of nanotube element 965, because nanotube element 965 is porous, is generally the porous more than 90%.At least some holes in upper and lower conducting element 950 and the 955 filled with nanotubes elements 965.Therefore, hi an alternative embodiment, upper and lower conducting element 950 and 955 need not to extend beyond nanotube element 965 1 ends so that contact with nanotube element 965 and contact with each other.
Fig. 3 D illustrates switch 900D, and it is another modification of the 2-TNS 10 ' of Figure 1B, and uses preferred approach to make.In the present embodiment, last conducting element 950 and following conducting element 955 contact with each other, and overlapping with upper surface, lower surface and the side surface of nanotube element 965, form nearly ohmic properties contact.The through hole 960 that following contact element 955 is filled in the insulator 915.This is connected in electrode (not shown) under the insulator 915 with nanotube element 965.Last conducting element 980 and following conducting element 985 contact with each other, and overlapping with upper surface, lower surface and the side surface of nanotube element 965 on controlled overlap length 907.
Fig. 3 E illustrates switch 900E, it be Figure 1A 2-TNS 10 another modification and by using preferred approach to make.In the present embodiment, last conducting element 950 and following conducting element 955 contact with each other, and overlapping with upper surface, lower surface and the side surface of nanotube element 965, form nearly ohmic properties contact.At least some of material filled with nanotubes element 965 mesopores in the element 950 and 955.The through hole 960 that following contact element 955 is filled in the insulator 915.This is connected in electrode (not shown) under the insulator 915 with nanotube element 965.Last conducting element 951 and following conducting element 956 contact with each other, and overlapping with the upper and lower surface of nanotube element 965 on controlled overlap length 907.At least some holes in the material filled with nanotubes element 965 in the element 951 and 956.In the present embodiment, heat management is not to realize by the controlled overlap length between nanotube element and the conducting element, but realize by one or more other thermal management technologies as herein described.
Fig. 4 illustrates the cross-sectional view of another execution mode of non-volatile two-terminal nanotube switch (2-TNS) 2500.In the present embodiment, conducting element 2515 and 2520 is directly deposited on the surface of insulator 2530 and by graphical.Zone between the conducting element 2515 and 2520 of insulator 2522 pattern fillingizations, and be flattened.Nanotube element 2525 conformally is deposited on conducting element 2515 and 2520, and overlapping with the upper surface of at least a portion of the upper surface of conductor 2515 and 2520 and insulator 2522, all these is by substrate 2535 supportings.At one end, nanotube element 2525 is overlapping with the upper surface of conducting element 2515, forms nearly ohmic properties contact.At opposite end, nanotube element 2525 contacts with the upper surface of contact element 2520 on controlled overlap length 2540.
Fig. 5 illustrates the cross-sectional view of another execution mode of non-volatile 2-terminal nanotube switch (2-TNS) 2200.In the present embodiment, conducting element 2215 and 2220 all directly is deposited on insulator 2230 surfaces, and by graphical.Conducting element 2220 has thickness T 1, and it is in the scope of for example 5-500nm.Nanotube element 2225 conformally is deposited on conducting element 2215 and 2220, contacts with the upper surface of these elements and the upper surface of side surface and insulator 2230, and this insulator is by substrate 2235 supportings.Then, come nanotube element 2225 is carried out graphically, make that the whole upper wall and the sidewall of it and conducting element 2215 are overlapping, form nearly ohmic properties contact by conventional in greater detail photoetching technique below using.Nanotube element 2225 is overlapping at sidewall joint areas 2240 and conducting element 2220, provides to be about the controlled overlapping of T1.Nanotube element 2225 all right controlled overlap lengths 2245 are overlapping with conducting element 2220 tops, and this length limits on photoetching ground as described in more detail below.Total controlled overlap length 2250 is roughly defined by the length T 1 and overlap length 2245 sums of sidewall contact area 2240.
Fig. 6 illustrates the cross-sectional view of an embodiment of the present invention.Structural similarity in the microphoto shown in structure shown in Figure 6 and Fig. 2 C, and has components identical: be respectively silicon substrate 63C, insulator 62C, nanostructure construction element 65, the first and second conducting element 70C and 75C, overlapping region 80D as shown in Figure 6, but do not have passivation layer 64 among Fig. 2 C.Insulator 62C is arranged on above the silicon substrate 63C and below nanotube element 65.The first and second conducting element 70C and 75C be positioned partially at respectively insulator layer 62C and nanotube element 65 on.The first conducting element 70C is overlapping with nanotube element 65 in the 80C of overlapping region, and passivation layer 64 is arranged on conducting element 70C and 75C and the nanotube element 65.
Can use material shown in Figure 1A-1B and 2A-2I and method make as described in execution mode.The further details of making the two-terminal nanotube switch element and comprising the device of this switch is below described in more detail.Some additional execution modes and preparation method thereof are below also described.
A plurality of two-terminal nanotube switches that illustrate in the execution mode as herein described, wherein heat management is by realizing nanotube element and the overlapping controlled overlap length of conducting element.Yet, in addition or as an alternative, should be appreciated that execution mode as herein described also can carry out heat management by other technology.Execution mode as herein described has common nanotube articles feature, this nanotube articles have be arranged in two terminals in each at least one overlapping nanotube of at least a portion.Can carry out heat and/or fulgurite reason or engineering design to strengthen one or more characteristics of switch to some better embodiment.For example, in some embodiments, nanotube and a terminal are overlapping, form the contact of nearly ohmic properties, and with the overlapping controlled overlap length of another terminal.In some embodiments, can split one or more materials in the Central Shanxi Plain selects, such as nanotube, conducting element, insulator layer and/or wherein in many better embodiment, can comprise the passivation layer of copolymer or mixed layer, to strengthen the heat history in the nanotube element.
Can be used for switch is become from " wiping " or " opening " state of relative high electrical resistance " programming " or " closure " state of relatively low resistance with the stimulation circuit of at least one electric connection in the terminal of two-terminal nanotube switch execution mode.This circuit also can be used for measuring two resistance between the terminal, and reads definite on off state in (NDRO) operation in non-destructive.
Making has the 2-terminal nanotube switch of controlled overlapping region
In the execution mode of two-terminal nanotube switch, wherein heat management is by arranging nanotube element and conducting element to realize such as the appointment geometrical relationship of controlled overlap length, can strengthen switch performances to the accurate control of this relation.Some characteristic of non-volatile 2-terminal nanotube switch (2-NTS) can be controlled overlap length function, the zone 40 ' of the switch 10 ' shown in Figure 1B for example.Use description to make the Several Methods of the controlled overlap length of specifying geometry.Also some additional execution modes and preparation method thereof will be described.In some embodiments, controlled overlap length is the size of conducting element, for example the width of conducting element or thickness.Generally speaking, can use the techniques described herein to make overlap length between 1-150nm, the preferable 15-50nm.
In order to make controlled overlap length between nanotube element and conducting element, some method is used nanotube element and good etching density and the etched preferable manufacture method of controlling of the timing under the temperature with horizontal alignment.The controlled length that this method will contact the nanotube element with conducting element exposes.This length is corresponding to the controlled overlap length 40 ' among Figure 1B, though specific implementations or a plurality of execution mode can have and geometrical relationships different shown in Figure 1B between nanotube element and conducting element.
Other method is used the preferable manufacture method of the sidewall spacers of nanotube element with horizontal alignment and well-controlled thickness, wherein definition nanotube element with expose this element will with the overlapping controlled length of conducting element after this partition is removed.This length is corresponding to the controlled overlap length 40 ' of Figure 1B, though specific implementations or a plurality of execution mode can have and geometrical relationships different shown in Figure 1B between nanotube element and conducting element.
Other method is used the preferable manufacture method based on photoetching, and wherein the nanotube element is complied with the horizontal properties of one or more conducting elements and also complied with its vertical features in some cases.In the situation of nanotube element adjustment level feature, element is set up and litho pattern changes into and an overlapping controlled overlap length of conducting element.This length is corresponding to the controlled overlap length 40 ' of Figure 1B, though in the present embodiment, the nanotube element can have different geometrical relationships with conducting element.Also comply with in the situation of vertical features of conducting element at the nanotube element, contact with the vertical features of conducting element on the length that the nanotube element can limit at the thickness by this feature, and can on the length that photoetching limits, contact with horizontal properties.Vertical and horizontal length defines the controlled overlap length corresponding to length 40 ' among Figure 1B together, though specific implementations or a plurality of execution mode can have and geometrical relationships different shown in Figure 1B between nanotube element and conducting element.
Fig. 7 illustrates and makes 2-TNS and based on the general process of the device of 2-TNS.Fig. 7 is the high-level flowchart of making the basic skills 800 of better embodiment of the present invention.2-TNS can make by initial configuration (step 802) at first is set, and later nanotube element and possible conducting element will form on this initial configuration.In simple execution mode, initial configuration is the substrate that can form all elements of 2-TNS subsequently thereon.In some embodiments, initial configuration be with the part of device level definition make, the semiconductor structure of planarization, it has the filling hole with metal (binding post) that conductive path is provided between the planarized surface of the semiconductor structure that transistor terminal and gained are partly made.In some embodiments, initial configuration comprises two conducting elements.In some embodiments, initial configuration even comprise the nanostructure that does not form the nanotube element.Generally speaking, the structure that does not also have a defined nanotube element can be regarded as initial configuration." initial configuration " is not to be intended to as the restriction term but the reference point of making as 2-TNS.
2-TNS can by after intermediate structure (step 804) be set make.In some embodiments, intermediate structure is characterized by defined nanotube element is provided on the surface of initial configuration (providing in the step 802).Following further describing, in some embodiments, intermediate structure has the nanotube element that contacts with an overlapping and near ohmic properties of conducting element.In some embodiments, intermediate structure has the nanotube element with the overlapping controlled overlap length of conducting element.For example, this length can be in the scope of 1-150nm." intermediate structure " is not to be intended to as the restriction term but the reference point of making as 2-TNS.
2-TNS can make by final structure (step 806) is set at last.In some embodiments, final structure is to finish the 2-TNS of making.This 2-TNS can be used in the nonvolatile RAM array of distribution as described further below.Some execution mode of final structure can comprise equidistant (on-pitch) circuit of memory array, periphery and other circuit layout, chip passivation, input and output pad (pad); These features and making and not shown thereof are because they have used known industrial manufacture method." final structure " is not to be intended to as the restriction term but as the reference point of the making of 2-TNS.
Use controlled etch to make the method for 2-TNS
Can use the timing engraving method shown in Fig. 8 A-8F to come the execution mode shown in the construction drawing 3B.With reference to Fig. 8 A, preferred methods deposits one deck insulator 1000 on the fabric (not shown).Conducting element 1005 in the through hole 1010 forms conductive path between the conductor (not shown) below nanostructure 1015 and the insulator 1000.Insulator 1000 and conducting element 1005 correspond respectively to insulator 915 and the conducting element 935 among Fig. 3 B.Insulator 1000 can be Si xNy, Al 2O 3Or other suitable insulation material, for example have the thickness in the 5-200nm scope, use known industrial technology to be deposited on the flat surfaces (not shown).Then, preferred methods deposits shown in Fig. 8 A and pattern dielectric body 1020, for example thick SiO of 5-50nm 2Use known industrial technology to come pattern dielectric body 1020.Resulting assembly can be regarded as initial configuration.
Then, preferred methods uses insulator 1020 to form as mask and graphical nanostructure 1015, thereby forms the nanotube element 1025 shown in Fig. 8 B.The method to form the nanotube element that forms also graphical nanostructure has description in the patent documentation of institute's combination.Then, shown in Fig. 8 C, preferred methods is optionally carried out controlled isotropic etching to insulator 1020.Horizontal and the vertical dimension of insulator 1020 is reduced by this controlled etch, thereby removes insulator region 1030.This depends on etched feature, and for example the size with insulator 1020 reduces 1-150nm on all directions.This makes nanotube element 1025 expose for example controlled length in the 1-150nm scope 1035 in zone 1050, and this length is corresponding to the size that reduces of insulator 1040, shown in Fig. 8 D.
Then, the conductor 1045 of preferred approach deposition shown in Fig. 8 E makes conductor 1045 contact with the exposed region 1050 of nanotube element 1025.Conductor 1045 can have the thickness in the 5-500nm scope, and can be by such as metal and other suitable metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and constitute.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, many walls and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xConductive nitride, oxide or silicide.Also can use the conductor and the semi-conducting material of other type.
Then, preferred approach uses known industrial technology to come patterned conductor 1045 so that the conducting element 1055 shown in Fig. 8 F to be provided.Conducting element 1055 is overlapping at exposed region 1050 with nanotube element 1025.Controlled overlap length 1035 shown in Fig. 8 F is in the scope of for example 1-150nm, and corresponding to as shown in Figure 1 controlled overlap length 40, although nanotube element 1025 has different geometrical relationships with conducting element 1055 in the present embodiment.Structure shown in Fig. 8 F can be regarded as final structure.This structure can be included in following other device in greater detail.
Can use directional etch method shown in Fig. 9 A-9C to take to realize the means of different of the intermediate structure shown in Fig. 8 D.Fig. 9 A illustrates the initial configuration shown in Fig. 8 A, and it is by using known industrial technology and comprise nanostructure 1115 and comprising conformal sacrifice layer 1122 such as silicon.The thickness of layer 1122 is good control, and can be for example in the 1-150nm scope.The preferred approach of used thickness control is that the thickness of conformal sacrifice layer 1122 will be determined the controlled overlap length between nanotube element and the conducting element because in subsequent step.The assembly of Fig. 9 A can be regarded as initial configuration.
Then, preferred approach uses the known industrial technology such as RIE to come the conformal sacrifice layer 1122 of directional etch, stays sidewall areas 1130, shown in Fig. 9 B.Then, preferred approach uses insulator 1120 and sidewall spacers 1130 to come graphical nanostructure 1115 as mask together.This forms the nanotube element 1125 shown in Fig. 9 B.Deposition and graphical nanostructure have description with the method that forms the nanotube element in the patent documentation of institute's combination.
Then, preferred approach uses known industrial technology to come the remaining sidewall spacers 1130 of etching (removing), exposes nanotube element 1125 in zone 1150, shown in Fig. 9 C.In this moment of technology, the intermediate structure shown in Fig. 9 C is corresponding to the intermediate structure shown in Fig. 8 D.Insulator 1000 and 1100, conducting element 1005 and 1105, nanotube element 1025 and 1125, insulator 1040 and 1120 and controlled overlap length 1035 and 1135 correspond to each other respectively.This method is as continuing as described in respect to Fig. 8 E and 8F, to form the non-volatile 2-terminal nanotube switch (2-TNS) 1070 shown in Fig. 8 F.
Figure 10 A-10I illustrates and uses regularly etch process controlled overlapping region of formation between nanotube element and conducting element to make its another execution mode and method.Initial configuration 1600 is created shown in Figure 10 A or is provided, and it comprises it can being the substrate 1602 of silicon or any suitable material (or combination of materials).The insulator 1604 that is deposited on the substrate 1602 can make from silicon nitride or any suitable material.Metal closures 1608 is arranged in the part of substrate 1602 and insulator 1604, makes its upper surface and insulator 1604 be similar to and flush.Nanostructure 1610 is applied to structure 1600, forms intermediate structure 1612, shown in Figure 10 B.The method that applies nanostructure 1610 has description in the patent documentation of institute's combination, and followingly repeats no more for succinct purpose.
Oxide skin(coating) 1614 is applied to the intermediate structure 1612 of Figure 10 B, forms the intermediate structure 1616 among Figure 10 C.Photoresist coating (resist coat) 1618 is applied to intermediate structure 1616 and graphical, stays the intermediate structure 1620 shown in Figure 10 D.In structure 1620, the zone 1619 of nanostructure 1610 is exposed.Then, middle structure 1620 is implemented dry etching process to remove the nanostructure object area 1619 of exposure, form nanotube element 1650.Then, remove remaining photoresist, form the intermediate structure 1622 shown in Figure 10 E.Middle structure 1622 is implemented the part (as in Figure 10 E dotted line shown in) of wet etching process to remove oxide skin(coating) 1614, the nanotube element area 1626 that stays remaining oxide 1624 and expose.Zone 1626 has for example length of 1-150nm.Figure 10 F illustrates intermediate structure 1628.
Shown in Figure 10 G, deposits conductive material 1630 on intermediate structure 1628.Photoresist 1632 is deposited on the electric conducting material 1630 and graphical, forms intermediate structure 1634 thus above the nanotube element area 1626 that is exposed, to stay the zone of photoresist 1632.Electric conducting material 1630 and photoresist 1632 are implemented suitable etch process, stay remaining conducting element 1636.Conducting element 1636 is overlapping with nanotube element 1650 in zone 1638, to form intermediate structure 1640, shown in Figure 10 H.
With being applied to by the layer 1642 that copolymer or other material blends constitute in some embodiments can be the intermediate structure 1640 of inter-metal dielectric (intermetal dielectric), forms the final structure 1644 shown in Figure 10 G.Notice that insulating barrier 1604 can be used as passivation layer pre-sealed (preseal).
The method of using photoetching to make 2-TNS
Figure 11 A-11C shows and does not rely on controlled etch but use photoetching technique to form the method for controlled contact overlapping region.Show the method for the execution mode that uses photoetching technique construction drawing 4 at Figure 11 A-11C.With reference to Figure 11 A, preferred approach is depositing electrically conductive element 2605 and 2610 and it is carried out graphically on substrate 2600.Interconnection, metallic wiring layer and binding post that substrate 2600 can comprise semiconductor device, polysilicon gate and be used for contacting with other layer.Conducting element 2605 and 2610 can have the thickness of the good control in the 5-500nm scope, and can be by such as metal and other suitable metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and constitute.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, many walls and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xOther conductive nitride, oxide or silicide.Also can use the conductor and the semi-conducting material of other type.Patterned conductive element 2605 and 2610 preferred approach can be used known photoetching technique and/or known etching technique, such as reactive ion etching (RIE).
Then, still with reference to Figure 11 A, preferred approach uses known manufacturing technology to deposit and planarization insulator 2622.Zone between the insulator 2622 filled conductive elements 2605 and 2610.Then, still with reference to Figure 11 A, preferred approach contact element 2605 and 2610 and insulator 2622 on depositing nano works 2615 conformally.The method that applies nanostructure 2615 has description in the references of institute's combination, and at this for repeating no more for purpose of brevity.Assembly among Figure 11 A can be regarded as initial configuration.
Then, preferred approach uses known semi-conductor industry manufacture method to come deposition, graphical and alignment lithography layer 2620 on nanostructure 2615, shown in Figure 11 B.Determined to further describe controlled overlap length between nanotube element and the conducting element through the alignment relative of patterned lithography layer 2620 and conducting element 2610 as following.Figure 11 B can be regarded as intermediate structure.
Then, preferred approach is used through patterned lithography layer 2620 and is come graphical nanostructure 2615 as mask.This can form the nanotube 2625 shown in Figure 11 C, and finishes the making corresponding to the two-terminal switch 2670 of switch shown in Figure 4 2500.Then, preferred approach is used such as SiO 2, Si xN y, Al 2O 3Known insulator and the semiconductor manufacturing in other known insulator of using deposit protection insulating barrier (not shown).
2-TNS 2670 comprises the nanotube element 2625 overlapping with conducting element 2650 tops, forms nearly ohmic properties contact.Nanotube element 2625 is overlapping with conducting element 2610 on controlled overlap length 2640, and this length is in 1-150nm length range for example.Overlap length 2640 by through patterned lithography layer 2620 with respect to the alignment of conducting element 2610 and determine.
The execution mode of Fig. 5 can be made by using photoetching technique and conformal nanotube element, shown in Figure 12 A-13.With reference to Figure 12 A, preferred approach is depositing electrically conductive element 2305 and 2310 and it is carried out graphically on substrate 2300.Interconnection, metallic wiring layer and binding post that substrate 2300 can comprise semiconductor device, polysilicon gate and be used for contacting with other layer.Element 2305 and 2310 can have the thickness of the good control in the 5-500nm scope, and can be by such as metal and other suitable metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and constitute.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, many walls and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xOther conductive nitride, oxide or silicide.Also can use the conductor and the semi-conducting material of other type.Patterned conductive element 2305 and 2310 preferred approach can be used known photoetching technique and known etching technique, such as reactive ion etching (RIE).
Then, still with reference to Figure 12 A, preferred approach depositing nano works 2315 conformally on conducting element 2305 and 2310, thus overlapping with the part of the upper surface of the upper surface of element 2305 and 2310 and side surface and substrate 2300.The method of formation and graphical nanostructure has description in the references of institute's combination.Assembly shown in Figure 12 A can be regarded as initial configuration.
Then, preferred approach uses known semi-conductor industry manufacture method to come deposition, graphical and alignment lithography layer 2320 on nanostructure 2315, shown in Figure 12 B.Determined to further describe controlled overlap length between nano-component and the conducting element 2310 through the alignment relative of patterned lithography layer 2320 and conducting element 2310 as following.Assembly shown in Figure 12 B can be regarded as intermediate structure.
Then, preferred approach is used through patterned lithography layer 2320 and is come graphical nanostructure 2315 as mask.This can form nanotube 2325 as shown in figure 13, and finishes the making corresponding to the two-terminal nanotube switch 2370 of switch shown in Figure 5 2200.Then, preferred approach is used such as SiO 2, SiN, Al 2O 3Deposit protection insulating barrier (not shown) with the known insulator of employed other known insulator in the semiconductor manufacturing.
It is described as above to be relevant to Fig. 5, and nanotube element 2325 should the zone be defined by sidewall overlapping region 2340 (having the length roughly the same with the thickness T 1 of conducting element 2310) and controlled overlap length 2345 (for example 1-150nm) with conducting element 2310 is overlapping in zone 2350.
In the execution mode shown in Figure 12 A-13, the overlapping total length in two surfaces of nanotube element 2325 and conducting element 2310 has defined controlled overlapping region.Yet in other embodiments, in fact nanotube element 2325 can contact to define controlled overlapping region with upper surface with two of conducting element 2310, and this regional length can influence one or more electrical characteristics of resulting 2-TNS switch.
Making has the intensive 2-terminal nanotube switch of controlled overlapping region
Though above-mentioned execution mode is intensive relatively 2-TNS (promptly making on than small size a plurality of), more intensive scalable Nonvolatile nanotube two-terminal switch is possible.Make some method of intensive switch and use preferable manufacture method to make photo frame structure (picture frame structure), this can be provided for the intensive 2-TNS of many purposes.
Other described method of making intensive switch is used the preferable manufacture method of the nanotube element with vertical orientation.In these methods, the spacing between the conducting element by thickness but not lithographic equipment control.The thickness of removable (maybe can sacrifice) film is used to define vertical orientated nanotube element and the controlled overlap length between the conducting element.Perhaps, the thickness of conducting element self defines controlled overlap length.
Make the method for photo frame design 2-TNS
The U.S. Patent application No.10/864 that is entitled as " Non-volatile ElectromechanicalField Effect Devices and Circuits using Same and Methods of Manufacturing Same (circuit and the manufacture method thereof of non-volatile dynamo-electric fieldtron and this device of use) " that the photo frame designing technique of The execution mode that intensive relatively 2-TNS is provided is the photo frame design.Photo frame design have can with the symmetrical feature of the proportional convergent-divergent of metal basic principle (metal ground rule) of each technology generation of definition. nanotube three end structures was submitted on June 9th, 2004; The U.S. Patent application No.10/936 that is entitled as " Patterned Nanoscopic Articles and Methodsof Making the Same (graphical nanoscale goods and manufacture method thereof) " that submitted on September 8th, 186 and, 2004 has description in, 119. Below further describe the photo frame design example of Nonvolatile nanotube two-terminal switch with respect to Figure, 14 A-14J.
With reference to Figure 14 A, preferred approach deposits insulator 1800 on the fabric (not shown).Conducting element 1805 in the through hole 1810 forms conductive path between the conductor (not shown) below nanostructure 1815 and the insulator 1800.In this, this initial configuration is similar to the part of the structure shown in Fig. 3 B.For example, insulator 1800 among Figure 14 A and conducting element 1805 correspond respectively to insulator 915 and the conducting element 935 among Fig. 3 B.Yet different with an end that is in the nanotube element, conducting element 1805 is designed to be in the center of the following photo frame switch that further describes in the present embodiment.Insulator 1800 can be for example to use known industrial technology to be deposited on SiN, the Al of thickness in the 5-200nm scope on the flat surfaces (not shown) 2O 3Or other suitable insulative materials.Assembly shown in Figure 14 A can be regarded as initial configuration.
Then, but preferred approach deposits as shown in Figure 14B and graphical optional conductive element 1807.Optional member 1807 has the nearly ohmic properties of improving resistance and contacts but can provide between nanostructure 1815 and conducting element 1805.But optional member 1807 can be such as the metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and other suitable metal and combination thereof.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, many walls and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xOther conductive nitride, oxide or silicide.Also can use the conductor and the semi-conducting material of other type.
Then, preferred approach deposition and graphical thickness be 5-50nm such as SiO 2Insulator 1820, for example shown in Figure 14 C.Can use known industrial technology that insulator 1820 is carried out graphically.
Then, preferred approach deposition and graphical conformal sacrifice layer 1822 such as silicon are shown in Figure 14 D.Layer 1822 has the thickness such as the good control in the 1-150nm scope that uses known industrial technology control.The preferred approach of used thickness control is because the thickness of conformal sacrifice layer 1822 will be determined nanotube element in the subsequent technique and the controlled overlap length between the conducting element.
Then, preferred approach is used and is come the conformal sacrifice layer 1822 of directional etch such as the known industry method of RIE, thereby for example stays the sidewall areas 1830 shown in Figure 14 E.
Then, preferred approach uses insulator 1820 and sidewall 1830 to come graphical nanostructure 1815 as mask, thereby forms the nanotube element 1825 shown in Figure 14 F.Graphical nanostructure has description with the method that forms the nanotube element in the patent documentation of institute's combination.
Then, preferred approach uses known industrial technology to come the remaining sidewall spacers 1830 of etching (removing), thereby exposes the nanotube element 1825 in the zone 1835, shown in Figure 14 G.
Then, the conductor 1845 of preferred approach deposition shown in Figure 14 H.Conductor 1845 is overlapping with the exposed region 1835 of nanotube element 1825, shown in Figure 14 H.Conductor 1845 can have the thickness in the 5-500nm scope, and can be by such as metal and other suitable metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and constitute.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, many walls and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xOther conductive nitride, oxide or silicide.Also can use the conductor and the semi-conducting material of other type.Assembly shown in Figure 14 B-14H can be regarded as intermediate structure.
Then, preferred approach uses known industrial technology to come patterned conductor 1845 to form the conducting element 1855 shown in Figure 14 I.Conducting element 1855 is overlapping with nanotube element 1825 in exposed region 1835 with controlled overlap length 1860.Overlap length 1860 is in the scope of for example 1-150nm.Though present embodiment has different geometrical relationships between conducting element and nanotube switch, controlled overlap length 1860 is corresponding to the length 40 ' shown in Figure 1B.
Figure 14 I illustrates the cross section that comprises the photo frame 2-TNS 1870 of the supporting insulator 1800 on the (not shown) and the conducting element 1805 in the through hole 1810 at the bottom of the back lining.Figure 14 J illustrates the plane graph corresponding to the switch 1870 of the cross section shown in Figure 14 I.Can see that conducting element 1855 is overlapping with the periphery or the outward flange of nanotube element 1825, and can see that conducting element 1807 is overlapping with the central area of nanotube element 1825.Execution mode shown in Figure 14 I and 14J can be regarded as final structure.
Photo frame 2-TNS structure has many potential uses because of its density, scalable and symmetry.Except being used for memory (for example nonvolatile RAM) unit, the non-volatile two-terminal nanotube switch of photo frame can for example be used as the fuse/anti-fuse switch able to programme and re-programmable between the metal level and/or be used for reconfigurable distribution, as described in more detail below.
The method that thin film technique is used to make intensive 2-TNS
Figure 15 A-15N illustrates the right making of vertical orientated 2-TNS.With reference to Figure 15 A, preferred approach deposits such as SiO on the fabric (not shown) 2Insulating barrier 1200.In corresponding through hole 1210A and 1210B, conducting element 1205A and 1205B are set.
Then, the insulator 1212 of preferred approach deposition shown in Figure 15 A, it can be for example to use known industrial technology to be deposited on last, SiN, the Al of thickness in the 2-200nm scope in insulator 1200 surfaces 2O 3Or other suitable insulative materials.The thickness of insulator 1212 is used for defining such as conducting element 1205A and the interval between the conducting element that subsequent process steps deposits.More accurate by the comparable use photoetching in interval of using the controlled deposition bed thickness to define between the conducting element.
Then, preferred approach is used thickness the sacrifice layer 1215 such as silicon 1-150nm scope in of known industrial technology deposition shown in Figure 15 A.The preferred approach of used thickness control is because the thickness of sacrifice layer 1215 will be determined the controlled overlap length between nanotube element and the conducting element in subsequent technique.Assembly shown in Figure 15 A can be regarded as initial configuration.
Then, preferred approach uses known industrial technology to come graphical sacrifice layer 1215, forms the sacrifice insulator 1220 shown in Figure 15 B.
Then, preferred approach deposition supplementary insulation material and planarization embed in the insulator 1225, shown in Figure 15 C will sacrifice insulator 1220.Can deposit non-conformal insulating barrier and use such as the directional etch of RIE and come dark etching, wherein sacrifice insulator 1220 surfaces and serve as etching and stop.The gained surface need not very flat to keep sacrificing the THICKNESS CONTROL of insulator 1220.
Then, the graphical and directional etch sacrifice insulator 1220 of preferred approach is shown in Figure 15 D.These methods form sacrifices insulator 1230 and directional etch insulator 1225, thereby optionally stops on insulator 1200 surfaces.These methods are exposed conducting element 1205A and 1205B and are stayed opening 1245.For example can use the directional etch of selecting at bottom insulator 1200 and conducting element 1205 such as RIE.
Then, shown in Figure 15 E, preferred approach uses the method for describing in the patent documentation of institute's combination to deposit conformal nanostructure 1235.
Then, preferred approach deposits conformal protection insulator 1240 on nanostructure 1235, shown in Figure 15 F.Protection insulator 1240 can use SiN, Al 2O 3Perhaps other suitable insulative materials.
Then, preferred approach for example uses that TEOS deposits insulator 1250, shown in Figure 15 G.TEOS deposits and filling opening 1245 by using known industrial technology.SiO 2It is another example that can be used for the insulator of this purpose.Then, preferred approach uses known industrial technology that insulator 1250 is carried out planarization, shown in Figure 15 H.This exposes the zone of protection insulator 1240.
Then, preferred approach optionally removes the expose portion of protection insulator 1240.Can use directional etch, obtain the structure shown in Figure 15 I such as RIE.
Then, preferred approach be used to use for example ashing (ashing) or as remove the exposed region of nanostructure 1235 in conjunction with other proper technology described in the patent documentation.Figure 15 J illustrates the resulting structures with vertical orientated nanotube element 1255.
Then, preferred approach removes sacrifices insulator region 1230, shown in Figure 15 K.This exposes zone 1260 ends at vertical orientated nanotube element 1255.This regional length is by the thickness definition of the sacrifice insulator 1230 that is removed.
Then, the conductor 1265 of preferred approach deposition shown in Figure 15 L.Conductor 1265 is overlapping with the exposed region of nanotube element 1255.Conductor 1265 has the thickness in the 5-500nm scope, and can be by such as metal and other suitable metal of Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and constitute.Can use metal alloy such as TiAu, TiCu, TiPd, PbIn and TiN etc.
Then, preferred approach uses known industrial technology to come patterned conductor 1265 to form conducting element 1270A and the 1270B shown in Figure 15 M.Element 1270A and 1270B respectively with the terminal overlapping controlled overlap length 1280A and the 1280B separately of nanotube element 1255.These length are in 1-150nm scope for example.Controlled spacing 1285 between conducting element 1270A and the 1205A is determined by the thickness of insulator 1212, as it is described to be relevant to Figure 15 A.The assembly of Figure 15 B-15M can be regarded as intermediate structure.
Then, shown in Figure 15 N, preferred approach uses conducting element 1270A and 1270B to carry out the directional etch of the insulator 1250 selected at insulator 1225 and insulator 1240 as mask layer.Opening 1290 is created in this etching, and stops on the surface of insulator 1240.Then, reuse conducting element 1270A and 1270B carry out the insulator 1240 selected at insulator 1250 and insulator 1200 as mask layer etching.Then, with conducting element 1270A and 1270B once more with the etched mask of doing nanotube element 1255 of electing property of exposed region.This etching forms two independently the nanotube element fragment 1255A and the 1255B of vertical orientation.Conducting element 1205A and 1205B and corresponding nanotube element fragment 1255A and 1255B are overlapping, form nearly ohmic properties contact, and form conductive path between the corresponding contact (not shown) below fragment and the insulator 1200.This has formed mirror image non-volatile 2-terminal nanotube switch (2-TNS) 1295A and 1295B shown in Figure 15 N.Assembly shown in Figure 15 N can be regarded as final structure.
Vertical orientated mirror image non-volatile 2-terminal nanotube switch (2-TNS) 1295A and 1295B comprise conducting element 1270A and 1270B, these elements and corresponding nanotube element fragment 1255 overlapping corresponding controlled overlap length 1280A and 1280B.Though the geometry of present embodiment is different with shown in Figure 1B in many aspects, length 1280A and 1280B are corresponding to the controlled overlap length 40 ' shown in Figure 1B.
Make the another kind of method of intensive 2-TNS and use the preferable manufacture method that adopts vertical orientated nanotube element, wherein the controlled overlap length between nanotube element and the conducting element is determined by the sidewall areas (also can be described as concave surface) of optionally sheltering groove.People's such as Bertin U.S. Patent No. 5,096,849 teachings selectivity shelter the manufacture method in recess sidewall zone, and adopted this method to control controlled overlap length at this.Vertical orientated nanotube element can be used for forming may be more intensive 2-TNS, and can be made into following further describe right.
With reference to Figure 16 A, preferred approach deposits on substrate 2800 and patterned conductor 2805.Following interconnection, metallic wiring layer and binding post that substrate 2800 can comprise semiconductor device, polysilicon gate and be used for contacting with other layer.Conductor 2805 can have the thickness of the good control in the 5-500nm scope, and can be by such as metal and other suitable metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and constitute.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, many walls and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xOther conductive nitride, oxide or silicide.Also can use the conductor and the semi-conducting material of other type.The preferred approach of patterned conductor 2805 can be used known photoetching technique and/or known etching technique, such as reactive ion etching (RIE).
Then, preferred approach deposition and planarization insulator 2810 make the surface co-planar of insulator 2810 and conductor 2805, shown in Figure 16 A.Insulator 2810 by substrate 2800 supportings can have for example thickness in the 5-500nm scope, and can use SiO 2, SiN, Al 2O 3Or one or more dielectric layers of other suitable insulative materials.
Then, preferred approach deposition insulator 2815.Insulator 2815 can have the thickness in the 5-500nm scope, shown in Figure 16 A, and can be by SiO 2, SiN, Al 2O 3Or other suitable insulative materials constitutes.The THICKNESS CONTROL of insulator 2815 conductor 2805 upper surface and be deposited on interval between the lower surface of second conductor on insulator 2815 upper surfaces, further describe as following.
Then, still with reference to Figure 16 A, preferred approach is deposited conductor layer 2820 on insulator 2815.Conductor layer 2820 has thickness T 1 in 5-500nm scope for example by the deposit thickness that uses good control, and can be by such as metal and other suitable metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and constitute.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, many walls and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xOther conductive nitride, oxide or silicide.Also can use the conductor and the semi-conducting material of other type.Figure 28 A can be regarded as initial configuration.
Then, preferred approach deposits on conductor 2820 and patterned mask layer 2825, shown in Figure 16 B.Mask layer 2825 can be a lithography layer for example, and can come graphical by using in the semi-conductor industry known method.
Then, preferred approach removes the expose portion of (etching) conductor layer 2820, obtains the conductor 2830 shown in Figure 16 C.Known engraving method such as RIE can be used for defining conductor 2830.
Then, preferred approach deposition and planarization insulator 2835 make the upper surface of insulator 2835 and the upper surface coplane of conductor 2830, shown in Figure 16 D.Insulator 2835 can be by SiO 2, SiN, Al 2O 3Or other suitable insulative materials constitutes.Perhaps, can use the structure of in this step of this technology, not introducing insulator 2835 planarizations.Yet the planarization in this step can make things convenient for subsequent process steps.
Then, preferred approach deposition and patterned mask layer 2840 form the opening 2845 shown in Figure 16 E.Opening 2845 is corresponding to the perpendicular grooves position, with in subsequent process steps, be used for making by directly on conducting element the depositing nano tube elements form vertical Nonvolatile nanotube two-terminal switch.
Then, preferred approach directional etch conductor 2830, directional etch insulator 2815 and direct etched conductors 2805, and on the surface of substrate 2800, stop forming the groove 2860 shown in Figure 16 F.Can use any suitable directional etch manufacture method to form groove 2860, for example can use reactive ion etching (RIE).The method that forms groove 2860 is separated into two conducting element 2850A and 2850B with conductor 2830.The method that forms groove 2860 also is separated into conductor 2,805 two conducting element 2855A and 2855B.The method that forms groove 2860 also forms the corresponding groove opening in insulator 2815.
Then, preferred approach uses known semiconductor fabrication techniques to remove mask layer 2840, and this layer can be a photoresist.Then, preferred approach is at the conformal nanostructure 2865 of deposition on the bottom and sidewall of groove 2860, on the upper surface of conducting element 2650A and 2650B and on the upper surface of insulator 2835, shown in Figure 16 G.The method of depositing nano works has description in the patent documentation of institute's combination.
Then, preferred approach usefulness is insulator 2870 filling grooves 2860 of TEOS for example, make the surperficial near flatization of insulator 2860, and shown in Figure 16 H, this structure can be come further planarization by for example CMP as required.
Then, preferred approach etches opening 2875 in the insulator 2870 of grooved area, shown in Figure 16 L.This exposes the bottom section of nanostructure 2865.Opening 2865 does not need to be positioned at the groove area center, but opening 2875 should not expose the sidewall areas (part) of nanostructure 2865.The preferred approach of etching insulator TEOS or other insulator is known in the semi-conductor industry.
Then, use preferred approach use for example ashing or optionally remove the bottom section of opening 2875 bottom-exposed in conjunction with other proper technology described in the patent documentation.This has formed vertical orientated nanostructure fragment 2865A and 2865B, shown in Figure 16 I.
Then, preferred approach for example uses that the insulator of TEOS comes filling opening 2875, and carries out the insulator 2880 of near flatization to obtain near flatization, and shown in Figure 16 J, this structure can be come further planarization by for example CMP as required.
In this moment of this technology, need the controlled overlap length between vertical orientated nanostructure fragment 2865A of definition and 2865B and corresponding conducting element 2850A and the 2850B.Can use the method for optionally sheltering the recess sidewall zone (or recessed zone) that has vertical orientated nanostructure.People's such as Bertin U.S. Patent No. 5 .096 has described the prior art processes (manufacture method) of material in the selective removal silicon substrate further groove in 849.Have the adjustment manufacturing technology of the groove that comprises insulator, nanostructure and conductor as prior art U.S. Patent No. 5,096,849 described oppose side walls, preferable manufacture method is proceeded as described further below.
The insulator 2880 of preferred approach directional etch (for example using RIE) planarization also removes insulating material, until the surperficial following desired depth D1 of conducting element 2850A and 2850B, shown in Figure 16 K.This has defined the upper surface of residue groove filling insulator 2885.Also can use preferred approach with the part selective removal of nanostructure fragment 2865A and 2865B to the D1 degree of depth, form nanotube element 2890A and 2890B.Depth D 1 has defined the nanotube element 2890A that is capped (promptly protected) and the top edge of 2890B with respect to conducting element 2850A and 2850B upper surface respectively.In some embodiments, RIE removes the part of insulating material and nanostructure fragment simultaneously in same step.Yet, under the situation that the nanostructure part is not removed fully by RIE technology, can use preferred approach to use other proper technology described in the patent documentation of for example ashing or institute's combination to remove the nanostructure of exposure.
The overlapping controlled overlap length of nanostructure 2890A and 2890B and conducting element 2850A and 2850B by difference T1-D1 definition.T1 is in the scope of for example 5-500nm, and overlap length T1-D1 can be in the scope of for example 1-150nm.Assembly shown in Figure 16 B-16K can be regarded as intermediate structure.
Then, preferred approach removes remaining insulator 2885, shown in Figure 16 L.Perhaps, can add the further insulator material, and this structure is carried out the planarization (not shown).Assembly shown in Figure 16 L can be regarded as final structure.2- TNS 2895A and 2895B are that mirror image is right.Switch 2895A comprises the nanotube element 2890A that contacts to form nearly ohmic properties with the whole high superposed of conducting element 2855A one side.The overlapping controlled overlap length 2892A of nanotube element 2890A and conducting element 2850A, this length can define in the length range of for example 1-150nm and by T1-D1.Switch 2895B comprises the nanotube element 2890B that contacts to form nearly ohmic properties with the whole high superposed of conducting element 2855B one side.The overlapping controlled overlap length 2892B of nanotube element 2890B and conducting element 2850B, this length can define in the length range of for example 1-150nm and by T1-D1.Though the geometry of present embodiment is different with shown in Figure 1B in many aspects, length 2892A and 2892B are corresponding to the controlled overlap length 40 ' shown in Figure 1B.
Make the another kind of method of intensive 2-TNS and use preferable manufacture method, the controlled overlap length between wherein vertical orientated nanotube element and the conducting element is determined by the thickness of conducting element.Overlap length control and work simplification that this method can be improved.This manufacture method is used the conducting element that comprises first and second conductors that electrically contact.First conductor has controlled sidewall thickness and is overlapping with vertical orientated nanotube element on this thickness.This thickness has defined controlled overlap length.Second conductor forms the wiring layer with a plurality of switch interconnection.Vertical orientated nanotube element can form the structure of crypto set more and can be made into right as described further below.
With reference to Figure 17 A, preferred approach deposits on substrate 3000 and patterned conductor 3005.Interconnection, metallic wiring layer and binding post that substrate 3000 can comprise semiconductor device, polysilicon gate and be used for as described further below contacting with other layer.Conductor 3005 can use the deposit thickness of well-controlled and have thickness in the 5-500nm scope, and can be by such as metal and other suitable metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and constitute.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, many walls and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xOther conductive nitride, oxide or silicide.Also can use the conductor and the semi-conducting material of other type.The preferred approach of patterned conductor 3005 can be used known photoetching technique and/or known etching technique, such as reactive ion etching (RIE).
Then, preferred approach deposition and planarization insulator 3010 make the surface co-planar of insulator 3010 and conductor 3005, shown in Figure 17 A.Insulator 3010 by substrate 3000 supportings can have for example thickness in the 5-500nm scope, and can use SiO 2, SiN, Al 2O 3Or the dielectric layer of other suitable insulative materials.
Then, preferred approach deposition insulator 3015 is shown in Figure 17 A.Insulator 3015 can have for example thickness in the 5-500nm scope, and can be by SiO 2, SiN, Al 2O 3Or other suitable insulative materials constitutes.The THICKNESS CONTROL of insulator 3015 conductor 3005 upper surface and be deposited on interval between the lower surface of another conductor on insulator 3015 upper surfaces, further describe as following.
Then, still with reference to Figure 17 A, preferred approach is deposited conductor layer 3018 on insulator 3015.The thickness of conductor layer 3018 has been determined the controlled overlap length between the nanotube element and first conductor, as described further below.Conductor layer 3018 can have the thickness in 5-500nm scope for example by the deposit thickness that uses good control, and can be by such as metal and other suitable metal of Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and constitute.Can use metal alloy such as TiAu, TiCu, TiPd, PbIn etc.
Then, the conductor layer 3020 that preferred approach deposition and conductor layer 3018 electrically contact is shown in Figure 17 A.The nanotube two-terminal switch that conductor layer 3020 further describes below being used to interconnect.Conductor layer 3020 can have the thickness in 5-500nm scope for example by the deposit thickness that uses good control, and can be by such as metal and other suitable metal of Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and constitute.Can use metal alloy such as TiAu, TiCu, TiPd, PbIn, TiN etc.
Then, preferred approach deposits insulator 3022 on the upper surface of conductor layer 3020.Insulator 3022 can have for example interior thickness of 5-500nm scope, shown in Figure 17 A, and can be by SiO 2, SiN, Al 2O 3Or other suitable insulative materials constitutes.Figure 17 A can be regarded as initial configuration.
Then, preferred approach deposits on insulator 3022 and patterned mask layer 3025, shown in Figure 17 B.Mask layer 3025 can be a lithography layer for example, and by using the known method of semi-conductor industry graphical.
Then, preferred approach optionally removes the expose portion of insulator 3022 and conductor layer 3020 and 3018.Then, preferred approach removes patterned mask layer 3025, stays through patterned insulator 3022 ', conductor 3030 and conductor 3032, shown in Figure 17 C.These methods are exposed the part of insulator 3015.Can use the part that removes different layers such as the preferable known engraving method of RIE.
Then, preferred approach deposition and planarization insulator 3035 make the upper surface of insulator 3035 insulation (covering) conductors 3030, shown in Figure 17 D.The thickness of insulator 3035 on conductor 3030 upper surfaces is unimportant, and can change from for example 5nm to 500nm.Insulator 3035 can be by SiO 2, SiN, Al 2O 3Or other suitable insulative materials constitutes.
Then, preferred approach deposition and patterned mask layer 3040 form the opening 3045 shown in Figure 17 E.Opening 3045 is used to make by directly deposit the vertical Nonvolatile nanotube two-terminal switch that vertical orientated nanotube element forms on conducting element corresponding to the position of perpendicular grooves.
Then, preferred approach directional etch conductor 3030, the upper strata of exposing conductor 3032, and form conductor 3050A and 3050B, shown in Figure 17 F.Can use the preferable known engraving method of selecting at conductor 3032 such as RIE.This step is separated into two conductors with conductor 3030, i.e. conductor 3050A and 3050B.
Then, preferred approach uses known industrial technology to deposit and graphically such as SiO 2, SiN, Al 2O 3Or the conformal sacrifice layer 3047 of other insulator, shown in Figure 17 F.Layer 3047 has the thickness in 1-150nm scope for example.The THICKNESS CONTROL of sacrifice layer 3047 is unimportant, is defined as follows the controlled contact overlap length that further describes because sacrificial layer thickness is not used in.
Then, preferred approach uses the known commercial run such as RIE to come the conformal sacrifice layer 3047 of directional etch.This stays sidewall spacers 3048A and 3048B on the sidewall areas of corresponding conductor 3050A and 3050B.This also makes the upper surface part of conductor 3032 expose, shown in Figure 17 G.
Then, preferred approach directional etch conductor 3032, directional etch insulator 3015 and directional etch conductor 3005, and stop on the surface of substrate 3000, to form the groove 3060 shown in Figure 17 H.Can use and adopt the known orientation etching manufacture method of reactive ion etching (RIE) to form groove 3060.The method that forms groove 3060 is separated into two electric conductors, i.e. conductor 3052A and 3052B with conductor 3032.The method that forms groove 3060 also is separated into conductor 3,005 two conducting elements, i.e. 3055A and 3055B.The method that forms groove 3060 also forms the corresponding groove opening in insulator 3015.
Then, preferred approach is at the conformal nanostructure 3065 of deposition on the bottom and sidewall of groove 3060, on the upper surface of insulator 3035 and on the upper surface of sidewall spacers 3048A and 3048B, shown in Figure 17 I.Nanostructure 3065 can be as depositing as described in the patent documentation of institute's combination.
Then, preferred approach for example uses that the insulator of TEOS comes filling groove 3060, makes the surperficial near flatization of insulator 3070, shown in Figure 17 J.
Then, etching openings 3075 in the insulator 3070 of preferred approach in the grooved area shown in Figure 17 K exposes the bottom section of nanostructure 3065.Opening 3075 does not need to be positioned at the center of grooved area, and still, opening 3075 should not expose the sidewall areas (part) of nanostructure 3065.The preferred approach of etching insulator TEOS or other insulator is known in the semiconductor industry.
Then, preferred approach uses other proper technology described in the patent documentation of for example ashing or institute's combination to come to remove in opening 3075 bottoms (etching) nanostructure exposed region.Resulting structures with vertical orientated nanostructure fragment 3065A and 3065B is shown in Figure 17 K.
Then, preferred approach for example uses that the insulator of TEOS comes filling opening 3075, and the insulator 3080 of near flatization to obtain the near flatization shown in Figure 17 L, and this structure can be carried out further planarization by for example CMP as required.Assembly shown in Figure 17 B-17L can be regarded as intermediate structure.
Then, preferred approach removes (etching) insulator 3080 and exposes the horizontal top of nanostructure fragment 3065A and 3065B.Then, preferred approach use for example ashing or remove these horizontal top in conjunction with other proper technology described in the patent documentation, to form nanotube element 3090A and 3090B.Resulting structures with vertical orientated nanotube element 3090A and 3090B is shown in Figure 17 M.Assembly shown in Figure 17 M can be regarded as final structure.
Switch 3095A and 3095B are that mirror image is right, shown in Figure 17 M.Switch 3095A comprises the nanotube element 3090A that contacts to form nearly ohmic properties with the whole high superposed of conducting element 3055A.The whole high superposed of the sidewall of nanotube element 3090A and conductor 3052A.The height of conductor 3052A has defined controlled overlap length 3092A, and this length can be in the length range of for example 1-150nm.Switch 3095B comprises the nanotube element 3090B that contacts to form nearly ohmic properties with the whole high superposed of conducting element 3055B.The whole high superposed of the sidewall of nanotube element 3090B and conductor 3052B.The height of conductor 3052B has defined controlled overlap length 3092B, and this length can be in the length range of for example 1-150nm.Though the geometry of present embodiment different with shown in Figure 1B aspect a lot, length 3092A and 3092B are corresponding to the controlled overlap length 40 ' shown in Figure 1B.
The example making step
Initial configuration is by having the hot SiO of 30nm 2Layer 4 " the Si wafer constitutes.Graphical one group of golden alignment mark defines the array of 60 7 square millimeters of tube cores on wafer.Use O 2The ashing machine by oxygen gas plasma wafer carries out preliminary treatment in 2 minutes.The nanotube aqueous solution that will mainly comprise the 3ml of MWNT (greater than 50%) and SWNT (and bundle) is distributed on the oxide skin(coating) of Si wafer.Apply the nano tube structure thing by spin coating proceeding, this technology has in the list of references of institute's combination more fully to be described.After the nanotube spin coating, wafer is placed on the baking tray to descend to toast at 150 ℃, and measures the sheet resistance of gained nanostructure by the 4-point probe.Repeat this nanotube deposition program is lower than about 1-2k Ω up to the sheet resistance of nanostructure designated value.Between the nanotube spin coating and afterwards wafer is placed on the baking tray 150 ℃ of bakings down.
Be spin-coated on the PMMA photoresist of 400nm on the nanostructure and place on the baking tray 180 ℃ of bakings 5 minutes down.Use electron beam lithography (EBL) to come the exposed photoresist zone, and in MIBK:IPA solution, develop.This has opened the controlled length window on the nanostructure that will become the overlapping region of controlled length between nanostructure and the conducting element.Germanium bilayer on the aluminium oxide of electron beam evaporation plating (10nm/100nm respectively) is deposited and peels off.This is peeled off under 70 ℃ and finishes in NMP.By using plasma reactive ion etching (RIE) that this hard mask pattern is transferred on the nanostructure, make that the nanostructure except this active region is removed.This has defined nanotube articles.
The hard mask of NT is stripped from and (is used 10: 1 DI under the room temperature: peroxide 5 minutes) to remove Ge and the TMAH solution (Microposit 321 developer solutions, following 10 minutes of room temperature) of peeling off aluminium oxide.Deposit the PMMA photoresist once more.Use EBL in photoresist, to write conducting element pattern and as above equally development.Use electron beam evaporation plating to deposit the Pd metal of 100nm.(Ti of 2nm is as the adhesive between Pd and the oxide.) NMP finishes under 70 ℃ and peel off.Shipley 1805 photoresists are spun on the wafer.Contact photoetching machine is used for graphical bigger hard contact, and these contacts comprise pad and are connected to the trace of conducting element.Photoresist is developed in Microposit 321 developer solutions.The Au of deposition 200nm (having Ti) as the 2nm of the adhesive of Au and oxide.NMP finishes under 70 ℃ and peels off.
10 tube cores are carried out electrical testing, and between nanotube element and conducting element, having the device of the overlapping region that never overlaps onto the variation length in the overlapping scope of 500nm, measuring element rate of finished products.Each device comprises two conducting elements (or terminal).This test uses probe to carry out at wafer scale, and some wafer is cut and by installing and wire-bonded is encapsulated to ceramic DIN Chip Packaging.Use DC source ammeter (source-meter) and test these devices by use arbitrary-function generator/pulse pattern generator.For the reading device state, apply 1 deep-sited pulse and dash and measure corresponding electric current.High or unlimited resistance corresponding to " opening " state and relatively low resistance corresponding to " closure " state.
Usually the state of " opening " presents the resistance of two conducting elements of leap on the G Ω magnitude, and " closure " state presents the resistance of 10k Ω to a few M Ω magnitudes.These states can switch between two states by potential pulse.The required state of device can limit by introducing electric current during programming (PROGRAM) pulse (this device is switched to low resistance state) and set, and does not perhaps set by do not introduce restriction of current during wiping (ERASE) pulse (this device is switched to high resistance state).This electric current restriction (flexibility) of programming pulse can be set in 800nA and the amplitude of this pulse can be set in 5V.The amplitude of erasing pulse can be set in 8V.The width of programming and erasing pulse can be set in 6ms and 1 μ s respectively.These devices its " open " and " closure " state during resistance can be by the records that time be able to repeatedly up to a hundred that device is switched between " opening " and " closure " state.Device is made mistakes and is defined as resistance greater than " closure " state of 10M Ω and resistance " opening " state greater than 10M Ω.Discovery has typical fault percentage less than the overlapping device of 100nm NT-metal less than 5%.
The two-terminal nanotube switch of (as-fabricated) is just made in test
Figure 18 is the flow chart of step that the execution mode of initial device operability test 100 is shown.The operation of the 2-TNS device that test 100 assessment such as this paper illustrated embodiment are made.At first device under test (DUT) 2-TNS receives and reads (READ) operation (step 200) so that measure the state of making DUT.Read operation (step 200) is usually undertaken by the voltage that two suitable conducting elements crossing over conducting element 15 among Figure 1A for example and 20 DUT apply 1-3V.Measurement is flow through two conducting elements and such as the electric current of the nanotube element of the nanotube element 25 among Figure 1A.In some embodiments, this electric current is usually in the scope of 100nA-100 μ A.By this information, can determine the resistance between first and second conducting elements of device.The state of device is determined in this and then permission.Generally speaking, the impedance between first and second conducting elements of device is the function of device state, and also can determine by the electrical characteristics of measuring switch.
Generally speaking, preferably between first and second conducting elements, has relatively low resistor path R LOWState under making made DUT.As mentioned above, relatively low resistor path is corresponding to " closure " or " programming " device state, and wherein electric current relatively easily flows through between first and second conducting elements by the nanotube element.Relative high electrical resistance path R HIGHCorresponding to " opening " or " wiping " device state, wherein the electric current relative difficult flows through between first and second conducting elements by the nanotube element.In better embodiment, R HIGHAt least be R LOWTen times.In better embodiment, R HIGHGreater than 1M Ω.R HIGHAnd R LOWState all is non-volatile, and promptly these states remain unchanged when power is removed or lack.
If resistance R=R that read operation (step 200) is measured HIGH, then this DUT is abandoned.If resistance R=R that read operation (step 200) is measured LOW, then this DUT being implemented erase cycles (step 400), below will describe in detail more.
In erase cycles (step 400), DUT is preferably from R LOWLow resistance state switch to R HIGHHigh resistance state.If DUT is not wiped free of and remains on R LOWState, then this DUT is abandoned.If DUT is wiped free of and is transformed into R HIGHState, then this DUT is accepted and carries out program cycles (step 600), below will describe in detail more.
In the program cycles (step 600), preferably with DUT from R HIGHState switches to R LOWState.If this DUT is not programmed and remains on R HIGHState, then this DUT is abandoned.If DUT is programmed and is transformed into R LOWState, then this DUT is accepted as console switch (step 700).Hi an alternative embodiment, for example under the situation of high yied process, can suppose that DUT when just having made is console switch (step 700) and omits other step in the operational testing 100.
Figure 19 is the flow chart that the step of erase cycles (step 400) is shown.Erase cycles (step 400) preferably switches to relative higher-resistivity state with DUT from relatively low resistance states.Fig. 5 illustrates the corresponding waveform 410 of wiping.Erase cycles (step 400) is by read operation (step 210) beginning.If the resistance R=R of read operation (step 210) measuring element FIGH, then this device has been in relative higher-resistivity state.Like this, erase cycles (step 400) finishes.If the device resistance R=R that read operation (step 210) is measured LOW, then DUT is applied and wipes waveform (step 410).These waveforms preferably switch to high resistance state with DUT from low resistance state.
Between the conducting element of DUT, apply maximum voltage, be about 8V in one embodiment, as shown in figure 20.With reference to the conducting element among Figure 1A 15 and 20.This voltage causes having the corresponding current of maximum current, and this maximum current is represented successful erase operation and is 15 μ A in one embodiment.The result of erase cycles (step 400) and the polarity of erasing voltage and/or to wipe the sense of current irrelevant.The polarity of voltage among Figure 20 and the sense of current can be inverted, and can not change erase process (step 400).
In some embodiments, maximum erasing voltage is in the 8-10V scope.Wiping electric current changes on the scope of relative broad and depends on nanotube density and/or controlled overlap length in the nanotube element usually.For having the DUT that crosses over 5-10 the nanotube (or nanotube electric network) of distance between the conducting element, electric current can be in the scope of 1-30 μ A, perhaps can be higher.Be difficult to know that at the erasing pulse section start operation wipes electric current and be what,, thereby make the instantaneous electric current of wiping be difficult to know because this device reacts to this voltage on the time scale of extremely lacking.The voltage of erase cycles (step 400), electric current and success are with contacting the metallurgy marked change such as Al, W, Ti, Pd.
Yet required voltage, electric current and the time of erase cycles (step 400) can change with the controlled overlap length between nanotube element and the conducting element.With reference to the length 40 ' among Figure 1B.For waveform shown in Figure 20 410, for the exemplary overlapping dimension between 50-100nm, the erasing time is about 300ns.Generally speaking, short controlled overlap length causes the short erasing time usually.For example, erasing time in millisecond scope can be caused, and erasing time in the nano-seconds can be caused less than about 50nm or littler length greater than the controlled overlap length of about 100nm.There is such relation: the long bigger erasing voltage amplitude of overlapping common needs.
Waveform 410 among Figure 20 illustrates the DUT that uses single erasing pulse to wipe.Yet, in many non-volatile application, can use a plurality of erasing pulses successfully to wipe DUT.Counter (step 420) among Figure 19 is used for putting on DUT) the erase cycles number count.If period reaches maximum definition period, N MAX, then give up this DUT.N MAXMaximum permissible value depend on application requirements, process detail and specific implementations, but do not wish N MAXThe circulation above 10-12.
Figure 21 is the flow chart that the step of program cycles (step 600) is shown.Program cycles (step 600) preferably switches to relatively low resistance states with DUT from relative higher-resistivity state.Figure 22 A illustrates corresponding programming waveform 710.Program cycles (step 600) is by read operation (step 230) beginning.If the resistance R=R of read operation (step 230) measuring element LOW, then this device has been in low resistance state.Like this, program cycles (step 600) finishes.If the device resistance R=R that read operation (step 230) is measured HIGH, then DUT is applied programming waveform (step 610).These waveforms preferably switch to low resistance state with DUT from high resistance state.
Between the conducting element of DUT, apply maximum voltage, be about 5V in one embodiment, shown in Figure 22 A.With reference to the conducting element among Figure 1A 15 and 20.The corresponding current that has maximum current during this voltage causes programming, this maximum current are 30 μ A in one embodiment.The programming operation that this expression is successful.The result of program cycles (step 600) and the polarity of program voltage and/or program current orientation independent.The polarity of voltage among Figure 22 A and the sense of current can be inverted, and can not change programming process (step 600).
In some embodiments, program voltage is preferably in the 3-5V scope.For having the DUT that crosses over 5-20 the nanotube (or nanotube electric network) of distance between the conducting element, electric current can be in the scope of 1-60 μ A.Be difficult to know that at the erasing pulse section start operation wipes electric current and be what,, thereby make the instantaneous electric current of wiping be difficult to know because this device reacts to this voltage on the time scale of extremely lacking.The voltage of program cycles (step 600), electric current and success are with contacting metallurgy and marked change such as Al, W, Ti, Pd.
The sequential of program cycles (step 600) is the marked change with the controlled overlap length between nanotube element and the conducting element not.Length 40 ' with reference to Figure 1B.
The success of program cycles can be confirmed by read operation (step 240).In one embodiment, the electric current of about 7.5 μ A is corresponding to relatively low resistance states.Electric current at the off state during the read operation can be in the pA scope.
Waveform 710 among Figure 22 A illustrates the DUT that uses single programming pulse to programme.Yet, in many non-volatile application, can use a plurality of programming pulses DUT that successfully programmes.Counter (step 620) among Figure 21 is used for the programming pulse number that is applied to DUT is counted.If cycle-index reaches maximum predetermined cycle-index, M MAX, then give up this DUT.M MAXMaximum permissible value depend on application requirements, process detail and specific implementations, yet, do not expect M MAXThe circulation above 10 to 12.
The maximum cycle of " opening " between state and low resistance " closure " state at high resistance that DUT can bear before losing efficacy is an important parameter.The waveform 710 of Figure 22 A illustrates the voltage and current of the DUT of experience following steps: read, programme, read, wipe.Before being illustrated in and losing efficacy, uses Figure 22 B circulate the repeatedly resistance value 650 of DUT of about 5,000 ten thousand operations of these steps.Figure 22 B is illustrated in the R in about 10k Ω to 40 Ω scope LOWValue, and the R that surpasses 10G Ω HIGHValue.The dispersion of these values has reflected the resolution of measuring equipment.Value R HIGHAnd R LOWRatio surpass 5 magnitudes, make corresponding states be easy to electrical detection.
Generally speaking, the 2-TNS with two states that detect easily can be used as nonvolatile RAM (NRAM).Two states can be used as the information state of device.
Use has the nram memory array structure and preparation method thereof of the unit of a transistor and a two-terminal nanotube switch
The two-terminal nanotube switch can be used for producing nonvolatile RAM (NRAM) array that has many desired characters than memory array of the prior art, as submitting to simultaneously and having that the U.S. Patent application No. (waiting to deliver) that is entitled as " Memory Arrays Using Nanotube Articles With Reprogrammable Resistance (use has the memory array of the nanotube articles of re-programmable resistance) " with commonly-assigned us of the present invention described in detail.For example, comprise the 2-TNS array of memory devices can realize at least with up-to-date technology in the same intensive memory density of memory cell, provide nondestructive and read (NDRO) to operate, lose or the Nonvolatile data when removing power keeps and random access time fast.
As submit on the same day with the present invention and the U.S. Patent application No. (waiting to deliver) of being entitled as of commonly-assigned us " Non-Volatile Shadow Latch Using ANanotube Switch (using the non-volatile shadow latch of nanotube switch) " in greater detail, minimizing of NRAM cellar area is desirable, because the NRAM array that is made of a plurality of unit uses still less silicon area, has higher performance and consumes still less power.Memory performance strengthens and power consumption reduces, because shorter array lines has capacitive load still less.And NRAM array area still less causes littler chip size to be used for the NRAM function, causes more chip of each wafer and corresponding lower memory cost.As industrial known, can come the computing unit area with regard to minimum feature size F.Generally speaking, have some execution mode of selecting the NRAM unit of transistorized two-terminal nanotube switch for use, cell density can be similar with the cell density such as the DRAM unit of stack capacitor device DRAM unit.At this, about 8F 2The cellar area size expect that wherein F is the minimal characteristic area of given technology.For other execution mode that comprises the transistorized two-terminal nanotube switch of as above integrated selection, but density portion depends on the number of the two-terminal switch of storehouse.At this, about 4 to 6F 2The cellar area size expect that and can realize similar cell density with flash cell, this is than DRAM unit crypto set more.
In order to make better embodiment of the present invention, preferred approach comprises one or more in the method for above-mentioned manufacturing 2-TNS.Between nanotube element and conducting element, adopt the controlled overlapping thermal technology's of coming journey to design the 2-TNS of this switch though said method uses, can use any method to come thermal technology's journey to design this switch.
Generally speaking, though not shown, should be appreciated that, element in said embodiment and storage operation circuit electric connection, this circuit and above-mentioned stimulation circuit are similar.In described NRAM array, storage operation circuit and bit line, word line and program/erase/read line electric connection, this makes this circuit can select the one or more unit in the array and with above the described similar fashion of stimulation circuit is changed and/or the state of determining unit.
A kind of method of making the NRAM array is shown in Figure 23 A-23E.Figure 23 A illustrates the initial configuration 1300 with planarized upper surface 1355.Unit selecting transistor 1335 comprises source electrode 1315, drain electrode 1310 and the channel region 1330 that forms in silicon substrate 1305.The grid of making of the part of sidewall spacers 1325 and the following array word line that further describes in the array plane view 1320 uses known MOSFET device operation method to control the ON and the OFF state of channel region 1330.Being embedded into binding post 1340 in the dielectric 1350 provides from source electrode 1315 to initial configuration the conductive path of 1300 planarized surface 1355.Being embedded into binding post 1345 in the dielectric 1350 provides from 1310 power paths to the planarized surface 1355 of initial configuration 1300 that drain.
Then, the preferred approach that more than further describes forms intermediate structure 1070A and 1070B, and they are the 2-TNS devices with bottom transistor electric connection, shown in Figure 23 B.Structure 1070A is corresponding to the non-volatile two-terminal switch 1070 shown in Fig. 8 F.Structure 1070B is the mirror image with structure 1070A of corresponding distribution and interconnection.For example the conducting element 1005 of 2-TNS 1070A contacts with binding post 1340 overlapping and near ohmic properties with nanotube element 1025.This forms conductive path between the source electrode 1315 of nanotube element 1025 and transistor 1335, realize wiping among the 2-TNS 1070A, programming and/or read operation.In a similar manner 2-TNS 1070B is connected to the transistorized source electrode of 1355 belows, surface of structure 1300.
Then, preferred approach deposition and planarization insulator 1360 are shown in Figure 23 C.Insulator 1360 can be to use for example TEOS or another insulator of known semiconductor making method deposition and planarization.
Then, preferred approach is used known semiconductor making method etching vias in insulator 1360 and insulator 1000, exposes the upper surface of binding post 1345, shown in the cross section 1395 of Figure 23 D.
Then, preferred approach deposition and patterned conductive layer are to form binding post 1370 and bit line 1375 and the bit line 1375 ' shown in the corresponding flat view 1395 ' of Figure 23 E shown in the cross section 1395 of Figure 23 D.By binding post 1370 and 1345 at bit line 1375 (1375 ') with drain and form conductive path between 1310.If transistor 1335 is in the OFF state, then channel region 1330 does not form and bit line 1375 (1375 ') and nanotube element 1025 electric insulations.Yet,, form the conducting channel that connects drain electrode 1310 and source electrode 1315 if transistor 1335 is in the ON state.This forms conductive path by binding post 1370 and 1345, drain electrode 1310, raceway groove 1330, source electrode 1315, binding post 1340 and conducting element 1005 between bit line 1375 (1375 ') and nanotube element 1025.
Figure 23 D and 23E illustrate the different views of transistor 1335, and it is used to use grid 1320 to select (or not selecting) unit 1390A, and this grid still is the part of word line 1320 '.Other unit such as unit 1390B can be selected such as other word line of 1325 ' by activating.Nanotube element 1025 among conducting element 1055 ' and the unit 1390A is overlapping preferably be the controlled overlap length 1050 of 1-150nm, and the overlapping same approximately controlled overlap length 1050 of other nanotube element in while and other memory cell.Therefore, conducting element 1055 ' a plurality of unit that interconnect, and this element is as above describedly in detail being wiped, is being used in programming and/or the read operation.The non-volatile memory cells 1390A and the 1390B that comprise a selection transistor and a non-volatile two-terminal switch layout are mirror image each other.Finish the manufacturing of NRAM function (not shown) and the additional preferred approach of passivation and use known semiconductor fabrication.
Shown in memory array cross section 1395 and the corresponding memory plane view 1395 ', and obtain the cellar area of 10F2 corresponding to the memory cell 1390A of the non-volatile two-terminal switch 1070 shown in Fig. 8 F and 1390B (Figure 23 E).
Second manufacture method shown in Figure 24 and describe, by using vertical orientated SWNT works switch 1295A shown in Figure 15 N and 1295B that the cellar area of unit 1390A and 1390B is reduced about 30%, between adjacent cells, to realize source electrode-source electrode spacing more closely, following further describing.
Figure 24 A illustrates the initial configuration 1400 with planarization top structure 1455.Interval between structure 1400 spreads with respect to the source electrode shown in Figure 23 A 1315 has reduced the interval between source electrode 1415 diffusions.The nearlyer interval of source diffusion needs distinct methods to make non-volatile both-end intermediate structure, following further describing.Unit selecting transistor 1435 comprises source electrode 1415, drain electrode 1410 and the channel region 1430 that forms on silicon substrate 1405.Grid 1420 making of sidewall spacers 1425 and a following array word line part that further describes in the array plane view uses known MOSFET device operation method to control the ON and the OFF state of channel region 1430.The binding post 1440 that embeds dielectric 1450 provides the conductive path of the planarized surface 1455 of the semiconductor structure of making from source electrode 1415 to part 1400.Being embedded into binding post 1445 in the dielectric 1450 provides from 1410 conductive paths to the planarized surface 1455 of initial configuration 1400 that drain.
Then, the preferred approach that more than further describes forms and the intermediate structure 1295A and the 1295B of the two-terminal nanotube memory device of bottom transistor interconnection separately, shown in Figure 24 B.Intermediate structure 1295A and 1295B vertical orientated is used for neighboring nonvolatile both-end device is positioned at the source diffusion 1415 that tight spacing is more opened.Structure 1295A is identical with non-volatile two-terminal switch structure 1295A shown in Figure 15 N.Structure 1295B is identical with the non-volatile two-terminal switch structure 1295B shown in Figure 15 N.Structure 1295B is the mirror image with structure 1295A of corresponding distribution and interconnection.For example, the conducting element 1205A of 2-TNS 1295A contacts with binding post 1440 overlapping and near ohmic properties with nanotube element 1255A.This forms conductive path between nanotube element 1255A and transistor 1435 source electrodes 1415, realize wiping in 2-TNS 1070A, programming and/or read operation.2-TNS 1270B is connected in the transistor source of structure 1400 surperficial 1455 belows in a similar manner.
Then, preferred approach deposition and planarization insulator 1460 are shown in Figure 24 C.Insulator 1460 can be to use known semiconductor making method to deposit for example TEOS or another insulator of also planarization.
Then, preferred approach uses known method for semiconductor manufacturing to come etching vias in insulator 1460 and insulator 1200, exposes the upper surface of the binding post 1445 shown in the cross-sectional view 1495 of Figure 24 D.
Then, preferred approach deposition and patterned conductive layer form conductive connector 1470 and bit line cross section 1475 and the bit line plane graph 1475 ' as shown in corresponding flat view 1495 ' among Figure 24 E shown in Figure 24 D.Conductive path forms between bit line 1475 (1475 ') and drain electrode 1410 by binding post 1470 and 1445.If transistor 1435 is in the OFF state, then do not form channel region 1430, and bit line 1475 (1475 ') and nanotube element 1255A electric insulation.Yet,, in zone 1430, form the conducting channel that connects drain electrode 1410 and source electrode 1415 if transistor 1435 is in the ON state.This forms conductive path by binding post 1470 and 1445, drain electrode 1410, raceway groove 1430, source electrode 1415, binding post 1440 and conducting element 1205A between bit line 1475 (1475 ') and nanotube element 1255A.
Figure 24 D and 24E illustrate and are used to use grid 1420 to select the different views of the transistor 1435 of (or not selecting) unit 1490A, and this grid also is the part of word line 1420 '.Conducting element 1270A (1270A ') is overlapping with nanotube element 1255A preferably be the controlled overlap length 1275A of 1-150nm, while and the overlapping approximately uniform controlled overlap length of other nanotube element in another memory cell.Therefore, conducting element 1270A a plurality of unit that interconnect, and this unit above detailed description wipe, programme and/or read operation in use.Comprise a non-volatile memory cells 1490A who selects a transistor and a non-volatile two-terminal switch layout and 1490B and be mirror image each other.Finish the making of NRAM function (not shown) and the additional preferred approach of passivation and use known semiconductor fabrication.
Memory cell 1490A has identical about 7E with 1490B (Figure 24 E) 2Cellar area, it is than having about 10F 2The unit 1390A of cellar area and 1390B (Figure 23 E) are little by about 30%.
The cellar area of describing among Figure 25 A-E and illustrating unit 1390A shown in Figure 13 E and 1390B reduces another manufacture method of about 30%.This can make that conducting element is adjacent with the binding post that is connected bit line and drain electrode and finish by the unit 1070A of Figure 23 D and 1070B are exchanged.This realizes source electrode-source electrode spacing more closely, following further describing between adjacent cells.Need the supplementary insulation step in case the short circuit that causes because of the through hole misregistration between stop bit line and the conducting element at the upper section part branch of binding post of contact bit line, following further describing.
Figure 25 A illustrates the initial configuration 1500 with planarization top structure 1555.Unit selecting transistor 1535 comprises source electrode 1515, drain electrode 1510 and the channel region 1530 that forms on silicon substrate 1505.At the grid of making by a sidewall spacers 1525 and a following array word line part that in the array plane view, further describes 1520, control the ON and the OFF state of channel region 1530 by using known MOSFET device operation method.The binding post 1540 that embeds dielectric 1550 provides from source electrode 1515 to initial configuration the conductive path of 1500 planarized surface 1555.Being embedded into binding post 1545 in the dielectric 1550 provides from 1510 conductive paths to the planarized surface 1555 of initial configuration 1500 that drain.
Then, the preferred approach that more than further describes forms and the 2-TNS 1070A and the 1070B of bottom transistor interconnection separately, shown in Figure 25 B.Structure 1070A is corresponding to the non-volatile two-terminal switch structure 1070 shown in Fig. 8 F.Structure 1070B is the mirror image with structure 1070A of corresponding distribution and interconnection.Compare with Figure 23 B, the position of 2- TNS 1070A and 1070B is with respect to the corresponding bottom transistor of for example transistor 1535 and exchange.The conducting element 1005 of 2-TNS contacts with binding post 1540 overlapping and near ohmic properties with nanotube element 1025.This forms conductive path between nanotube element 1025 and transistor 1535 source electrodes 1515, realize wiping in 2-TNS 1070A, programming and/or read operation.
Then, preferred approach deposition and planarization insulator 1560 are shown in Figure 25 C.Insulator 1560 can be to use known semiconductor making method to deposit for example TEOS or another insulator of also planarization.
Then, preferred approach uses known method for semiconductor manufacturing to come etching vias in insulator 1560 and insulator 1000, exposes the upper surface of the binding post 1545 shown in the cross section 1595 of Figure 25 D.
Then, preferred approach deposits conformal dielectric film and uses insulator 1580 coating via openings sidewalls.If through hole does not correctly align and exposes conducting element 1055, then insulator 1580 will make the expose portion insulation of conducting element 1055 and prevent and binding post 1570 short circuits.Insulator 1580 can be SiO for example 2
Then, preferred approach deposition and patterned conductive layer form conductive connector 1570 and bit line cross section 1575 and the bit line plane graph 1575 ' shown in corresponding flat view 1595 ' among Figure 25 E shown in Figure 25 D.Conductive path forms between bit line 1575 (1575 ') and drain electrode 1510 by binding post 1570 and 1545.If transistor 1535 is in the OFF state, then do not form channel region 1530, and bit line 1575 (1575 ') and nanotube element 1025 electric insulations.Yet,, form the conducting channel that connects drain electrode 1510 and source electrode 1515 if transistor 1535 is in the ON state.This forms conductive path by binding post 1570 and 1545, drain electrode 1510, raceway groove 1530, source electrode 1515, binding post 1540 and conducting element 1005 between bit line 1575 (1575 ') and nanotube element 1025.
Figure 25 D and 25E illustrate and are used to use grid 1520 to select the different views of the transistor 1535 of (or not selecting) unit 1590A, and this grid also is the part of word line 1520 '.Other unit such as unit 1590B can be selected such as other word line of 1525 ' by activating.Conducting element 1055 (1055 ') forms also interconnection such as the switch region 1050 in a plurality of non-volatile memory cells of 1590A and 1590B (Figure 25 E), and above detailed description wipe, programme and/or read operation in use.The non-volatile memory cells 1590A and the 1590B that comprise a selection transistor and a non-volatile two-terminal switch layout are mirror image each other.Finish the making of NRAM function (not shown) and the additional preferred approach of passivation and use known semiconductor fabrication.
Unit 1590A has identical about 7F with 1590B (Figure 25 E) 2Cellar area, it is identical with the area of unit 1490A and 1490B (Figure 24 E) and than having about 10F 2The unit 1390A of cellar area and 1390B (Figure 23 E) are little by 30%.
Figure 26 has illustrated and has described the other method of making the NRAM array with 2-TNS.Non-volatile two-terminal nanotube switch 2370a is corresponding to non-volatile two-terminal nanotube switch 2370 shown in Figure 13.Shown in the memory array organization 2400 shown in cross section among Figure 26, non-volatile memory cell structure 2490A comprise with transistor 2435 interconnection and with the non-volatile 2-TNS 2370A of a bit line, first word line and one second word line interconnection, following further describing.Non-volatile memory cell structure 2490B is the mirror image of 2490A, and 2-TNS 2370B is the mirror image of 2-TNS 2370A.
Preferred approach is made NRAM array element structure 2400 as shown in figure 26.At first, preferred approach is made the initial configuration 2402 with planarized surface 2404.
Then, preferred approach uses the above preferred approach that further describes with respect to Figure 12 A-13 to be produced on the intermediate structure that comprises mirror image 2- TNS 2370A and 2370B on the surface 2404 of initial configuration 2402.
Then, preferred approach is finished the making of the nonvolatile memory chip on intermediate structure to finish nram memory array structure 2400 as shown in figure 26.
In operation, conductive path forms between bit line 2475 and drain electrode 2410 by the binding post 2445 in the dielectric 2460 and 2470.If transistor 2435 is in the OFF state, then do not form channel region 2430, and bit line 2475 and nanotube element 2325 electric insulations.Yet,, form the conducting channel that connects drain electrode 2410 and source electrode 2415 if transistor 2435 is in the ON state.This forms conductive path by binding post 2470 and 2445, drain electrode 2410, raceway groove 2430, source electrode 2415, binding post 2440 and conducting element 2305A between bit line 2475 and nanotube element 2325.
Transistor 2435 is used to use grid 2420 to select (or not selecting) unit 2490A, this grid also be with corresponding row in the part of the common word line shared of other unit.Other unit such as unit 2490B can be selected by activating other word line.In nram memory array structure 2400, conducting element 2310A is overlapping with nanotube element 2325 in the zone 2350 of controlled overlap length, simultaneously with other unit in the overlapping identical controlled overlap length of other nanotube element.Therefore, the corresponding row of the unit that conducting element 2310A interconnection is similar to 2490A is formed on the shared electrical connection of aforesaidly wiping, using in programming and/or the read operation.Non-volatile memory cells 2490A and 2490B comprise one and select a transistor and a non-volatile two-terminal switch and have to be the corresponding layout of mirror image each other.Finish the making of NRAM function (not shown) and the additional preferred approach of passivation and use known semiconductor fabrication.
Shown in Figure 27 and described the other method of making NRAM array with 2-TNS.Shown in the memory array organization 2700 shown in the cross section of Figure 27, non-volatile memory cell structure 2790A comprise with transistor 2735 interconnection and with the 2-TNS2670A of a bit line, first word line and one second word line interconnection, following further describing.
Non-volatile two-terminal nanotube switch 2670A is corresponding to the non-volatile two-terminal nanotube switch 2670 shown in Figure 11 C.Non-volatile memory cell structure 2790B is the mirror image of 2790A, and 2-TNS 2670B is the mirror image of 2-TNS 2670A.
Preferred approach is made NRAM array element structure 2700 as shown in figure 27.At first, preferred approach is made the initial configuration 2702 with planarized surface 2704.
Then, preferred approach uses the above preferred approach that further describes with respect to Figure 11 A-11C to make the intermediate structure that comprises 2-TNS 2670A and 2670B on the surface 2704 of initial configuration 2702.
Then, preferred approach is finished the making of the nonvolatile memory chip on intermediate structure to finish nram memory array structure 2700 as shown in figure 27.
In operation, conductive path forms between bit line 2775 and drain electrode 2710 by the binding post 2745 in the dielectric 2760 and 2770.If transistor 2735 is in the OFF state, then do not form channel region 2730, and bit line 2775 and nanotube element 2625 electric insulations.Yet,, form the conducting channel that connects drain electrode 2710 and source electrode 2715 if transistor 2735 is in the ON state.This forms conductive path by binding post 2770 and 2745, drain electrode 2710, raceway groove 2730, source electrode 2715, binding post 2740 and conducting element 2605A between bit line 2775 and nanotube element 2625.
Transistor 2735 is used to use grid 2720 to select (or not selecting) unit 2790A, this grid also be with corresponding row in the part of the common word line shared of other unit.Other unit such as unit 2790B can be selected by activating other word line.In nram memory array structure 2700, conducting element 2610A is overlapping with nanotube element 2625 in the zone 2640 of the controlled overlap length of for example 1-150nm, simultaneously with other unit in the overlapping approximately uniform controlled overlap length of other nanotube element.Therefore, other cell interconnection that conducting element 2610A is similar to the unit 2790A in the corresponding row in parallel forms the shared electrical connection of using in wiping of as above describing in detail, programming and/or the read operation.Each self-contained one of non-volatile memory cells 2790A and 2790B select transistor and a non-volatile two-terminal switch, and have and be the corresponding layout of mirror image each other.Finish the making of NRAM function (not shown) and the additional preferred approach of passivation and use known semiconductor fabrication.
Figure 28 describes and shows the other method of making the NRAM array with 2-TNS.Non-volatile two-terminal nanotube switch 2895A shown in Figure 28 is corresponding to the vertical orientated non-volatile two-terminal nanotube switch 2895A shown in Figure 16 L.2-TNS 2895A and transistor 2935 interconnection are shown in memory array organization 2900 in the cross section of Figure 28.Design vertical orientated switch to minimize NRAM cell size (area).
Expectation is simplified manufacture method and is reduced cellar area simultaneously and corresponding NRAM array area, because the NRAM array that is made of a plurality of unit uses still less silicon area, has higher performance and consumes still less power.Design vertical orientated switch to reduce NRAM cell size (area).
Non-volatile memory cell structure 2990A comprise with transistor 2935 interconnection and with the 2-TNS 2895A of a bit line, first word line and one second word line interconnection, further describe as following.Non-volatile memory cell structure 2990B is the mirror image of 2990A, and 2-TNS 2895B is the mirror image of 2895A.Insulator 2925 is corresponding to the insulator among Figure 16 L 2815.
Preferred approach is made NRAM array element structure 2900 as shown in figure 28.
At first, preferred approach is made the initial configuration 2902 with planarized surface 2904.
Then, preferred approach uses the above preferred approach that further describes with respect to Figure 16 A-16L to make the intermediate structure that comprises 2- TNS 2895A and 2895B on the surface 2904 of initial configuration 2902.
Then, preferred approach is finished the making of the nonvolatile memory chip on intermediate structure to finish nram memory array structure 2900 as shown in figure 28.
In operation, conductive path forms between bit line 2975 and drain electrode 2910 by the binding post 2945 in the dielectric 2960 and 2970.If transistor 2935 is in the OFF state, then do not form channel region 2930, and bit line 2975 and nanotube element 2890A electric insulation.Yet,, form the conducting channel that connects drain electrode 2910 and source electrode 2915 if transistor 2935 is in the ON state.This forms conductive path by binding post 2970 and 2945, drain electrode 2910, raceway groove 2930, source electrode 2915, binding post 2940 and conducting element 2855A between bit line 2975 and nanotube element 2890A.
Transistor 2935 is used to use grid 2920 to select (or not selecting) unit 2895A, this grid also be with corresponding row in the part of the common word line shared of other unit.Other unit such as unit 2895B can be selected by activating other word line.In nram memory array structure 2900, the controlled overlap length 2892A of conducting element 2850A and the overlapping for example 1-150nm of nanotube element 2890A, simultaneously with other unit in the overlapping approximately uniform controlled overlap length of other nanotube element.Therefore, the corresponding row of the unit that conducting element 2850A interconnection is similar to unit 2895A forms the shared electrical connection of aforesaidly wiping, using in programming and/or the read operation.
Comprising one selects the non-volatile memory cells 2895A and the 2895B of the corresponding layout of a transistor and a non-volatile two-terminal switch to be mirror image each other.Finish the making of NRAM function (not shown) and the additional preferred approach of passivation and use known semiconductor fabrication.
Figure 29 describes and shows the other method of making the NRAM array with 2-TNS.Non-volatile two-terminal nanotube switch 3095A shown in Figure 29 is corresponding to the vertical orientated non-volatile two-terminal nanotube switch 3095A shown in Figure 17 M.2-TNS 3095A and transistor 3135 interconnection are shown in memory array organization 3100 in the cross section of Figure 29.Design vertical orientated switch to minimize NRAM cell size (area).
Non-volatile memory cell structure 3190A comprise with transistor 3135 interconnection and with the 2-TNS 3095A of a bit line, first word line and one second word line interconnection, further describe as following.Non-volatile memory cell structure 3190B is the mirror image of 3190A, and non-volatile two-terminal nanotube switch arrays cellular construction 3095B is the mirror image of 3095A.
Preferred approach is made NRAM array element structure 3100 as shown in figure 31.
At first, preferred approach is made the initial configuration 3102 with planarized surface 3104.
Then, preferred approach uses the above preferred approach that further describes with respect to Figure 17 A-17M to be produced on the intermediate structure that comprises 2- TNS 3095A and 3095B on the surface 3104 of initial configuration 3102.
Then, preferred approach is finished the making of the nonvolatile memory chip on intermediate structure to finish nram memory array structure 3100 as shown in figure 29.
In operation, conductive path forms between bit line 3175 and drain electrode 3110 by the binding post 3145 in the dielectric 3160 and 3170.If transistor 3135 is in the OFF state, then do not form channel region 3130, and bit line 3175 and nanotube element 3090A electric insulation.Yet,, form the conducting channel that connects drain electrode 3110 and source electrode 3115 if transistor 3135 is in the ON state.This forms conductive path by binding post 3170 and 3145, drain electrode 3110, raceway groove 3130, source electrode 3115, binding post 3140 and conducting element 3055A between bit line 3175 and nanotube element 3090A.
Transistor 3135 is used to use grid 3120 to select (or not selecting) unit 3190A, this grid also be with corresponding row in the part of the common word line shared of other unit.Other unit such as unit 3190B can be selected by activating other word line.In nram memory array structure 3100, the controlled overlap length 3092A of conducting element 3050A and the overlapping for example 1-150nm of nanotube element 3090A, simultaneously with other unit in the overlapping approximately uniform controlled overlap length of other nanotube element.Therefore, the corresponding row of the unit that conducting element 3050A interconnection is similar to unit 3190A forms the shared electrical connection of aforesaidly wiping, using in programming and/or the read operation.
Comprising one selects the non-volatile memory cells 3095A of transistor and a non-volatile two-terminal switch and corresponding layout and 3095B to be mirror image each other.Finish the making of NRAM function (not shown) and the additional preferred approach of passivation and use known semiconductor fabrication.
Use method as herein described and execution mode, those skilled in the art can make the nonvolatile RAM of any execution mode that uses the two-terminal nanotube switch.Even can make certain NRAM array of different execution modes more than that comprises the both-end nanotube switch.
For example, the non-volatile two-terminal switch 1870 of the photo frame shown in Figure 14 I and the 14J can be substituted by 2-TNS 1070A in the NRAM unit shown in Figure 23 D and 23E and Figure 25 D and the 25E and 1070B.Can design other NRAM unit (not shown) of the advantage of utilizing the non-volatile two-terminal nanotube switch 1870 of intensive photo frame.
Non-volatile two-terminal nanotube switch as the high density of intersection points switch
Data processing, communication and client's solution have been stipulated semiconductor design, test, aging and encapsulation technology selection.The example that product covered comprises: smart card/recreation, the mobile/handheld equipment such as mobile phone, personal computer, desk-top/work station and server/large-scale computer.These requirements are driven by miniaturization, performance, power, reliability, quality and marketization time.For some application, such as aviation, parts are exposed under the adverse circumstances such as high radiation level.In some applications, the same requirement such as security feature that hardly may reverse-engineering.
The marketization time comprises quick hardware prototype and produces speed-raising, has caused the increase such as the use of the reconfigurable logic of pre-distribution of field programmable gate array (FPGA).For many application, select to replace asic chip such as the pre-distribution Reprogrammable logic of FPGA because the complexity of ASIC logic chip is increased to 15-20 (or more than) conductor level, cause cost to rise and the marketization time elongated.The density of the re-programmable logic chip of pre-distribution is more than lower its demand that makes of asic chip.Some ASIC design beginning also comprises the reconfigurable logic region that embeds pre-distribution.
The size and the electrical characteristics of the switch of pre-distribution have been determined reconfigurable logical architecture and potential use in essence.The switch of the pre-distribution of the minimum of current use is the anti-fuse-switch of non-volatile disposable programmable (OPT) both-end of the prior art between the logic line shown in Figure 30 A and 30B.Size (area) minimum of the anti-fuse of non-volatile OTP because it is the cross point switches that places between the pre-distribution logic conductor, and can be programmed to selectivity interconnection various logic conductor, shown in Figure 30 A and 30B.The reconfigurable logic function that the anti-fuse of non-volatile OTP both-end of prior art is used for designing pre-distribution is having description below with reference to document: " the Programmable Elements and Their Impact on FPGA Architecture; Performance; and Radiation Hardness (programmable element and to the influence of FPGA framework, performance and radiation hardness) " of JohnMcCollum, Altera Corp (Altera), nineteen ninety-five.The PowerPoint demonstration document of being quoted " 80_McCollum_5_PROGRAMMABLE LOGIC_ALTERA.ppt " can Http:// klabs.orgIn find.Prior art finds to use between two metal levels dielectric layer to form anti-fuse.
Figure 30 A illustrates the anti-fuse 1900 of prior art that is in ON (closure) or programming conduction state 1920.Figure 30 A illustrates the anti-fuse 1900 of prior art that is in programming OFF (opening) non-conductive state 1910 before.When anti-fuse 1900 was in conduction state 1920, conductor 1930 and 1940 was electrically connected by the resistance less than 100 ohm.At non-conductive state, conductor 1930 and 1940 is not electrically connected, and the electric capacity that is added by anti-fuse is very little, for example less than every node 1fF.
The advantage of the anti-fuse 1900 of prior art comprises by the density of using the cross point switches configuration to realize, low electric capacity, relatively low resistance and non-volatile.And, being difficult to chip is carried out " reverse-engineering " with the trace logic function, this is very important in Secure Application.This switch can bear the adverse circumstances such as high temperature and high radiation level (radiation hardness switch).
The shortcoming of the anti-fuse 1900 of prior art is included in the high voltage programming (10-12V) under the high electric current (every anti-fuse 10mA usually).And, because anti-fuse only can be programmed once (OTP), so can not reject the anti-fuse of defective fully from the Reprogrammable logical gate of pre-distribution.For these and other restriction, the programming relative complex and in system, use usually before in socket (testing apparatus), carry out.
Needed is a kind of other advantage that keeps this density and the anti-fuse 1900 of prior art, eliminate or reduce the method for shortcoming (restriction) simultaneously, especially from the reconfigurable logical gate of pre-distribution, reject defect switch and eliminate in system before the use needs of program switch in socket.
2-TNS 1870 shown in Figure 14 I and 14J and more than the non-volatile two-terminal nanotube switch of other switch of further describing can eliminate or fully reduce the limitation of the prior art switch 1900 shown in Figure 30 A and the 30B.For example 2-TNS 1870 can be used for replacing the anti-fuse-switch 1900 of prior art.2-TNS 1870 is easy to be integrated between the metal level, is little cross point switches, and most important, and as above further describing ground can be by repetitive erasing and programming.As a result, the reconfigurable logical gate of pre-distribution can assemble with the 2-TNS integrated and test fully that can be used for programming.
In some embodiments, non-volatile two-terminal nanotube switch have 8-10V erasing voltage, 4-6V program voltage and usually less than the relatively low programming of every switch 100 μ A with wipe electric current.Because these switches are easy to detect, and need compare little about 100 times electric current with the anti-fuse 1900 of prior art and programme, so, can in system environments, programme based on the reconfigurable logic chip of the pre-distribution of 2-TNS.The adverse circumstances ability to bear of nanotube and high security (hardly may " reverse-engineering ") mean that this logic can be used for harsh AEROSPACE APPLICATION and can for example programme in the space.
Figure 31 illustrates from the cross section of the Nonvolatile nanotube cross point switches 2000 that the 2-TNS shown in Figure 14 I and the 14J 1870 and conductor layer 2060 and 2055 are integrated.Conductor 2055 is corresponding to the conducting element 1855 shown in Figure 14 I, and with the controlled overlap length of nanotube element 1825 overlapping for example 1-150nm in zone 1850, as above further describe.Insulator 2002 is corresponding to the insulator 1800 shown in Figure 14 I.Conductor 2060 electrically contacts by the nanotube element 1825 of binding post 1805 with 2-TNS 1870.
When Nonvolatile nanotube cross point switches 2000 was in " closure " of relatively low resistance or ON state, conductor 2055 and 2060 was in and electrically contacts preferably relatively.When Nonvolatile nanotube cross point switches 2000 was in relative high electrical resistance " opening " or ON state, conductor 2055 and 2060 was in relative relatively poor electrically contacting.
Figure 32 A and 32B illustrate the schematic diagram 2100 of Nonvolatile nanotube cross point switches 2000 shown in Figure 31.Figure 32 A and 32B illustrate and use Nonvolatile nanotube cross point switches 2100 to replace the anti-fuse cross point switches 1900 of prior art shown in Figure 30 A and the 30B.Conductor 2130 and 2140 among Figure 32 A and the 32B corresponds respectively to the conductor 1930 and 1940 among Figure 30 A and the 30B.Figure 32 A illustrates and is in the nanotube cross point switches 2100 of just making/programme " closure " state 2110 that as above further describes." closure " state can characterize by have relatively low resistance between conductor 2130 and 2140, and this resistance is in some embodiments for example less than 100 ohm or less than 1000 ohm.Figure 32 B illustrates and is in the above nanotube cross point switches 2100 of wiping " opening " state 2120 that further describes.The state 2120 of nanotube cross point switches 2100 is corresponding to the state 1910 of the anti-fuse 1900 of prior art.The state 2110 of nanotube cross point switches 2100 is corresponding to the state 1920 of the anti-fuse 1900 of prior art.Nanotube cross point switches 2100 can be programmed, and to become state 2110 from state 2120, is wiped free of then to turn back to state 2120.Further describe as above, observed up to a million this circulations.The operation of each switch can be verified before shipment comprises the product of reconfigurable logic of pre-distribution.
Because the relatively low program current of Nonvolatile nanotube cross point switches 2100 is wiped with programing function also possible in system environments on the chip.The high voltage that more than further describes requires and can produce on chip, and is of people's such as Bertin U.S. Patent No. 6,346,846.High voltage can be programmed on the chip, and is of people's such as Bertin U.S. Patent No. 5,818,748.
Figure 14 is more than described, 31 and 32 chapters and sections have been described the two-terminal nanotube switch as the re-programmable cross point switches of high density electricity, this switch provides re-programmable contact between first conducting element of insulator upper surface and binding post (vertical filling vias) end.Second conductor that the opposite end contact of binding post contacts with same insulator lower surface.Above chapters and sections have been described the application of electric Reprogrammable cross point switches.
Two-terminal nanotube switch as the electricity of the high density between two or more wiring layers Reprogrammable nanotube through-hole interconnection
Other execution mode of electric re-programmable through-hole interconnection switch is below described.In these execution modes, the nanotube element replaces using usually the binding post through-hole interconnection such as the electric conducting material of tungsten, aluminium, copper and/or other conductor.Provide electric Reprogrammable to connect between the layer of the Nonvolatile nanotube two-terminal switch that the nanotube element further describes more than using.These execution modes are realized the electric Reprogrammable distribution interconnection after chip manufacturing and the encapsulation.
Adverse circumstances can be born based on the electric Reprogrammable through-hole interconnection of nanotube element, and high radiation level can be born such as high-temperature operation (for example above 200 degrees centigrade).High temperature holds anti-and the anti-particular characteristics that derives from the nanotube element is held in radiation.
Electric Reprogrammable interconnection based on the nanotube element provides very high fail safe.Under security consideration, it can be the electric Reprogrammable (for example open, switch ON state is wiped free of) of nanosecond or maximum microsecond levels that switch connects.Even use the retrograde engineering of hardware, these interference networks can not be determined.
Generally speaking, though not shown, should be appreciated that in the described execution mode element can with the stimulation circuit electric connection that is similar to above-mentioned stimulation circuit.In described re-programmable interconnection, stimulation circuit and conducting terminal and one or more wiring layer conducting terminal electric connection, this make this circuit can with and above at forming on the described similar fashion of stimulation circuit that changes switch between two states reprogramming ground between one or more wiring layers or disconnecting and interconnecting.
Figure 33 A-33G illustrates a kind of method of making as the two-terminal nanotube switch of the high density Reprogrammable nanotube through-hole interconnection between two wiring layers.
At first, the conductor 3205 of preferred approach deposition controlled thickness is shown in Figure 33 A.Conductor 3205 can have the thickness in the 5-500nm scope and can use such as the metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and other suitable metal and combination thereof and forms.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, many walls and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xOther conductive nitride, oxide or silicide.Also can use the conductor and the semi-conducting material of other type.
Then, preferred approach is used known industrial technology to deposit and is graphically defined conductor length, width (not shown) and opening 3215 conductor 3210 to hold the vertical through hole shown in Figure 33 A.Opening 3215 in the conductor 3210 forms by using the known RIE etching of selecting at conductor 3205, and opening 3215 is shown in the cross section of Figure 33 A.Conductor 3210 is enough wide, makes hole 3215 stay around the enough wide regional (not shown) of opening 3215 and makes conductor 3210 be still continuous conductor.Use the width and the length of coming patterned conductor 3205 with the measure-alike masks that is used to define conductor 3210, make conductor 3205 and 3210 form composite conductor, wherein the lower surface of the upper surface of conductor 3205 and conductor 3210 is in electricity and Mechanical Contact, except opening 3215.Conductor 3210 can have the thickness in the 5-500nm scope and can use such as the metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and other suitable metal and combination thereof and forms.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, many walls and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xOther conductive nitride, oxide or silicide.Also can use the conductor and the semi-conducting material of other type.
Then, preferred approach uses known commercial run to deposit and planarization insulator 3220.Insulator 3220 filling openings 3215 also provide smooth upper surface 3222, shown in Figure 33 A.Insulator 3220 can be the SiO of thickness in the 2-500nm scope 2, SiN, Al 2O 3, BeO, polyimides or other suitable insulative materials.Assembly shown in Figure 33 A can be regarded as initial configuration.
Then, preferred approach uses known industrial technology to come deposition and patterned conductor 3225 on the upper surface 3222 of insulator 3220, and planarization should the surface to form the insulator 3224 shown in Figure 33 B.Conductor 3225 has the thickness of 5-500nm scope, can use such as metal and other suitable metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and is combined to form.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, many walls and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xOther conductive nitride, oxide or silicide.Also can use the conductor and the semi-conducting material of other type.
Then, preferred approach deposition, exposure also form the mask layer with opening 3,235 3230 shown in Figure 33 B, with the position of the electric Reprogrammable through hole that further describes below defining.
Then, preferred approach directional etch conductor 3225, directional etch insulator 3220 and directional etch conductor 3205 stop on the surface of insulator 3200 to form the through hole 3240 shown in Figure 33 C.Use the known orientation etching manufacture method of reactive ion etching (RIE) to can be used for forming for example groove 3240.
Then, preferred approach is at the conformal nanostructure layer 3245 of deposition on the bottom and sidewall of groove 3240, on the upper surface of conducting element 3225A and 3225B and on the upper surface of insulator 3224, shown in Figure 33 D.The technology that the deposition of works 3245 is described in can the patent documentation by institute's combination is finished.
Then, preferred approach is used for example insulator 3250 filling grooves 3240 of TEOS of known industrial technology, makes the flattening surface of insulator 3250, shown in Figure 33 E.
Then, preferred approach uses known industry method to come graphical and etching insulator 3250, shown in Figure 33 F, exposes the part of nanostructure 3245.Use the expose portion of the removable nanostructure 3245 of etching of RIE.Nanostructure 3245 can only partly be removed by the etching step of insulator 3250, perhaps is not removed fully.
If nanostructure 3245 is not removed by whole, then preferred approach can use for example ashing or remove the expose portion of nanostructure in conjunction with other proper technology described in the references.This obtains the nanotube element 3267 shown in Figure 33 F.
Then, preferred approach deposition and planarization insulator 3260 are finished the electric Reprogrammable through-hole interconnection structure 3280 based on the Nonvolatile nanotube element shown in Figure 33 G.
The sidewall that structure 3280 is included in conductor 3225A and upper surface place and nanotube element 3267 are overlapping and form the conducting element 3225A that nearly ohmic properties contacts.The sidewall that structure 3280 also is included in conductor 3225B and upper surface place and nanotube element 3267 are overlapping and form the conducting element 3225B that nearly ohmic properties contacts.The sidewall 3275 of nanotube element 3267 is forming through hole between conducting element 3225A and the conducting element 3205A and between conducting element 3225B and the conducting element 3205B.The conductor 3210A and the 3210B that are in electricity and Mechanical Contact with corresponding conducting element 3205A and 3205B can be used for interconnection.
Nanotube element 3267 and the overlapping controlled overlap length of determining by the thickness of conducting element 3205A of the sidewall of conductor 3205A.Nanotube element 3267 is also overlapping by the definite controlled overlap length of the thickness of conducting element 3205B with the sidewall of conductor 3205B.Therefore, conducting element 3225A, nanotube element 3267 and conducting element 3205A form a 2-TNS 3270A, and conducting element 3225B, nanotube element 3267 and conducting element 3205B form the 2nd 2-TNS 3270B.
In operation, if 2-TNS 3170A is in closure state, then between conducting element 3225A and 3205A, form being electrically connected of good (for example relatively low resistance).In some embodiments, the resistance between element 3225A and the 3205A can be in the scope of for example 10-1000 Ω for " closure " state.If 2-TNS3270 is in " opening " state, then there is the electrical connection of relative relatively poor (for example high electrical resistance) relatively between conducting element 3225A and the 3205A.In some embodiments, the resistance between element 3225A and the 3205A can be in for example greater than 1M Ω or this scope greater than 1G Ω to " opening " state.Switch 3270B has corresponding state and characteristic.This paper has illustrated the general operation and the characteristic of non-volatile two-terminal nanotube switch.
Two-terminal nanotube switch as the electricity of the high density between two above wiring layers Reprogrammable nanotube through-hole interconnection
In some applications, be desirably in and have non-volatile electric Reprogrammable nanotube through-hole interconnection between the plural wiring layer.In the example that is described further below, the non-volatile electric Reprogrammable interconnection between four wiring layers is shown.Four layers only for the purpose of illustration; More level is inferior to be possible.
Figure 34 A illustrates and similar structure shown in Figure 33 C, comprises four layers of through-hole interconnection but expand to.The preferred approach that is used for the initial configuration shown in the construction drawing 33A also can be used for making have stacked conducting element 3305A-C and a plurality of wiring layers of 3310A-C shown in Figure 34 A.
Then, preferred approach is used and is deposited and patterned conductive element 3325A and 3325B in order to the similar method of those methods that defines the conductor 3225 shown in Figure 33 B.
Then, be relevant to the preferable groove formation method that the formation of the groove 3240 shown in Figure 33 C further describes more than preferred approach is used and come the groove 3330 of etching shown in Figure 34 A.
Then, preferred approach is used above and is deposited nanostructure 3340 shown in Figure 34 B in the preferred approach of describing in the patent documentation of institute's combination.
Then, the preferred approach that is relevant to insulator 3250 descriptions shown in Figure 33 E more than preferred approach is used is come the surface of filling vias 3330 and planarization insulator 3350 with insulator 3350.
Then, be relevant to expose portion that preferred approach that the nanotube element 3267 of making shown in Figure 33 F further describe comes pattern dielectric body 3350 and remove nanostructure more than preferred approach is used to form the nanotube element 3367 shown in Figure 34 D.
Then, be relevant to the method that the insulator 3260 shown in Figure 33 G further describes more than preferred approach is used and deposit and the insulator 3360 of planarization shown in Figure 34 E, thereby obtain electric Reprogrammable through-hole interconnection structure 3380 based on multi-stage non-volatile nanotube element.
The sidewall that structure 3380 is included in conducting element 3325 and upper surface place and nanotube element 3367 are overlapping and form the conducting element 3325 that nearly ohmic properties contacts.The sidewall 3375 of nanotube element 3367 forms through hole between conducting element 3325 and conductor 3305A, 3305B and 3305C.
Nanotube element 3367 and the overlapping controlled overlap length of determining by the thickness of element 3305A, 3305B and 3305C of the sidewall of conducting element 3305A, 3305B and 3305C.Therefore, conducting element 3325, nanotube element 3367 and conducting element 3305A form a 2-TNS 3370A; And conducting element 3325, nanotube element 3367 and conducting element 3305B form the 2nd 2-TNS 3370B; And conducting element 3325, nanotube element 3367 and conducting element 3305C form the 3rd 2-TNS 3370C.
In operation, if corresponding 2-TNS 3370A, 3370B and/or 3370C are in " closure " state, being electrically connected of good (for example relatively low resistance) of formation between any or all in conducting element 3325 and conducting element 3305A, 3305B, 3305C then.In some embodiments, the resistance between element 3225 and the 3305A can be in the scope of for example 10-1000 Ω for " closure " state.If corresponding 2-TNS3370A, 3370B and/or 3370C are in " opening " state, then there is the electrical connection of relative relatively poor (for example relative high electrical resistance) among conducting element 3325 and conducting element 3305A, 3305B, the 3305C between any or all.In some embodiments, the resistance between element 3325 and the 3305A can be in for example greater than 1M Ω or the scope greater than 1G Ω to " opening " state.Other switch in the structure 3380 has corresponding state and characteristic.This paper has illustrated the general operation and the characteristic of non-volatile two-terminal nanotube switch.
Whole combinations of single or multiple connections can activate between any in conductor 3325 and conductor 3305A, B and C.And, the connection among permission conductor 3305A, B and the C between any combination or a plurality of combination.
As example, with reference to electric Reprogrammable through-hole interconnection 3380 structures shown in Figure 34 E based on the Nonvolatile nanotube element, if switch A " closure ", switch B " open " and switch C " closure ", then be connected, so conducting element 3325 also is connected in element 3305C and 3310C and 3305A and 3310A owing to conducting element 3325A contacts with nearly ohmic properties with nanotube sidewall 3375.This also is connected to each other conducting element 3305C and 3305A, because switch C is in " closure " state and switch A is in " closure " state.
Two-terminal nanotube switch as the high density electricity Reprogrammable nanotube through-hole interconnection between two or more wiring layers with bigger density
Shown in Figure 33 and 34 and more than the cross section hypothesis through hole that further describes center on by conductive layer around the whole girth of via openings.Because alignment factor and to the requirement around enough conductor borderline regions of through hole is provided with bumping pad (landing pad) on each level.This bumping pad requires between the upper conductors at different levels spacing to increase and reduce distribution density.Through hole connects also and can not need bumping pad near the metal wire setting, thereby increases conductor wirings density by the spacing that reduces between the conductor.
Figure 35 illustrates the plan view 3400 of the conductor 3430 on top and one or more low conductive wires levels 3450.Top conductor line 3430 on the insulator 3410 comprises bumping pad 3440 in the position that through hole is set.Increase the spacing between the conductor on all distribution levels and require 3420 so that satisfy minimum spacing.One or more wiring layers 3450 are connected by through hole 3445 interconnection and with conductor 3430.Through hole 3445 comprises the nanotube element.Vertical view 3400 is corresponding to the cross section shown in above-described Figure 33 and 34, wherein through hole 3445 corresponding to shown in Figure 33 G based on 3380 shown in the electric Reprogrammable through-hole interconnection 3280 of Nonvolatile nanotube element and Figure 34 E.
Figure 36 is illustrated in the plan view 3500 of the conductor 3530 on top and one or more low conductor wirings levels 3550.Bumping pad has been removed that the spacing that makes between the conductor reduces and distribution density increases.Through hole 3545 is positioned at the corner by the crossing definition of top and more rudimentary conductor.Similarly can make by being relevant to the method that Figure 33 and 34 further describes more than using with 3380 among 3280 and Figure 34 E of Figure 32 G based on the electric Reprogrammable through-hole interconnection of Nonvolatile nanotube element, except the cross-sectional area of the spacing between nanotube element and the conductor littler because only there is the through hole its perimeter to contact with each conductor level.Conductor 3530 is by the upper surface of image conversion to insulator 35 10.Conductor 3650 is positioned at than contacting on the upper surface of low insulation body (not shown) and with the lower surface of insulator 3510.
Replace execution mode
In some embodiments, Single Walled Carbon Nanotube is preferable, and in other embodiments, many walls (for example double-walled) carbon nano-tube is preferable.And nanotube can combine use with nano wire.The nano wire that nano wire as herein described is meant the nano wire gathering, nano-cluster of single nano wire, non-woollen yarn knitting, twine with the nanotube that comprises nanostructure, a nanometer ball of string etc.
As mentioned above, be used to the to interconnect interconnection distribution of nanometer tube device terminal can be to have such as SiO 2, polyimides etc. the conventional distribution such as AlCu, W or Cu distribution of suitable insulating barrier.Interconnection can also be to be used for the single wall of distribution or many walls nanotube.
The present invention also can realize by other concrete form and not deviate from its spirit and inner characteristic.Therefore, embodiments of the present invention can be regarded as illustrative and be nonrestrictive.
Related application
The application relates to below with reference to document, their by awarded give assignee of the present invention and by reference integral body be incorporated into this:
" Electromechanical Memory Array Using Nanotube Ribbons and Method forMaking Same (using electromechanical memory array of nanometer pipe racks and preparation method thereof) ", the U.S. Patent application No.09/915 that submit to July 25 calendar year 2001,093, present U.S. Patent No. 6,919,592;
" Electromechanical Memory Having Cell Selection Circuitry Constructed WithNT Technology (having the dynamo-electric memory that circuit is selected in the unit that uses the NT technique construction) ", the U.S. Patent application No.09/915 that submit to July 25 calendar year 2001,173, present U.S. Patent No. 6,643,165;
" Hybrid Circuit Having NT Electromechanical Memory (hybrid circuit) " with the dynamo-electric memory of NT, the U.S. Patent application No.09/915 that submit to July 25 calendar year 2001,095, present U.S. Patent No. 6,574,130;
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" Methods of Making Electromechanical Three-Trace Junction Devices (making the method for dynamo-electric three trace bonded device) ", the U.S. Patent application No.10/033 that submit to December 28 calendar year 2001,032, present U.S. Patent No. 6,784,028;
" Nanotube Films and Articles (nanotube films and goods) ", the U.S. Patent application No.10/128 that on April 23rd, 2002 submitted to, 118, present U.S. Patent No. 6,706,402;
" Methods of Nanotube Films and Articles (methods of nanotube films and goods) ", the U.S. Patent application No.10/128 that on April 23rd, 2002 submitted to, 117, present U.S. Patent No. 6,835,591;
" Methods of Making Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements andArticles (making the method for carbon nano-tube film, layer, works, band, element and goods) "; The U.S. Patent application No.10/341 that on January 13rd, 2003 submitted to, 005;
" Methods of Using Thin Metal Layers to Make Carbon Nanotube Films; Layers; Fabrics; Ribbons; Elements and Articles (using thin metal layer to make the method for carbon nano-tube film, layer, works, band, element and goods) ", the U.S. Patent application No.10/341 that on January 13rd, 2003 submitted to, 055;
" Methods of Using Pre-formed Nanotubes to Make Carbon Nanotube Films; Layers; Fabrics; Ribbons; Elements and Articles (using preformed nanotube to make the method for carbon nano-tube film, layer, works, band, element and goods) ", the U.S. Patent application No.10/341 that on January 13rd, 2003 submitted to, 054;
" Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles (carbon nano-tube film, layer, works, band, element and goods) ", the U.S. Patent application No.10/341 that on January 13rd, 2003 submitted to, 130;
" Non-volatile Electromechanical Field Effect Devices and Circuits using Sameand Methods of Forming Same (non-volatile dynamo-electric fieldtron and use its circuit and the method that forms them) ", the U.S. Patent application No.10/864 that on June 9th, 2004 submitted to, 186;
" Devices Having Horizontally-Disposed Nanofabric Articles and Methods ofMaking the Same (having device of horizontally disposed nanostructure Tetramune and preparation method thereof) ", the U.S. Patent application No.10/776 that on February 11st, 2004 submitted to, 059, U.S. Patent Publication No.2004/0181630;
" Devices Having Vertically-Disposed Nanofabric Articles and Methods ofMaking the Same (having device of vertically disposed nanostructure Tetramune and preparation method thereof) ", the U.S. Patent application No.10/776 that on February 11st, 2004 submitted to, 572, U.S. Patent Publication No.2004/0175856;
" Patterned Nanoscopic Articles and Methods of Making the Same (goods of patterned nanoscale and preparation method thereof) ", U.S. Patent application No.10/936,119, U.S. Patent Publication No.2005/0128788.
The present invention also can realize by other concrete form and not deviate from its spirit and inner characteristic.Therefore, embodiments of the present invention can be regarded as illustrative and be nonrestrictive.

Claims (129)

1. two-terminal switch device comprises:
First conducting terminal;
With isolated second conducting terminal of described first conducting terminal;
Nanotube articles with a plurality of nanotubes, described nanotube articles be configured to described first and second conducting terminals all permanently direct physical contact; And
With the stimulation circuit of at least one electric connection of described first and second conducting terminals,
Described stimulation circuit is configured to form first voltage difference between described first conducting terminal and second conducting terminal, thereby makes the resistance of the nanotube articles between described first and second conducting terminals change to relative high electrical resistance from relatively low resistance,
Described stimulation circuit is configured to form second voltage difference between described first conducting terminal and second conducting terminal, thereby makes the resistance of the nanotube articles between described first and second conducting terminals change to relatively low resistance from relative high electrical resistance,
The described relative high electrical resistance of the nanotube articles between wherein said first and second conducting terminals is corresponding to first state of described two-terminal switch device, and the described relatively low resistance of the nanotube articles between described first and second conducting terminals is corresponding to second state of described two-terminal switch device, and
Described first and second states of wherein said two-terminal switch device are non-volatile.
2. two-terminal switch device as claimed in claim 1 is characterized in that, selects one or more thermal characteristicss of described two-terminal switch device to minimize the heat that flows out described nanotube articles.
3. two-terminal switch device as claimed in claim 1 is characterized in that, described nanotube articles is permanent overlapping with at least a portion of controlled geometrical relationship and described first conducting terminal.
4. two-terminal switch device as claimed in claim 3, it is characterized in that, described controlled geometrical relationship allows electric current to flow between described first conducting terminal and described nanotube articles, and caloric restriction flows between described first conducting terminal and described nanotube articles.
5. two-terminal switch device as claimed in claim 3 is characterized in that, described controlled geometrical relationship is the overlapping of predetermined extent.
6. two-terminal switch device as claimed in claim 5 is characterized in that, in the scope that overlaps 1-150nm of described predetermined extent.
7. two-terminal switch device as claimed in claim 5 is characterized in that, in the scope that overlaps 15-50nm of described predetermined extent.
8. two-terminal switch device as claimed in claim 5 is characterized in that, the overlapping size by described first conducting terminal of described predetermined extent defines.
9. two-terminal switch device as claimed in claim 1 is characterized in that, described first conducting terminal comprises the material that can conduct electricity and can not heat conduction.
10. two-terminal switch device as claimed in claim 1 is characterized in that, also comprises the passivation layer that is arranged on the described nanotube articles.
11. two-terminal switch device as claimed in claim 10 is characterized in that, described passivation layer comprise can not heat conduction material.
12. two-terminal switch device as claimed in claim 11 is characterized in that described passivation layer is limited in heat in the described nanotube articles.
13. two-terminal switch device as claimed in claim 1 is characterized in that, the resistance of described first state is ten times of resistance of described second state at least.
14. two-terminal switch device as claimed in claim 1 is characterized in that, the impedance of described first state is ten times of impedance of described second state at least.
15. two-terminal switch device as claimed in claim 1 is characterized in that, described first state is by the resistance characterization more than 1 megohm.
16. two-terminal switch device as claimed in claim 1 is characterized in that, described second state is by the resistance characterization below 100 kilohms.
17. two-terminal switch device as claimed in claim 1 is characterized in that, described first voltage difference comprises the electrostimulation that is chosen to provide erase operation.
18. two-terminal switch device as claimed in claim 17 is characterized in that, described erase operation comprises: described stimulation circuit is crossed over described first and second conducting terminals and is applied high voltage.
19. two-terminal switch device as claimed in claim 18 is characterized in that described high voltage is in the 3-10V scope.
20. two-terminal switch device as claimed in claim 17, it is characterized in that, described erase operation comprises: described stimulation circuit applies one or more potential pulses to form voltage difference between described first and second conducting terminals, the number of the amplitude of wherein said potential pulse, the waveform of described potential pulse and described potential pulse is enough to described two-terminal switch device is become described first state together.
21. two-terminal switch device as claimed in claim 1 is characterized in that, described second voltage difference comprises the electrostimulation that is chosen to provide programming operation.
22. two-terminal switch device as claimed in claim 21 is characterized in that, described programming operation comprises: described stimulation circuit is crossed over described first and second conducting terminals and is applied low-voltage and low current.
23. two-terminal switch device as claimed in claim 22 is characterized in that, described low-voltage is in the 1-5V scope, and low current is in the 100nA-100uA scope.
24. two-terminal switch device as claimed in claim 21, it is characterized in that, described programming operation comprises: described stimulation circuit applies one or more potential pulses to form voltage difference at described first and second conducting terminals, and the number of the amplitude of wherein said potential pulse, the waveform of described potential pulse and described potential pulse is enough to described two-terminal switch device is become described second state together.
25. two-terminal switch device as claimed in claim 1, it is characterized in that, it is poor that described stimulation circuit is configured to form tertiary voltage between described first and second conducting terminals, described the 3rd waveform has at least one wave character, and this wave character is selected as determining the state of described two-terminal switch device.
26. two-terminal switch device as claimed in claim 25 is characterized in that, described tertiary voltage difference comprises the electrostimulation that is chosen to provide nondestructive read operation.
27. two-terminal switch device as claimed in claim 26, it is characterized in that, described nondestructive read operation comprises: described stimulation circuit is crossed over described first and second conducting terminals and is applied resistance between voltage and described first and second conducting terminals of sensing, and described voltage is enough low to make it not change the state of described two-terminal switch device.
28. two-terminal switch device as claimed in claim 27 is characterized in that described voltage is less than 2V.
29. two-terminal switch device as claimed in claim 1 is characterized in that, the edge of at least one and described nanotube articles is permanent overlapping in described first and second conducting terminals.
30. two-terminal switch device as claimed in claim 1 is characterized in that, the opposing ends of described nanotube articles is permanent overlapping with each at least a portion of described first and second conducting terminals respectively.
31. two-terminal switch device as claimed in claim 1 is characterized in that, one of described first and second conducting terminals be with the peripheral permanent overlapping of described nanotube articles and with the nonoverlapping photo frame structure in the central area of described nanotube articles.
32. two-terminal switch device as claimed in claim 31 is characterized in that the central area of another of described first and second conducting terminals and described nanotube articles is permanent overlapping.
33. two-terminal switch device as claimed in claim 1 is characterized in that, described first conducting terminal has a plurality of surfaces, and wherein said nanotube articles contacts with at least a portion with upper surface and be permanent overlapping with it.
34. two-terminal switch device as claimed in claim 1 is characterized in that at least one of described first and second conducting terminals has vertical orientated feature, wherein said nanotube articles contacts with at least a portion of described vertical orientated feature.
35. two-terminal switch device as claimed in claim 1 is characterized in that, described nanotube articles comprises the nano tube structure object area that defines orientation.
36. two-terminal switch device as claimed in claim 1 is characterized in that described nanotube articles comprises double-walled nanotubes.
37. two-terminal switch device as claimed in claim 1 is characterized in that described nanotube articles comprises single-walled nanotube.
38. two-terminal switch device as claimed in claim 1 is characterized in that described nanotube articles comprises many walls nanotube.
39. two-terminal switch device as claimed in claim 1 is characterized in that described nanotube articles comprises nanotube bundle.
40. two-terminal switch device as claimed in claim 1 is characterized in that, the one or more nanotubes in the described nanotube articles are selected to has specific breathing pattern radially by force.
41. two-terminal switch device as claimed in claim 40 is characterized in that, described specific by force radially breathing pattern show as hot bottleneck.
42. two-terminal switch device as claimed in claim 40, it is characterized in that, described specific strong radially breathing pattern is corresponding to the pattern that disconnects that is connected between the nanotube and the conductor that cause in the described device, and the conductor in the wherein said two-terminal switch device comprises one or more in described first conducting terminal, described second conducting terminal, nanotube and the nanotube fragment.
43. two-terminal switch device as claimed in claim 1 is characterized in that, described first and second conducting terminals are metals.
44. two-terminal switch device as claimed in claim 43 is characterized in that, described metal comprises among Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb and the Sn at least one.
45. a double-end storage spare comprises:
First conducting terminal;
With isolated second conducting terminal of described first conducting terminal;
Nanotube articles with a plurality of nanotubes, described nanotube articles be configured to described first and second conducting terminals permanently direct physical contact; And
With the stimulation circuit of at least one electric connection in described first and second conducting terminals,
Described stimulation circuit is configured to form first voltage difference between described first conducting terminal and second conducting terminal, thereby make and open one or more gaps between the one or more nanotubes and one or more conductor in the described device, and the resistance of opening the nanotube articles between described first and second conducting terminals in described one or more gaps becomes relative high electrical resistance from relatively low resistance
Described stimulation circuit is configured to form second voltage difference between described first conducting terminal and second conducting terminal, thereby the one or more gaps in the closed described device between one or more nanotubes and the one or more conductor, and the closure in described one or more gaps makes the resistance of the nanotube articles between described first and second conducting terminals become relatively low resistance from relative high electrical resistance
Wherein, the conductor in the described device comprises one or more in described first conducting terminal, described second conducting terminal, nanotube and the nanotube fragment,
Wherein, the relative high electrical resistance of the nanotube articles between described first and second conducting terminals is corresponding to first state of described device, and the relatively low resistance of the nanotube articles between described first and second conducting terminals is corresponding to second state of described device, and
Described first and second states of wherein said double-end storage spare are non-volatile.
46. double-end storage spare as claimed in claim 45, it is characterized in that, described first voltage difference is selected as at least a portion of described nanotube articles was carried out heating to open the one or more gaps in the described conductor, so that first state of described double-end storage spare to be provided.
47. double-end storage spare as claimed in claim 46 is characterized in that, described first voltage difference is selected as by the joule heating at least a portion of described nanotube articles being carried out heating.
48. double-end storage spare as claimed in claim 45 is characterized in that, one or more thermal characteristicss of selecting described double-end storage spare are to minimize the heat that flows out described nanotube articles.
49. double-end storage spare as claimed in claim 48, it is characterized in that, thereby by arrange described nanotube articles and described first conducting terminal to minimize the heat that flows out described nanotube articles with controlled geometrical relationship, described controlled geometrical relationship caloric restriction flows out described nanotube articles and flows into described first conducting terminal.
50. double-end storage spare as claimed in claim 49 is characterized in that, described controlled geometrical relationship is the overlapping of predetermined extent.
51. double-end storage spare as claimed in claim 50 is characterized in that, described predetermined extent overlapping less than 50nm.
52. double-end storage spare as claimed in claim 48 is characterized in that, can conduct electricity and material that can not heat conduction is used for the heat that first conducting terminal minimizes the described nanotube articles of described outflow by selecting one.
53. double-end storage spare as claimed in claim 52 is characterized in that, described material has high conductivity and lower thermal conductivity.
54. double-end storage spare as claimed in claim 52 is characterized in that, selects described material from the group of conducting polymer and doped semiconductor.
55. double-end storage spare as claimed in claim 45, it is characterized in that described first waveform is selected as opening described one or more gap by forming the gap between one or more in described one or more nanotubes and described first and second conducting terminals.
56. double-end storage spare as claimed in claim 45 is characterized in that, described first voltage difference is selected as opening described one or more gap by one or more nanotubes are separated with one or more other nanotubes.
57. double-end storage spare as claimed in claim 45 is characterized in that, described first voltage difference is selected as opening described one or more gap by one or more nanotubes being broken into two or more nanotube fragments.
58. double-end storage spare as claimed in claim 45 is characterized in that, described first voltage difference is selected as comprising the threshold voltage according that surpasses described nanotube articles.
59. double-end storage spare as claimed in claim 45 is characterized in that, described first voltage difference is selected as by exciting in the described nanotube articles one or more phonon modes of one or more nanotubes to open described one or more gap.
60. double-end storage spare as claimed in claim 59 is characterized in that, described one or more phonon modes show as hot bottleneck.
61. double-end storage spare as claimed in claim 59 is characterized in that, described one or more phonon modes are optical phonon patterns.
62. double-end storage spare as claimed in claim 59 is characterized in that, the one or more nanotubes in the described nanotube articles are selected to has specific breathing pattern radially by force.
63. double-end storage spare as claimed in claim 59 is characterized in that, the one or more nanotubes in the described nanotube articles are selected to has defect mode.
64. double-end storage spare as claimed in claim 45 is characterized in that, described second voltage difference is selected as by one or more nanotubes are attracted and closed described one or more gaps to one or more conductors.
65., it is characterized in that described second voltage difference is selected as by producing electrostatic attraction one or more nanotubes being attracted to one or more conductors as the described double-end storage spare of claim 64.
66. double-end storage spare as claimed in claim 45, it is characterized in that, described first voltage difference is selected as opening the one or more gaps that characterized by gap size, and described second waveform is selected as having the next closed one or more gaps by this characterization of size of enough big amplitude.
67. double-end storage spare as claimed in claim 45 is characterized in that, also comprises the passivation layer that is arranged on the described nanotube articles.
68., it is characterized in that described passivation layer is limited in heat in the described nanotube articles as the described double-end storage spare of claim 67.
69. double-end storage spare as claimed in claim 45 is characterized in that, described double-end storage spare can switch above 1,000,000 times between described first and second states repeatedly.
70. double-end storage spare as claimed in claim 45 is characterized in that, described nanotube articles comprises the nano tube structure object area that defines orientation.
71. double-end storage spare as claimed in claim 45 is characterized in that, described nanotube articles comprises double-walled nanotubes.
72. double-end storage spare as claimed in claim 45 is characterized in that, described nanotube articles comprises single-walled nanotube.
73. double-end storage spare as claimed in claim 45 is characterized in that, described nanotube articles comprises many walls nanotube.
74. double-end storage spare as claimed in claim 45 is characterized in that, described nanotube articles comprises nanotube bundle.
75. double-end storage spare as claimed in claim 45 is characterized in that, described first and second conducting terminals are metals.
76. a selectable memory cell comprises:
Unit selecting transistor comprises grid, source electrode and drain electrode, and wherein said grid and word line electrically contact, and described drain electrode and bit line electrically contact;
The two-terminal switch device, comprise first conducting terminal, second conducting terminal and nanotube articles with a plurality of nanotubes, described nanotube articles and described first and second conducting terminals all permanently direct physical contact, the source electrode of wherein said first conducting terminal and described unit selecting transistor electrically contacts, and described second conducting terminal electrically contacts with the line that is used to carry out programing function, erase feature or read functions; And
With described word line, bit line be used to carry out the storage operation circuit of the line electric connection of programing function, erase feature or read functions,
Described storage operation circuit comprises a circuit, and this circuit is configured to generate and on described word line
Apply and select signal selecting the described memory cell of selecting, and, generate and carry out in described being used for
Apply erase signal on the line of programing function, erase feature or read functions, described erase signal has at least one waveform characteristic, this waveform characteristic is selected as making that the resistance of the nanotube articles between described first and second conducting terminals becomes relative high electrical resistance from relatively low resistance
Described storage operation circuit comprises a circuit; This circuit is configured to generate and applies the selection signal to select the described memory cell of selecting at described word line; And; Generate and apply programming signal at described line for carrying out programing function, erase feature or read functions; Described programming signal has at least one waveform characteristic; This waveform characteristic is selected as so that the resistance of the nanotube articles between described first and second conducting terminals becomes relatively low resistance from high resistance relatively
The described relative high electrical resistance of the nanotube articles between wherein said first and second conducting terminals is corresponding to the first information state of described memory cell, and the described relative high electrical resistance of the nanotube articles between described first and second conducting elements is corresponding to second information state of described memory cell, and described first and second information states are non-volatile.
77. the memory cell of selecting as claimed in claim 16, it is characterized in that, described storage operation circuit comprises a circuit, being used for generating and applying on described word line selects signal to select the described memory cell of selecting, and, generate and apply on the described line that is used to carry out programing function, erase feature or read functions and read signal, the described signal that reads has at least one waveform characteristic, and this waveform characteristic is selected as determining the information state of described memory cell.
78. as the described memory cell of selecting of claim 77, it is characterized in that, determine that the information state of described memory cell does not change the information state of described memory cell.
79. as the described memory cell of selecting of claim 76, it is characterized in that, also comprise being connected to the described a plurality of memory cells of selecting that are used to carry out programing function, erase feature or read functions line.
80., it is characterized in that one or more thermal characteristicss of described device are selected to and minimize the heat that flows out described nanotube articles as the described memory cell of selecting of claim 76.
81., it is characterized in that described nanotube articles is permanent overlapping with at least a portion of controlled geometrical relationship and described second conducting terminal as the described memory cell of selecting of claim 76.
82. as the described memory cell of selecting of claim 81, it is characterized in that, described controlled geometrical relationship allows electric current to flow between described second conducting terminal and described nanotube articles, and caloric restriction flows between described second conducting terminal and described nanotube articles.
83., it is characterized in that described controlled geometrical relationship is the overlapping of predetermined extent as the described memory cell of selecting of claim 81.
84., it is characterized in that the overlapping size by described first conducting terminal of described predetermined extent defines as the described memory cell of selecting of claim 83.
85. as the described memory cell of selecting of claim 83, it is characterized in that, in the scope that overlaps 1-150nm of described predetermined extent.
86. as the described memory cell of selecting of claim 76, it is characterized in that, one in described first and second conducting terminals is and peripheral permanent overlapping and not overlapping with the central area of the described nanotube articles photo frame structure of described nanotube articles that the central area of another in described first and second conducting terminals and described nanotube articles is permanent overlapping.
87., it is characterized in that described second conducting terminal has a plurality of surfaces as the described memory cell of selecting of claim 76, and described nanotube articles contacts with at least a portion more than a surface and permanent overlapping with it.
88., it is characterized in that described second conducting terminal has vertical orientated feature as the described memory cell of selecting of claim 76, and described nanotube articles contacts with at least a portion of described vertical orientated profile.
89., it is characterized in that the described memory cell of selecting has less than 10F as the described memory cell of selecting of claim 76 2The definition area, wherein F comprises minimum feature size, 22nm≤F≤180nm.
90., it is characterized in that described nanotube articles comprises the nano tube structure object area that defines orientation as the described memory cell of selecting of claim 76.
91., it is characterized in that described nanotube articles comprises double-walled nanotubes as the described memory cell of selecting of claim 76.
92., it is characterized in that described nanotube articles comprises many walls nanotube as the described memory cell of selecting of claim 76.
93., it is characterized in that described nanotube articles comprises nanotube bundle as the described memory cell of selecting of claim 76.
94., it is characterized in that described first and second conducting terminals are metals as the described memory cell of selecting of claim 76.
95. a re-programmable both-end fuse-antifuse device comprises:
First conductor;
Second conductor of opening with first conductor separation;
Nanotube articles has a plurality of nanotubes, described nanotube articles and described first and second conductors all permanently direct physical contact,
The nanotube density that described nanotube articles comprises is selected as making that described device can be in response to striding
Be connected on the first threshold voltage on described first and second conductors and open the electrical connection between described first and second conductors and produce the high resistance state of described nanotube articles, to form first device state, and can be in response to being connected across second threshold voltage on described first and second conductors electrical connection between closed described first and second conductors and produce the low resistance state of described nanotube articles, to form second device state
Wherein said first and second device states are non-volatile.
96., it is characterized in that described Reprogrammable both-end fuse-antifuse device can switch at least one 1,000,000 times repeatedly as the described Reprogrammable both-end of claim 95 fuse-antifuse device between described first and second device states.
97., it is characterized in that described Reprogrammable both-end fuse-antifuse device is a cross point switches as the described Reprogrammable both-end of claim 95 fuse-antifuse device.
98., it is characterized in that described nanotube articles is permanent overlapping with at least a portion of controlled geometrical relationship and described first conductor as the described Reprogrammable both-end of claim 95 fuse-antifuse device.
99. as the described Reprogrammable both-end of claim 95 fuse-antifuse device, it is characterized in that, described controlled geometrical relationship allows electric current to flow between described first conductor and described nanotube articles, and caloric restriction flows between described first conductor and described nanotube articles.
100., it is characterized in that described controlled geometrical relationship is the overlapping of predetermined extent as the described Reprogrammable both-end of claim 95 fuse-antifuse device.
101. as the described Reprogrammable both-end of claim 95 fuse-antifuse device, it is characterized in that, in described first and second conductors one is peripheral permanent overlapping and not overlapping with the central area of the described nanotube articles photo frame structure with described nanotube articles, and the second area of another and described nanotube articles in described first and second conductors is permanent overlapping.
102., it is characterized in that described nanotube articles comprises the nano tube structure object area that defines orientation as the described Reprogrammable both-end of claim 95 fuse-antifuse device.
103., it is characterized in that described nanotube articles comprises single-walled nanotube as the described Reprogrammable both-end of claim 95 fuse-antifuse device.
104., it is characterized in that described nanotube articles comprises many walls nanotube as the described Reprogrammable both-end of claim 95 fuse-antifuse device.
105., it is characterized in that described nanotube articles comprises double-walled nanotubes as the described Reprogrammable both-end of claim 95 fuse-antifuse device.
106., it is characterized in that described nanotube articles comprises nanotube bundle as the described Reprogrammable both-end of claim 95 fuse-antifuse device.
107., it is characterized in that described first and second conductors are metals as the described Reprogrammable both-end of claim 95 fuse-antifuse device.
108. the interconnection of the Reprogrammable between a plurality of wiring layers, described interconnection comprises:
First conducting terminal;
A plurality of wiring layers, each described wiring layer comprises the wiring layer conducting terminal;
Stimulation circuit is with described first conducting terminal and each wiring layer conducting terminal electric connection;
Nanotube articles with a plurality of nanotubes, described nanotube articles be aligned to described first conducting terminal permanently direct physical contact, and with each wiring layer conducting terminal permanently direct physical contact,
Described stimulation circuit is configured to form between the wiring layer conducting terminal in described first conducting terminal and a plurality of wiring layer conducting terminal first voltage difference, thereby make described nanotube articles in described a plurality of wiring layers, form interconnection between two wiring layers, described nanotube articles has relatively low resistance states
Described stimulation circuit is configured to form between the wiring layer conducting terminal in described first conducting terminal and a plurality of wiring layer conducting terminal second voltage difference, thereby make described nanotube articles disconnect in described a plurality of wiring layer the interconnection between two wiring layers, described nanotube articles has higher relatively resistance states.
109. as the interconnection of the described Reprogrammable of claim 108, it is characterized in that described stimulation circuit comprises a circuit, be used for disconnecting all interconnection in response to safety factor.
110., it is characterized in that one or more thermal characteristicss of described Reprogrammable interconnection are selected to and minimize the heat that flows out described nanotube articles as the described Reprogrammable interconnection of claim 108.
111., it is characterized in that described nanotube articles is permanent overlapping with at least a portion of controlled geometrical relationship and each described wiring layer conducting terminal as the described Reprogrammable interconnection of claim 108.
112. as the described Reprogrammable interconnection of claim 111, it is characterized in that, described controlled geometrical relationship allows electric current to flow between each described wiring layer conducting terminal and described nanotube articles, and caloric restriction flows between each described wiring layer conducting terminal and described nanotube articles.
113., it is characterized in that described controlled geometrical relationship is the overlapping of predetermined extent as the described Reprogrammable interconnection of claim 111.
114., it is characterized in that the size of overlapping each by described wiring layer conducting terminal of described predetermined extent is defined as the interconnection of the described Reprogrammable of claim 113.
115., it is characterized in that, in the scope that overlaps 1-150nm of described predetermined extent as the described Reprogrammable interconnection of claim 113.
116., it is characterized in that described nanotube articles comprises the nano tube structure object area that defines orientation as the described Reprogrammable interconnection of claim 108.
117., it is characterized in that described nanotube articles comprises double-walled nanotubes as the described Reprogrammable interconnection of claim 108.
118., it is characterized in that described nanotube articles comprises many walls nanotube as the described Reprogrammable interconnection of claim 108.
119., it is characterized in that described nanotube articles comprises nanotube bundle as the described Reprogrammable interconnection of claim 108.
120., it is characterized in that described wiring layer conducting terminal comprises metal as the described Reprogrammable interconnection of claim 108.
121. a method of making double-end storage spare, described method comprises:
First conducting terminal is set;
Be provided with and isolated second conducting terminal of described first conducting terminal;
The stimulation circuit of at least one electric connection of setting and described first and second conducting terminals, described stimulation circuit is configured to form voltage difference between described first conducting terminal and second conducting terminal;
Setting comprises the nanotube articles of a plurality of nanotubes, described nanotube articles and described first and second conducting terminals all permanently direct physical contact, each of described nanotube articles and described first and second conducting terminals is permanently overlapping, described nanotube articles is made response to the electrostimulation from described stimulation circuit, thereby described electrostimulation is applied on described first and second conducting terminals and forms voltage difference between described first conducting terminal and second conducting terminal, first voltage difference between described first conducting terminal and second conducting terminal makes described nanotube articles have relatively low resistance states, and second voltage difference between described first conducting terminal and second conducting terminal makes described nanotube articles have higher relatively resistance states.
122., it is characterized in that the isotropic etching process by regularly is placed to described nanotube with described first and second conducting terminals and contacts as the described method of claim 121.
123. as the described method of claim 121, it is characterized in that, by the directional etch process described nanotube be placed to described first and second conducting terminals and contact.
124., it is characterized in that the thickness of the overlapping and expendable film of described predetermined extent is relevant as the described method of claim 121.
125., it is characterized in that the thickness of at least one is relevant in overlapping and described first and second conducting terminals of described predetermined extent as the described method of claim 121.
126., it is characterized in that also comprise and make second memory spare, described second memory spare has the structure as the mirror image of described double-end storage spare structure as the described method of claim 121.
127., it is characterized in that as the described method of claim 121, described nanotube articles is set comprises and select one or more nanotubes to be used to form described nanotube articles, wherein said nanotube presents specific breathing pattern radially by force.
128., it is characterized in that the described memory cell of selecting has less than 6F as the described memory cell of selecting of claim 76 2The definition area, wherein F comprises minimum feature size, 22nm≤F≤180nm.
129. a two-terminal switch device comprises:
First conducting terminal;
With isolated second conducting terminal of described first conducting terminal;
Nanotube articles with a plurality of nanotubes, described nanotube articles be configured to described first and second conducting terminals all permanently direct physical contact; And
With the stimulation circuit of at least one electric connection of described first and second conducting terminals,
Described stimulation circuit is configured to form first voltage difference between described first conducting terminal and second conducting terminal, thereby makes the resistance of the nanotube articles between described first and second conducting terminals change to relative high electrical resistance from relatively low resistance,
Described stimulation circuit is configured to form second voltage difference between described first conducting terminal and second conducting terminal, thereby makes the resistance of the nanotube articles between described first and second conducting terminals change to relatively low resistance from relative high electrical resistance.
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