CN101241860A - 制造金属氧化物半导体场效应晶体管的方法 - Google Patents
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Abstract
一种制造金属氧化物半导体场效应晶体管(MOSFET)的方法,通过以下步骤形成晶体管:在衬底上方将栅结构图案化;在栅结构的侧面上形成间隔件;在栅叠层的交替的侧面,在衬底内形成导体区域。栅结构和导体区域形成晶体管。为了减少大功率等离子引入的损伤,本方法最初对晶体管施加第一功率水平的等离子以在晶体管上方形成第一应力层。在施加第一低功率等离子之后,本方法对晶体管施加具有第二功率水平的第二等离子以在第一应力层上方形成第二应力层。第二功率水平比第一功率水平高(例如,至少高5倍)。
Description
技术领域
本发明的实施方式涉及金属氧化物半导体场效应晶体管(MOSFETS),更为具体的,涉及在不损坏下方的晶体管并不牺牲其性能的前提下形成应力层(stressing layer)的改进方法。
背景技术
现有的逻辑晶体管在加工的很多阶段中受到等离子损伤。这种等离子损伤由于更多的等离子加工工艺的使用而加重,例如,随着通过增强的空穴载流子迁移率来提高逻辑性能的等离子生成的应力衬垫(stress liner)的导入。基于大功率高密度的等离子的膜(HDP)优于常规的等离子增强化学气相淀积(PECVD)膜,原因是减少了被隔离的和内嵌的器件之间的性能偏差。但是,晶体管暴露于高能等离子工艺有时会影响晶体管的整体可靠性。事实上,有时在可靠性以及性能上会有明显降低,如厚栅氧化物击穿、增强的偏置温度不稳定性(NBTI),以及因这样的基于大功率等离子的膜造成的其他问题。
发明内容
鉴于前述问题,本发明的实施方式提供了一种制造金属氧化物半导体场效应晶体管(MOSFET)的方法。该方法通过以下步骤形成晶体管:在衬底上方对栅结构进行图案化;在栅结构的侧面形成隔离件;在栅叠层的交替的侧面,在衬底内形成导体区域。栅结构和导体区域构成晶体管。为了减少大功率等离子引入的损伤,本方法最初对晶体管施加具有第一功率水平的等离子以在晶体管上方形成第一应力层。在施加第一较低功率等离子之后,本方法对晶体管施加具有第二功率水平的第二等离子以在第一应力层上方形成第二应力层。第二功率水平比第一功率水平高(例如,至少高5倍)。
本发明的特征之一为,第一等离子和第二等离子具有相同的化学结构(但以不同的功率水平施加)。这样,第一应力层和第二应力层包含相似的材料。等离子工艺都包含高密度等离子(HDP)工艺。
本发明实施方式的这些以及其他方面,在结合下述说明以及附图的基础上,将得到更好的理解。但是应该明白,以下说明尽管指出了本发明的优选实施方式以及其许多细节,但仅是说明性的,而本发明并不限于此。在本发明的实施方式范畴内在不偏离本发明主旨的前提下,可以对本发明做出各种改动和修正,本发明的实施方式包括所有类似修正。
附图说明:
本发明的实施方式根据以下详细说明参照附图将得到更好的理解,其中:
图1为说明本发明实施方法的流程图。
图2给出了根据本发明的具有两个应力层的晶体管的示意图。
具体实施方式
本发明的实施方式和各种特征及其优点详细在参考附图所示和后述详细说明的非限制性实施方式的基础上得到充分解释。应注意附图中给出的本特征并非按比例画出。为了避免不必要地妨碍本发明的实施方式,省略了对公知的部件和加工工艺的说明。此处所用的例子仅用于帮助理解,其中本发明的实施方式可实现,并进而允许本领域技术人员实施本发明的实施方式。因此,示例不应被解释为对本发明的实施方式的范围的限定。
如上所述,晶体管在许多工艺阶段暴露于潜在的等离子损伤。该等离子损伤由于更多的等离子加工工艺的使用而加重,例如,伴随着等离子生成的应力衬垫的导入。基于大功率高密度的等离子的膜(HDP)优于传统的等离子增强化学气相淀积(PECVD),原因是减少了被隔离的和内嵌的器件之间的性能偏差。但是,晶体管暴露于大功率等离子工艺有时会影响晶体管的整体可靠性。
为了克服这样的问题,本发明使用了双层方法,而不采用淀积单层应力产生膜。在第一步骤,在低功率工艺下淀积应力衬垫薄层。此后,在大功率工艺下淀积相对较厚的应力衬垫。该方法提高了晶体管的整体可靠性而不影响其性能。
更为具体的,整体可靠性得到了提高,这是因为,当形成了较低功率初始应力衬垫时,它对于晶体管的脆弱区域的损伤的可能性较低。较低的功率水平比较高的功率水平产生更少的损伤。晶体管然后通过第一较低功率应力衬垫的保护,防止被第二大功率等离子膜所损伤。这样,本发明享有与第二大功率应力衬垫相关的性能提高的所有好处,而不受等离子导致的损伤。第一低功率应力衬垫被制造得足够厚以保护晶体管的脆弱部分,但又被保持得足够薄以使得来自第二应力衬垫的应力可以在晶体管内产生应力。这样,低功率膜通过防止暴露于后续大功率等离子工艺以保护晶体管,从而提高晶体管的可靠性。
如图1中的流程图所示,本发明的实施方式提供了一种制造MOSFET或者其他具有这种有利特征的类似晶体管结构的方法。本方法通过在衬底100上方来图案化栅结构而产生晶体管。本领域一般技术人员公知,这样的栅结构可包括栅氧化物、栅导体、栅盖(getecap)等。接着,在栅结构的侧面上形成间隔件(例如氧化物或者氮化物等)(102),并在栅叠层的交替的侧面(alternate sides)的衬底内形成导体区域(例如源、漏等)(104)。此外,形成该结构的必要工艺在本领域是公知的。形成场效应晶体管和应力产生层的细节是本领域公知的,为了简洁省略了该结构和相关加工工艺的细节。例如,参见美国专利申请公开2006/0160317和2006/0214225(通过引用包含于此),其中讨论了详细讨论了晶体管和应力层的细节。栅结构和导体区域构成晶体管。
为了减少大功率等离子引入的损伤,本方法最初对晶体管施加了具有第一功率水平的第一等离子以在晶体管上形成第一应力层(106)。在施加第一较低功率等离子之后,本方法对晶体管施加具有第二功率水平的第二等离子以在第一应力层上方形成第二应力层(108)。
第一低功率应力衬垫被制造得足够厚以保护晶体管的脆弱部分,但又被保持得足够薄以使得来自第二应力衬垫的应力可以在晶体管内产生应力。本发明不限于第一或者第二层的任何具体厚度尺寸。而是,每个不同类型的晶体管会受益于可通过例行实验发现的第一和第二层的具体厚度,并可根据设计者对应力和损伤最小化的要求而改变。
类似地,所用具体功率水平将视晶体管尺寸及其设计、所需特性以及其他事项变化,且本发明不限于任何特定的功率水平。但是,第一和第二功率水平之间的差异不是微小的差异,而是本质上的。例如第二功率水平至少为第一功率水平的5倍。因此,例如,如果第一功率水平为5W,第二功率水平至少为25W并可以实质地更高。然后在步骤110中,可以形成各种接触、隔离区域等以完成晶体管结构。
本发明的特征之一为,第一等离子和第二等离子具有相同的化学结构(但以不同的功率水平实施)。这样,第一应力层和第二应力层包含类似的材料(例如二者均提供压缩力或者二者均提供伸张力)。等离子工艺均包含高密度工艺(HDP)。
形成的结构示于图2。更具体地,200表示衬底,202、204代表栅结构。204包含栅导体而202包含栅氧化物。如上所述,栅结构的形成对应于流程图中地步骤100。206代表在流程图的步骤102中形成的间隔件。导体区域表示为280并对应于流程图的步骤104。210代表第一低功率应力引入层并形成于步骤106。212代表形成于步骤108的第二大功率应力引入层。
这样,如上所示,此类晶体管的整体可靠性得到提高,这是因为,当形成了较低功率初始应力衬垫时,它对于晶体管的脆弱区域的损伤的可能性较低。较低的功率水平比较高的功率水平产生更少的损伤。晶体管然后通过第一低功率应力衬垫的保护,防止被第二大功率离子膜损伤。这样,本发明享有与第二大功率应力衬垫相关的性能提高的所有好处,而不受等离子导致的损伤。
以上所述具体实施方式将充分展示本发明的一般性质,在不偏离一般概念的前提下,其他人可以通过运用当前技术很容易地修正和/或将该具体实施方式适用于不同的应用,因此这些适应性改动和修正应该被理解为在公开的实施方式的等价的含义和范畴之内。要理解,此处所采用的措辞或术语为用于说明之目的而非限定性的。因此,尽管本发明的实施方式就优选实施方式而言已经得到说明,本领域技术容易认识到,在不偏离本发明的主旨和所附的权利要求的范围的前提下,本发明的实施方式可以通过修正得到实现。
Claims (6)
1.一种制造金属氧化物半导体场效应晶体管(MOSFET)的方法,所述方法包括以下步骤:
在衬底上方将栅结构图案化;
在所述栅结构的侧面上形成间隔件;
在所述栅叠层的交替的侧面,在所述衬底内形成导体区域,其中所述栅结构和所述导体区域包含晶体管;
对所述晶体管施加具有第一功率水平的第一等离子以在所述晶体管上方形成第一应力层;
对所述晶体管施加具有第二功率水平的第二等离子以在所述第一应力层上方形成第二应力层,
其中所述第二功率水平比所述第一功率水平高。
2.权利要求1中记载的方法,其中,
所述第一等离子和所述第二等离子具有相同的化学结构和不同的功率水平,以使所述第一应力层和所述第二应力层包含相似的材料。
3.权利要求1中记载的方法,其中,
所述施加所述第一等离子的步骤和所述施加第二等离子的步骤包括高密度等离子(HDP)工艺。
4.一种制造金属氧化物半导体场效应晶体管(MOSFET)的方法,所述方法包括以下步骤:
在衬底上方将栅结构图案化;
在所述栅结构的侧面上形成间隔件;
在所述栅叠层的交替的侧面,在所述衬底内形成导体区域,其中所述栅结构和所述导体区域包含晶体管;
对所述晶体管施加具有第一功率水平的第一等离子以在所述晶体管上方形成第一应力层;
对所述晶体管施加具有第二功率水平的第二等离子以在所述第一应力层上方形成第二应力层,
其中所述第二功率水平至少为所述第一功率水平的5倍。
5.权利要求4中记载的方法,其中,
所述第一等离子和所述第二等离子具有相同的化学结构和不同的功率水平,以使所述第一应力层和所述第二应力层包含相似的材料。
6.权利要求4中记载的方法,其中,
所述施加第一等离子的步骤和所述施加第二等离子的步骤包括高密度等离子(HDP)工艺。
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US11/616,147 US7521308B2 (en) | 2006-12-26 | 2006-12-26 | Dual layer stress liner for MOSFETS |
US11/616,147 | 2006-12-26 |
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US8106462B2 (en) * | 2010-01-14 | 2012-01-31 | International Business Machines Corporation | Balancing NFET and PFET performance using straining layers |
US9023696B2 (en) | 2011-05-26 | 2015-05-05 | Globalfoundries Inc. | Method of forming contacts for devices with multiple stress liners |
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US7115954B2 (en) * | 2000-11-22 | 2006-10-03 | Renesas Technology Corp. | Semiconductor device including stress inducing films formed over n-channel and p-channel field effect transistors and a method of manufacturing the same |
US7022561B2 (en) * | 2002-12-02 | 2006-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS device |
US8008724B2 (en) * | 2003-10-30 | 2011-08-30 | International Business Machines Corporation | Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers |
DE102004057762B4 (de) * | 2004-11-30 | 2010-11-11 | Advanced Micro Devices Inc., Sunnyvale | Verfahren zur Herstellung einer Halbleiterstruktur mit Ausbilden eines Feldeffekttransistors mit einem verspannten Kanalgebiet |
US20060160371A1 (en) | 2005-01-18 | 2006-07-20 | Metz Matthew V | Inhibiting growth under high dielectric constant films |
US7388278B2 (en) | 2005-03-24 | 2008-06-17 | International Business Machines Corporation | High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methods |
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KR20080060142A (ko) | 2008-07-01 |
KR101286269B1 (ko) | 2013-07-15 |
US20080153217A1 (en) | 2008-06-26 |
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