CN101198930B

CN101198930B - System and method for supporting data value coherence in computer system

Info

Publication number: CN101198930B
Application number: CN2005800501216A
Authority: CN
Inventors: M·温伯格; L·温伯格; N·O·尼尔森; M·赫梅特克
Original assignee: Telefonaktiebolaget LM Ericsson AB
Current assignee: Telefonaktiebolaget LM Ericsson AB
Priority date: 2005-04-13
Filing date: 2005-04-13
Publication date: 2011-07-27
Anticipated expiration: 2025-04-13
Also published as: JP2008536236A; CA2604573A1; EP1869551A1; CN101198930A; US20080178157A1; US8095915B2; WO2006110069A1

Abstract

The invention concerns the general data value problem, and especially the residence problem in a computer system when executing program code translated from a source code representation (10) into a target code representation (30). A basic idea of the invention is to associate references to target data value containers (40) in the target code with corresponding address information of original data value containers (20) of the source code during program code translation, and store information related to target code instructions together with associated address information of original data value containers at execution of target code to uphold a data value view (50) of the original source code representation. In this way, tracking of data values of original source code (10) at execution of translated target code (30) in a target system is supported in a highly efficient manner.

Description

Be used for supporting the system and method for the data value consistency of computer system

Technical field

Present invention relates in general to field of computer technology, relate more particularly to computing machine microarchitecture, compiler technologies and debugging technique, the problem of the data value consistency in the program code computer-chronograph system of especially serving as interpreter.

Background technology

The field of computing machine microarchitecture itself relates to the computer-internal structure Design so that support computation model.Compiler technologies is a kind ofly to be used for supporting computer program code is translated into the technology of another kind of form from a kind of form, and debugging technique normally is used for the technology of debugging, and in other words is exactly the technology that finds the mistake in the computer program.

When code when a kind of format translate becomes another kind of form, the conforming forfeiture of code position and data value is a problem.When source code when higher level lanquage is translated into object format downwards, perhaps when code when a kind of " target " format translate becomes another kind of " target " form, all can expose described problem.Therefore, can in one or several step, translate into object code to described source code.Under latter event, can be considered as " source " and/or " target " form to any intermediate code format.In each translation steps, all source format and object format will be arranged, although the source format in the given translation steps may be the object format in the last translation steps.

When changing in the process of the source code of representing with higher level lanquage being translated into object code and optimizing, can't be supported in the direct mapping between destination register and the source variable.Described transfer process moves and deletes the instruction that variate-value is operated.Described transfer process can also be used the variate-value at the difference place in the program after different registers or memory location are kept at translation.Described transfer process even can use a register to preserve described value, meanwhile, its dependent variable keeps their value in this identical register or memory location.In addition, described transfer process may be have been removed described value save register during the some parts of lifetime of a variable; Replace this register with the constant load, perhaps as mentioned above, use the register of also preserving from one or more values of other (a plurality of) variablees.Report each variable resident state (residency) (just a certain program put described variable resident register or memory location and value that they had) be a technical matters.When carrying out, not only report currency but also the report variable also is a problem in the desired value of a certain program point.

Especially, when for the machine of another kind of type or system and the binary code of carrying out in one type machine or the system is changed and when optimizing, the value that is stored in the original binary code in some register will be stored in other registers in resulting code to being predefined in.In the field of computer technology, target architecture is optimized with adaptive after present original architecture state (such as content of registers) be a problem especially.

The general considerations of conforming forfeiture can resolve into following subject matter:

Is instruction address in how object code being represented mapped to the instruction address in the source code representation?

The address of the data value container of the map addresses of the data value container such as register or memory variable in how object code being represented in the source code representation?

Is the correct data value address in the source code representation got back in a plurality of effective example mapping of the data value capsule address in how object code being represented?

First problem has been set forth the problem of code position.Latter two problems relates to the data value problem.

Described data value problem is described as report sometimes or follows the tracks of the problem of putting the desired value of desired original register (being variable perhaps) in a certain program under the situation of general higher level lanquage.

Determine whether that the problem that can visit original register or variable in the register of its assignment typically is known as the resident problem of summarizing in list of references [1].

List of references [1] is noticed, for the resident state of detection variable suitably, use the lifetime of this variable just enough, the so-called lifetime is just from giving this variable assignments a register up to the last scope of using the code of this register another instruction.But described resident state can last till that another value is by assignment this register to the value that comprises this variable.This program point is evicting from a little of this variable.In [1], the evicting from of detection variable a little by optimized code application data flow analysis in debugger is implemented.

Correlation technique

List of references [2] relates to a kind of built-in debugging support equipment, and it realizes the multiprocessor simulated environment so that improve debugging efficiency on a plurality of multi-purpose computers.

List of references [3] relates to a kind of software debugging port that is used for microprocessor.When with sheet on trace high-speed cache when using in combination, this software debugging port is provided for rebuilding the tracking information that stream is carried out in instruction on processor, and can check content of registers under the situation that does not stop processor operations.

List of references [4] relates to a kind of debugging support equipment, it has the unusual control assembly of debugging, these parts keep buffer status when receiving from the unusual generation of the debugging of CPU core instruction, and programmable counter changed to the address of the unusual handle of debugging, and this register turned back to the state of described debugging before generating receiving when recovering instruction.

List of references [5] discloses a kind of debugging interface with compact trace record memory device, and this compactness trace record memory device has a plurality of trace data memory elements.The form of described memory element comprises the trace code field of the type of representing tracking information and the trace data field of representing the type of tracking information data.

List of references [6] relates to a kind of programmable logic device (PLD) (PLD), and it provides the ability of observing and controlling the logic state of buried internal node.Described PLD is provided for the shadow memory cell of internal node, and described internal node is such as being logic element register, storage unit and I/O register.Sample/load data path comprises BDB Bi-directional Data Bus and shift register, and it is convenient to internal node is sampled so that observe its logic state and internal node is loaded so that control its logic state.

Summary of the invention

A general objects of the present invention is to realize and support a kind of general solution to described data value problem.

Specific purpose provides a kind of when the solution of carrying out when source code representation is translated into the program code that object code represents the so-called resident problem the computer system.

Especially, expectation provides the mechanism of the data value consistency between a kind of object code after supporting original source code and translating.

When providing a kind of object code that is used on computer system carrying out after the translation, a specific purpose of the present invention supports to follow the tracks of the method for the data value of original source code.

Another specific purpose of the present invention provides a kind of equipment or module that is used for the view of the data value container (such as register or memory variable) of support original source code when the object code after the corresponding translation of execution on computer system.

A specific purpose is the register consistance of supporting between original register and the destination register.

Especially, purpose is to keep the data value view of primitive compuer system after for system optimization of a various computing machine and adaptive described program code, especially when at this goal systems to being predefined in the binary code of carrying out on this primal system and changing and when optimizing.

According to a first aspect of the present invention, when being provided, the version after a kind of translation that is used on computer system carrying out the source code that is known as object code supports to follow the tracks of the method for the data value of original source code, said method comprising the steps of:, utilize the appropriate address information of the raw value container of described source code to tag to the index of the target data values container in the object code instruction at the program code translate duration; When carrying out object code, storage and object code instruct relevant information together with the tagged address information of the raw value container of described source code as trace information, and the data value view that uses the address information of the raw value container of described source code to provide original source code to represent together with trace information.

According to a second aspect of the present invention, the computer system of the data value consistency between the version after a kind of translation that is used to this original program code of supporting the original program code and being known as object code is provided, described system comprises: be used to carry out the device of object code, object code instruction be coupled with label so as target data values container in the object code instruction to be provided and the appropriate address information of the raw value container of original program code between index; Be used for when carrying out this object code storage and at least one object code of the assignment of the data value container of the described original program code of expression instruct relevant information together with the tagged address information of described raw value container as trace information, and use the address information of the raw value container of described original program code that the device of the data value view of described original program code is provided together with trace information.

As described, the present invention relates to general data value problem, especially when carrying out the resident problem of translating into from source code representation the program code computer-chronograph system that object code represents.

Basic thought of the present invention is at the program code translate duration index to the target data values container in the object code to be associated with the appropriate address information of the raw value container of source code, and the information that storage is relevant with object code when carrying out object code is together with the relative address information of raw value container, so that support the data value view that original source code is represented.Like this, follow the tracks of the data value of original source code in the time of can being supported in the object code of carrying out in the goal systems after the translation in mode very efficiently.

The example of data value container has comprised common microcomputer register and the distribution in the high-level programming language variable of storer.Therefore, for the register situation, the invention provides for the conforming support of register between the destination register group of the original registers group of source code and object code.The situation that relates to memory variable has reflected for the solution of the resident problem of data value more generally.

The present invention also makes the data value view that might keep the primitive compuer system after for system optimization of a various computing machine and adaptive program code.

In a preferred embodiment of the invention, during code translation, object code instruction is tagged, so that related between the raw value container in target data values container (such as destination register or target variable) and the source code in the object code is provided about data value consistency.

Preferably, the information that is stored together with the described raw value capsule address that is associated when object code is carried out comprises corresponding target instruction target word address information and/or corresponding instruction operand value.Under latter event, permission is followed the tracks of the value of raw value container and be need not with reference to any target data values container.

Advantageously, top trace information is written in the custom-designed extra register file, and it is known as parasitism (ghost) register file below, and preferably is implemented as the hardware register file in the microcomputer architecture structure.

The target instruction target word that has added label comprises one or more target instruction target words of the assignment of expression raw value container, and described raw value container is such as being register or variable in the source code.To support in order providing to follow the tracks of fully, can in described parasitic register file, the data value capsule address information original source code to move to another clauses and subclauses from clauses and subclauses (or register).Like this, the present invention supports wherein to depend on the situation that the execution route got may be given destination register (or variable) different original register (or variable) values inherently.This also is suitable for for the situation of wherein the different instances of original register (or variable) having been translated into the parallel example of destination register.

In order to reflect the resident state of the raw value container in the goal systems consistently, the present invention preferably also comprises the logic of the order continuity that is used to support parasitic register file operation.

In addition, the present invention preferably also is provided for the operations flows processing of optionally metoxeny register file operation.Described operational processes logic typically the operation of the normal operations stream that separates self processor convert assignment to, move at described extra register file, storage and blank operation.Described conversion is subjected to the control in the operation of preceding conversion in the so-called read waiting time window of original normal operations and described extra register file usually.

Therefore, extra field in the instruction word of object code, extra register file and certain operational processes logic allow also to keep the state of the data value container of original source code outside the state of target data values container when object code is carried out, and if necessary even allow to keep the state of two kinds of different Computer Architectures.

Except the memory devices of described parasitic register file or equivalence, the present invention also provides the integrated system of independent " compilation time " and " working time " assembly and this independent assembly to make up.Example comprises operating and is used to carry out so-called tagged compilation time assembly and can operates be used for relevant information is stored in assembly working time in the described parasitic register file.

The invention provides following advantage:

Solution at the resident problem of data value of variable and register.

Support for the data value consistency in the computer system.

Improved the ability of efficient debugging and trace analysis.

The data value of original source code is followed the tracks of in permission when the object code of carrying out after translating.

Keep the possibility of the data value view that original source code represents during object code after carrying out corresponding translation.

The register consistance is supported.

In order on a different computer system, to carry out program code carried out optimizing and adaptive after, for the support of the data value tracking of primitive compuer system.

When below reading during, will recognize that other advantages provided by the present invention to the description of embodiments of the invention.

Description of drawings

By with reference to the description of carrying out below in conjunction with accompanying drawing, will understand the present invention and further purpose and advantage best.

Fig. 1 is the synoptic diagram of mechanism that is used to support the data value consistency between original source code and the object code that illustrates in accordance with a preferred embodiment of the present invention;

Fig. 2 is the schematic flow diagram that is used for the exemplary group method of the data value of tracking original source code when carrying out corresponding object code, comprising debugging and/or trace analysis;

Parasitic register file in the example processor environment of Fig. 3 explanation specific embodiment according to the present invention;

Fig. 4 is the synoptic diagram of destination register file and parasitic register file, the example that its difference that described parasitic register file is shown is used;

Fig. 5 is the synoptic diagram of destination register file and parasitic register file, thereby it illustrates when the destination register in the sequence code and is made the order destination register use an example of described parasitic register file when having several parallel example by parallelization;

Fig. 6 explanation is used to guarantee the example of parasitic register file pipeline step logic of the order continuity of parasitic register file operation;

Fig. 7 explanation is used for an example of the operations flows processing logic of optionally metoxeny register file operation; And

Overflow example with over-loading operation in Fig. 8 explanation parasitic register file in accordance with a preferred embodiment of the present invention.

Embodiment

In whole accompanying drawing, identical Reference numeral will be used to corresponding or similar elements.

Past does not solve described data value problem fully, and especially, microprocessor industry and academia also do not have to solve the hardware supported for following the tracks of the raw value container value that is optimized code translation in computer system easily.This support will be alleviated the computer program debugging problem in this system greatly.

At first will be in the ordinary course of things as the general solution of data value resident state problem is described the present invention.Subsequently, with respectively in the support of register consistance with follow the tracks of under the situation of the memory variable in the higher level lanquage and illustrate the present invention.

Fig. 1 is the synoptic diagram of mechanism that is used to support the data value consistency between original source code and the object code that illustrates in accordance with a preferred embodiment of the present invention.Described program code is represented to provide with original source code, and it is called source code 10 simply, and operates about one group of data value container 20 (such as register or memory variable).The data value container of original source code is known as the raw value container.Source code 10 is translated into object code to be represented, it is called object code 30 simply.This object code 30 is about another group data value container 40 operations.The data value container of object code is known as the target data values container.Described code translation generally includes the distribution of code conversion, optimization and its registers and static variable.Yet,, be that the index to the target data values container in the object code instruction is associated with the appropriate address information of the raw value container of source code one of the program code translate duration additional task according to the present invention.Preferably, this is that instruction tags and realizes the relevant information that relates to the raw value container by utilization to object code.For example, the described process of tagging can utilize the address/name of original container to come the destination container of mark (perhaps tagging) instruction.During object code working time, when execution had added the object code 30 of label, instruction manipulation numerical value was endowed the target data values container, and also was moved between different target containers usually.In addition, according to the present invention, the information relevant with the object code instruction and the address information that is associated of raw value container are stored in one group so-called " parasitism " or " shadow " data value container 50 together.Like this, can keep or support the data value view that original source code is represented in working time, thereby greatly facilitate debugging and/or trace analysis at object code.

In the microcomputer architecture structure, be used to support the data value container 50 of the data value view of original source code to be preferably implemented in " parasitism " register file, although also there is the embodiment of replacing, comprising using common transaction memory.Described " parasitism " data value container 50 can also be the memory location that is assigned to the variable in the high-level programming language.

Fig. 2 is the schematic flow diagram that is used for the exemplary group method of the data value of tracking original source code when carrying out corresponding object code, comprising debugging and/or trace analysis.In the code translation stage, preferably tag to object code instruction, so that related (S1) between the raw value container in target data values container (such as destination register or target variable) and the source code in the object code is provided about data value consistency.When carrying out object code, information such as the target instruction target word address information and/or corresponding instruction operand value are stored together (S2) with the raw value capsule address that is associated.In the debug phase, can analyze original source code based on the trace information of being stored.As will explaining after a while, when target instruction target word address information and raw value capsule address were used as the trace information storage, debugging utility can use the target instruction target word address information to be reproduced in through effective value in the object code of optimizing.If instruction manipulation numerical value is stored itself, then can be not with reference to the value of following the tracks of the raw value container under the situation of any target data values container.

Code profiler and translater (compiler typically) are analyzed described code usually so that the data value information of container of original source code is provided, can be after a while in the process of carrying out resulting object code with selected working time information use described data value information of container so that the data value container view of original source code is provided.

Therefore, the invention provides solution, especially at by time report variate-value (under the situation of higher level lanquage translation) or original register value (under the situation at binary translation) being set through optimized code and/or reporting they reside in the problem in which destination register at trace/breakpoint place after the translation at data value resident state problem.

The register consistance

Below will be about original register in the source code and the destination register labor data value problem in the object code.

For different register consistency problems is described, provide two basic code examples below.Register in the original architecture is known as original register OREG.Register about target architecture is known as destination register treg:s.

Example 1:

Ld tregB, ADDR0; // destination register tregB is from the storer of address AD DR0

// middle value

Mv tregA, tregB; // value of destination register tregB is moved among the tregA

Ld tregB, ADDR1; //tregB obtains new value

St tregA, ADDR2; // the previous value of tregB is spilt into address AD DR2 place

// storer

Ld tregC, ADDR2 // heavily loaded in register tregC the previous value of tregB

conditional_jump?L1；

Mv tregC, tregD; // value of tregD is loaded among the tregC

L1)

Mv tregE, tregC; // in the assignment of tregE, use the value of tregD or tregB before

// one value

Suppose that tregB initially obtains the value (article one presumptive instruction just loads OREG1 from ADDR0) of original register OREG1 from the memory cell of ADDR0, and tregD comprises the value of OREG2, what value does tregE obtain at the L1 place? the answer of this problem depend on described code be carry out by which paths and compiler can provide which information about described assignment.This means a solution, wherein not only use multidate information but also use static information described problem.

Described optimizing process can also be assigned to the value in the original register at the different time points place in the source code the identical time point in the object code.This explanation in example 2.

Example 2:

LD OREGA, ADDR1; // load with the value among the storage address ADDR1

//OREGA

The calculating chain ... // here is based on the value among the OREGA

The result of ... // adopt among the OREGB

ST OREGB, ADDR1 // new value is stored in the storer

LD OREGA, ADDR2 // load OREGA with another value

... // another calculates chain based on new value

The result of ... // adopt among the OREGC

ST OREGC, ADDR2 // next new value is stored in the storer

Here, the OREGA register is used to the value of different time.In wideer distribution machine (such as VLIW (very long instruction word) machine), these two calculating chains may be by parallelization.

Two examples of //OREGA be translated in treg17 and treg19, preserve two

// individual parallel example.

ld?treg17，addr1；ld?treg19，addr2；nop；nop；

// these two calculating chains by parallelization on each VLIW machine function unit.

// storage produces gr21 and gr23 also by parallelization

st?treg21，addr1，st?treg23，addr2

This causes a problem, constitutes which example of OREGA because which value debugger and/or trace utility routine need know.

In our method, which destination register is the dynamic calculation in the goal systems normally be endowed about which original register (under the situation of binary translation) or variable (under the situation of senior translation).This information preferably is maintained in " parasitism " register file.Therefore, at any set point place, described by searching for " parasitism " register file is determined the resident state of original register (or variable).The original register (or variable) that finds at this place is resident, and what do not find is not resident.

Resident problem for translation system about original register in the source code or variable, compare with [1], the simple relatively hardware embodiment of our method utilization replaces the data-flow computation in the debugger in conjunction with tagging with the instruction in the original register pair compiler under some assignment.

An advantage of this method is, still can report the original register of having evicted from (or variate-value), as long as it is not evicted from by another original register (or variable) value.

Suppose below the sourse instruction address at compile duration by owing to corresponding target instruction target word, and be provided for trace/debugging utility by rights.

In a preferred embodiment, the coding of the destination register in the target instruction target word primitive (such as VLIW or RISC primitive) has the extra field that is used for original register address.If this field has effective original register address, then the result of described operation also will be written in the conforming parasitic register of supporting original registers group.Unless be used for trace and debugging purpose, otherwise should the parasitism registers group will never be read.Therefore, allow the long operation awaits time for parasitic register file.This means that described parasitic register file is in outside the critical path, and can be its visit being carried out the pipeline system arrangement satisfying regularly demand, and parasitic register file can be placed on the almost any position on the chip.Support " the original register value in the destination register " to follow the tracks of if desired, then described parasitic register file transmits the register label of emulation usually between parasitic register element.When supporting that " only original register value " followed the tracks of, tag if move operation is not carried out original register, then also be this situation.In these cases, because described move operation is reading and writing of combination, therefore need read from parasitic register file usually.Because the GRF stand-by period, move operation means the dependence to contiguous GRF operation.This can handle the tolerance limit of long GRF operation awaits time by utilizing.Provide more contents below about this respect.

Compiler is known the mapping from original registers group to the destination register group, if the assignment of the original register in instruction expression source code, then this compiler utilizes the address/name of this original register to come to tag to the destination register of this instruction.In the above example, this will mean:

Example 1:

Ld tregB (OREG1), the value of ADDR0 // original register OREG1 is loaded into

Among the //tregB

Mv tregA (OREG1), tregB; The value of // original register OREG1 is moved to

Among the //tregA

Ld tregB, ADDR1; //tregB obtains new value

St tregA, ADDR2; The value of //OREG1 is spilt into address AD DR1 place

// storer

Ld tregC (OREG1), the value of ADDR1//OREG1 by heavy duty in register tregC

conditional_jump?L1；

Mv tregC (OREG2), tregD; The value of //OREG2 is loaded among the tregC

L1)

Mv tregE, tregC; The value of //OREG 1 or OREG2 is used in tregE's

In // the assignment

Described compiler can't infer that the value that original register OREG1 still is OREG2 will be endowed tregE, because this depends on the approach of the statement that arrives the L1 place.Therefore, do not having under the situation of multidate information, can not differentiate is to give tregE OREG1 or the value of OREG2.Yet, what can infer is that the nearest value of OREG1 is the value from ADDR0 because there are not other values to be endowed destination register with label OREG1.Equally, the nearest value of OREG2 is the value (wherein tregD certainly may obtaining its value from storer previously, as OREG1) of tregD.

Example (1) means, in order only to preserve the nearest value of original register, utilizes original purpose ground register to tag for the target destination register and in working time described value to be write parasitic register subsequently just enough at compiling/link time.Where reside in order to follow the tracks of the every bit place of original register value in program, for the situation that depends on that wherein the execution route got may be given destination register different original register values, must in parasitic register file, have the support of working time.As below will explaining, this preferably special parasitic register manipulation type by mobile message in parasitic register file realize.

Example 2:

Two examples of //OREGA have been translated into preserve two also in gr17 and gr19

// row example.

ld?treg17(OREGA)，addr1；ld?treg19(OREGA)，addr2；nop；nop；

Therefore the extra field in the target instruction target word word, extra register file and certain operational processes logic allow to keep the state of the data value container of the object code after original source code and the translation when object code is carried out, and if necessary in addition allow when object code optimised so that keep the state of two kinds of different Computer Architectures when being different from execution on the goal systems of primal system.

Parasitic register file in the example processor environment of Fig. 3 explanation specific embodiment according to the present invention.In simplifying view, this example processor 100 has level Four: instruction takes out 110, decoding 120, carry out 130 and submit 140 to.This processor system also has general register file 40 and parasitic register file 50.When the ordinary instruction of operation on storer and common aspect architecture register file 40 was submitted, the normal codes from decoder stage 120 flowed the parasitic register manipulation of decoding and it is submitted to parasitic register 50.The data routing that writes from parasitic register file to storer uses normal memory to write data routing.Preferably, parasitic register file 50 resides in and carries out the place of pipeline at a distance of a plurality of pipeline steps, so that handle read waiting time under possible situation.The actual number of described a plurality of pipeline steps is selected to easy to implement.The memory read data path is omitted, and the common structure of other necessity also is omitted, such as data read address bus, instruction address bus or the like.

Can read in the trace information of storage in the parasitic register file (GRF) 50 by debugging utility 200, so that original source code is carried out debugging and/or trace analysis.This debugging utility can also read information from general register file 40 certainly, so that support the object code debugging.This debugging utility reads in the snapshot of the GRF that stores in the storer.In practice, normally the content ordering of GRF is obtained the snapshot of GRF in the storer by carrying out parasitic storage operation, just as by (common) storage operation the general register file storage to storer.The actual coding of parasitic storage operation can be in the opcode field or be in the address field.

In one particular embodiment of the present invention, from the angle of compiler/linker, an instruction has three kinds can write the mode that register is write in the destination to register:

1) only is written to destination register.

2) be written to destination register and be written to parasitic register.

3) only be written to parasitic register.

Parasitic registers group for example can be in three kinds and write under the pattern.The said write pattern comprises that in the middle of the instruction that register is write the different registers of respectively organizing writes the destination.

First to write pattern be the situation that does not wherein write the register consensus information.Under this pattern, only in the middle of instruction, find register to write destination situation 1.

Second to write pattern be that the standard register consistance is supported just, only to be tagged situation at the destination register of not removing in the statement to original register assignment.Under this pattern, can in instruction, find register to write destination situation 1 and 2.Just, the instruction that has not with the tagged destination register of original register will be written to destination register, will be written in destination register and the parasitic register and have the instruction that has added the destination register of label with original register.

The 3rd to write pattern be that a kind of extra register consistance is supported situation, just, compiler will be preserved " parasitism " assignment statement, wherein with original register label with write destination 3 labels and come to tag to destination register, also be like this even removed true assignment in optimization.Under this writes pattern, in the middle of instruction, find all registers to write the destination situation.This means except register writes destination situation 1 and 2 (second writes pattern), also in the middle of instruction, finding register to write destination situation 3 under this pattern.Have instruction that register writes destination 3 and represent the instruction of during optimizing, having been removed by compiler.

Under the conforming situation of register, the 3rd to write pattern mainly be interesting in theory, because its registers can not be separated parasitic register with the assignment of destination register, just, its registers will also be distributed in the instruction of having removed.Therefore, only there be the parasitic existence of assignment in code to use and to overflow and bring influence (depending on the register file size) register.May have means to save the situation for these problems, the 3rd write pattern such as only using, destination register group (if enough big) is divided into two groups (bigger one group is used for true assignment, and less one group is used for parasitic assignment) or only uses the 3rd to write pattern in combination with the tracking of original register value " only to " for one or several original register.

In use, in the processor control register, specify the pattern that writes.

Debugger/trace utility routine can be visited the instruction address that one group of parasitic register and each parasitic register are written into.It also will have register and write the destination sign, thereby it can infer how parasitic register is write.This will make described utility routine can be reproduced in effective original register value in the object code after the optimization.

Parasitic register file comprise usually with target architecture in the as many clauses and subclauses of register number, and preferably also comprise one and overflow the zone.If it is the same big with described destination register group that this overflows the zone, then all parasitic registers can easily be overflowed.Each clauses and subclauses preferably includes original register number and this register is written into and/or the stored instruction address of data value.

In a kind of specific exemplary embodiments, add additional optional information, thereby each clauses and subclauses preferably includes following field:

OR

RWD

TMIA

E

V

The original register number of OR-

The RWD-register writes destination (normally 1 bit, coding situation 2 and 3)

TMIA-target machine instruction address

The value that E-has evicted from (normally 1 bit)

The V-value

Table I

When the original register value in the tracking target register, desired value field (V) not, this is because can find this value in corresponding destination register.

When only following the tracks of original register value, desired value field (V), this is that in this case, (a plurality of) old value will be evicted from from destination register because destination register may be endowed new value.

The RWD field normally writes by being used for second that mode value in the processor control register of (first will not be present in parasitic register) of destination produces.Write under the pattern if processor is in the 3rd, then the 3rd write the destination and be endowed the RWD field, and the target destination register is defined as sky.The coding of the non-retouching operation of destination register also can be realized by 1 bit in 1 bit in the operational code or mode bit field and the target destination register.Write destination 2 iff the needs register, then can omit the RWD field.

(bit of holding instruction) another option is to use a register entries among the register address figure as empty mark.To not change its content to writing of this register entries.If be used, then this register entries can be used to always produce zero.

If the E bit is set up, then this value (V) is evicted from from the destination register of TMIA by a non-original register value.

Fig. 4 and Fig. 5 illustrate under the situation of " sequence code " and " parallel codes " exemplary operation to parasitic register file respectively.Parasitic register file and destination register file are depicted as located adjacent one another.As a rule be not this situation, in order to avoid disturb with route and placement around the destination register file.Accompanying drawing only provides logical view.Fig. 4 and Fig. 5 are corresponding to above-described example 1) and 2).

The example 1 of Fig. 4) is used to be illustrated in when enabling " source register value in the tracking target register " and when enabling " the only value of tracing source register ", the difference of parasitic register file used.For the sake of clarity, the V field all exists in both cases here.Example 1) be presented as sequence code, just, it is not as yet by the parallel for example VLIW instruction word that turns to.Use for parasitic register is identical, and no matter it still is that the VLIW instruction word writes from the RISC instruction word.

Operation when the solid arrow line among Fig. 4 is illustrated in the value of tracing source register, and the operation that empty arrow line is added when being illustrated in source register value in the tracking target register.For example, the operation " ld tregB (OREG1); ADDR0 " that the value of carrying out at target instruction target word IA place among the ADDR0 is loaded among the destination register tregB means information [OREG1,2, IA, [ADDR0]] be written to parasitic register " ghost tregB ", wherein OR is OREG1, RWD equals 2, and the target machine instruction address is IA, and value V is that memory location from ADDR0 obtains.The value of tregB is moved to operation " move tregA (OREG1); tregB " among the tregA to be mapped to the value of tregB is given in the parasitism operation of parasitic register ghost tregA, wherein OR equals OREG1, RWD equals 2, and the instruction address of this move operation also is written among the ghost tregA: [OREG1,2, IA, tregB].

At example 1) in, in the time can inferring statically, utilize original register address to tag to move operation by compiler.Another alternative is not tag (tagging only for initial assignment or load operation) to move operation, but make parasitic move operation always parasitic source register value (OR, RWD, TMIA, E V) copies parasitic destination register to.To the description of parasitic register file operation and below compiler presuppose this alternative in describing.

Whether the control bit in the processor control register (EVICT) the untagged destination register assignment of definition (being the invalid register address in the parasitic register field) should make the previous assignment of the original register address (OR) in the parasitic register invalid.This will allow two kinds of different uses.If the original register value in the destination register should be tracked, then EVICT should always be set up.Therefore, only under only to the interested situation of original register value, this EVICT control bit is only significant.If be eliminated, even then original register value is not present in the destination register, they also are saved, and they rewrite the instruction that only added label with original register.If be set up, then original register value may be expelled from parasitic register file by untagged assignment.This can be summarized in the Table II below:

A processor control bit EVICT----＞tracing mode! V

Remove " do not have and rewrite "

Be provided with " rewriting "

Only original register value	When original register value disappeared from destination register, they also were saved	When original register value disappeared from destination register, they were not saved
			Original register value in the tracking target register	Illegally, because if parasitic register is not correctly upgraded, then described tracking will be wrong	Allow the original register value in the tracking target register

Table II

If will carry out snapshot or ex-post analysis, then forbidding is followed the trail of, and reads parasitic register memory and be written to primary memory by parasitic register dump routine.

By inserting trap, can preserve the snapshot of original architecture registers group or checkpoint for analyzing after a while to parasitic register dump routine.

When the example 2 of Fig. 5) being used to be illustrated in destination register in the sequence code by parallelization to the use of parasitic register file, thereby " in proper order " destination register has several parallel " examples ".

Parasitic register file inner structure

Described parasitic register file (comprise and overflow the zone) is a working storage, and it supports the register view of original source code or the original architecture of emulation on target architecture.Operate this working storage by two kinds of basic operation types.

Parasitic register manipulation type

A kind of operation is an assign operation, and it is the spinoff of carrying out ducted arithmetic or load instructions.These arithmetic or load instructions are pointed out corresponding original register title clearly in its original register destination field.

Another kind of operation is a move operation.This move operation is derived from carries out ducted move.Its difference is that this operation is not pointed out clearly and will be written to the title of the original register in the parasitic register file.Move operation must copy the OR field by the parasitic register entries of move operation source destination register numeral index to the parasitic register entries by move operation destination destination register numeral index.

Be not that all move operations in the destination register file all will cause move operation in the parasitic register file.For example, will NOP when it arrives parasitic register at the non-move operation that does not add the OR label of evicting under the situation.The move operation that has added the OR label will be converted into parasitic register assignment operation.

Parasitic storage operation is used to parasitic content of registers is written in the storer.When obtaining the snapshot of parasitic content of registers, each given viewpoint in code flow uses parasitic storage operation.The code that comprises parasitic storage instruction can be code or the normal codes in unusual or the interruption routine, and this depends on people want how to be provided with described observation.Subsequently, use these to observe snapshot as input to the analysis debugging software.

The NOP instruction is blank operation, and it is not operated parasitic register file.

Parasitic move operation must read from parasitic register file, so that its OR value can be written in the parasitic register file.Assign operation only needs to be written to parasitic register file.The assign operation support is sent to OR information the parasitic register file from compiler static state.Move operation support OR information in parasitic register file dynamic, carry out relevant transmission.

In order to support to move and assign operation, a kind of preferred solution is to provide one to write inbound port and a read port for each effective efficiency processor unit (promptly producing entity for each valid function in this processor) for parasitic register file.In other words, each issue read port of groove and one write inbound port.

Parasitic register manipulation order continuity

Because read operation had a stand-by period before finishing, so the extra logic of our needs is supported the order continuity in the operations flows.In this stream, must write the result that move operation reads before after a while any other operation, no matter read or write the destination clauses and subclauses of this move operation.If this continuity do not supported, then parasitic register file will be not according to by the assignment of the dynamic execution route appointment of compiler and target machine and the buffer status that move operation is described original architecture.About the general discussion of the data hazards under the execution pipeline situation referring to list of references [7].

Therefore, for the complexity debugging, parasitic register file needs certain logic to guarantee this continuity.This is described under the help of Fig. 6, and this figure explanation is used to guarantee the example (describing an operations flows) of parasitic register file pipeline step logic of the order continuity of parasitic register file operation.

Because parasitic register file 50 needs the as many operations flows of number of the functional unit in support and the machine, so this logic will be replicated.For the sake of brevity, Fig. 6 has omitted the transmission of RWD and TMIA unit and has write.The store path (promptly arriving the data routing of carrying out pipeline) and the memory address path of storer have also been omitted.

In this embodiment, introduced a plurality of pipeline registers (P1, P2, P3 ...).These registers comprise RWD sign, TMIA value (all being omitted), destination destination register numbering (dtreg), original register number (oreg in Fig. 6, if this operation is an assignment) or source destination register (streg is if this operation is mobile) and function designator (assignment or mobile).

Forwarding and write control unit 60 preferably monitor the pipeline register data, if and detect move operation, it will be forwarded to source destination register numbering (streg) and read address port, have data (OR value) from register file when being in last pipe stage with this move operation of box lunch to write.

If in pipeline, detect one or more assignment, then will be set to the data that writing in writing moving in last the OR assignment before described move to the move operation source.In this case, the expired OR value that is transmitted will be left in the basket.

This preferably realizes by last pipeline step register destination destination register numbering (in the parasitic file write index) and previous pipeline step register source destination register numbering (if this pipeline register comprises move operation) compared.If these two destination register index are complementary, then will load wait transmits the OR value from parasitic file register with the OR value of last pipeline register.(crossing time value) will be left in the basket in next circulation to come the OR of autoparasitism file to transmit, and use will be written to the new OR value of described mobile source-register.

Explain this example logic below by false code.Needed storage organization (register) is known as the element P0 in the port interface structure, last the pipeline step before the promptly parasitic register file.Note that described code and imperfect, for example omitted and ignored the sign processing.Also omitted the storage operation processing.Read although described storage operation is GRF, it does not write GRF, and is written to storer.All operations before described storage is transmitted by the moving source address and is supported described continuity.Described false code provides as just exemplary summary, so that the better understanding to described logic is provided.

P0.radr; // reading the address, it is used to movable address and transmits

P0.rdata; // when move operation will be done in parasitic file, from described mobile

The source

// reading of data, OR value are so that be written to the destination that this moves.

P0.we; // write-enable.

P0.rdati; // if ignore to come the data of autoparasitism register file, then read and ignore

// sign.

P0.wadr; // write the address, promptly at the last part of assign operation and move operation

In

// use write the address.

P0.wdata // write data, or from the OR value of assign operation, or come

From

The OR value of // move operation.Move operation OR value or be derived to parasitic literary composition

Reading of // part perhaps is derived from the assign operation in the source of this move operation

Write

// go into data.

P0.wadr // write address, assignment or move operation destination.

The input data of last the pipeline step in described forwarding and the write control unit are the data of first preceding pipeline step P1, P2, P3.

{ P3-P1}.dtreg; // destination destination register numbering is in parasitic register file

{。##.##1},

// write index

{ P3-P1}.streg; // source destination register reads rope in the parasitic register file

// draw.If operation is mobile, then is effective number.

{ P3-P1}.oreg; // original register number, the OR data value.If operation is an assignment,

// then be effective number.

{ P3-P1}.op; // operation, i.e. blank operation, mobile or assignment

If move operation is arranged in // the pipeline, then it triggers the forwarding of reading the address.

IF(P4.op＝＝’move’)

THEN

P0.radr:＝streg；

P0.rdati:=FALSE; // accept the data that are transmitted

ENDIF

IF(P1.op＝＝’assignment’)

If // the operation that will carry out is an assignment.

THEN

// .. utilizes the destination destination register to load and writes the address.

P0.wadr:＝P1.dtreg；

// .. and the explicit OR value that will write

P0.wdata:＝P1.oreg；

P0.we:＝TRUE；

ELSE

IF(P1.op＝＝’move’)

If // the operation that will carry out is mobile.

THEN

P0.wadr:＝P1.dtreg；

// .. and the OR value that loads from parasitic register file

P0.wdata:＝P0.rdata；

P0.we:＝TRUE；

ELSE

IF(P1.op＝＝’nop’)

If // operation is blank operation, then forbidding writes.

THEN

P0.we:＝FALSE；

END

If the operation in the source of this move operation is upgraded in // mobile front.

IF(P2.op＝＝’move’AND?P2.streg＝＝P1.dtreg)

THEN

IF(P1.op＝＝’assignment’)

// .. and be assignment .. in preceding operation

THEN

The OR value loading data register of operation before // .. is used in

P0.rdata:＝P1.oreg；

// .. and ignored time value.

P0.rdati:＝TRUE；

ELSE

IF(P1.op＝＝’move’)

// .. otherwise, if be mobile in preceding operation

THEN

// .. utilizes the OR value .. that is taken out that moves the preceding again

P0.rdata:＝P0.rdata；

// .. and ignore the value of coming the autoparasitism file that this moves.

P0.rdati:＝TRUE；

If ENDIF // operation is NOP, then do nothing.

ENDIF

Utilize more pipeline step can handle longer read waiting time.Along with the increase at the number of preceding operation, will more or less more complicated for the source contents of move operation in the forwarding of preceding renewal and the processing of control.

Top example is simplified, because it has only described an operations flows.For the moving source retouching operation, must check from other operations flows in preceding operation.By the stand-by period of register memory also selected must be low, thereby needn't check a plurality of move operations.In described forwarding window, exist a plurality of move operations will increase the number of the required memory storage of possible a plurality of modification values.

Parasitic register file 50 is outside critical path, because can follow the tracks of operation generation activity with the circulation of any proper number towards the finishing of operation of parasitic register file.This is convenient to parasitic register file and little support logical groups thereof are placed on the chip Anywhere.If location and route timing problems, then the pipeline step of only in the operation transmission path, adding some.

Parasitic register manipulation stream is handled

Fig. 7 explanation is used for an example of the operations flows processing logic of optionally metoxeny register file operation.Can move to analysis, so that guarantee enough analysis times backward from parasitic register file 50 in preceding operation.The incoherent instruction code that this operations flows processing logic 70 filters from each functional unit (FU) to parasitic register file blank operation.If before moving is the source retouching operation, then this operations flows processing logic 70 move operation of being transmitted that can also cancel reads the address, and replaces this move operation with assign operation.New assign operation is obtained its destination register value from source retouching operation the preceding.

Described operations flows is handled also will convert some move operations to blank operation and assign operation (referring to top description to parasitic register manipulation type).It can also convert some loadings to move operation (comparing with following description to its registers) with storage (overflowing and heavy duty).

Processing 70 to described operations flows can be placed on Anywhere, and parasitic register file 50 also is like this.Parasitic register file 50 and operational processes 70 need not be contiguous.

Debugger/trace utility routine is analyzed

This utility routine reads parasitic register data from storer.Each obtained snapshot will comprise following data usually:

Target machine instruction address (when snapshot takes place).

Parasitic register file content.

This utility routine will use described snapshot target machine instruction address himself to index in the target machine code now.Here it will find a plurality of target machines (for example VLIW) primitive, and wherein each all has the attribute of the instruction address of source code.

These source code instruction addresses make described utility routine himself mapping can be got back in the source code.

Compiler

In this scheme, the task of compiler is that the destination register of original register value being given the instruction of destination register is tagged.This at first is to carry out in the translating phase of compiler, and wherein, every source statement is translated into one or several object statement.If this source statement is to original register assignment, then the described object statement of one of them bar will be given a virtual or symbol register this value, and it represents original register herein.

But the task of compiler does not stop at the translating phase usually.Compiler must be kept label on the virtual register in whole optimization and its registers stage, finally information is delivered to linker and object format up to it.

Hypothesis has provided " standard " or " additionally " consistance (about the top pattern that writes 2 and 3) with as an option to compiler below.If provide " nothing " consistance, then carry out common compiling.

Translating phase

Translating phase is the stage in the described compiler, and in this stage, sourse instruction is translated into a sequence that comprises one or more target instruction target word.This normally realizes by the intermediate form of translating into expression target program or object from the intermediate form of expression source program or object.In general, described translation is to carry out towards size unlimited symbol or virtual register group.In other words, the described translating phase need not bother and give target instruction target word destination register.After this, up to its registers stage, when mentioning destination register, we will refer to the virtual target register.

Yet, should be appreciated that " translation " this expression also comprises overall code translation or the conversion from the source code to the object code, comprising optimizing and its registers.

In this scheme, the task of described compiler in the translating phase is that the numbering or the title of register come to tag to the target destination register with representing original purpose for the instruction utilization after each translation.This label is saved usually and is an attribute in the intermediate form of representing described target program.More particularly, it is stored in the data structure of the instruction of expression after the described translation.

Compiler is selected the target instruction target word that original register value is loaded into the sourse instruction in the target destination register to the expression in the target instruction target word sequence to be tagged.

This means not to be to utilize described original purpose ground register to tag for all target load instructions.For example, will or check that instruction tags other working times not to address computations, interim computations, index or pointer inspection certainly, because they do not represent to load or original register.This has opened and has not made the original register value that is arranged in the destination register that is endowed non-original register value invalid or make its invalid option (referring to top).

Optimizing phase

Optimizing phase is such stage, wherein alternatively the target program of being represented by intermediate form is usually analyzed, is changed and adjusts, so that be suitable for particular target system.Its registers of Xie Shiing and instruction scheduler also can be considered to the optimizing phase after a while.

In general, the task of compiler in the optimizing phase remains on (translating phase setting) original register label on the target destination register of the instruction that loads original register value in whole transfer process.

Different situations may appear:

Having added the instruction of label will be removed-and if for compiler has provided this option of " additionally " consistance, then this instruction is not removed, but have the attribute of " only being written to parasitic register ".If provided " standard " conforming option, then removed this instruction.

The instruction that has added label will be replaced-and label on the destination register is moved in the destination register in this instruction of replacing old instruction.

The instruction that has added label will be raised or descend-the have target instruction target word of the label on the unaltered destination register is raised or descends.

Its registers

Its registers refers to unlimited example virtual or the symbol registers group in the wherein said code and is endowed situation from the physical register title of target architecture.Because the number of the physical register in the machine is limited, so register allocator inserts and removes instruction sometimes, and it is responsible for register value come in and go out storer and the loading between register, storage and move.The way of register value being stored and being loaded into storer because the idle physical register that can obtain at a certain program point place is limited is known as " register overflows ".Therefore, virtual register example needn't be mapped to an example of physical register.

As other stages, the task of register allocator remains on original register label on the target destination register in the whole its registers stage exactly, and no matter the different intermediate representations of destination register in the different phase of its registers how.

For the tracing mode of " only source register value ", it only must participate in keeping label in assignment procedure.This will cause parasitic register file to be endowed value in the parasitic register in working time.

For the tracing mode of " the original register value in the tracking target register value ", the move operation in the parasitic register file will be responsible for following the tracks of the value between each register.Yet, spilt into storer and subsequently by the original register value of heavy duty in order to follow the tracks of, if can infer statically, then the flooding code generator of register allocator must tag for the destination register of the load instructions of being inserted with original register title or numbering.If can not, then described flooding code must comprise that the parasitic register that overflows the zone from the register that overflowed to parasitic register file moves, and described heavily loaded code must comprise from parasitic register file overflow the zone to parasitic register file corresponding to moving the zone of destination register group.

The current intelligence of can encoding in such a way:

Overflow storage by the compiler mark, thereby make it arrive parasitic register file.The processing logic of this parasitism register file overflows storage to this and converts one to and move, and this moves parasitic register data transferred to and overflows the zone.

By compiler mark heavy duty load instructions, thereby make the processing logic of parasitic register file convert thereof into from overflowing move (the common loading that arrives parasitic register file is converted into assignment) corresponding to the zone of destination register group of zone to parasitic register file.The OR value that this heavy duty loads is given the destination register that is overflowed numbering by compiler, and it is used as the source-register operand in the parasitic register move operation subsequently.

In this Table III below the expression and in Fig. 8, illustrate.

Target instruction target word	Corresponding operating in the parasitic register file
		st.spill?treg，ADDR_spillpos.	mv?treg+size，treg
ld.reload?treg[OR＝＝spilled treg]， ADDR_spillpos.	mv?treg，[OR]+size

Table III

Fig. 8 explanation be used for " dynamically " situation parasitic register file 50 overflow example with over-loading operation.

Because described tracing mode is a processor state, therefore support the compiler of two kinds of tracing modes may tagging for heavily loaded code under the situation, perhaps be incorporated into overflowing the zone or overflowing moving of zone of parasitic register file from this.

Instruction scheduler

Instruction scheduler is such stage, and in this stage, instruction is placed in the code flow, thus the microarchitecture of machine utilized efficiently, and the constraint of stand-by period and hardware resource can not destroy by code, kept the semanteme of program certainly yet.

This can cause instruction to be moved in the sequence code stream, and for the VLIW system, this stage also means the parallel VLIW word that changes into of instruction.

In this scheme, the original register label in the instruction scheduler hold instruction.

Linker

Linker is such stage, in this stage, and the resolved one-tenth physical address in relocatable address.Here do not relate to register usually, if but link time optimization is arranged, be applicable to that then the same rule of the optimization in the compiler also is applicable to described link time optimization.

As previously mentioned, parasitic operation registers (assignment, blank operation, mobile) can alternatively directed common transaction memory.So reverse analysis is left to the analysis phase (implementing) after the unloading trace data or is left to debugger in SW.Lose compression at this to data.So with the bigger data set (operation affairs) of the support logic of parasitic register file exchange and to the off-line of parasitic register mirror image logical reconstruction the how.Described trace must be even as big as holding the action that defines all destination registers, and described definition will always can directly be visited when having parasitic register file.

Under general high-level situation, follow the tracks of the value in the variable that has distributed storer

When the value of tracking variable, aforesaid coding to parasitic register words is different.Replace the OR field of preserving original register number, described OR field is represented the variable in a certain context now.Described coding is undertaken by translation system (compiler/linker), thereby each variable of living in the scope of program address has unique encoding number.This variable code field is known as variable coding (VE) hereinafter.

Described coding must be provided for debugger/trace system as the output from translation system.Described TMIA field is the key of resolving described variable coding, because this TMIA always is included in the address realm, it always has unique variable identity for the VE that is associated with this TMIA.

Compiler utilizes the variable code clerk to give from each target instruction target word of variable bit load registers and tags.As in the register consistance situation, this causes the assignment in parasitic register file or the equivalent modules.When mobile variate-value between destination register, as in the register consistance situation, this causes the move operation in the parasitic register file.

Should be noted that the zone of overflowing that in variate-value tracking situation, does not need parasitic register file, always spilt into the variable store position because preserve the register of variate-value.Subsequently, compiler certainly must be to tagging described variable heavy duty to the instruction in the destination register file.

This method illustrates resident state and the currency that is present in the variable in the register.

Above-described embodiment only provides as an example, should be appreciated that to the invention is not restricted to this.Be retained in this more modification that discloses also claimed ultimate principle, changes and improvements all within the scope of the invention.

List of references

[1]“Evicted?Variables?and?the?Interaction?of?Global?RegisterAllocation?and?Symbolic?Debugging”，Ali-Reza?Adl?Tabatabai，ThomasGross，Proceeding?of?the?20th?ACM?symposium?on?Principles?ofProgramming?Languages.

[2]JP?8221296

[3] United States Patent (USP) 6,185, and 732

[4]JP?2000181746

[5] United States Patent (USP) 6,094, and 729

[6] United States Patent (USP) 6,243, and 304

[7]“Computer?Architecture，A?Quantitative?Approach”，John?L.Hennessy，David?A.Patterson，Morgan?Kaufmann?Publishers，chapter?3.4‘Data?Hazards’.

Claims

1. support to follow the tracks of the method for the data value of original source code during the version after the translation that is used on computer system carrying out the source code that is known as object code, said method comprising the steps of:

-at the program code translate duration, utilize the appropriate address information of the raw value container of described source code to tag to the index of the target data values container in the object code instruction;

-when carrying out object code, storage and object code instruct relevant information together with the tagged address information of the raw value container of described source code as trace information, and the data value view that uses the address information of the raw value container of described source code to provide original source code to represent together with trace information.

2. the described method of claim 1, wherein, the described information relevant with the object code instruction comprise the following at least one of them:

-corresponding target instruction target word address information; And

-corresponding instruction operand value, it allows the value of following the tracks of the raw value container under the situation of reference target data value container not.

3. the described method of claim 1, wherein, described storing step may further comprise the steps: the relevant data value capsule address information of the described information relevant with the object code instruction together with described original source code is written in the parasitic register file.

4. the described method of claim 3 is further comprising the steps of: that the first parasitic register of the data value capsule address information of described original source code from described parasitic register file moved to the second parasitic register.

5. the described method of claim 3, wherein, the address information of the target data values container of expression is carried out index to described parasitic register file in the object code instruction.

6. the described method of claim 3, further comprising the steps of: support the order continuity of parasitic register file operation based on a plurality of pipeline registers, described a plurality of pipeline registers are used for handling read waiting time so that reflect the resident state of raw value container in goal systems consistently.

7. the described method of claim 3, wherein, to the operation of described parasitic register file comprise assignment, move, storage and blank operation, and described method comprises that also the operations flows that is used for optionally metoxeny register file operation handles.

8. the described method of claim 1, wherein, described object code instruction comprises the object code instruction of the assignment that at least one represents the raw value container in the described source code.

9. the described method of claim 1, wherein, described original source code is suitable for the primitive compuer system, and described object code is suitable for the target computer system different with this primitive compuer system.

10. the described method of claim 1, wherein, described trace information is stored in the data value container corresponding to the variable that has distributed storer in the general high-level programming language.

11. the computer system of the data value consistency between the version after the translation that is used to this original program code of supporting the original program code and being known as object code, described system comprises:

-be used to carry out the device of object code, the object code instruction be coupled with label so as target data values container in the object code instruction to be provided and the appropriate address information of the raw value container of original program code between index;

-be used for when carrying out this object code storage and at least one object code of the assignment of the data value container of the described original program code of expression instruct relevant information together with the tagged address information of described raw value container as trace information, and use the address information of the raw value container of described original program code that the device of the data value view of described original program code is provided together with trace information.

12. the described system of claim 11 also comprises: be used for the device that the index to the target data values container of object code instruction is associated with the appropriate address information of the raw value container of described original program code at the program code translate duration.

13. the described system of claim 12, wherein, the described information relevant with the instruction of at least one object code comprise the following at least one of them:

-corresponding object code instruction address information; And

14. the described system of claim 12, wherein, the described device that is used for storing comprises: be used for a described information relevant with described at least one object code instruction is written to parasitic register file together with the relative address information of described raw value container device.

15. the described system of claim 14 also comprises: the device that is used for the data value capsule address information of described original program code is moved to from the first parasitic register entries of described parasitic register file the second parasitic register entries.

16. the described system of claim 14, wherein, the address information of the target data values container of expression is carried out index to described parasitic register file in the object code instruction.

17. the described system of claim 14 also comprises: be used for supporting based on a plurality of pipeline registers the device of the order continuity of parasitic register file operation, described a plurality of pipeline registers are used to handle read waiting time.

18. the described system of claim 14, wherein, to the operation of described parasitic register file comprise assignment, move, storage and blank operation, and described system also comprises the operations flows processing logic that is used for optionally metoxeny register file operation.

19. the described system of claim 11 also comprises: the device that is used for the original program code being carried out debugging and/or trace analysis based on institute's canned data.

20. the described system of claim 11, wherein, described original program code is suitable for the primitive compuer system, and described object code is suitable for the target computer system different with this primitive compuer system.

21. the described system of claim 11, wherein, described trace information is stored in the data value container corresponding to the memory location that is assigned to variable in the general high-level programming language.