CN101145786B - Integral triangle circuit using time division structure and related method - Google Patents
Integral triangle circuit using time division structure and related method Download PDFInfo
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- CN101145786B CN101145786B CN2006101274856A CN200610127485A CN101145786B CN 101145786 B CN101145786 B CN 101145786B CN 2006101274856 A CN2006101274856 A CN 2006101274856A CN 200610127485 A CN200610127485 A CN 200610127485A CN 101145786 B CN101145786 B CN 101145786B
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Abstract
An integral triangle circuit with a time-sharing structure comprises a coefficient generating unit, an integral triangle processing unit, and a storage unit. The coefficient generating unit is used for generating coefficient of integral triangle operation. The integral triangle processing unit is used for carrying out triangle operation based on the coefficient of integral triangle operation generated by the coefficient generating unit. The storage unit is used for storing the integral triangle operation result of the integral triangle processing unit. The integral triangle circuit is used for carrying out multi-order integral triangle operation through the coefficient generating unit, integral triangle processing unit and storage unit.
Description
Technical field
The present invention provides a kind of integral triangle circuit (Sigma-Delta Circuit) and method thereof, especially refers to a kind of integral triangle circuit and method thereof of using time division structure.
Background technology
Present Audio Processing is used CPU (central processing unit, Central Processing Unit) or DSP (digital signal processor more; Digital Signal Processor) etc. universal processor is realized; Another kind method then is to go up and realize in FPGA (a formula programmable gate array, FieldProgrammable Gate Array); Because the operational frequency range of integral triangle modulator is low, can be easy to go up realization in FPGA.Integral triangle modulator (Sigma-Delta Modulator) has been used on analog to digital converter (A/D Converter) and the digital to analog converter (D/AConverter) widely; It is main because the integral triangle modulator has the ability of noise shaping (Noise Shaping); Can suppress the quantizing noise in the signal frequency range, and then improve signal noise ratio (Signal ToNoise Ratio).Therefore, in the application circuit of high-res (Resolution), middle low speed, the integral triangle modulator generally receives an acclaim.
Please refer to Fig. 1.Fig. 1 is the sketch map of the single order integral triangle modulator 10 of prior art.Single order integral triangle modulator 10 comprises an adder 12, an integrator 13, a quantizer (Quantizer) 14, a digital to analog converter 16 and a filter 18.The principle of integral triangle is earlier rough estimating signal to calculate error, pass through integration then after, further compensating error again.As shown in Figure 1; The feedback signal SFB of one input signal In1 and digital to analog converter 16 gets into adder 12 and subtracts each other, and obtains an error signal Se, and error signal Se passes through the integration of integrator 13 again; Quantize via quantizer 14 subsequently; Because quantization error can cause noise also to be quantized, at last again through wave filter 18 with noise filtering, to export signal Out1.
Please refer to Fig. 2.Fig. 2 is the sketch map of the second order integral triangle modulator 20 of prior art.Second order integral triangle modulator 20 comprises an adder 12, an integrator 13, a second adder 22, a second integral device 23, a quantizer 14, a digital to analog converter 16 and a filter 18.The exponent number of integral triangle modulator (Order) depends on the number of feedback cycle.As shown in Figure 2, the feedback signal SFB of an input signal In1 and digital to analog converter 16 gets into adder 12 and subtracts each other, and obtains an error signal Se, and the integration that error signal Se passes through integrator 13 again is to obtain an integrated signal Si.Integrated signal Si gets into second adder 22 with the feedback signal SFB of digital to analog converter 16 again and subtracts each other; Pass through the integration of second integral device 23 subsequently; Quantize via quantizer 14 again; Because quantization error can cause noise to be quantized in the lump, at last again through wave filter 18 with noise filtering, to export signal Out1.Therefore, second order integral triangle modulator 20 has been done twice integral triangle operation altogether.
By that analogy, along with the exponent number increase of integral triangle operation, the circuit of integral triangle modulator also becomes increasingly complex.Please refer to Fig. 3, Fig. 3 is the sketch map of five rank integral triangle modulators 30 of prior art.As shown in Figure 3, five rank integral triangle operation are to be carried out by a first integral triangulation process unit PE1, a second integral triangulation process unit PE2, a third integral triangulation process unit PE3, one the 4th integral triangle processing unit PE4 and one the 5th integral triangle processing unit PE5.The integral triangle processing unit on each rank comprises a multiplier, an adder and an integrator at least.For instance, second integral triangulation process unit PE2 comprises multiplier a (2), b (2), g (l), c (2), integrator 332 and adder 321,322.In Fig. 3, after an input signal In1 carries out the integral triangle operation on first rank through first integral triangulation process unit PE1, more in regular turn through the integral triangle operation on second rank, the 3rd rank, quadravalence and the 5th rank.After accomplishing the integral triangle operation on five rank, quantize, postpone a unit clock pulse via delayer 37 again, export signal Out1 at last via quantizer 34.Through five rank integral triangle modulators 30, can draw the five rank integral triangle operation of input signal In1.Yet five rank integral triangle modulators 30 need eight adders, 18 multipliers and five integrators at least, and these elements are quite wasted hardware area.
Because Audio Processing is merely the processing of KHz level frequency, can be if directly realize too in the waste hardware cost.Therefore present design uses universal processors such as CPU or DSP to realize that its hardware cost is too high more, and can cause frequency of operation to rise, and therefore is difficult in FPGA and goes up realization.Because in the prior art; Multistage integral triangle circuit need use a lot of adders, multiplier and integrator; If be used in more multistage integral triangle operation; Then need spend more adder, multiplier and integrator, these elements not only increase the also corresponding hardware area that increased of cost of manufacture.
Summary of the invention
The present invention provides the integral triangle circuit of a kind of use time division structure (Time Sharing Architecture), and this delta circuit comprises a coefficient generating unit, an integral triangle processing unit and a memory cell.This coefficient generating unit is used for producing coefficient of integral triangle operation.This integral triangle processing unit is used for the coefficient of integral triangle operation that produces according to this coefficient generating unit, carries out integral triangle operation.This memory cell is used for storing the integral triangle operation result of this integral triangle processing unit.Wherein, this integral triangle circuit is used for carrying out multistage integral triangle operation through this coefficient generating unit, this integral triangle processing unit and this memory cell.
The present invention provides a kind of time division structure that in an integral triangle circuit, uses to come the method for processing audio; This method comprises the generation coefficient of integral triangle operation; According to the coefficient of integral triangle operation that is produced, carry out integral triangle operation, and storage integral triangle operation result.Wherein, carry out multistage integral triangle operation through above-mentioned steps.This method also comprises a plurality of coefficients of reception, receives a status signal, and is exported by selection one coefficient in these a plurality of coefficients according to this status signal.This method also comprises the integral triangle operation result is quantized.
Description of drawings
Fig. 1 is the sketch map of the single order integral triangle modulator of prior art.
Fig. 2 is the sketch map of the second order integral triangle modulator of prior art.
Fig. 3 is the sketch map of five rank integral triangle modulators of prior art.
Fig. 4 uses the sketch map of the integral triangle circuit of time division structure for the embodiments of the invention explanation.
Fig. 5 is the sketch map of the integrator of Fig. 4.
Fig. 6 is another sketch map of the integrator of Fig. 4.
Fig. 7 uses the sketch map of the integral triangle circuit of time division structure for another embodiment of the present invention explanation.
Fig. 8 uses the sketch map of time division structure integral triangle circuit for explanation.
Fig. 9 is the sketch map of an Audio Processing structure.
Figure 10 uses time division structure to come the sketch map of the flow process of processing audio for the present invention is illustrated in the integral triangle circuit.
The main element symbol description
10 single order integral triangle modulators
12,321,322,45,46,52,62,75 adders
13,332,42 integrators
14,34,84 quantizers
16 digital to analog converters
18 filters
In1 input signal Out1 exports signal
20 second order integral triangle modulators
22 second adders, 23 second integral devices
Se error signal S
FBFeedback signal
The Si integrated signal
S
2The second computing signal
30 5 rank integral triangle modulators
PE1 first integral triangulation process unit
PE2 second integral triangulation process unit
PE3 third integral triangulation process unit
PE4 the 4th integral triangle processing unit
PE5 the 5th integral triangle processing unit
a(2)、b(2)、g(l)、c(2)、
431,432,433,434,73 multipliers
37,54,64,76 delayers
40,70 integral triangle circuits, 41 coefficient generating unit
44,74 integral triangle processing units
47 memory cell
The MUX1 first multiplexer MUX2 second multiplexer
MUX3 the 3rd multiplexer
A [l]-a [n], c [l]-c [n], g [l]-g [n], a, c, g coefficient
411,413,415 control ends
412,414,416 outputs
ST1 status signal CNT1 count signal
X、y、
Addsub_res, wen, wptr, rptr, dfram, d2ram parameter
522,524 inputs
622 first input ends, 624 second inputs
The MUX11-MUX66 multiplexer
AA ' dotted line
The t time shaft
The CF1 coefficient
The ADC1 analog to digital converter
I
2S standard digital phonetic matrix
92 sample rate converters, 94 audio treatment units
95 integral triangle modulators, 96 power amplifiers
97 low pass filters, 98 loud speakers
80 flow process 802-810 steps
Embodiment
Please refer to Fig. 4.Fig. 4 uses the sketch map of the integral triangle circuit 40 of time division structure for one embodiment of the invention.Integral triangle circuit 40 comprises a coefficient generating unit 41, an integral triangle processing unit 44 and a memory cell 47.Coefficient generating unit 41 is used for producing coefficient of integral triangle operation a, c, g, and it comprises the first multiplexer MUX1, the second multiplexer MUX2 and the 3rd multiplexer MUX3.The first multiplexer MUX1 comprises n input, a control end 411 and an output 412.This n input is used for receiving n coefficient a [1]-a [n], and control end 411 is used for receiving a status signal ST1, and output 412 is used for according to status signal ST1 by selecting coefficient a output among n coefficient a [1]-a [n].The second multiplexer MUX2 comprises n input, a control end 413 and an output 414.This n input is used for receiving n coefficient c [1]-c [n], and control end 413 is used for accepting state signal ST1, and output 414 is used for according to status signal ST1 by selecting coefficient c output among n coefficient c [1]-c [n].The 3rd multiplexer MUX3 comprises n input, a control end 415 and an output 416.This n input is used for receiving n coefficient g [1]-g [n], and control end 415 is used for accepting state signal ST1, and output 416 is used for according to status signal ST1 by selecting coefficient g output among n coefficient g [1]-g [n].Integral triangle processing unit 44 is used for the coefficient of integral triangle operation a, c, the g that are produced according to coefficient generating unit 41, carries out integral triangle operation.Integral triangle processing unit 44 is general integral triangle processing unit, comprises a multiplier, an adder and an integrator usually at least.As shown in Figure 4; Integral triangle processing unit 44 comprises four multipliers 431,432,433,434; Two adders 45,46 and an integrator 42, wherein, the coefficient of multiplier 431,432,433,434 is respectively coefficient a, a, g, the c that is produced by coefficient generating unit 41.Output signal Out can be expressed as following formula:
Out1≡[∫[a×(In1-y)-g×x]]×c。
If need to carry out five rank integral triangle operation, then make n equal 5, in each rank integral triangle operation, import different coefficient a, c, g and carry out integral triangle operation, can accomplish five rank integral triangle operation.Memory cell 47 is used for storing the integral triangle operation result of integral triangle processing unit 44.Integral triangle circuit 40 is carried out multistage integral triangle operation through coefficient generating unit 41, integral triangle processing unit 44 and memory cell 47.Wherein, memory cell 47 be a random access memory (Random AccessMemory, RAM).
Please refer to Fig. 5.Fig. 5 is the sketch map of the integrator 42 of Fig. 4.Integrator 42 can be made up of an adder 52 and a delayer 54, and forms a feedback loop.Adder 52 comprises two inputs 522,524, is used for receiving the value of an input signal In1 and previous output signal respectively, the value of input signal In1 and previous output signal is carried out addition after, to produce one second computing signal S
2, the second computing signal S
2Postpone a clock pulse to produce last output signal Out1 by delayer 54 again.
Please refer to Fig. 6.Fig. 6 is another sketch map of the integrator 42 of Fig. 4.Integrator 42 can be made up of an adder 62 and a delayer 64, and forms a feedback loop.Adder 62 comprises a first input end 622; Be used for receiving an input signal In1; Reach one second input 624, be coupled to the output of delayer 64, be used for receiving value through the previous output signal after clock pulse of delay; The value of the previous output signal after clock pulse of input signal In1 and process delay is carried out addition, to produce last output signal Out1.
Can know that by Fig. 5 and Fig. 6 the structure of integrator can be considered an adder and a delayer.Therefore the integral triangle processing unit 44 of Fig. 4 can further be simplified to an adder and a multiplier, and arrange in pairs or groups a plurality of multiplexers and a plurality of delayer are to carry out the not computing of same order again.Thus, can reduce more adder and multiplier, further save more hardware area.
Please refer to Fig. 7.Fig. 7 uses the sketch map of the integral triangle circuit 70 of time division structure for another embodiment of the present invention.Integral triangle circuit 70 comprises a coefficient generating unit 41, an integral triangle processing unit 74 and a memory cell 47.Coefficient generating unit 41 is used for producing coefficient of integral triangle operation a, c, g.Coefficient generating unit 41 comprises the first multiplexer MUX1, the second multiplexer MUX2 and the 3rd multiplexer MUX3.Wherein the first multiplexer MUX1, the second multiplexer MUX2 and the 3rd multiplexer MUX3 are used for producing coefficient of integral triangle operation a, c, g, and its operation principle is identical with the embodiment of Fig. 4, narrate no longer in detail in this.Integral triangle processing unit 74 is used for the coefficient of integral triangle operation a, c, the g that are produced according to coefficient generating unit 41, carries out integral triangle operation.Integral triangle processing unit 74 is the integral triangle processing unit after simplifying, and it comprises a multiplier 73, an adder 75, four delayers 76, six multiplexer MUX11-MUX66 and quantizers 84.Memory cell 47 is used for storing the integral triangle operation result of integral triangle processing unit 74, in present embodiment, can be used to store a plurality of parameter addsub_res, wen, wptr, rptr, dfram, d2ram.Because the structure of integrator can be considered an adder and a delayer, integral triangle processing unit 74 is selected which parameter to carry out add operation by through a plurality of multiplexer MUX11-MUX44 in the left-half of dotted line AA '.Integral triangle processing unit 74 then is coefficient a, c, the g that selects coefficient generating unit 41 to be produced through a multiplexer MUX55 earlier at the right half part of dotted line AA ', selects which parameter to get into multiplier 73 to carry out multiplying by through another multiplexer MUX66.Delayer 76 among the figure is used for postponing a clock pulse.Quantizer 84 is used for the integral triangle operation result is quantized.Integral triangle processing unit 74 can be saved the number of multiplier 73 and adder 75 through the selection of a plurality of multiplexer MUX.Integral triangle circuit 70 is carried out multistage integral triangle operation through coefficient generating unit 41, integral triangle processing unit 74 and memory cell 47.Wherein, delayer 76 is a D flip-flop, and memory cell 47 is a random-access memory.
Please refer to Fig. 8.Fig. 8 uses time division structure in the sketch map of integral triangle circuit for explanation.On t on the time shaft; Being divided into is five stages 1,2,3,4,5; Carry out integral triangle operation by five integral triangle processing unit PE1-PE5 respectively; Can select the current state stage by status signal ST1, select to desire in each stage the computing of carrying out (like add operation, multiplying) by count signal CNT1.Through coefficient generating unit 41, can produce different coefficients in the different state stage, for example, produce coefficient a (1), c (1), g (1) in the phase I, by that analogy, produce coefficient a (5), c (5), g (5) in five-stage.Therefore through coefficient generating unit 41 and status signal ST1,, only need an integral triangle processing unit 74 to carry out the integral triangle operation of different phase through this kind time division structure.Use through a plurality of multiplexer MUX11-MUX66 and count signal CNT1 again; Can further save the number of multiplier and adder in the circuit; Only need a multiplier and an adder to carry out different add operations or multiplying, can accomplish integral triangle operation.
Please refer to Fig. 9.Fig. 9 is the sketch map of an Audio Processing structure 90.Audio Processing structure 90 comprises an analog to digital converter ADC1, a sample rate converter 92, an audio treatment unit 94, an integral triangle modulator 95, a power amplifier 96, a low pass filter 97 and a loud speaker 98.Analog to digital converter ADC1 is used for conversion of signals is become number format, like standard digital phonetic matrix I
2S (Inter-ICSound).Standard digital phonetic matrix I
2The signal of S carries out the conversion of sampling rate through sample rate converter 92 earlier or resamples, handle through audio treatment unit 94 again, after carry out integral triangle operation via integral triangle modulator 95 again.Wherein, integral triangle modulator 95 can be integral triangle circuit 40 or the integral triangle circuit 70 among Fig. 7 among Fig. 4, utilizes time division structure to reduce the use number of adder and multiplier.Through the signal behind the integral triangle modulator 95, deliver to power amplifier 96 again, power amplifier 96 can be a D class A amplifier A or a class ab ammplifier.Last signal is delivered to loud speaker 98 and is play, and loud speaker 98 is loudspeaker.Low pass filter 97 is coupled between power amplifier 96 and the loud speaker 98, is used for filtered noise.
Please refer to Figure 10.Figure 10 uses time division structure to come the sketch map of the flow process 80 of processing audio for the present invention is illustrated in the integral triangle circuit.Flow process 80 can be expressed as following step:
Step 802: produce coefficient of integral triangle operation.
Step 804:, carry out integral triangle operation according to the coefficient of integral triangle operation that is produced.
Step 806: storage integral triangle operation result.
Step 808: repeating step 802-808.
Step 810: the result quantizes to integral triangle operation.
In step 802, can according to the calculation step of present exponent number and desire execution, from a plurality of coefficients, select coefficient output through the utilization of a multiplexer.In step 804,, carry out integral triangle operation according to the coefficient of integral triangle operation that is produced.In step 806, the integral triangle operation result is stored in the memory.In step 808,, therefore need repeat to produce the required coefficient of each rank integral triangle operation to carry out the required integral triangle operation in each rank owing to need to carry out the integral triangle operation on n rank.In step 810, after accomplishing all integral triangle operation, last operation result is quantized, accomplish the signal flow of one whole.Wherein, the generation of coefficient of integral triangle operation is controlled by a status signal ST1, and the calculation step that exponent number that integral triangle operation is carried out and desire are carried out then is to be controlled by status signal ST1 and count signal CNT1.
Integral triangle circuit and correlation technique thereof that the above embodiments only are used for explaining use time division structure of the present invention do not limit to category of the present invention.The delayer of being mentioned in the literary composition 76 is not limited to D flip-flop, also can be the delayer of other patterns.Memory cell 47 also is not limited to a random-access memory, also can use other storage device.The number of the multiplexer that coefficient generating unit 41 is comprised corresponds to the coefficient of integral triangle operation number, is not limited to described three multiplexers of embodiment.Integral triangle circuit 40 and the integral triangle circuit of being mentioned in the literary composition 70 all is to use the integral triangle circuit of time division structure; Only integral triangle circuit 70 is through the use of a plurality of multiplexer MUX11-MUX66; Save more adder and multiplier; But be not limited to embodiments of the invention, more variation can be arranged, all belong to category of the present invention.
By on can know, the present invention provide one use time division structure integral triangle circuit.In integral triangle circuit 40 and integral triangle circuit 70; Produce different coefficients through coefficient generating unit 41; Can produce required coefficient in the calculation step of different exponent numbers and desire execution; Control the calculation step that present exponent number and desire are carried out by status signal ST1 and count signal CNT1, can carry out multistage integral triangle operation in regular turn.And, can save more adder and multiplier through the use of a plurality of multiplexer MUX11-MUX66.Thus, can omit more integral triangle operation unit and save elements such as more adder and multiplier, avoid hardware area and cost waste.In addition, frequency of operation still is controlled in the reasonable range, as audio sample rate 44.1KHz; If always have five rank integral triangle operation; Each rank integral triangle operation comprises the calculation step that the Pyatyi desire is carried out, and then frequency of operation is (44.1K * 5 * 5) Hz, still can on FPGA, realize.
The above is merely the preferred embodiments of the present invention, and all equivalences of carrying out according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.
Claims (16)
1. integral triangle circuit that uses time division structure includes:
One coefficient generating unit is used for producing coefficient of integral triangle operation;
One integral triangle processing unit is used for the coefficient of integral triangle operation that produces according to this coefficient generating unit, carries out integral triangle operation; And
One memory cell, the integral triangle operation result who is used for storing this integral triangle processing unit;
Wherein, this integral triangle circuit is used for carrying out multistage integral triangle operation through this coefficient generating unit, this integral triangle processing unit and this memory cell,
Wherein this integral triangle processing unit comprises:
One adder; This adder has a first input end, one second input and an output; This first input end is used for receiving an input signal; This second input is used for receiving an output signal, and this adder is used for this input signal and this output signal are carried out add operation to produce a computing signal; And
One integrator has this output that an input is coupled to this adder, is used for receiving this computing signal, reaches this second input that an output is coupled to this adder, and this integrator is used for this computing signal is carried out integration with this output signal of generation,
Wherein this integral triangle processing unit also comprises one first multiplexer, and this first multiplexer comprises:
One first input end is coupled to this output of this adder, is used for receiving the operation result of this adder;
One second input is coupled to this memory cell, is used for receiving the previous integral triangle operation result of this integral triangle processing unit;
Two control ends are used for receiving a status signal and a count signal respectively; And
One output, operation result or the previous integral triangle operation result of this integral triangle processing unit that this status signal that is used for being received according to this two control end and this count signal are selected this adder of output.
2. integral triangle circuit as claimed in claim 1, wherein this coefficient generating unit also comprises a plurality of second multiplexers, and wherein each second multiplexer comprises:
A plurality of inputs are used for receiving a plurality of coefficients;
One control end is used for receiving this status signal; And
One output is used for according to this status signal by selecting coefficient output in these a plurality of coefficients.
3. integral triangle circuit as claimed in claim 1, wherein this integrator comprises:
One second adder; Have a first input end, one second input and an output; This first input end is used for receiving this computing signal; This second input is used for receiving this output signal, and this second adder is used for this computing signal and this output signal are carried out add operation to produce one second computing signal; And
One delayer; Have an input and be coupled to this output of this second adder; Be used for receiving this second computing signal, reach an output, be coupled to this second input of this second adder; This delayer is used for clock pulse of this second computing signal delay, should the output signal to produce.
4. integral triangle circuit as claimed in claim 3, wherein this delayer is a D flip-flop, is used for this second computing signal of breech lock and in this output signal of next clock pulse output.
5. integral triangle circuit as claimed in claim 1, wherein this integral triangle processing unit also comprises a quantizer, is coupled to this output of this integrator, and this quantizer is used for this output signal is quantized.
6. integral triangle circuit as claimed in claim 1; Wherein this integral triangle processing unit also comprises one the 3rd multiplexer; Be coupled to the output of this coefficient generating unit, the 3rd multiplexer is used for being exported by selection one coefficient in a plurality of coefficients according to this status signal and this count signal.
7. integral triangle circuit as claimed in claim 6, wherein this integral triangle processing unit also comprises a multiplier, and this multiplier comprises:
One first input end is coupled to the output of the 3rd multiplexer, is used for receiving the coefficient that the 3rd multiplexer is exported;
One second input is coupled to this first multiplexer, is used for receiving the operation result or the previous integral triangle operation result of this integral triangle processing unit of this adder; And
One output;
Wherein, the coefficient that this multiplier is used for this first multiplexer is exported and the operation result or the previous integral triangle operation result of this integral triangle processing unit of this adder carry out multiplying, to produce the integral triangle operation result.
8. integral triangle circuit as claimed in claim 1, wherein this memory cell is a memory.
9. integral triangle circuit as claimed in claim 1, wherein this memory cell is a random-access memory.
10. one kind is used time division structure to come the method for processing audio in an integral triangle circuit, and this method comprises:
Produce coefficient of integral triangle operation;
According to the coefficient of integral triangle operation that is produced, carry out integral triangle operation; And
Storage integral triangle operation result;
Wherein, carry out multistage integral triangle operation through above-mentioned steps,
Wherein, carry out integral triangle operation and comprise according to the coefficient of integral triangle operation that is produced:
Receive an input signal and an output signal, this input signal and this output signal are carried out add operation to produce a computing signal; And
This computing signal is carried out integration with this output signal of generation,
Wherein should carry out integral triangle operation, also comprise according to the coefficient of integral triangle operation that is produced:
Receive the operation result of this add operation;
Receive previous integral triangle operation result;
Receive a status signal and a count signal; And
Select to export the operation result or the previous integral triangle operation result of this add operation according to this status signal that is received and this count signal.
11. method as claimed in claim 10, it also comprises:
Receive a plurality of coefficients;
Receive this status signal; And
Export by selection one coefficient in these a plurality of coefficients according to this status signal.
12. method as claimed in claim 10 is wherein carried out integration to this computing signal and is comprised to produce this output signal:
This computing signal and this output signal are carried out add operation to produce one second computing signal; And
With clock pulse of this second computing signal delay, should the output signal to produce.
13. method as claimed in claim 12 wherein postpones a clock pulse and refers to this second computing signal of breech lock and export this output signal in next clock pulse.
14. method as claimed in claim 10, it also comprises:
This output signal is quantized.
15. method as claimed in claim 10 wherein according to the coefficient of integral triangle operation that is produced, is carried out integral triangle operation, also comprises according to this status signal and this count signal to be exported by selection one coefficient in a plurality of coefficients.
16. method as claimed in claim 15 wherein should be carried out integral triangle operation according to the coefficient of integral triangle operation that is produced, and also comprised:
The coefficient of output is selected in reception according to this status signal and this count signal;
Receive the operation result or the previous integral triangle operation result of this add operation; And
To selecting the coefficient of output and the operation result or the previous integral triangle operation result of this add operation to carry out multiplying, to produce the integral triangle operation result according to this status signal and this count signal.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0531604A1 (en) * | 1991-06-28 | 1993-03-17 | ALCATEL BELL Naamloze Vennootschap | Digital sigma-delta modulator |
| CN1150507A (en) * | 1994-06-07 | 1997-05-21 | 芬西泰克元件公司 | Oversampled high-order modulator |
| US6396428B1 (en) * | 2001-06-04 | 2002-05-28 | Raytheon Company | Continuous time bandpass delta sigma modulator ADC architecture with feedforward signal compensation |
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2006
- 2006-09-15 CN CN2006101274856A patent/CN101145786B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0531604A1 (en) * | 1991-06-28 | 1993-03-17 | ALCATEL BELL Naamloze Vennootschap | Digital sigma-delta modulator |
| CN1150507A (en) * | 1994-06-07 | 1997-05-21 | 芬西泰克元件公司 | Oversampled high-order modulator |
| US6396428B1 (en) * | 2001-06-04 | 2002-05-28 | Raytheon Company | Continuous time bandpass delta sigma modulator ADC architecture with feedforward signal compensation |
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