CN101101898A - 层叠封装的底部衬底及其制造方法 - Google Patents

层叠封装的底部衬底及其制造方法 Download PDF

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CN101101898A
CN101101898A CNA200710079435XA CN200710079435A CN101101898A CN 101101898 A CN101101898 A CN 101101898A CN A200710079435X A CNA200710079435X A CN A200710079435XA CN 200710079435 A CN200710079435 A CN 200710079435A CN 101101898 A CN101101898 A CN 101101898A
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insulating barrier
hole
central layer
pad
solder ball
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CN100562995C (zh
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朴正现
闵炳烈
柳济光
姜明杉
郑会枸
金智恩
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Abstract

本发明披露了一种层叠封装的底部衬底及其制造方法。通过焊球电连接至顶部衬底的层叠封装的底部衬底包括：芯板；焊球垫，对应于焊球的位置形成在芯板的表面上；绝缘层，层压在芯板上；通孔，通过去部分除绝缘层以露出焊球垫；以及金属层，填充在通孔中并与焊球电连接，该层叠封装的底部衬底允许在不增加焊球尺寸的情况下，增加装配在底部衬底上的IC数量，并允许通过控制层压在底部衬底上的绝缘层的厚度使得焊球的尺寸和间距更小，从而在顶部衬底和底部衬底之间可以传输更多的信号。

Description

层叠封装的底部衬底及其制造方法
相关申请的交叉参考
本申请要求于2006年7月6日提交到韩国知识产权局的第10-2006-0063633号韩国专利申请的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及层叠封装的底部衬底及其制造方法。
背景技术
随着电子工业的发展，要求电子组件具有高性能、高密度和小型化。为了满足这些要求，对实现通过将电子器件(诸如IC)装配在印刷电路板上制造的所谓“封装衬底”的建议和要求在增加，其中，在实现封装衬底的多种方法中，通过在一个封装衬底上层压另一个封装衬底而制造的所谓“层叠封装(POP)”作为一种很好的替换方法正倍受关注。
关于POP，在将一个电子器件装配在衬底上以符合高端和高密度产品的要求的趋势中，已经出现了通过在衬底上堆叠多个电子器件而制造的所谓“叠层封装”。
在实现POP的处理中，封装的总体厚度是非常重要的，并且从将一个IC装配在衬底上的趋势看，已经产生了将两个或更多IC装配在衬底上以使POP更高端的要求。但是，这种方法在实现POP中存在限制，这是因为在将两个或更多IC装配在衬底上的情况下，增加了封装的总厚度。
关于POP的传统结构，IC装配在位于下面的底部衬底的表面上。利用用于印刷电路板的一般制造方法来制造底部衬底。如上所述，存在对其中装配有两个或更多IC的多叠层的需要，但是很难通过传统制造方法在保持POP的总体高度的同时增加装配在底部衬底上的IC数量。
为此，通过应用所谓“管芯变薄(Die Thinning)”方法(通过该方法切除IC芯片的除必要部分以外的其他部分)已经作出了所有努力来解决以上问题。但是，随着在运行已应用了该方法的IC芯片一段很长的时间时会导致功能误差(function-error)的出现，已经作出了尝试以更适当地减小衬底厚度，来提高POP的装配能力并实现多叠层。
此外，在传统POP中，在制造IC稀释剂(IC thinner)的情况下，为将两个或更多IC堆叠在底部衬底上，就导致了处理中的问题以及热变形等。
而且，不是通过使IC变薄而是通过增加将顶部封装电连接至底部封装的焊球的尺寸，可以增加封装之间的间隙。但是，当堆叠的IC数量增加时，增加焊球数量造成了设计焊球垫(solder ball pad)的数量及其之间的间隔的限制。
发明内容
本发明的多个方面提供了层叠封装的底部衬底及其制造方法，其保证封装之间的间隙，以使在底部衬底上可以装配两个或更多电子器件，而不增加总体厚度，以实现POP。
本发明的一个方面提供了一种通过焊球电连接至顶部衬底的层叠封装的底部衬底，其包括：芯板(core board)；焊球垫，对应于焊球位置形成在芯板的表面上；绝缘层，层压在芯板上；通孔，通过去除部分绝缘层形成，以露出焊球垫；以及金属层，填充在通孔中并与焊球电连接。
绝缘层可以通过将光刻胶层压在芯板上并通过加热使其硬化而形成。
电子器件可以装配在底部衬底上，并且底部衬底可以进一步包括：焊垫(bonding pad)，形成在芯板上并电连接至电子器件；以及空穴，通过去除部分绝缘层形成，以露出焊垫。
本发明的另一个方面提供了一种层叠封装，包括：芯板；焊球垫和焊垫，形成在芯板的表面上；绝缘层，层压在芯板上；通孔，通过去除部分绝缘层而形成，以露出焊球垫；金属层，填充在通孔中；焊球，电连接至金属层；空穴，通过去除部分绝缘层形成，以露出焊垫；电子器件，装配在空穴上且与焊垫电连接；以及顶部衬底，与芯板接合以覆盖电子器件并与焊球电连接。
绝缘层可以通过将光刻胶层压在芯板上并通过加热使其硬化而形成。
本发明的又一个方面提供了一种制造通过焊球与顶部衬底电连接的层叠封装的底部衬底的方法，其包括：(a)对应于焊球的位置在芯板的表面上形成焊球垫；(b)将绝缘层层压在芯板上；(c)通过去除部分绝缘层形成通孔，以露出焊球垫；以及(d)在通孔中填充金属层。
操作(a)可以进一步包括在芯板的表面上涂敷阻焊剂。
电子器件可以装配在底部衬底上，并且操作(a)可以包括在芯板的表面上形成与电子器件电连接的焊垫，以及操作(c)可以包括通过去除部分绝缘层而形成空穴，以露出焊垫。
绝缘层可以包括光刻胶，并且操作(c)可以包括选择性地曝光和显影绝缘层。该方法可以在操作(c)和操作(d)之间进一步包括操作：(h)通过加热使绝缘层硬化。
该方法在操作(h)和操作(d)之间可以进一步包括：在空穴上涂敷光刻胶。可以通过施加电在焊球垫上形成镀层来执行操作(d)。该方法可以在操作(d)之后进一步包括：去除涂敷在空穴上的光刻胶。
本发明的另一方面提供了一种制造层叠封装的方法，其包括：(a)在芯板的表面上形成焊球垫和焊垫；(b)将绝缘层层压在芯板上；(c)通过去除部分绝缘层形成通孔，以露出焊球垫，以及通过去除部分绝缘层形成空穴，以露出焊垫；(d)在通孔中填充金属层；(e)将电子器件装配在空穴上，以与焊垫电连接；(f)使焊球与金属层接合；以及(g)使顶部衬底与芯板接合，以覆盖电子器件并与焊球电连接。
操作(a)可以包括在芯板的表面上涂敷阻焊剂。绝缘层可以包括光刻胶，并且操作(c)可以包括选择性曝光和显影绝缘层。
该方法在操作(c)和操作(d)之间可以进一步包括操作：(h)通过加热使绝缘层硬化。该方法在操作(h)和操作(d)之间可以进一步包括：在空穴上涂敷光刻胶。可以通过施加电在焊球垫上形成镀层来执行操作(d)。
该方法在操作(d)和操作(e)之间可以进一步包括：去除涂敷在空穴上的光刻胶。
本发明的其他方面和优点将部分地在以下说明中进行描述，并且部分通过该描述将变得显而易见，或可以通过实施本发明而了解。
附图说明
图1是示出根据本发明的层叠封装的底部衬底的实施例的截面图；
图2是示出根据本发明的层叠封装的底部衬底的制造方法的实施例的流程图；
图3是示出根据本发明的层叠封装的底部衬底的制造过程的实施例的流程图；
图4是示出根据本发明的层叠封装的底部衬底的制造方法的另一实施例的流程图；
图5是示出根据本发明的层叠封装的实施例的截面图。
具体实施方式
以下将参考附图更详细地描述本发明的一些实施例。在参考附图的描述中，不论图号，以相同和相应的参考标号表示那些部件，并且省略赘述。
图1是示出根据本发明的层叠封装的底部衬底的实施例的截面图。参考图1，示出了芯板10、焊球垫12、焊垫14、绝缘层20、空穴24、和金属层28。
本实施例的特征在于：制造具有通过制造印刷电路板的传统方法形成的一层或多层电路图案的底部衬底的芯板10；然后通过在封装之间插入通过硬化光刻胶形成的绝缘层20和通过电镀焊球垫12的一部分而形成的金属层28，来保证封装之间的间隙，以使更多的电子器件可以装配在底部衬底上。
根据本实施例的POP的底部衬底是用于通过焊球与顶部衬底电连接的POP的衬底。以下，用于底部封装的衬底被称为“底部衬底”，而用于顶部封装的衬底被称为“顶部衬底”，但是“顶部衬底”和“底部衬底”都不一定限于上部或下部的位置，并且在以与本实施例相同的结构制造POP的范围内，底部衬底可以位于上部，顶部衬底可以位于下部。
根据本实施例的POP的底部衬底通过将绝缘层20层压在芯板10上形成，以保证到顶部衬底的更多空间。以覆盖装配在底部衬底上的电子器件的高度的厚度来层压绝缘层20。如上所述，如果装配在底部衬底上的电子器件的高度仅为被焊球的尺寸覆盖，则焊球的尺寸还随着所装配的电子器件的数量的增加而增加，从而在设计中强加更多的约束。
在本实施例中，用于封装之间的电连接的焊球与绝缘层20接合，并且通过利用去除层压的绝缘层20的相应部分形成通孔而露出形成在对应于焊球位置的芯板10表面上的焊球垫12。如下所述，在通孔中，通过电镀来填充金属层28，并且实现到焊球的电连接。
在底部衬底中，形成与电子器件电连接的焊垫14，其上装配有电子器件。上述焊球12和焊垫14可以分别以不同的工艺来形成，或可以在在芯板10上形成电路图案的过程中作为电路图案的一部分来形成。
为了装配电子器件，通过去除绝缘层20的相应部分而在层压在芯板10上的绝缘层20中形成空穴24，以露出将要装配电子器件的部分(即，形成焊垫14的部分)。代替在底部衬底上装配电子器件并使用焊球与顶部衬底电连接，通过在绝缘层20中形成空穴24和装配电子器件来获得对应于绝缘层20的厚度(即，空穴24的深度)的空间，使得可以装配更多的电子器件。这样，在不增加焊球尺寸的情况下，通过控制绝缘层20的厚度，来保证底部衬底和顶部衬底之间的足够间隙。
由于在绝缘层20被层压在芯板10上之后，焊球垫12和焊垫14的多个部分将被选择性地去除，因此，其优选地包括可用于曝光、显影和蚀刻处理的感光材料。绝缘层20可以包括其性质可以改变的材料，以使在已经选择性地去除了必要部分之后，在随后的蚀刻处理过程中不被去除。例如，在光刻胶被层压在芯板10上作为绝缘层20的材料的情况下，在通过曝光、显影和蚀刻形成通孔和空穴24之后，通过施加红外辐射或热使绝缘层20硬化可以使绝缘层20在随后的蚀刻处理过程中不被去除。
对于可用于曝光和显影、以及通过硬化可以用作绝缘材料的材料，可以使用诸如“FR-4”、“BT树脂”等通常使用的材料，以及具有如下化学式(1)的双键结构(double joining structure)的材料。
Figure A20071007943500121
化学式(1)
图2是示出根据本发明的层叠封装的底部衬底的制造方法的实施例的流程图，并且图3是示出根据本发明的层叠封装的底部衬底的制造过程的实施例的流程图。参考图3，示出了芯板10、焊球垫12、焊垫14、绝缘层20、通孔22、空穴24、光刻胶26、以及金属层28。
根据本实施例，为了制造通过焊球与顶部衬底电连接的POP的底部衬底，首先，如图3(a)所示，在芯板10的表面上形成焊球垫12和焊垫14(100)。如上所述，在在芯板10表面上形成电路图案的过程中，可以将焊球垫12和焊垫14作为电路图案的多个部分来形成。
焊球垫12是焊球将被接合以与顶部衬底电连接的部分，以及焊垫14是与装配在底部衬底上的电子器件电连接的部分。在已经形成了包括焊球垫12和焊垫14的电路图案之后，在芯板10表面上涂敷阻焊剂，并且在衬底上执行表面处理工艺。
接下来，如图3(b)所示，将绝缘层20层压在芯板10上(102)。对于绝缘层20的材料，如上所述，可以使用诸如光刻胶等可以通过曝光和显影选择性地蚀刻且其性质可以通过硬化而改变的材料。
绝缘层20的层压可以通过层压膜式(film-type)绝缘材料来执行，或通过涂敷液体型(liquid-type)绝缘材料等来执行。绝缘层20起到在POP中保持封装与封装之间(即，底部衬底和顶部衬底之间)的间隙并且保护在封装之间接通电信号的金属层28的作用，所以可靠地形成之。
接下来，如图3(c)中所示，通过对绝缘层20选择性地应用曝光、显影和蚀刻来去除绝缘层20的多个部分，以使用底版薄膜(照相底版薄膜，原图薄膜，art work film)等使焊球垫12和焊垫14露出。从而，在形成焊球垫12的部分中形成通孔22，并且在形成空穴24的部分中形成焊垫14(104)。
在通过去除一部分绝缘层20形成通孔22和空穴24之后，将红外辐射或热施加至绝缘层20以使绝缘层20硬化(106)。这样是为了防止绝缘层20在随后的蚀刻处理过程中被去除。
接下来，如图3(d)所示，在露出焊垫14的空穴24的空间内涂敷光刻胶(108)。由于在焊垫14涂有光刻胶26时，其可以在随后电镀处理过程中用作阻挡焊垫14上的不必要的镀层部分的抗蚀剂。
接下来，如图3(e)所示，通过给芯板10的电路图案(诸如焊球垫12等)施加电并执行电镀，在部分焊球垫12上镀上镀层。从而，作为镀层的金属层28被填充在通过选择性地去除绝缘层20形成的通孔22中(110)。对于电镀金属，可以使用锡、铜等。同样地，填充在通孔22中的金属层28用作在芯板10的焊球垫12和焊球之间的电连接路径。
最后，如图3(f)所示，为了涂敷焊垫14，剥落或去除涂敷在空穴24的一部分上的光刻胶26，从而完成根据本实施例的POP的底部衬底的制造(112)。从而，露出焊垫14使得电子器件可以装配在空穴24的空间内。
如上所述，使用热或红外线硬化绝缘层20，以保留硬化的绝缘层20而不会使其在去除涂敷在空穴24的空间内的光刻胶26的过程中被剥落。
图4是示出根据本发明的层叠封装的底部衬底的制造方法的另一实施例的流程图。
上述POP的底部衬底的制造方法可以应用在POP制造过程中。即，根据上述实施例，在制造了底部衬底之后，可以装配电子器件，并使顶部衬底与插入的焊球接合，以制造多叠层POP。
首先，在芯板10表面上形成焊球垫12和焊垫14(200)。如上所述，在芯板10的表面上形成电路图案的过程中，可以将焊球垫12和焊垫14作为电路图案的多个部分来形成。在形成包括焊球垫12和焊垫14的电路图案之后，在芯板10表面上涂敷阻焊剂，并且在衬底上执行表面处理工艺。
接下来，将绝缘层20层压在芯板10上(202)。如上所述，对于绝缘层20的材料，可以使用诸如光刻胶等的可通过曝光和显影被选择性地蚀刻并且其性质可以通过硬化而改变的材料。绝缘层20起到在POP中保持封装与封装之间(即，底部衬底和顶部衬底之间)的间隙、以及保护在封装之间接通电信号的金属层28的作用，因此可靠地形成之。
接下来，通过选择性地曝光、显影和蚀刻绝缘层20去除绝缘层20的一部分，以露出焊球垫12和焊垫14。从而，在形成焊球垫12的部分中形成通孔22，并且在形成焊垫14的部分中形成空穴24(204)。
在通过去除绝缘层20的一部分形成通孔22和空穴24之后，对绝缘层20施加红外辐射或热以硬化绝缘层20(206)。这样防止了在随后的蚀刻过程中绝缘层20被去除。
接下来，在露出焊垫14的空穴24的空间中涂敷光刻胶(208)。当焊垫14涂有光刻胶26的情况下，其可以在随后的电镀处理过程中用作阻挡焊垫14上的不必要的镀层部分的阻焊剂。
接下来，通过给电路图案(诸如芯板10的焊球垫12等)施加电并执行电镀，在焊球垫12的一部分上镀上镀层。从而，作为电镀层的金属层28被填充在通过选择性地去除绝缘层20而形成的通孔22中(210)。填充在通孔22中的金属层28起到芯板10的焊球垫12和焊球之间的电连接的路径的作用。
接下来，为了涂敷焊垫14，剥落和去除涂敷在空穴24的一部分上的光刻胶，从而制造了底部衬底。因此，露出了焊垫14，因此可以在空穴24的空间内装配电子器件。因为绝缘层20通过施加热或红外射线被硬化，因此在去除涂敷在空穴24的空间中的光刻胶26的处理过程中，硬化后的绝缘层20保留而不被剥落。
接下来，在空穴24内装配电子器件，使得电子器件与焊垫14电连接(214)、焊球与填充在通孔22中的金属层28接合(216)，然后层压顶部衬底以与焊球电连接(218)。另一电子器件可以装配在顶部衬底上，在这种情况下，具有装配在顶部衬底上的电子器件的封装被堆叠在具有装配在底部衬底上的电子器件的封装上，从而完成POP的制造。
图5是示出根据本发明的层叠封装的实施例的截面图。参考图5，示出了芯板10、焊球垫12、焊垫14、绝缘层20、金属层28、焊球30、电子器件32、底部衬底40、以及顶部衬底50。
在制造根据上述POP制造方法制造的POP中，将绝缘层20层压在底部衬底40上，并且形成通孔22和空穴24，以保证足够的间隙而不增加焊球30的尺寸，以使得可以实现多叠层的结构。
即，在根据本实施例的POP结构中，将电子器件32装配在图1所述的底部衬底40的空穴24中，与焊垫14电连接，焊球30与填充在通孔22中的金属层28接合，然后装配有电子器件32的顶部衬底50堆叠在其上，与焊球30电连接。
如上所述，在底部衬底40的结构中，在芯板10表面上形成包括焊球垫12和焊垫14的电路图案，层压绝缘层20，通过去除绝缘层20的多个部分形成通孔22和空穴24，以露出焊球垫12和焊垫14，然后通过在通孔22中填充镀层来在焊球30和焊球垫12之间实现电路径。
为了使绝缘层20占据POP的封装之间(即，底部衬底40和顶部衬底50之间)的间隙，优选地使用为形成通孔22和空穴24而可以被选择性地去除、并且在去除涂敷在空穴24中的光刻胶26的过程中不被一起去除的材料。
例如，在根据本发明实施例的在将光刻胶作为绝缘层20层压在芯板10上的情况中，在通过曝光、显影和蚀刻形成通孔22和空穴24之后，可以通过施加热和红外射线等使其硬化，以使在随后的蚀刻过程中不被去除。
根据上述本发明的一些方面，可以增加装配在底部衬底上的IC数量，而不增加焊球尺寸，通过控制层压在底部衬底上的绝缘层的厚度可以使焊球的尺寸和间距(pitch)更小，从而可以在顶部衬底和底部衬底之间传输更多的信号。
此外，通过控制作为层压在底部衬底上的绝缘材料的光刻胶的厚度可以容易地控制封装之间的间隙，从而可以在底部衬底上堆叠和装配更多的电子器件。
尽管已经参考具体实施例描述了本发明，但可以理解，对于本领域技术人员来说，在不脱离通过所附权利要求及其等价物限定的本发明的精神和范围的情况下，可以作出多种改变和修改。

Claims (20)

1.一种通过焊球电连接至顶部衬底的层叠封装的底部衬底，所述底部衬底包括：
芯板；
焊球垫，对应于所述焊球的位置形成在所述芯板的表面上；
绝缘层，层压在所述芯板上；
通孔，通过去除部分所述绝缘层而形成，以露出所述焊球垫；以及
金属层，填充在所述通孔中并与所述焊球电连接。
2.根据权利要求1所述的层叠封装的底部衬底，其中，所述绝缘层通过将光刻胶层压在所述芯板上并通过加热使其硬化而形成。
3.根据权利要求1所述的层叠封装的底部衬底，其中，在所述底部衬底上装配电子器件，所述底部衬底进一步包括：
焊垫，形成在所述芯板上，并且电连接至所述电子器件；
以及
空穴，通过去除部分所述绝缘层形成，以露出所述焊垫。
4.一种层叠封装，包括：
芯板；
焊球垫和焊垫，形成在所述芯板的表面上；
绝缘层，层压在所述芯板上；
通孔，通过去除部分所述绝缘层而形成，以露出所述焊球垫；
金属层，填充在所述通孔中；
焊球，电连接至所述金属层；
空穴，通过去除部分所述绝缘层而形成，以露出所述焊垫；
电子器件，装配在所述空穴上，并与所述焊垫电连接；
顶部衬底，与所述芯板接合以覆盖所述电子器件并与所述焊球电连接。
5.根据权利要求4所述的层叠封装，其中，所述绝缘层通过将光刻胶层压在所述芯板上并通过加热使其硬化而形成。
6.一种制造通过焊球与顶部衬底电连接的层叠封装的底部衬底的方法，所述方法包括：
(a)对应于所述焊球的位置，在芯板表面上形成焊球垫；
(b)将绝缘层层压在所述芯板上；
(c)通过去除部分所述绝缘层形成通孔，以露出所述焊球垫；以及
(d)将金属层填充在所述通孔中。
7.根据权利要求6所述的方法，其中，所述操作(a)进一步包括在所述芯板的表面上涂敷阻焊剂。
8.根据权利要求6所述的方法，其中，在所述底部衬底上装配电子器件，所述操作(a)包括在所述芯板的表面上形成与所述电子器件电连接的焊垫，以及所述操作(c)包括通过去除部分所述绝缘层形成空穴，以露出所述焊垫。
9.根据权利要求8所述的方法，其中，所述绝缘层包括光刻胶，并且所述操作(c)包括选择性地曝光和显影所述绝缘层。
10.根据权利要求9所述的方法，在所述操作(c)和所述操作(d)之间进一步包括以下操作：
(h)通过加热使所述绝缘层硬化。
11.根据权利要求10所述的方法，在所述操作(h)和所述操作(d)之间进一步包括：在所述空穴上涂敷光刻胶。
12.根据权利要求11所述的方法，其中，通过施加电在所述焊球垫上形成镀层来执行所述操作(d)。
13.根据权利要求12所述的方法，在所述操作(d)之后进一步包括：去除涂敷在所述空穴上的所述光刻胶。
14.一种制造层叠封装的方法，所述方法包括：
(a)在芯板的表面上形成焊球垫和焊垫；
(b)将绝缘层层压在所述芯板上；
(c)通过去除部分所述绝缘层形成通孔，以露出所述焊
球垫，以及通过去除部分所述绝缘层形成空穴，以露出所述焊垫；
(d)在所述通孔中填充金属层；
(e)将所述电子器件装配在所述空穴上以与所述焊垫电连接；
(f)将所述焊球与所述金属层接合；以及
(g)将顶部衬底与所述芯板接合，以覆盖所述电子器件并与所述焊球电连接。
15.根据权利要求14所述的方法，其中，所述操作(a)包括在所述芯板的表面上涂敷阻焊剂。
16.根据权利要求14所述的方法，其中，所述绝缘层包括光刻胶，以及所述操作(c)包括选择性曝光和显影所述绝缘层。
17.根据权利要求16所述的方法，在所述操作(c)和操作(d)之间进一步包括以下操作：
(h)通过加热使所述绝缘层硬化。
18.根据权利要求17所述的方法，在所述操作(h)和所述操作(d)之间进一步包括：在所述空穴上涂敷光刻胶。
19.根据权利要求18所述的方法，其中，通过施加电在所述焊球垫上形成镀层来执行所述操作(d)。
20.根据权利要求19所述的方法，在所述操作(d)和所述操作(e)之间进一步包括：去除所述空穴上涂敷的所述光刻胶。
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CN102728957B (zh) * 2009-02-23 2015-09-16 韩美半导体株式会社 半导体封装及制造半导体封装的方法
CN103515336A (zh) * 2012-06-27 2014-01-15 英飞凌科技股份有限公司 芯片封装、芯片布置、电路板以及用于制造芯片封装的方法
US9859198B2 (en) 2012-06-27 2018-01-02 Infineon Technologies Ag Chip packages, chip arrangements, a circuit board, and methods for manufacturing chip packages
CN104995732A (zh) * 2012-12-20 2015-10-21 英闻萨斯有限公司 用于具有封装键合元件的微电子封装的结构
CN107393878A (zh) * 2013-12-05 2017-11-24 株式会社村田制作所 元器件内置模块
CN107393878B (zh) * 2013-12-05 2019-11-08 株式会社村田制作所 元器件内置模块
CN110010581A (zh) * 2018-01-05 2019-07-12 意法半导体(格勒诺布尔2)公司 绝缘接触间隔件

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