CN101042640A - Digital signal processor with bit expansion and bit compressing compressing cell - Google Patents

Digital signal processor with bit expansion and bit compressing compressing cell Download PDF

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Publication number
CN101042640A
CN101042640A CN 200710039868 CN200710039868A CN101042640A CN 101042640 A CN101042640 A CN 101042640A CN 200710039868 CN200710039868 CN 200710039868 CN 200710039868 A CN200710039868 A CN 200710039868A CN 101042640 A CN101042640 A CN 101042640A
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data
unit
register
bit
digital signal
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张达文
李兴仁
金荣伟
刘春晖
林锦麟
杨一茜
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Shanghai Hualong Information Technology Development Center
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SHANGHAI HUALONG INFORMATION TECHNOLOGY DEVELOPMENT CENTER
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Abstract

This invention discloses one digital signal processor with bit expend and bit compression unit, which comprises digital signal processor nuclear, order memory and data memory, wherein, the nuclear comprises program control unit, order coding unit, address generation unit and data computation unit. This invention is characterized by the following: the computation unit is integrated with one bit expend and bit compression unit; the unit is composed of timer, displacement device and two source operation number and one aim register device.

Description

A kind of digital signal processor that has position expansion and position compression unit
Technical field:
What the present invention relates to is a kind of digital signal processor, particularly a kind of digital signal processor that has position expansion and position compression unit.
Background technology:
As everyone knows, the function of microprocessor almost completely depends on instruction set, so to a certain extent, the development of microprocessor has also been represented in the development of instruction set.Gradually become strong at microprocessor function nowadays, under the development trend that speed constantly speeds, instruction set is also in continuous development, develop into the complicated order instruction set from lean instruction set, it is simple but the reduced instruction set computer of instruction set feature richness presents spiralling state to revert to the individual instructions function from sophisticated vocabulary again.
Informationalized basis is digitizing.One of digitized core technology is a digital signal processing.The task of digital signal processing need be finished by the DSP device to a great extent.The DSP technology has become cutting edge technology people's growing interest and that obtain developing rapidly.DSP is transformed into digital signal in simulating signal to carry out the application specific processor that high-speed real-time is handled, also fast 10~50 times than the fastest CPU of its processing speeds later on.Under current digital times background, DSP has become the basic device in fields such as communication, computing machine, consumer electronics product.Insider's prophesy, DSP will be an electronic product with fastest developing speed in the following integrated circuit, and become the determinative that electronic product updates.
Digital signal processing can only rely on MPU (microprocessor) to finish before DSP occurs.But the processing speed that MPU is lower can't satisfy the requirement of high-speed real-time.Therefore, there is the seventies people to propose theory and the algorithm basis of DSP.And DSP only rests on the textbook, even if the dsp system of developing also is made up of discrete assembly, its application only is confined to military affairs, the aviation big department of navigating.
Along with the development of large scale integrated circuit technology, nineteen eighty-two the first dsp chip that has been born in the world.This DSP device adopts micron technology NMOS fabrication techniques, though power consumption and size are big slightly, arithmetic speed is faster tens times than MPU, has especially obtained widespread use in phonetic synthesis and coding decoder.The appearance of dsp chip indicates that the DSP application system has strided forward major step by large scale system to miniaturization.Along with CMOS development of technology and development, the second generation is arisen at the historic moment based on the dsp chip of CMOS technology, and its memory capacity and arithmetic speed significantly improve, and becomes the basis of speech processes, image hardware handles technology.In the later stage eighties, third generation dsp chip comes out, and arithmetic speed further improves, and it is applied to scope and progressively expands communication, computer realm to.
The nineties, DSP was with fastest developing speed, had occurred the 4th generation and the 5th generation DSP device in succession.Present DSP belong to the 5th generation product, it was compared with the 4th generation, level of integrated system is higher, with DSP core and peripheral assembly comprehensive integration on one chip.The high dsp chip of this integrated level is not only exhibited one's skill to the full in communication, computer realm, and is penetrated into people's current consumption field gradually, and prospect is very considerable.
Characteristics and the advantage of existing DSP
1. hardware characteristics
(1) DSP belongs to Modified Harvard framework, and promptly it has two internal buss: data bus, program bus.Program is separated with data space, and independently address bus and data bus are respectively arranged, and gets finger and reading and can carry out simultaneously, has reached 9,000,000,000 floating-point operation/seconds (9000MFLOPS) at present.
(2) adopt line production.The execution of every instruction is divided into some steps such as instruction fetch, decoding, peek, execution, is finished respectively by a plurality of functional units in the sheet.Be equivalent to many executing instructions, thereby improved arithmetic speed greatly.
(3) hardware multiplier independently.Multiplying order was finished in the monocycle, optimized a large amount of repetition multiplication in convolution, digital filtering, FFT, relevant, the matrix operation scheduling algorithm.
(4) cyclic addressing (Circular addressing), bit-reversed special instructions such as (bit-reversed) improves addressing, ordering and computing velocity in the computings such as FFT, convolution greatly.The time of 1024 FFT is less than 1 μ s.
(5) independently dma bus and controller.One or more groups independently dma bus is arranged, and with program, the data bus concurrent working of CPU, under the condition that does not influence CPU work, DMA speed reaches more than the 800Mbyte/s.
(6) multiprocessor interface.A plurality of processors can be walked abreast very easily or work in series to improve processing speed.
(7) JTAG (Joint Test Action Group) standard testing interface (IEEE 1149 standard interfaces).Be convenient to DSP is done in-circuit emulation on the sheet and the debugging under many DSP condition.
2. software feature
(1) count addressing immediately: operand can directly obtain from instruction for counting immediately.
(2) directly address: data-carrier store is divided into 2 mPage or leaf, every page 2 nWord.A data page pointer is set, points to a data page, add the page or leaf bias internal address of a n-bit, form the data address of (m+n)-bit with m-bit.Help accelerating addressing speed like this.
(3) indirect addressing: 1. 8 background registers, specify a background register arithmetical unit to do the computing of 16-bit unsigned number by a background register pointer, determine a new address, in the background register of packing into one.2. the content of 8 background registers is quite flexible, can pack into, add, deducts immediately and count; Can adorn the people address from data-carrier store; Can also do some indexed addressings.3. owing to adopt reverse carry, be achieved the bit-reversed addressing.
(4) Du Te multiplying order:, actually finish a multiply operation, an add operation and a data-moving operation by a multiplying order
The DSP that reaches its maturity still has the improved place of many needs, also is faced with lot of challenges simultaneously.
(1) how reasonably arranging data flow process makes it between each performance element of DSP ensuring escapement from confliction and carries out smoothly, is still the important problem that DSP developer faces.Because the complicacy of design when being mapped to algorithm on the DSP objectives hardware, still can not adopt high-level programming language, must use assembly language, and the executed in parallel mechanism of device is had understanding fully aware of.And this programmed that is confined to assembly language improves the bottleneck of software development efficiency just.
(2) the parallel construction aspect also has problems.In order to realize higher handling capacity, just must handle the more data position in the time in specific unit.The VLIW technology has been represented the depth of parallelism of instruction-level.Superscalar architecture and super pipeline configuration are also attempted more to be instructed in an instruction cycle.The data level depth of parallelism is represented by wideer data word, vectorization and data flow architecture.Because the width of data word is bigger, so each instruction cycle instruction can handle more data, improved accessible data bits of each clock period.The task level or the transaction-level depth of parallelism are embodied in multitask, multithreading and the multiprocessor design.These structures are expected to improve the data processing handling capacity, but data that increase and instruction width and the raising of thing followed data processing handling capacity will be paid certain cost.When code density and data width and application were complementary, they can play help, but when data word width and processor were inequality, they can bring a lot of troubles on the contrary.
(3) high-speed cache is just becoming more and more important to the total throughout of system on a large amount of available sheets, because the rambus of standard and interface can't provide support for the GB data transmission rate of each MAC in the system.Can all the other parts of system match with high speed processor and also just become a big problem, and each clock period of two mac processors that has 2 ALU unit may need 4 data words, or per second needs a plurality of data words of 4 gigabits.
Summary of the invention:
The purpose of this invention is to provide a kind of digital signal processor that has position expansion and position compression unit.Its concrete technical scheme is as follows:
Digital signal processor of the present invention comprises digital signal processor kernel, command memory, data-carrier store; Described digital signal processor kernel comprises procedure control unit, instruction decoding unit, address-generation unit, data operation unit; Wherein, procedure control unit provides instruction address by instruction bus to command memory, and the reception instruction is delivered to instruction decoding unit with it from command memory, instruction decoding unit will be deciphered later data and send to data operation unit and address-generation unit respectively, the data operation unit is with in its status information write state register, procedure control unit is understood the information of data operation unit by above-mentioned status register, and give data-carrier store or data register with operation result, address-generation unit is given data-carrier store with address value, specifies the position of corresponding storage and read-write; It is characterized in that,
Inner integrated position, described data operation unit is expanded and a position compression unit.
It is worthy of note that the position of being mentioned in the foregoing invention content is expanded and a position compression unit comprises: counter, shift unit and two source-registers and a destination register; Make like this:
When the execute bit extended operation, scan to highest significant position from the least significant bit (LSB) of source-register, according to 1 number in the 16 bit mask fields, get a high position from the low level of source-register, with these according to from low to high order, be successively placed in the destination register with 16 bit mask fields in 1 corresponding position, position, other position is with 0 filling, The above results exists in the destination register.
When the execute bit squeeze operation, according to 1 number in the 16 bit mask fields, scan to highest significant position from the least significant bit (LSB) of source-register, according to 1 position in the 16 bit mask fields, in the relevant position of source-register, these positions are extracted, order by from low to high from the least significant bit (LSB) of destination register, is successively placed in the destination register, fill with 0 other position of destination register, and The above results exists in the destination register.
According to technique scheme, beneficial effect of the present invention is as follows:
(1) the present invention is under the prerequisite that does not increase the processor hardware resource, make full use of existing resource, original instruction set is expanded, having increased the position expands and the position condensed instruction, these two instructions are according to ' 1 ' position in the mask field, a binary number is chosen in corresponding position in source operand, then to these number or the compression or expansions of being jumped out.These two instructions are different with the bit manipulation instruction in the general processor.General bit manipulation instruction is just made identical operations to each of each operand, each is equality when being operated, operate a certain position that perhaps can the assigned operation number, or zero clearing or set, but these newly-increased two instructions, can can compress also and can expand the appointed one or more arbitrarily operations of making in the operand, this has overcome former instruction set deficiency in this respect.
Mathematics Application such as the position that (2) the present invention increased newly is expanded and the position condensed instruction will be expanded to matrix, matrix compression are brought many facilities.
(3) the invention solves in the processor handling problem of correspondence position data in two registers.Use relative little hardware resource, realized under the minimum associative operation said conditions, the data manipulation of related register, to may be the operation that a paragraph assembly instruction repertorie is finished in the past, only just can reach identical purpose by an instruction, thereby improved processor performance, realized higher data throughout.
Description of drawings:
Fig. 1 is the one-piece construction block diagram that contains digital signal processor of the present invention.
Fig. 2 is a position of the present invention extended class command function synoptic diagram.
Fig. 3 is position of the present invention extended class instruction realization flow figure.
Fig. 4 is position compression class command function synoptic diagram of the present invention.
Fig. 5 is position compression class instruction realization flow figure of the present invention.
Embodiment:
Below in conjunction with accompanying drawing technical scheme of the present invention is further described.
As shown in Figure 1, the digital signal processor that the present invention uses comprises digital signal processor kernel, command memory, data-carrier store, wherein the digital signal processor kernel comprises procedure control unit, instruction decoding unit, address-generation unit, data operation unit, and inner integrated position is expanded and a position compression unit in the data operation unit.
As shown in Figure 2, position extended class instruction of the present invention is realized by two source-registers and 1 destination register.Source-register and destination register are 16.Data represented 16 bit mask numbers in the source-register 1, the data in the source-register 2 are by the augmented source data.According to ' 1 ' number in the 16 bit mask fields, get a high position from the low level of source-register, with these according to from low to high order, be successively placed in the destination register with 16 bit mask fields in ' 1 ' corresponding position, position, fill with ' 0 ' other position.The result deposits destination register in.
As shown in Figure 3, for reducing processor resource, 16 positional operands are divided into two sections operate.At first according to screening number, calculate in high-order screening number and the low level screening number ' 1 ' number respectively; According to ' 1 ' number in the low level screening number,, these data are sent into the data extending module with the low level screening number from begun to take out the data of corresponding number by the low level of augmented source data; Again from the low level of remaining data get with high-order screening number the corresponding data of ' 1 ' number, send into the data extending module with high-order screening number.In the data extending module, according to ' 1 ' position in the screening number, the number that expanded that takes out is once extended to the relevant position according to from low to high order, fill with ' 0 ' all the other positions.The result of two data enlargement modules is spliced into 16 results.
As shown in Figure 4, compression class in position of the present invention instruction is realized by two source-registers and a destination register.Source-register and destination register are 16.Data represented 16 bit mask numbers in the source-register 1, the data in the source-register 2 are to be compressed source data.According to 1 number in the 16 bit mask fields, scan to highest significant position from the least significant bit (LSB) of source-register, according to 1 position in the bit field shielding, relevant position at source-register, these positions are extracted, by order from low to high, from the least significant bit (LSB) of destination register, be successively placed in the destination register, fill with 0 other position of destination register.The result exists in the destination register.
As shown in Figure 5, for reducing processor resource, 16 positional operands are divided into two sections operate.The least-significant byte of most-significant byte, screening number least-significant byte and the compressed data of screening number most-significant byte and compressed data is put into two data extraction modules respectively.In data extraction module, extract data according to ' 1 ' position in the shadow data in the relevant position of compressed data, the data that extract are placed from low to high high-order not enough supplying with ' 0 '.Simultaneously, calculate in high-order screening number and the low level screening number ' 1 ' number respectively.According to ' 1 ' number in the low level screening number, in 8 results of low data extraction module, by the data that take out in turn from low to high, be placed on the low level of result register,, write 8 results of high position data extraction module thereon, 16 high-order not enough supplying of result register with ' 0 '.
More than be one of embodiments of the present invention,, do not spend performing creative labour, on the basis of the foregoing description, can do multiple variation, can realize purpose of the present invention equally for those skilled in the art.But this variation obviously should be in the protection domain of claims of the present invention.

Claims (2)

1, a kind of digital signal processor that has position expansion and position compression unit comprises digital signal processor kernel, command memory, data-carrier store; Described digital signal processor kernel comprises procedure control unit, instruction decoding unit, address-generation unit, data operation unit; Wherein, procedure control unit provides instruction address by instruction bus to command memory, and the reception instruction is delivered to instruction decoding unit with it from command memory, instruction decoding unit will be deciphered later data and send to data operation unit and address-generation unit respectively, the data operation unit is with in its status information write state register, procedure control unit is understood the information of data operation unit by above-mentioned status register, and give data-carrier store or data register with operation result, address-generation unit is given data-carrier store with address value, specifies the position of corresponding storage and read-write; It is characterized in that,
Inner integrated position, described data operation unit is expanded and a position compression unit.
2, have according to claim 1 that the position is expanded and the digital signal processor of position compression unit, it is characterized in that the position in the described data operation unit is expanded and the position compression unit comprises: counter, shift unit and two source-registers and a destination register; Make like this:
When the execute bit extended operation, scan to highest significant position from the least significant bit (LSB) of source-register, according to 1 number in the 16 bit mask fields, get a high position from the low level of source-register, with these according to from low to high order, be successively placed in the destination register with 16 bit mask fields in 1 corresponding position, position, other position is with 0 filling, The above results exists in the destination register.
When the execute bit squeeze operation, according to 1 number in the 16 bit mask fields, scan to highest significant position from the least significant bit (LSB) of source-register, according to 1 position in the 16 bit mask fields, in the relevant position of source-register, these positions are extracted, order by from low to high from the least significant bit (LSB) of destination register, is successively placed in the destination register, fill with 0 other position of destination register, and The above results exists in the destination register.
CN 200710039868 2007-04-24 2007-04-24 Digital signal processor with bit expansion and bit compressing compressing cell Pending CN101042640A (en)

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CN102279726A (en) * 2010-06-11 2011-12-14 联芯科技有限公司 Method and device for controlling data addressing
CN102567254A (en) * 2010-12-31 2012-07-11 重庆重邮信科通信技术有限公司 Method for performing data normalization processing by use of DMA (direct memory access) controller
US9218185B2 (en) 2014-03-27 2015-12-22 International Business Machines Corporation Multithreading capability information retrieval
US9354883B2 (en) 2014-03-27 2016-05-31 International Business Machines Corporation Dynamic enablement of multithreading
CN105677298A (en) * 2015-12-30 2016-06-15 李朝波 Method and device for extending immediate operand in computer instruction
US9417876B2 (en) 2014-03-27 2016-08-16 International Business Machines Corporation Thread context restoration in a multithreading computer system
US9594660B2 (en) 2014-03-27 2017-03-14 International Business Machines Corporation Multithreading computer system and program product for executing a query instruction for idle time accumulation among cores
US9804846B2 (en) 2014-03-27 2017-10-31 International Business Machines Corporation Thread context preservation in a multithreading computer system
US9921849B2 (en) 2014-03-27 2018-03-20 International Business Machines Corporation Address expansion and contraction in a multithreading computer system
US10095523B2 (en) 2014-03-27 2018-10-09 International Business Machines Corporation Hardware counters to track utilization in a multithreading computer system
CN109240652A (en) * 2017-10-27 2019-01-18 广州恒强信息科技有限公司 It is a kind of that information management system is given special care to based on J2EE
CN110554886A (en) * 2018-05-30 2019-12-10 赛灵思公司 Data splitting structure, method and on-chip implementation thereof
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Cited By (22)

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Publication number Priority date Publication date Assignee Title
CN102279726A (en) * 2010-06-11 2011-12-14 联芯科技有限公司 Method and device for controlling data addressing
CN102279726B (en) * 2010-06-11 2013-06-19 联芯科技有限公司 Method and device for controlling data addressing
CN102567254A (en) * 2010-12-31 2012-07-11 重庆重邮信科通信技术有限公司 Method for performing data normalization processing by use of DMA (direct memory access) controller
US9459875B2 (en) 2014-03-27 2016-10-04 International Business Machines Corporation Dynamic enablement of multithreading
US9354883B2 (en) 2014-03-27 2016-05-31 International Business Machines Corporation Dynamic enablement of multithreading
US9218185B2 (en) 2014-03-27 2015-12-22 International Business Machines Corporation Multithreading capability information retrieval
US9417876B2 (en) 2014-03-27 2016-08-16 International Business Machines Corporation Thread context restoration in a multithreading computer system
US9454372B2 (en) 2014-03-27 2016-09-27 International Business Machines Corporation Thread context restoration in a multithreading computer system
US10095523B2 (en) 2014-03-27 2018-10-09 International Business Machines Corporation Hardware counters to track utilization in a multithreading computer system
US9594660B2 (en) 2014-03-27 2017-03-14 International Business Machines Corporation Multithreading computer system and program product for executing a query instruction for idle time accumulation among cores
US9594661B2 (en) 2014-03-27 2017-03-14 International Business Machines Corporation Method for executing a query instruction for idle time accumulation among cores in a multithreading computer system
US9804846B2 (en) 2014-03-27 2017-10-31 International Business Machines Corporation Thread context preservation in a multithreading computer system
US9804847B2 (en) 2014-03-27 2017-10-31 International Business Machines Corporation Thread context preservation in a multithreading computer system
US9921849B2 (en) 2014-03-27 2018-03-20 International Business Machines Corporation Address expansion and contraction in a multithreading computer system
US9921848B2 (en) 2014-03-27 2018-03-20 International Business Machines Corporation Address expansion and contraction in a multithreading computer system
US10102004B2 (en) 2014-03-27 2018-10-16 International Business Machines Corporation Hardware counters to track utilization in a multithreading computer system
CN105677298A (en) * 2015-12-30 2016-06-15 李朝波 Method and device for extending immediate operand in computer instruction
CN105677298B (en) * 2015-12-30 2018-03-27 李朝波 A kind of method and apparatus for extending immediate in computer instruction
CN109240652A (en) * 2017-10-27 2019-01-18 广州恒强信息科技有限公司 It is a kind of that information management system is given special care to based on J2EE
CN110554886A (en) * 2018-05-30 2019-12-10 赛灵思公司 Data splitting structure, method and on-chip implementation thereof
CN110554886B (en) * 2018-05-30 2021-12-10 赛灵思公司 Data splitting structure, method and on-chip implementation thereof
CN112666860A (en) * 2020-12-15 2021-04-16 合肥中感微电子有限公司 Extended processing system of digital signal, processing method thereof and processor

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