CN100593231C - Multi-chip stack encapsulation method - Google Patents

Multi-chip stack encapsulation method Download PDF

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Publication number
CN100593231C
CN100593231C CN 200710185057 CN200710185057A CN100593231C CN 100593231 C CN100593231 C CN 100593231C CN 200710185057 CN200710185057 CN 200710185057 CN 200710185057 A CN200710185057 A CN 200710185057A CN 100593231 C CN100593231 C CN 100593231C
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those
chip
pin
lead frame
groups
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CN 200710185057
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CN101431033A (en
Inventor
沈更新
陈煜仁
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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Priority to CN 200710185057 priority Critical patent/CN100593231C/en
Publication of CN101431033A publication Critical patent/CN101431033A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors

Abstract

A multi-chip stacking and packaging method comprises: a lead frame is composed of a plurality of inner pins and a plurality of external pins, the inner pins comprise a plurality of parallel first inner pin group and a parallel second inner pin group, and center approaching regions of the first inner pin group and the second inner pin group are respectively provided with radiating fins; a first chip is fixedly connected to the lower surface of the lead frame, and the first chip is provided with an active surface and a plurality of first welding pads; a plurality of first metal leads are formedto electrically connect the first welding pads on the first chip, the first inner pin group and the second inner pin group; and a second chip is fixedly connected to the upper surface of the lead frame, and the second chip is provided with an active surface and a plurality of second welding pads.

Description

Multi-chip stack packaging method
Technical field
The invention relates to the encapsulating structure of integrated circuit, particularly relevant for a kind of method for packing of the multi-chip stack in conjunction with LOC (Lead on Chip) and COL (Chip on Lead) technology.
Background technology
In recent years, semi-conductive back segment preparation technology is carrying out three-dimensional space (Three Dimension; Encapsulation 3D) reaches higher density or capacity of internal memory etc. in the hope of utilizing minimum area.In order to reach this purpose, the mode that present stage has been developed use chip stack (chip stacked) is reached three-dimensional space (Three Dimension; Encapsulation 3D).
In known technology, for example United States Patent (USP) the 6th, 744,121, promptly discloses a kind of structure of using lead frame to form multi-chip stack, as shown in Figure 1a.Clearly, in the encapsulating structure of Fig. 1,,, protect the plain conductor of lower floor's chip by the formed difference in height of bending so lead frame has been done repeatedly bending for the plain conductor of avoiding lower floor's chip contacts with the back side of upper layer stacks chip.Yet,, cause follow-up chip to be difficult for aiming at through the lead frame easy deformation that repeatedly bends.In addition, the lead frame of bending can make that encapsulating structure is loose, causes and can't dwindle encapsulation volume.In addition because lead frame has been done repeatedly bending, so each chip and lead frame stick together the area deficiency, in annotating membrane process, cause the chip disengaging easily.
In addition, at United States Patent (USP) the 6th, 838,754 and United States Patent (USP) the 6th, 977,427, also disclose a kind of structure of using lead frame to form multi-chip stack, shown in Fig. 1 b and Fig. 1 c, same, in the embodiment of Fig. 1 b and Fig. 1 c, all may be in the process of upper strata chip and lower floor's chip join, the back side that the upper strata chip takes place contacts with plain conductor on the lower floor chip and causes problems such as short circuit or plain conductor peel off.
In addition, a plurality of chip stacks make this multi-chip stack structure when operation in a packaging body time, can produce thermal effect; When if this thermal effect can't promptly drain into outside the multi-chip stack structure, the reliability of chip is reduced.
Summary of the invention
Purpose of the present invention is providing a kind of multi-chip stack packaging method.
Another main purpose of the present invention is the multi-chip stack packaging method of substrate with the lead frame providing a kind of, and utilize the metal distance member to be connected with radiating fin on the lead frame, the thermal effect that makes multi-chip stack structure be produced when operation can be by the radiating fin on the lead frame, thermal effect is drained into outside the multi-chip stack structure, to increase the reliability of chip.
For achieving the above object, multi-chip stack packaging method provided by the invention comprises:
One lead frame is provided, it has a upper surface and a lower surface, constituted by pin in a plurality of and a plurality of outer pin, pin includes first interior pin group of plurality of parallel and the second parallel interior pin group in those, and those pin groups and those pin groups' in second in first end is with a relative arrangement at interval, wherein in those in first in pin group and those second the pin group near middle section, each disposes a radiating fin;
Affixed one first chip, this first chip is fixed in this lower surface of this lead frame, and makes on the active surface of this first chip near a plurality of first weld pads that middle section disposed and be exposed between this interval of those pin groups and those second interior pin group ends in first;
Form a plurality of first plain conductors, those first weld pads of this first chip are electrically connected to those pin groups in pin groups and those second in first;
Form the metal distance member, pair of metal distance member at least is formed on the radiating fin of this lead frame;
Forming a polymer material layer, is filling in this in first in pin group and this second in the spacer region of pin group's end, and covers this first weld pad and this a plurality of first plain conductor in this first chip;
Affixed one second chip, this second chip has the back side an of active surface and relative this active surface, this back side is fixed on this polymer material layer and with this metal distance member contacts, and dispose a plurality of second weld pads near middle section on this active surface of this second chip;
Form a plurality of second plain conductors, those second weld pads on this active surface of this second chip are electrically connected to this upper surface of those first interior pin groups and those second interior pin groups; And inject
One mould stream to be forming a packaging body, coating this first chip, those first plain conductors, this second chip, those second plain conductors, those pin groups in pin groups and those second in first, and exposes this a plurality of outer pins.
Described method for packing wherein, is contained between the interval of those pin groups and those second interior pin group ends in first and disposes at least one bus.
Described method for packing, wherein, the width of this radiating fin is greater than pin in those.
Described method for packing, wherein, the height of this metal distance member is greater than the maximum camber of those first plain conductors.
Multi-chip stack packaging method provided by the invention also comprises:
One lead frame is provided, it has a upper surface and a lower surface, constituted by pin in a plurality of and a plurality of outer pin, pin includes first interior pin group of plurality of parallel and the second parallel interior pin group in those, and those pin groups and those pin groups' in second in first end is with a relative arrangement at interval, wherein in those in first in pin group and those second the pin group near middle section, each disposes a radiating fin;
One first chip is provided, and it has on the active surface near a plurality of first weld pads that middle section disposed and is exposed between this interval of those pin groups and those second interior pin groups in first;
Form one first adhesion layer,, be fixed in this lower surface of this lead frame by this first adhesion layer in order to affixed this first chip;
Affixed one first chip, by this first adhesion layer this first chip is fixed under this lead frame the surface, and makes on one of this first chip active surface near a plurality of first weld pads that middle section disposed and be exposed between this interval of those pin groups and those second interior pin group ends in first;
Form a plurality of first plain conductors, those first weld pads of this first chip are electrically connected to those pin groups in pin groups and those second in first by those first plain conductors;
Form the metal distance member, pair of metal distance member at least is formed on the radiating fin of this lead frame;
Form one second adhesion layer, be formed on this active surface of part of this first chip and coat those first plain conductors and this interval of those pin groups and those second interior pin group ends in first;
Affixed one second chip, one back side of this second chip is fixed in this upper surface of this lead frame by this second adhesion layer, and a back side of this second chip contacts with this metal distance member, and disposes a plurality of second weld pads near middle section on the active surface at relative this back side of this second chip;
Form a plurality of second plain conductors, those second weld pads on this active surface of this second chip are electrically connected to this upper surface of those first interior pin groups and those second interior pin groups; And
Inject mould stream forming a packaging body, coating this first chip, those first plain conductors, this second chip, those second plain conductors, those pin groups in pin groups and those second in first, and expose this a plurality of outer pins.
Described method for packing wherein, is contained between the interval of those pin groups and those second interior pin group ends in first and disposes at least one bus.
Multi-chip stack packaging method provided by the invention also comprises:
One lead frame is provided, it has a upper surface and a lower surface, constituted by pin in a plurality of and a plurality of outer pin, pin includes first interior pin group of plurality of parallel and the second parallel interior pin group in those, and those first interior pin groups are with relative at interval an arrangement with those second interior pin groups' end, wherein in those in first in pin group and those second the pin group near middle section, each disposes a radiating fin;
One first chip is provided, and it has on the active surface near a plurality of first weld pads that middle section disposed and is exposed between this interval of those pin groups and those second interior pin groups in first;
Affixed this first chip, this first chip is fixed in this lower surface of this lead frame, and makes on the active surface of this first chip near a plurality of first weld pads that middle section disposed and be exposed between this interval of those pin groups and those second interior pin group ends in first;
Form a plurality of first plain conductors, those first weld pads of this first chip are electrically connected to those pin groups in pin groups and those second in first by those first plain conductors;
Form the pair of metal distance member, with this is formed on the radiating fin of this lead frame to the metal distance member at least;
One second chip is provided, and it has a back side of an active surface and relative this active surface, and disposes a plurality of second weld pads near middle section on this active surface;
Form an adhesion layer on this back side of part of this second chip;
Affixed this second chip, this second chip is fixed in this upper surface of this lead frame and this adhesion layer covers those first plain conductors that are positioned on those first pin groups and those the second pin groups by this adhesion layer, and the back side of this second chip not shape have the part of this adhesion layer to contact with this metal distance member;
Form a plurality of second plain conductors, those second weld pads on this active surface of this second chip are electrically connected to this upper surface of those first interior pin groups and those second interior pin groups; And
Inject mould stream forming a packaging body, coating this first chip, those first plain conductors, this second chip, those second plain conductors, those pin groups in pin groups and those second in first, and expose this a plurality of outer pins.
Described method for packing wherein, is contained between the interval of those pin groups and those second interior pin group ends in first and disposes at least one bus.
Described method for packing, wherein, this adhesion layer can be selected from following group: adhesive tape (tape), glued membrane (die attached film), macromolecule (polymer) and B-Stage resin.
Described method for packing, wherein, the width of this radiating fin is greater than pin in those.
The method for packing of multi-chip stack provided by the invention utilizes distance member to guarantee the distance of upper and lower layer chip chamber, with the plain conductor on the protection lower floor chip.And utilize the metal distance member to be connected with radiating fin on the lead frame, the thermal effect that makes multi-chip stack structure be produced when operation can drain into thermal effect outside the multi-chip stack structure by the radiating fin on the lead frame, to increase the reliability of chip.
Description of drawings
Fig. 1 a is the cutaway view of a known multi-chip stack encapsulation;
Fig. 1 b is the cutaway view of another known multi-chip stack encapsulation;
Fig. 1 c is again the cutaway view of a known multi-chip stack encapsulation;
Fig. 2 is according to the present invention in the disclosed technology, the vertical view of the encapsulating structure of multi-chip stack;
Fig. 3 is according to the present invention in the disclosed technology, the schematic diagram of a specific embodiment of the encapsulating structure of multi-chip stack;
Fig. 4 is according to the present invention in the disclosed technology, the schematic diagram of another specific embodiment of the encapsulating structure of multi-chip stack;
Fig. 5 is according to the present invention in the disclosed technology, has the schematic diagram of specific embodiment of encapsulating structure of the multi-chip stack of bus;
Fig. 6 is according to the present invention in the disclosed technology, the schematic diagram of the another specific embodiment of the encapsulating structure of multi-chip stack;
Fig. 7 is according to the present invention in the disclosed technology, the schematic diagram of the another specific embodiment of the encapsulating structure of multi-chip stack; And
Fig. 8 is according to the present invention in the disclosed technology, has the schematic diagram of another specific embodiment of encapsulating structure of the multi-chip stack of bus.
Primary clustering symbol description in the accompanying drawing:
10 first chips
102 first weld pads
20 second chips
202 second weld pads
30 metal distance members
40 adhesion layers
50 first plain conductors
60 second plain conductors
70 macromolecular materials
80 packaging bodies
90 adhesion layers
100 lead frames
110 buses (bus bar)
120 pins
1201,1203 a plurality of interior pins
1202,1204 a plurality of outer pins
130 radiating fins
The encapsulating structure of 200 multi-chip stacks
Embodiment
For making purpose of the present invention, structure, feature and function thereof there are further understanding, cooperate embodiment to be described in detail as follows.
The present invention is a kind of mode of using chip stack in this direction of inquiring into, and the akin chip stack of a plurality of sizes is become a kind of tridimensional encapsulating structure.In order to understand the present invention up hill and dale, detailed encapsulation step and encapsulating structure thereof will be proposed in following description.Apparently, execution of the present invention does not limit the specific details that skill person had the knack of of the mode of chip stack.On the other hand, back segment preparation technologies' such as well-known chip generation type and chip thinning detailed step is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet,, can be described in detail as follows for preferred embodiment of the present invention, yet except these are described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, and its claim scope with application is as the criterion.
In the semiconductor packages preparation technology in modern times, all be a wafer (wafer) of having finished leading portion preparation technology (Front End Process) to be carried out thinning earlier handle (Thinning Process), the thickness of chip is ground between 2～20mil; Then, optionally coating (coating) or wire mark (printing) one deck macromolecule (polymer) material are in the back side of chip again, and this macromolecular material can be a kind of resin (resin), particularly a kind of B-Stage resin.Via a baking or irradiation preparation technology, make macromolecular material present a kind of semi-curing glue again with stickiness; Follow again, an adhesive tape that can remove (tape) is attached on the macromolecular material of semi-solid preparation shape; Then, carry out the cutting (sawing process) of wafer, make wafer become many chip (die); At last, just many chip can be connected with substrate and chip is formed the stack chip structure.
The present invention mainly provides a kind of method for packing that forms multi-chip stack, comprise: a lead frame is provided, have a upper surface and a lower surface, this lead frame is made of pin in a plurality of and a plurality of outer pin, and interior pin includes first interior pin group of plurality of parallel and the second parallel interior pin group, and the pin group and the second interior pin group's end is with a relative arrangement at interval in first, wherein in first in the pin group and second the pin group near middle section, each disposes a radiating fin; Affixed one first chip is fixed in the lower surface of lead frame with first chip, and it has an active surface and dispose a plurality of first weld pads near middle section on active surface; Form a plurality of first plain conductors, in order to electrically connect the pin group and the second interior pin group in first weld pad and first on first chip; Affixed one second chip is fixed in the upper surface of lead frame with second chip, and it has an active surface and dispose a plurality of second weld pads near middle section on active surface; Form the pair of metal distance member, the pair of metal distance member is formed on the radiating fin of lead frame and with the back side contact of the relative active surface of second chip; Form a plurality of second plain conductors, in order to electrically connect second weld pad of pin group to the second chip in the first interior pin group and second; And inject mould stream forming a packaging body, coating in first chip, first plain conductor, second chip, second plain conductor, first pin group in the pin group and second, and expose a plurality of outer pins.
The present invention then provides a kind of method that forms the encapsulating structure of multi-chip stack, comprise: a lead frame is provided, have a upper surface and a lower surface, constituted by pin in a plurality of and a plurality of outer pin, pin includes first interior pin group of plurality of parallel and the second parallel interior pin group in it, and the pin group and the second interior pin group's end is with a relative arrangement at interval in first, and in first in the pin group and second the pin group near middle section, each disposes a radiating fin; Affixed one first chip is fixed in the lower surface of lead frame with first chip, and first chip has an active surface and dispose a plurality of first weld pads near middle section on active surface; Form a plurality of first plain conductors, in order to first weld pad on first chip is electrically connected to the pin group and the second interior pin group in first; Form the pair of metal distance member on the radiating fin of lead frame; One second chip is provided, and it has an active surface and dispose a plurality of second weld pads near middle section on active surface, and disposes an adhesion layer on the back side of relative active surface; Affixed second chip is the upper surface that is fixed in lead frame by adhesion layer, and wherein adhesion layer covers a plurality of first plain conductors and pair of metal distance member, and the back side of second chip with the metal distance member is contacted; Form a plurality of second plain conductors, in order to those second weld pads on this active surface that pin group in the first interior pin group and second is electrically connected to the upper surface and second chip; And inject mould stream forming a packaging body, coating in first chip, first plain conductor, second chip, second plain conductor, first pin group in the pin group and second, and expose a plurality of outer pins.
Please consult Fig. 2 earlier, the vertical view of the disclosed a kind of conducting wire frame structure of expression the present invention.As shown in Figure 2, reference number 100 is a conducting wire frame structure; Reference number 110 is bus (bus bar); Reference number 120 is the pin of lead frame; And reference number 130 is a kind of radiating fin in the lead frame.At the description of drawings of following embodiment and collocation thereof is that generalized section according to the shown A of Fig. 2, B line segment illustrates.
At first, as shown in Figure 2, lead frame 100 has a upper surface and a lower surface, and the pin 120 of lead frame 100 is made of pin in a plurality of and a plurality of outer pin, and with the boundary of line segment 10 as interior pin and a plurality of outer pins, wherein a plurality of interior pins are made up of first interior pin group 1201 of plurality of parallel and second interior 1203 of the pin groups of plurality of parallel, and a plurality of first interior pin group 1201 and a plurality of second interior pin group's 1203 end is with a relative arrangement in interval.Simultaneously, in the pin 120 of lead frame 100 first in the pin group 1201 and second pin group 1203 near middle section, each disposes a radiating fin 130.The width of this radiating fin 130 can be wideer than interior pin, and also can a side of pin be sector outside close.In addition, lead frame 100 of the present invention can be optionally in a plurality of first in the pin group 1201 and a plurality of second pin group 1203 periphery respectively dispose a bus 110 again, it can be used as the electric connection that comprises power supply contact, ground contact or signal contact this bus 110.
Then, please refer to Fig. 3, represent the generalized section of multi-chip stack packaging structure of the present invention on the AA of lead frame 100 line segment.The assembly of the encapsulating structure 200 of multi-chip stack on the AA of lead frame 100 line segment comprises: the pin 120 of lead frame 100, first chip (or being called lower floor's chip), 10, second chip (or being called the upper strata chip) 20, a plurality of first plain conductors 50 and a plurality of second plain conductors 60 constitute.
Please refer to Fig. 3, at first, provide first chip 10, dispose a plurality of first weld pads 102 near middle section on its active surface; Simultaneously, on the part active surface of first chip 10, form an adhesion layer 40, this adhesion layer 40 can be adhesive tape (tape) or glued membrane (die attached film), the present invention is not limited, therefore, so long as have connection and stick together the adhesion material of function, be enforcement aspect of the present invention.Simultaneously, this adhesion layer 40 also can be formed at the lower surface of lead frame 100 earlier, and the present invention is not limited yet.Then, first chip 10 is pasted to the lower surface of lead frame 100, to form the structure of a Lead on Chip (LOC), wherein a plurality of first weld pads 102 in first chip 10 are exposed between the space from end of pin group 1203 in the first interior pin group 1201 and second.Follow again, carry out a routing preparation technology, first weld pad 102 is electrically connected on the first interior pin group 1201 and the second interior pin group 1203 with a plurality of first plain conductors 50.In the process of carrying out routing preparation technology, wire bonder (not being shown among the figure) can form metal distance member 30 on the radiating fin 130 in lead frame 100, and the height of this metal distance member 30 is greater than the maximum camber of first plain conductor 50; And this metal distance member 30 can be by a plurality of tin balls or metal coupling storehouse and is formed.
Then, in near first in the pin group 1201 and second pin group 1203 space from end district near, be coated with a kind of macromolecular material 70, first weld pad 102 and a plurality of first plain conductors 50 that macromolecular material 70 is covered in first chip 10 with tackness.Then, one second chip 20 is provided, and the back side of second chip 20 is pasted on the macromolecular material 70, so that second chip 20 is fixed on the upper surface of lead frame 100, to form the structure of a Chip on Lead (COL), wherein macromolecular material 70 can be a kind of resin (resin), particularly a kind of B-Stage resin.
At this moment, there has been metal distance member 30 to have (Fig. 4 is the generalized section of multi-chip stack packaging structure of the present invention on the BB of lead frame 100 line segment) as shown in Figure 4 on the upper surface of the radiating fin 130 in lead frame 100.Therefore, when the back side of second chip 20 is pasted on the macromolecular material 70, the back side of second chip 20 can contact with metal distance member 30, simultaneously, because the height of metal distance member 30 is greater than the maximum camber of first plain conductor 50, therefore, behind the back side and metal distance member 30 of second chip 20, promptly supported, a plurality of first plain conductors 50 in the chip 10 of winning can not touched with the back side of second chip 20 by metal distance member 30.
Above-mentioned second chip 20 is fixed in the upper surface of lead frame 100 after, promptly can optionally carry out one the baking preparation technology so that can further solidify macromolecular material 70.
Follow again, carrying out secondary routing preparation technology, be with a plurality of second plain conductors 60 with backhander line preparation technology, a plurality of second weld pads 202 on second chip 20 are electrically connected in first in the pin group 1201 and second on the pin group 1203.Follow again, interior pin group 1201 (1203) with first chip 10, second chip 20 and lead frame 100 coats with the formed adhesive body 80 of an injection molding preparation technology (molding), and the outer pin group 1202 (1204) of lead frame 100 is exposed to outside the adhesive body 80.At last, use a cutting or punching press (stamp) preparation technology, with outer pin group 1202 (1204) bending formings of lead frame 100, as shown in Figure 3.In addition, be stressed that the mode of radiating fin 130 its bendings in the lead frame 100 of the present invention can be identical with outer pin group 1202 (1204), also can be to the both sides of adhesive body 80 bending forming, shown in the dotted line among Fig. 4.After radiating fin 130 was with above-mentioned two kinds of bending formings, its back side and outer pin group 1202 (1204) were on same horizontal plane; Therefore, after encapsulating structure 200 of the present invention and circuit board (not being shown among the figure) electrically connect, radiating fin 130 also can contact with circuit board with the back side of the downward bending forming of above-mentioned dual mode, so can be by the suitable distribution of circuit board, thermal effect in the encapsulating structure 200 is passed on the radiating fin 130 by metal distance member 30, radiating fin 130 by broad transfers heat on the circuit board again, so can effectively thermal effect be drained into outside the encapsulating structure 200.Certainly, very apparent and easy to know, radiating fin 130 also can be selected upwards bending (not being shown among the figure), dispels the heat in unsettled mode, and this also is an one embodiment of the present invention.
In addition, as shown in Figure 5, it is the generalized section of another embodiment on the BB of lead frame 100 line segment of multi-chip stack packaging structure of the present invention.Clearly, the difference of Fig. 5 and Fig. 3 be in: increased the structure of bus 110 in the lead frame 100 of Fig. 5, it can be used as the electric connection that comprises power supply contact, ground contact or signal contact this bus 110.Because the process of the encapsulating structure of formation Fig. 5 is identical with Fig. 3, so repeat no more.
Then, please refer to Fig. 6 to Fig. 7, is the cutaway view of an embodiment again of multi-chip stack packaging structure of the present invention.At first, please refer to Fig. 6, so lead frame 100 structures in the present embodiment and aforesaid shown in Figure 2 identical are no longer repeat specification.
At first, as shown in Figure 6, provide first chip 10, dispose a plurality of first weld pads 102 near middle section on its active surface; Simultaneously, form an adhesion layer 40 on the part active surface of first chip 10, this adhesion layer 40 can be adhesive tape (tape) or glued membrane (die attached film), simultaneously, this adhesion layer 40 also can be formed at the lower surface of lead frame 100 earlier, and the present invention is not limited yet.Then, first chip 10 is pasted to the lower surface of lead frame 100, to form the structure of a Lead on Chip (LOC), wherein a plurality of first weld pads 102 in first chip 10 are exposed between the space from end of pin group 1203 in the first interior pin group 1201 and second.Follow again, carry out a routing preparation technology, first weld pad 102 is electrically connected on the first interior pin group 1201 and the second interior pin group 1203 with a plurality of first plain conductors 50.In the process of carrying out routing preparation technology, wire bonder (not being shown among the figure) can form metal distance member 30 on the radiating fin 130 in lead frame 100, and the height of this metal distance member 30 is greater than the maximum camber of first plain conductor 50; And this metal distance member 30 can be by a plurality of tin balls or metal coupling storehouse and is formed.
Then, in near first in the pin group 1201 and second pin group 1203 space from end district near, be coated with a kind of macromolecular material 70, first weld pad 102 and a plurality of first plain conductors 50 that macromolecular material 70 is covered in first chip 10 with tackness.
Follow, one second chip 20 is provided, and form adhesion layer 90 in the back side of second chip 20, this adhesion layer 90 can be the whole lower surface that is attached to second chip 20, and it also can select adhesion layer 90 is attached to respectively near the dual-side of second chip 20; In addition, adhesion layer 90 can be a kind of macromolecule (polymer) material, and this macromolecular material then can be a kind of resin (resin), particularly a kind of B-Stage resin; In addition, adhesion layer 90 also can be a kind of glued membrane.Then, by adhesion layer 90 second chip 20 is fixed in the interior pin group's 1021 (1203) of lead frame 100 upper surface.At this moment, the adhesion layer 90 at second chip, 20 back sides can cover first plain conductor 50.
Because, in aforementioned routing process, formed metal distance member 30, (Fig. 7 is the generalized section of multi-chip stack packaging structure of the present invention on the BB of lead frame 100 line segment) as shown in Figure 4 on the upper surface of the radiating fin in lead frame 100 130.Therefore, in the time of on the back side of second chip 20 is pasted to macromolecular material 70, the back side of second chip 20 can contact with metal distance member 30, simultaneously, because the height of metal distance member 30 is greater than the maximum camber of first plain conductor 50, therefore, behind the back side and metal distance member 30 of second chip 20, promptly supported, a plurality of first plain conductors 50 in the chip 10 of winning can not touched with the back side of second chip 20 by metal distance member 30.
Follow again, carrying out secondary routing preparation technology, be with a plurality of second plain conductors 60 with backhander line preparation technology, a plurality of second weld pads 202 on second chip 20 are electrically connected in first in the pin group 1201 and second on the pin group 1203.Follow again, interior pin group 1201 (1203) with first chip 10, second chip 20 and lead frame 100 coats with the formed adhesive body 80 of an injection molding preparation technology (molding), and the outer pin group 1202 (1204) of lead frame 100 is exposed to outside the adhesive body 80.At last, use a cutting or punching press (stamp) preparation technology, with outer pin group 1202 (1204) bending formings of lead frame 100, as shown in Figure 6.In addition, be stressed that the mode of radiating fin 130 its bendings in the lead frame 100 of the present invention can be identical with outer pin group 1202 (1204), also can be to the both sides of adhesive body 80 bending forming, shown in the dotted line among Fig. 7.After radiating fin 130 was with above-mentioned two kinds of bending formings, its back side and outer pin group 1202 (1204) were on same horizontal plane; Therefore, after encapsulating structure 200 of the present invention and circuit board (not being shown among the figure) electrically connect, radiating fin 130 also can contact with circuit board with the back side of the downward bending forming of above-mentioned dual mode, so can be by the suitable distribution of circuit board, thermal effect in the encapsulating structure 200 is passed on the radiating fin 130 by metal distance member 30, radiating fin 130 by broad transfers heat on the circuit board again, so can effectively thermal effect be drained into outside the encapsulating structure 200.Certainly, very apparent and easy to know, radiating fin 130 also can be selected upwards bending (not being shown among the figure), dispels the heat in unsettled mode, and this also is an one embodiment of the present invention.
In addition, as shown in Figure 8, it is the generalized section of another embodiment on the BB of lead frame 100 line segment of multi-chip stack packaging structure of the present invention.Clearly, the difference of Fig. 8 and Fig. 6 be in: increased the structure of bus 110 in the lead frame 100 of Fig. 8, it can be used as the electric connection that comprises power supply contact, ground contact or signal contact this bus 110.Because the process of the encapsulating structure of formation Fig. 6 is identical with Fig. 3, so repeat no more.
According to the above, the encapsulating structure of the disclosed multi-chip stack of the present invention has solved in known technology the distortion that bending produced repeatedly of lead frame do, in specific embodiments of the invention, its lead frame can not need repeatedly to bend the storehouse encapsulation that can carry out the multicore sheet, in addition, can dwindle the package dimension of multi-chip stack by the coupling assembling between chip and the lead frame as coupling assembling, the problem that can avoid short circuit that the plain conductor contact caused or plain conductor to peel off.
Though the present invention discloses as above with aforesaid preferred embodiment, right its is not in order to limit the present invention, those skilled in the art without departing from the spirit and scope of the present invention, when can doing a little change and retouching, therefore claim scope of the present invention must be looked the content that the claim scope of the present patent application defined and is as the criterion.

Claims (9)

1, a kind of multi-chip stack packaging method comprises:
One lead frame is provided, it has a upper surface and a lower surface, constituted by pin in a plurality of and a plurality of outer pin, pin includes first interior pin group of plurality of parallel and the second parallel interior pin group in those, and those pin groups and those pin groups' in second in first end is with a relative arrangement at interval, wherein in those in first in pin group and those second the pin group near middle section, each disposes a radiating fin;
Affixed one first chip, this first chip is fixed in this lower surface of this lead frame, and makes on the active surface of this first chip near a plurality of first weld pads that middle section disposed and be exposed between this interval of those pin groups and those second interior pin group ends in first;
Form a plurality of first plain conductors, those first weld pads of this first chip are electrically connected to those pin groups in pin groups and those second in first;
Form the metal distance member, pair of metal distance member at least is formed on the radiating fin of this lead frame, wherein the height of this metal distance member is greater than the maximum camber of those first plain conductors;
Form a polymer material layer, filling is in this in first in pin group and this second in the spacer region of pin group end, and covers this first weld pad and this a plurality of first plain conductor in this first chip;
Affixed one second chip, this second chip has the back side of an active surface and relative this active surface, this back side is fixed on this polymer material layer and with this metal distance member contacts, and dispose a plurality of second weld pads near middle section on this active surface of this second chip;
Form a plurality of second plain conductors, those second weld pads on this active surface of this second chip are electrically connected to those first interior pin groups and those second interior pin groups' upper surface; And
Inject mould stream forming a packaging body, coating this first chip, those first plain conductors, this second chip, those second plain conductors, those pin groups in pin groups and those second in first, and expose this a plurality of outer pins.
2, method for packing as claimed in claim 1 wherein, is contained between the interval of those pin groups and those second interior pin group ends in first and disposes at least one bus.
3, method for packing as claimed in claim 1, wherein, the width of this radiating fin is greater than pin in those.
4, a kind of multi-chip stack packaging method comprises:
One lead frame is provided, it has a upper surface and a lower surface, constituted by pin in a plurality of and a plurality of outer pin, pin includes first interior pin group of plurality of parallel and the second parallel interior pin group in those, and those pin groups and those pin groups' in second in first end is with a relative arrangement at interval, wherein in those in first in pin group and those second the pin group near middle section, each disposes a radiating fin;
Form one first adhesion layer, this first adhesion layer is fixed in this lower surface of this lead frame;
Affixed one first chip, by this first adhesion layer this first chip is fixed in the lower surface of this lead frame, and makes on the active surface of this first chip near a plurality of first weld pads that middle section disposed and be exposed between this interval of those pin groups and those second interior pin group ends in first;
Form a plurality of first plain conductors, those first weld pads of this first chip are electrically connected to those pin groups in pin groups and those second in first by those first plain conductors;
Form the metal distance member, pair of metal distance member at least is formed on the radiating fin of this lead frame, wherein the height of this metal distance member is greater than the maximum camber of those first plain conductors;
Form one second adhesion layer, be formed on this active surface of part of this first chip and coat those first plain conductors and this interval of those pin groups and those second interior pin group ends in first;
Affixed one second chip, one back side of this second chip is fixed in this upper surface of this lead frame by this second adhesion layer, and a back side of this second chip contacts with this metal distance member, and disposes a plurality of second weld pads near middle section on the active surface at relative this back side of this second chip;
Form a plurality of second plain conductors, those second weld pads on this active surface of this second chip are electrically connected to those first interior pin groups and those second interior pin groups' upper surface; And
Inject mould stream forming a packaging body, coating this first chip, those first plain conductors, this second chip, those second plain conductors, those pin groups in pin groups and those second in first, and expose this a plurality of outer pins.
5, method for packing as claimed in claim 4 wherein, is contained between the interval of those pin groups and those second interior pin group ends in first and disposes at least one bus.
6, a kind of method for packing of multi-chip stack comprises:
One lead frame is provided, it has a upper surface and a lower surface, constituted by pin in a plurality of and a plurality of outer pin, pin includes first interior pin group of plurality of parallel and the second parallel interior pin group in those, and those first interior pin groups are with relative at interval an arrangement with those second interior pin groups' end, wherein in those in first in pin group and those second the pin group near middle section, each disposes a radiating fin;
One first chip is provided, and it has on the active surface near a plurality of first weld pads that middle section disposed and is exposed between this interval of those pin groups and those second interior pin groups in first;
Affixed this first chip, this first chip is fixed in this lower surface of this lead frame, and makes on the active surface of this first chip near a plurality of first weld pads that middle section disposed and be exposed between this interval of those pin groups and those second interior pin group ends in first;
Form a plurality of first plain conductors, those first weld pads of this first chip are electrically connected to those pin groups in pin groups and those second in first by those first plain conductors;
Form the pair of metal distance member, with this is formed on the metal distance member on the radiating fin of this lead frame at least, wherein the height of this metal distance member is greater than the maximum camber of those first plain conductors;
One second chip is provided, and it has a back side of an active surface and relative this active surface, and disposes a plurality of second weld pads near middle section on this active surface;
Form an adhesion layer on this back side of part of this second chip;
Affixed this second chip, this second chip is fixed in this upper surface of this lead frame and this adhesion layer covers those first plain conductors that are positioned on those first pin groups and those the second pin groups by this adhesion layer, and the back side of this second chip not shape have the part of this adhesion layer to contact with this metal distance member;
Form a plurality of second plain conductors, those second weld pads on this active surface of this second chip are electrically connected to those first interior pin groups and those second interior pin groups' upper surface; And
Inject mould stream forming a packaging body, coating this first chip, those first plain conductors, this second chip, those second plain conductors, those pin groups in pin groups and those second in first, and expose this a plurality of outer pins.
7, method for packing as claimed in claim 6 wherein, is contained between the interval of those pin groups and those second interior pin group ends in first and disposes at least one bus.
8, method for packing as claimed in claim 6, wherein, this adhesion layer can be selected from following group: adhesive tape, glued membrane, macromolecule and B-Stage resin.
9, method for packing as claimed in claim 6, wherein, the width of this radiating fin is greater than pin in those.
CN 200710185057 2007-11-06 2007-11-06 Multi-chip stack encapsulation method Expired - Fee Related CN100593231C (en)

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