CN100592494C - Method for correcting layout design for correcting metallic coating of contact hole - Google Patents
Method for correcting layout design for correcting metallic coating of contact hole Download PDFInfo
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- CN100592494C CN100592494C CN200710039737A CN200710039737A CN100592494C CN 100592494 C CN100592494 C CN 100592494C CN 200710039737 A CN200710039737 A CN 200710039737A CN 200710039737 A CN200710039737 A CN 200710039737A CN 100592494 C CN100592494 C CN 100592494C
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- contact hole
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Abstract
The invention provides a method for modifying a pattern of a circuit layer covering contact hole in multilayered integrated circuit layout design. When design rules of the integrated circuit are shrunk, manufacture of an ideal pattern of the circuit metal layer covering contact hole or a circuit metal layer covering through hole is very difficult as for the multilayered integrated circuit structure because the size of devices is reduced. Sometimes, the through hole or the contact hole can not be in alignment with a circuit and be exposed out of the metal circuit. The invention provides a method for politically amplifying the size of the pattern of the metal circuit layer covering contact hole. By utilization of the method to modify the circuit layer pattern and then perform optical approximate correction on the circuit layer pattern so as to manufacture a mask, a better pattern outline can be obtained through photoetching on a wafer, thereby the problems are completely avoided.
Description
Technical field
The present invention relates to layout-design and lithographic process in the semi-conductor industry, relate in particular to a kind of method of revising the metallic coating of contact hole layout-design with variation of minimizing critical size and mis-alignment.
Background technology
Semiconductor device is the structure that multilayer circuit piles up, it between the adjacent circuit structure layer via layer (via layer), wherein there are a plurality of through holes of inserting metal plug square or rectangle to make the circuit of levels keep being electrically connected, the top layer circuit then is connected with extraneous by pulling out lead-in wire with the contact hole layer (Contact layer) of via layer structural similarity, through hole or contact hole can be referred to as contact hole, and its effect all is to keep each layer circuit to interconnect.Described through hole of this structural requirement or contact hole contact with assurance with the circuit good alignment of regulation, and through hole or contact hole pattern can not exceed the metal wire coverage of circuit layer, also are that circuit should cover contact hole pattern fully with the electric circuit metal layer at the contact hole place of coincidence.
When the design rule of integrated circuit shrinks,, for semiconductor fabrication process, to make desirable electric circuit metal layer covering contact hole or through-hole pattern and become very difficult because device size diminishes.Through hole or contact hole sometimes can occur can not aim at circuit, and through hole or contact hole expose the situation outside metallic circuit, will produce serious problem like this, for example, exceeds the place that covers metal at through hole and is easy to occur leakage current.Therefore, bad if metal covers the performance of contact hole or contact hole, the critical size of generation changes and mis-alignment will cause the product yield to reduce, even does not have yield.In this case, people can only deal with problems by two kinds of means usually:
1) change layout-design, this method can only be used in the time of minority, and most applications can not be changed layout-design;
2) adopt littler process window, this method is higher to the required precision of machine, directly causes yield to reduce.
Summary of the invention
Because design rule shrinks, make that the critical size that occurs easily when metal covers the structure of contact hole or through hole changes and problems such as mis-alignment, proposition the present invention at present.
The objective of the invention is to, the method that provides a kind of correction circuit layer to cover through-hole pattern makes and can effectively solve above-mentioned critical size variation and mis-alignment problem in this way.
Method provided by the invention, be that a kind of tactic is amplified the method that the metallic circuit layer covers contact hole place pattern dimension, carry out making mask after the optical approximate correction with the method modification circuit layer pattern and to it, finally can on wafer, photoetching obtain better pattern contour.
The concrete steps of described method are as follows:
At first utilize formula as follows to calculate value of magnification, amplify each limit of through hole or contact hole with calculated value contact hole pattern:
Value of magnification
Wherein a represents metal critical size changing value; B represents the critical size changing value of contact hole or through hole; C represents mis-alignment specification between contact hole or through hole and the metal wire edge; In fact, the error range decision that is allowed in the technical process of these three parameters by reality.
To enlarge the boolean calculation that pattern behind contact hole or the through hole and original metal layer pattern carry out " OR " then, and obtain two layer pattern complementations and be incorporated into together Butut, as metal layer pattern;
With the target of newly-generated metallic circuit Butut, this Butut is carried out the optical approximate correction as the optical approximate correction; The pretreatment stage that focuses on optical approximate correction operation of the present invention, specifically use which kind of optical approximate correction technique and unaffected in the back, therefore, following adopted is for example rule-based or all be applicable to the present invention based on the optical approximate correcting method of model.
The Butut of recording out through the optical approximate correction is used to make mask, and uses it for and make metal covering contact hole or through-hole structure.
Can be described in detail method of the present invention with reference to diagram, in the original layout-design, the position relation that the metal layer pattern of contact hole or through-hole pattern 2 and covering on it is 1 as shown in Figure 1a, though contact hole or through-hole pattern 2 are in the scope that covers metal level 1, in case but photoetching occurs contact hole or through-hole pattern 2 easily and exposes to the extraneous situation that covers metal level 1 to silicon chip.Utilize above-mentioned formula result of calculation provided by the invention, at first every limit of contact hole in the contact hole layer pattern or through-hole pattern 2 is amplified, contact hole after will amplifying then or via layer pattern 2 and the metallic circuit layer pattern 1 that covers are thereon done " OR " computing, make it be merged together pattern as the cover layer metallic circuit, the result is shown in Fig. 1 b.Fig. 1 b pattern is carried out the optical approximate correction, and revised Butut is recorded to and is used for photoetching formation covering metal level on the mask.
The invention has the advantages that, by such method, can be in design rule metallic circuit layer and contact hole or through hole junction be rationally amplified, can form the structure that good metal covers contact hole or through hole at last, the pattern contour on wafer is optimized more.In addition, this method is simple to operate, can't increase original processing procedure in operational difficulty.
For be more readily understood purpose of the present invention, feature with and advantage, below conjunction with figs. and embodiment are described in detail the present invention.
Description of drawings
The accompanying drawing that comprises among the application is a component part of specification, and accompanying drawing and specification and claims one are used from explanation flesh and blood of the present invention, are used for understanding better the present invention.
Fig. 1 a shown in the layout-design of the prior art, the position relation that contact hole or through-hole pattern 2 and the metal layer pattern that covers on it are 1, for the ease of display structure, the metal pattern layer on upper strata is done transparent expression, below identical;
Fig. 1 b has shown through in the revised layout-design of the present invention program, the position relation between the metal layer pattern of contact hole or through-hole pattern and covering on it;
Fig. 2 a has shown the position relation between contact hole in the circuit layout design of a reality or through-hole pattern and the cover layer metal pattern;
Fig. 2 b shown according to the present invention program to the correction of Fig. 2 a Butut after position relation between contact hole or through-hole pattern and the cover layer metal pattern;
Fig. 3 a～3d shown a reality according to the inventive method from revising the process of layout-design to lithographic results;
Fig. 4 a and 5a have shown respectively in the prior art metal being covered the various contact holes that occur after contact hole pattern carries out photoetching and cover metal can not aim at schematic diagram on the actual silicon chip that is reflected in; With
Fig. 4 b and Fig. 5 b shown respectively according to behind the present invention program's correction Butut, with the profile schematic diagram of pattern characteristics photoetching to the silicon chip
Embodiment
In order to understand technology of the present invention better, be described further below in conjunction with specific embodiments of the invention, but it does not limit the present invention.
Layout-design to the cover layer metal wire is revised
Fig. 2 a shows is the position relation between contact hole or through-hole pattern 2 and the cover layer metal pattern 1 in the original layout-design, metal live width L=240nm, distance between centers of tracks N=240nm, the limit spacing 10nm of the limit of contact hole pattern 2 and metal line pattern 1.
The value of magnification that utilizes formula as follows to calculate to contact hole pattern enlarges each limit:
Value of magnification
Wherein a represents metal critical size changing value; B represents the critical size changing value of contact hole or through hole; C represents mis-alignment specification between contact hole or through hole and the metal wire edge; These three values in fact all are the errors that every layer process of each technology node is allowed when making.Such as being the metal line layer of 170 nanometers for design size, the error of its permission is 10%, then a value gets 17, for design rule is the contact hole layer of 160 nanometers, all the other errors that need are 10%, then the b value gets 16, and the offset error of metal level and contact hole layer allows for 10 nanometers when designing simultaneously, and then the c value gets 10.
According to result of calculation, every limit of contact hole pattern 2 is all outwards enlarged 50nm, shown in Fig. 2 b, contact hole pattern 2 after will enlarging then and original metal circuit layer pattern 1 carry out the boolean calculation of " OR ", obtain two layer pattern complementations and be incorporated into together Butut, with the Butut that obtains as the cover layer metal pattern.
From revising the process of layout-design to lithographic results
Shown in Fig. 3 a, in the original Butut, contact hole pattern 2 is positioned at the line end of cover layer metal line pattern 1, and apart from the edge 55nm of line end, other data are identical with embodiment 1;
According to calculated value, the every limit of contact hole pattern is outwards enlarged 50nm, shown in Fig. 3 b, contact hole pattern is at the edge of adjusted range line end 5nm;
Contact hole pattern 2 after will enlarging then and original metal circuit layer pattern 1 carry out the boolean calculation of " OR ", obtain two layer pattern complementations and be incorporated into together Butut, with it as metal layer pattern.
With the target of resulting metal layer pattern as the optical approximate correction, this Butut is carried out the optical approximate correction, the result is shown in Fig. 3 c, can see that the place by correction of the present invention has obviously influenced the optical approximate correction result, covering contact hole pattern 2 places in metal line pattern 1 has comparatively suitable profile;
The Butut of recording out through the optical approximate correction is used to make mask, and uses it for and make the metal wire structure that covers.The actual pattern contour that reflects is shown in Fig. 3 d on the silicon chip, and the periphery is approximate oblong to be the metal wire zone, numeral 3 its outline lines of expression; The circle at line end place is the actual contact hole pattern that forms after the photoetching, numeral 4 its outline lines of expression.Can see that the actual contact hole that carves is covered under the metal level well, be unlikely to be exposed to metal level.
The metal that prior art and the present invention program form covers the contact hole pattern silhouette contrast
Accompanying drawing 4a and 5a shown respectively at present in actual applications after the pattern characteristics photoetching is to the silicon chip, several contact holes of appearance can not with cover metal level and aim at, cause part to be exposed to pattern contour schematic diagram outside the metal cladding.Fig. 4 b and Fig. 5 b shown respectively according to behind the present invention program's correction Butut, with the profile schematic diagram of pattern characteristics photoetching to the silicon chip.Among the figure, the outline line in the actual metal wire zone that forms after the numeral 3 expression photoetching; The actual contact hole pattern outline line that forms after the numeral 4 expression photoetching.Can clearly find out, same layout-design, after process method correction of the present invention, the problem that contact hole pattern that occurs under the various situations and metal cladding can not be aimed at can be resolved.
The technical staff of the industry should be appreciated that under the prerequisite that does not break away from spirit of the present invention or principal character, the present invention can also implement with other specific forms.Therefore, by whole technical schemes of the present invention, cited embodiment just is used to illustrate the present invention rather than restriction the present invention, and the present invention is not limited to the details of describing herein.The scope of protection of present invention is defined by appending claims.
Claims (5)
1, a kind of method of revising through hole or metallic coating of contact hole layout-design is characterized in that comprising the following steps:
A. utilize formula:
Calculate value of magnification, with the described value of magnification of the outside expansion in each limit of contact hole in the contact hole layer or through-hole pattern;
Wherein a represents metal critical size changing value; B represents the critical size changing value of contact hole or through hole; C represents mis-alignment specification between contact hole or through hole and the metal wire edge, the error that these three values are allowed when making for every layer process of each technology node;
B. contact hole after will enlarging or through-hole pattern and covering metal layer pattern thereon carry out the boolean calculation of " OR ", obtain two layer pattern complementations and are incorporated into together Butut, as metal layer pattern.
2, method according to claim 1 is characterized in that, the error range decision that is allowed in described a, b, the technical process of c value by reality.
3, method according to claim 1 is characterized in that, also comprises the following steps:
C. with the metal layer pattern that generates target, this Butut is carried out the optical approximate correction as the optical approximate correction.
4, method according to claim 3 is characterized in that, described optical approximate correcting method comprises the optical approximate correction based on model, and rule-based optical approximate correction.
5, according to claim 3 or 4 described methods, it is characterized in that, also comprise the following steps:
D. the Butut of recording out through the optical approximate correction is used to make mask, and uses it for and make metal covering contact hole or through-hole structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710039737A CN100592494C (en) | 2007-04-20 | 2007-04-20 | Method for correcting layout design for correcting metallic coating of contact hole |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710039737A CN100592494C (en) | 2007-04-20 | 2007-04-20 | Method for correcting layout design for correcting metallic coating of contact hole |
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| Publication Number | Publication Date |
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| CN101290904A CN101290904A (en) | 2008-10-22 |
| CN100592494C true CN100592494C (en) | 2010-02-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200710039737A Expired - Fee Related CN100592494C (en) | 2007-04-20 | 2007-04-20 | Method for correcting layout design for correcting metallic coating of contact hole |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8527915B2 (en) * | 2011-11-01 | 2013-09-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and system for modifying doped region design layout during mask preparation to tune device performance |
| CN103186031B (en) * | 2011-12-30 | 2017-11-07 | 联华电子股份有限公司 | The method corrected the method for layout patterns and make photomask |
| CN110852029B (en) * | 2018-07-27 | 2023-11-17 | 熠芯(珠海)微电子研究院有限公司 | Semiconductor chip and layout design method and device thereof |
| CN112668258B (en) * | 2020-12-22 | 2022-05-24 | 北京华大九天科技股份有限公司 | Generalized alignment wiring method |
| CN115600544A (en) * | 2021-07-08 | 2023-01-13 | 长鑫存储技术有限公司（Cn） | Integrated circuit design method and device |
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