CN100585839C - Chip encapsulation structure and technology - Google Patents
Chip encapsulation structure and technology Download PDFInfo
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- CN100585839C CN100585839C CN200510135700A CN200510135700A CN100585839C CN 100585839 C CN100585839 C CN 100585839C CN 200510135700 A CN200510135700 A CN 200510135700A CN 200510135700 A CN200510135700 A CN 200510135700A CN 100585839 C CN100585839 C CN 100585839C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
This invention provides one chip sealing structure, which comprises chip and buffer glue, wherein, the chip has main surface, back surface and multiple sides in between, wherein, the buffer glue is set on main and back surfaces with buffer glue Yang mode less between 1Mpa and 1Gpa to reduce heat stress force and to improve chip sealing structure reliability. This invention also provides one chip sealing process to form buffer glue to get best process final product rate.
Description
Technical field
The present invention relates to a kind of semiconductor element and its manufacture method, and be particularly related to a kind of chip-packaging structure and chip package process.
Background technology
In recent years, because the rise of the with rapid changepl. never-ending changes and improvements and semiconductor industry of electronic technology makes electronic product more humane, with better function constantly weed out the old and bring forth the new, and towards light, thin, short, little trend design.In semiconductor industry, the purpose of Chip Packaging is to prevent that bare chip is subjected to moisture, heat and The noise, and bare chip and external circuit be provided, for example printed circuit board (PCB) (PrintedCircuit Board, PCB) or the media that is electrically connected between other base plate for packaging.
Please refer to Fig. 1, it represents a kind of known chip-packaging structure.Chip-packaging structure 100 comprises chip 110, substrate 120 and packing colloid 130; its chips 110 is arranged on the surface of substrate 120; and packing colloid 130 and chip 110 are arranged at the same surface of substrate 120; and covering chip 110; in order to preventing that chip 110 is subjected to influences such as the moisture in the external world, heat and noise, and can protect chip 110 to avoid the destruction of external force.In addition, chip 110 can be electrically connected with substrate 120 by various junctures, is electrically connected to external circuit with the contact (not shown) by substrate 120 bottoms.In addition, the practice that other is also arranged is that contact is designed on the surface of packing colloid 130, and by in packing colloid 130, forming internal connection-wire structure, to connect chip 110 and contact.
It should be noted that, no matter be the method for packing of known which kind of form, when forming packing colloid, high temperature is provided earlier and is the adhesive material of half melting state, as epoxy resin (epoxy resin) etc., pass through steps such as pressing mold and cooling again, on substrate, forming packing colloid, and make packing colloid cover chip.Yet, because thermal coefficient of expansion (the Coefficient ofThermal Expansion of chip, substrate and packing colloid, CTE) difference, therefore in chip package process or when the reliability testing of product and actual motion, will be because of the difference of ambient temperature, and making the thermal strain that chip, substrate and packing colloid produce different sizes, the joint the three produces corresponding thermal stress simultaneously.And, along with the microminiaturization of chip-packaging structure and the raising of circuit integrated level, above-mentioned thermal stress effect will be more obvious, and may make substrate produce serious warpage (warpage), and take place in technology that weld pad on the chip is damaged, problem such as chip and substrate contraposition are forbidden.More severe patient will cause chip from strippable substrate (delaminate) and packaging body distortion (out of spec), and have influence on the operate as normal of chip and the qualification rate of packaging technology.
Summary of the invention
In view of the foregoing, purpose of the present invention just provides a kind of chip-packaging structure that can effectively reduce the thermal stress effect, and it has higher reliability (reliability).
A further object of the present invention provides a kind of chip package process, and it can reduce the influence of thermal stress in the technology, to obtain preferable manufacturing qualification rate.
Based on above-mentioned or other purpose, the present invention proposes a kind of chip-packaging structure, comprises chip and buffering colloid, its chips have active surface, the relative back side and be connected in active surface and the back side between a plurality of sides.In addition, the buffering colloid is arranged on the active surface and the back side at least, and the Young's modulus of buffering colloid is between 1MPa and 1GPa.
In one of the present invention embodiment, the buffering adhesive style is as comprising first glue-line and second glue-line, and wherein first glue-line is arranged on the active surface of chip, and second glue-line is arranged on the back side of chip.In another embodiment, first glue-line and second glue-line also for example may extend on the side of chip, and interconnect, with coating chip.
In one of the present invention embodiment, first glue-line is identical with the material of second glue-line.
In one of the present invention embodiment, packing colloid also comprises the 3rd glue-line, is arranged on the side of chip, and connects first glue-line and second glue-line, with coating chip.In addition, first glue-line, second glue-line can be identical materials with the 3rd glue-line.
In one of the present invention embodiment, chip-packaging structure also comprises a plurality of contacts and a plurality of intraconnections, and wherein contact is arranged at the surface of buffering colloid, and intraconnections is arranged in the buffering colloid, to connect chip and contact.
In one of the present invention embodiment, chip-packaging structure also comprises substrate, and chip is arranged on the substrate by the buffering colloid.
In the above-described embodiments, chip-packaging structure also can comprise packing colloid, and it is arranged on the substrate and covers buffering colloid and chip, and wherein the Young's modulus of packing colloid is greater than the Young's modulus of buffering colloid.In addition, chip-packaging structure also can comprise a plurality of contacts and a plurality of intraconnections, and wherein contact is arranged at the surface of packing colloid, and intraconnections is arranged in buffering colloid and the packing colloid, to connect chip and contact.
In one of the present invention embodiment, the material of buffering colloid for example is rubber (rubber) or silica gel (silicon).
The present invention also proposes a kind of chip package process, comprising: substrate is provided; Chip is set on substrate; And form the buffering colloid on substrate and chip, wherein cushion colloid and cover chip.
In one of the present invention embodiment, chip is set is included between chip and the substrate in the method for substrate adhesion layer is set, to connect chip and substrate by adhesion layer.
In one of the present invention embodiment, chip package process comprises that also a plurality of intraconnections of formation are in the buffering colloid, so that chip can be connected to the external world by intraconnections.
In one of the present invention embodiment, chip package process also comprises the formation packing colloid on substrate, so that packing colloid covers buffering colloid and chip.In addition, chip package process also can form a plurality of intraconnections in buffering colloid and packing colloid, so that chip can be connected to the external world by intraconnections.
The present invention also proposes another kind of chip package process, comprising: substrate is provided; Form the buffering colloid on substrate; And, insert chip in the buffering colloid.
In one of the present invention embodiment, above-mentioned another kind of chip package process comprises that also a plurality of intraconnections of formation are in the buffering colloid, so that chip can be connected to the external world by intraconnections.
In one of the present invention embodiment, above-mentioned another kind of chip package process also comprises the formation packing colloid on substrate, so that packing colloid covers buffering colloid and chip.In addition, also can form a plurality of intraconnections in buffering colloid and packing colloid, so that chip can be connected to the external world by intraconnections.
Based on above-mentioned, the present invention is provided with the buffering colloid in chip periphery, in order to absorb the effect of thermal stress, therefore can effectively reduce substrate warp and chip is subjected to stress rupture or from problems such as strippable substrates, and can further improve the qualification rate and the reliability of products of packaging technology.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 represents a kind of known chip-packaging structure.
Fig. 2 is expressed as a kind of chip-packaging structure of the present invention's preferred embodiment.
Fig. 3 A～3E represents a kind of chip package process of the present invention's preferred embodiment successively.
Fig. 4 A～4E represents another kind of chip package process of the present invention.
Fig. 5～9 are represented the set-up mode of other several different buffering colloids of the present invention respectively.
Figure 10 represents the another kind of chip-packaging structure of the present invention's preferred embodiment.
The main element description of symbols
100,200: chip-packaging structure
110,210,510,610,710,810,910,1010: chip
120,220,1020: substrate
130,230: packing colloid
212,512,612,712,812: the active surface of chip
214,514,614,714,814: the back side of chip
216,616,716,816: the side of chip
240,1040: intraconnections
242,1042: the top layer circuit
244,1044: contact
250,1050: protective layer
260,1060: soldered ball
270,570,670,770,870,970,1070: the buffering colloid
272: adhesion layer
274,572,574,672,674,676,772,774,872,874: glue-line
280: separation material
300: tool
Embodiment
Fig. 2 is expressed as a kind of chip-packaging structure of the present invention's preferred embodiment.As shown in Figure 2, the present invention is provided with buffering colloid 270 for chip 210 being provided the effect of stress buffer around chip 210, and chip is arranged on the substrate 220 by buffering colloid 270.In addition, packing colloid 230 covers buffering colloid 270 and chip 210, and is formed with a plurality of intraconnections 240 in buffering colloid 270 and the packing colloid 230.
Referring again to Fig. 2, the intraconnections 240 of part can be connected to the top layer circuit 242 on packing colloid 230 surfaces, and packing colloid 230 surfaces are provided with protective layer 250, and it exposes the top layer circuit 242 of part, with as a plurality of contacts 244.In addition, contact 244 is provided with soldered ball 260, and chip 210 can be electrically connected to the external circuit (not shown) with soldered ball 260 by intraconnections 240, top layer circuit 242.
In the present invention, buffering colloid 270 mainly is the effect in order to the absorption thermal stress, so its Young's modulus ought to be less than the Young's modulus of packing colloid 230, promptly between preferable scope: between the 1MPa to 1GPa.In practical application, for example can select rubber (rubber), silica gel (silicon) or other material that is suitable for to make buffering colloid 270.Thus, buffering colloid 270 just can be at two elements that the thermal expansion degree is different, for example chip 210 and packing colloid 230, or between chip 210 and the substrate 220, provide the effect of stress buffer.
Please refer to Fig. 3 A～3E, in order more to clearly demonstrate feature of the present invention, hereinafter the general describes with regard to the technology of above-mentioned chip-packaging structure again.
At first, as shown in Figure 3A, chip 210 is arranged on the substrate 220, the active surface 212 of its chips 210 and engages with substrate 220 with the back side 214 up, and the back side 214 of chip 210 is to be connected with substrate 220 by adhesion layer 272.What deserves to be mentioned is, this adhesion layer 272 for example is just to have become at chip back surface before carrying out the wafer cutting, or the mode in addition by a glue is formed on the substrate 220, and the material of the adhesion layer 272 that the present invention adopted for example is the buffering material of Young's modulus between 1MPa and 1GPa, as above-mentioned.
Then, shown in Fig. 3 B, form glue-line 274 on chip 210, its mesoglea 274 covers the active surface 212 and side 216 of chip 210, and is connected with adhesion layer 272, to constitute the buffering colloid 270 of coating chip 210.In the present embodiment, glue-line 274 can be selected the material identical with adhesion layer 272 for use, or different with adhesion layer 272, but the Young's modulus material between 1MPa and 1GPa equally.
Then, shown in Fig. 3 C, on substrate 220, form packing colloid 230, and make it cover chip 210 and buffering colloid 270.Generally speaking, packing colloid 230 normally adopts for example epoxy resin bigger dielectric materials of Young's modulus such as (epoxy resin), so that preferable protection and insulation effect to be provided.
Then, shown in Fig. 3 D, in packing colloid 230 and buffering colloid 270, form intraconnections 240, and form top layer circuits 242 on packing colloid 230 surfaces.In addition, form patterned protective layer 250 on the surface of packing colloid 230, wherein protective layer 250 has a plurality of openings, in order to exposing the top layer circuit 242 of part, with as contact 244.Afterwards, shown in Fig. 3 E, on each contact 244, form soldered ball 260, roughly to finish the manufacturing of chip-packaging structure 200, soldered ball 260 usefulness that can engage with external circuitry for chip-packaging structure 200 wherein.
In addition, the present invention also proposes the manufacture method of another kind of chip-packaging structure, please refer to the of the present invention another kind of chip package process shown in Fig. 4 A～4E.
At first, shown in Fig. 4 A, on substrate 220, form buffering colloid 270 earlier, wherein cushion in the colloid 270 and can be mixed with a plurality of separation materials (spacer) 280.Same, the buffering material that colloid 270 adopted for example is rubber or the buffering material such as silica gel of Young's modulus between 1MPa and 1GPa.Then, shown in Fig. 4 B, chip 210 is inserted in the buffering colloid 270, and will cushion colloid 270 moulding by tool 300, wherein separation material 280 helps to keep the position of chip 210 in buffering colloid 270.Then, carry out described step, form packing colloid 230 (Fig. 4 C) successively as above-mentioned embodiment; Make intraconnections 240 and top layer circuit 242 (Fig. 4 D); And on contact 244, form soldered ball 260 (Fig. 4 E), to finish the present invention's another kind of chip package process.
In above-mentioned two kinds of chip package process, buffering colloid 270 can be divided into two steps (adhesion layer 272 and glue-line 274) and form, or is formed on chip 210 peripheries once.Certainly, the present invention is not limited to above-mentioned two kinds in order to the method that forms the buffering colloid, and the buffering colloid also is not limited to be made of single material.In other words, the visual demand of the present invention changes the composition or the manufacturing step of buffering colloid, in the hope of obtaining optimized stress buffer effect, below will enumerate several different buffering adhesive body structures again.
Fig. 5～9 are represented the set-up mode of other several different buffering colloids of the present invention respectively, and wherein for simplicity of illustration, chip and buffering colloid are only drawn in Fig. 5～9.
Please refer to embodiment shown in Figure 5, wherein cushion first glue-line 572 that colloid 570 comprises the active surface 512 that is arranged at chip 510, and second glue-line 574 (for example being adhesion layer) that is arranged at the back side 514 of chip 510.
The buffering colloid 670 that Fig. 6 represents comprises first glue-line 672 of the active surface 612 that is arranged at chip 610; Be arranged at second glue-line 674 at the back side 614 of chip 610; And, be arranged at the 3rd glue-line 676 of the side 614 of chip 610.On making, first, second is to be formed by different step manufacturings with the 3rd glue-line 672,674 and 676, and has different materials respectively.
Fig. 7 represents the buffering colloid 770 that is made of first glue-line 772 of unlike material and second glue-line 774, wherein first glue-line 772 is arranged at the active surface 712 of chip 710, and second glue-line 774 is arranged at the back side 714 of chip 710, and first glue-line 772 and second glue-line 774 also extend to respectively on the side 716 of chip 710, and interconnect, with coating chip 710.On making, for example be that second glue-line 774 is provided earlier, and chip 710 parts are imbedded in second glue-line 774, on second glue-line 774, form first glue-line 772 that covers chip 710 afterwards again.
Fig. 8 represents similarly to cushion colloid 870 with Fig. 7, and it is made of first glue-line 872 of unlike material and second glue-line 874.Second glue-line 874 is arranged at the back side 814 of chip 810, and first glue-line 872 is arranged at the active surface 812 of chip 810, and extends on the side 816 of chip 810, with coating chip 810.When the represented difference of Fig. 8 and Fig. 7 is to make buffering colloid 870, provide first glue-line 872 earlier, and chip 810 is put surface as for second glue-line 874, on second glue-line 872, form first glue-line 872 that covers chip 810 afterwards again.
Fig. 9 represents by the formed packing colloid 970 of single material, it is coated on outside the chip 910, wherein packing colloid 970 can be by irritating mould one steps such as (molding), or forms the glue-line of identical material (that is form) by a plurality of step manufacturings shown in the foregoing description.
What deserves to be mentioned is that if the dielectric property of buffering colloid and the strength of materials are in allowed limits, the present invention also can not need additionally to form packing colloid,, and can reduce manufacturing cost with the simplification manufacturing process.Please refer to Figure 10, the another kind of chip-packaging structure of its expression the present invention's preferred embodiment.As shown in figure 10, chip 1010 is cushioned colloid 1070 and coats, and buffering colloid 1070 is arranged on the substrate 1020.In addition; be provided with a plurality of intraconnections 1040 in the buffering colloid 1070, it is connected to the top layer circuit 1042 on buffering colloid 1070 surfaces, and buffering colloid 1070 surfaces can be provided with protective layer 1050; it exposes the top layer circuit 1042 of part, with as a plurality of contacts 1044.In addition, contact 1044 is provided with soldered ball 1060, and chip 1010 can be electrically connected to the external circuit (not shown) with soldered ball 1060 by intraconnections 1040, top layer circuit 1042.In the present embodiment, buffering colloid 1070 can be the variform shown in Fig. 6～9, and the Young's modulus of its material is equally between 1MPa and 1GPa, for example is rubber (rubber), silica gel (silicon) or other material that is suitable for.
Except the foregoing description, buffering colloid of the present invention also can be applicable in the encapsulating structure of other type, to solve between chip and other potted element because the problem that thermal stress was caused, right this should belong to the person of ordinary skill in the field with reference to the scope that can understand after the disclosure of the present invention and spread to easily, just gives unnecessary details no longer one by one at this.
In sum, the present invention is by being provided with the buffering colloid in chip periphery, so that effect provides the effect of buffering to thermal stress.Therefore, chip-packaging structure proposed by the invention can effectively reduce substrate warp and chip is subjected to stress rupture or from problems such as strippable substrates, thereby has preferable reliability.On the other hand, the present invention's chip package process has preferable qualification rate too.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; when can doing a little change and improvement, so the present invention's protection range is as the criterion when looking the claim person of defining.
Claims (18)
1. chip-packaging structure is characterized in that comprising:
Substrate;
Chip, have active surface, the relative back side and be connected in this active surface and this back side between a plurality of sides, and this chip is disposed at this substrate top with this back side towards this substrate;
The buffering colloid, be arranged on this active surface at least and this chip and this substrate between, and the Young's modulus that should cushion colloid is between 1MPa and 1GPa;
A plurality of separation materials are disposed in this buffering colloid;
A plurality of contacts are disposed at the surface of this buffering colloid; And
A plurality of intraconnections are disposed in this buffering colloid, to connect this chip and above-mentioned these contacts.
2. the chip-packaging structure according to claim 1 is characterized in that this buffering colloid comprises:
First glue-line is arranged on this active surface of this chip; And
Second glue-line is arranged between this chip and this substrate.
3. the chip-packaging structure according to claim 2 is characterized in that this first glue-line and this second glue-line also extend on above-mentioned these sides of this chip, and interconnects, to coat this chip.
4. the chip-packaging structure according to claim 2 is characterized in that this first glue-line is identical with the material of this second glue-line.
5. the chip-packaging structure according to claim 2 is characterized in that this buffering colloid also comprises the 3rd glue-line, is arranged on this chip and states on these sides, and connect this first glue-line and this second glue-line, to coat this chip.
6. the chip-packaging structure according to claim 5 is characterized in that this first glue-line, this second glue-line are identical with the material of the 3rd glue-line.
7. the chip-packaging structure according to claim 1 is characterized in that the material of this buffering colloid comprises rubber or silica gel.
8. chip-packaging structure is characterized in that comprising:
Substrate;
Chip, have active surface, the relative back side and be connected in this active surface and this back side between a plurality of sides, and this chip is disposed at this substrate top with this back side towards this substrate;
The buffering colloid, be arranged on this active surface at least and this chip and this substrate between, and the Young's modulus that should cushion colloid is between 1MPa and 1GPa;
Packing colloid is disposed on this substrate and covers this buffering colloid and this chip, and wherein the Young's modulus of this packing colloid is greater than the Young's modulus of this buffering colloid;
A plurality of contacts are arranged at the surface of this packing colloid; And
A plurality of intraconnections are arranged in this buffering colloid and this packing colloid, to connect this chip and above-mentioned these contacts.
9. described according to Claim 8 chip-packaging structure is characterized in that this buffering colloid comprises:
First glue-line is arranged on this active surface of this chip; And
Second glue-line is arranged between this chip and this substrate.
10. the chip-packaging structure according to claim 9 is characterized in that this first glue-line and this second glue-line also extend on above-mentioned these sides of this chip, and interconnects, to coat this chip.
11. the chip-packaging structure according to claim 9 is characterized in that this first glue-line is identical with the material of this second glue-line.
12. the chip-packaging structure according to claim 9 is characterized in that this buffering colloid also comprises the 3rd glue-line, is arranged on this chip and states on these sides, and connect this first glue-line and this second glue-line, to coat this chip.
13. the chip-packaging structure according to claim 12 is characterized in that this first glue-line, this second glue-line are identical with the material of the 3rd glue-line.
14. the chip-packaging structure according to claim 9 is characterized in that the material of this buffering colloid comprises rubber or silica gel.
15. a chip package process is characterized in that comprising:
Substrate is provided;
Form the buffering colloid on this substrate; And
After forming this buffering colloid, chip is imbedded in this buffering colloid fully, make isolated this chip of this buffering colloid with extraneous.
16. the chip package process according to claim 15 is characterized in that also comprising forming a plurality of intraconnections in this buffering colloid, so that this chip can be connected to the external world by above-mentioned these intraconnections.
17. the chip package process according to claim 15 is characterized in that also comprising forming packing colloid on this substrate, so that this packing colloid covers this buffering colloid and this chip.
18. the chip package process according to claim 17 is characterized in that also comprising forming a plurality of intraconnections in this buffering colloid and this packing colloid, so that this chip can be connected to the external world by above-mentioned these intraconnections.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200510135700A CN100585839C (en) | 2005-12-31 | 2005-12-31 | Chip encapsulation structure and technology |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200510135700A CN100585839C (en) | 2005-12-31 | 2005-12-31 | Chip encapsulation structure and technology |
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| Publication Number | Publication Date |
|---|---|
| CN1996575A CN1996575A (en) | 2007-07-11 |
| CN100585839C true CN100585839C (en) | 2010-01-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200510135700A Expired - Fee Related CN100585839C (en) | 2005-12-31 | 2005-12-31 | Chip encapsulation structure and technology |
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Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9202769B2 (en) | 2009-11-25 | 2015-12-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming thermal lid for balancing warpage and thermal management |
| US8034661B2 (en) * | 2009-11-25 | 2011-10-11 | Stats Chippac, Ltd. | Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP |
| KR101906408B1 (en) * | 2011-10-04 | 2018-10-11 | 삼성전자주식회사 | Semiconductor package and method of manufacturing the same |
| CN202434493U (en) * | 2011-10-20 | 2012-09-12 | 新宝电机(东莞)有限公司 | Circuit encapsulation structure |
| CN103367266B (en) * | 2012-04-06 | 2016-05-18 | 南亚科技股份有限公司 | There is the semiconductor package of stress buffer body |
| CN104684840A (en) * | 2012-07-31 | 2015-06-03 | 惠普发展公司，有限责任合伙企业 | Device including interposer between semiconductor and substrate |
| TWI518852B (en) * | 2013-10-02 | 2016-01-21 | 矽品精密工業股份有限公司 | Semiconductor package and manufacturing method thereof |
| US9343385B2 (en) * | 2014-07-30 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device comprising a chip substrate, a mold, and a buffer layer |
| TWI660473B (en) * | 2017-12-26 | 2019-05-21 | Industrial Technology Research Institute | Package structure and forming method thereof |
| CN109962038A (en) * | 2017-12-26 | 2019-07-02 | 财团法人工业技术研究院 | Encapsulating structure and forming method thereof |
| CN108398063B (en) * | 2018-03-15 | 2019-07-30 | 深圳大成创安达电子科技发展有限公司 | A kind of electric detonator chip and its packaging method |
| CN109860127A (en) * | 2019-04-10 | 2019-06-07 | 深圳市槟城电子有限公司 | A kind of chip packing-body and its packaging technology |
| CN110823248A (en) * | 2019-10-16 | 2020-02-21 | 中国兵器工业集团第二一四研究所苏州研发中心 | Low stress set packaging method of MEMS gyroscope |
| CN116798961B (en) * | 2023-06-21 | 2024-03-15 | 上海韬润半导体有限公司 | Chip packaging structure and method for reducing thermal stress influence |
-
2005
- 2005-12-31 CN CN200510135700A patent/CN100585839C/en not_active Expired - Fee Related
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