CN100581202C - Dual phase pulse modulation decoder circuit - Google Patents

Abstract

A dual phase pulse modulation (DPPM) decoder circuit (Fig. 4) processes a DPPM signal (43), which is in the form of a series of high and low pulses (Fig. 2B) whose pulse widths represent successive groups of M data bits, so as to recover data carried by the signal. Each of the 2<M> possible data values of an M-bit group corresponds to one of 2M distinct pulse widths. Circuit blocks determine the width of each pulse by piping the DPPM signal through a short delay chain (49, 50) and using the delayed outputs (T3 ... T10) to clock flip-flop registers (51A-D, 52A-D) to sample the non-delayed signal (55, 56). The registered output (57A-D, 58A-D) is interpreted by logic gates (59-60, 63-66) to obtain the corresponding M-bit groups (73, 74). The decoder circuit may have two substantially identical pulse width determining blocks (odd and even numbered elements), one receiving the DPPM signal for measuring high pulses, and the other receiving an inverted DPPM signal for measuring the low pulses.

Description

Dual phase pulse modulation decoder circuit

Technical field

The present invention relates to be used for the signal transmission numerical data modulation and to the corresponding demodulation of received signal to recover entrained thus numerical data, and relate in particular to the certain modulation type that is used for coded data, such as pulse duration (width) modulation (PDM or PWM), ON/OFF keying, non-return-to-zero (NRZ) scheme, differential phase keying (DPSK) (DPSK), Multiple Frequency Shift Keying (MFSK) and various forms of polynary/the N primitive encoding.

Background technology

Usually according to modulation type dissimilar signals of communication is classified.Every kind of different modulation format all has and the relevant merits and demerits of its concrete application.Some factors that need consider when the modulation of selecting particular form comprise bandwidth, power consumption demand and potential signal propagation errors and to the recovery of raw information.For numerical data, be that clock signal or the modulation signal motor synchronizing that needs to separate is very important.Simplification that modulation and demodulation equipment or circuit are relevant or complexity also are the factors that needs decision.Low energy consumption particularly needs when using the transmission line of capacity load.

Every type signal modulation all has to carry out separates the dedicated decoders circuit that the mediation data are recovered.For example, be the demodulation phase-modulated signal, the patent No. that Harada submits to is No.5,614,861 United States Patent (USP) has been described a kind of system that utilizes one group of phase discriminator, and described phase discriminator has an input of received signal and at least one other input that receives the clock signal of particular phases delay.The result of phase demodulation is imported into and comprises the data generative circuit that testing result can be converted to the gate of a pair of data bit.On the contrary, be the demodulation phase shift keyed signal, the patent No. that Toshinori submits to is No.6,204,726 United States Patent (USP) comprises the phase discriminator of comparator input signal and frequency division master clock signal, for example just use subsequently that delay circuit, subtracter, clock-signal regenerator, phase compensator, adder and decision package carry out logical process to its result, thereby obtain data bit for each the keying phase shift in this signal.The decoder circuit that needs the signal modulation of a kind of low-power, high bandwidth, pulse width type.

Summary of the invention

The present invention is diphasic pulse modulation (DPPM) decoder circuit of a kind of DPPM of processing signal, wherein said signal has its duration the pulsewidth of a series of high and low impulse form of the continuous M-bit data bit group of (or " pulsewidth ") expression, thereby recovers the entrained data of this signal.2 of M-hyte ^MIn the individual possible data value each is all uniquely corresponding to 2 ^MIn the individual distinct pulse widths one.High signal pulse and low signal pulses are all represented the M-bit data.This decoder is changed back the ordered sequence of data bit with series of signal pulses and is not required independently or clock recovered.

More specifically, this decoder circuit can be implemented as by height that separates and low pulsewidth determines circuit (both are roughly the same), wherein be exclusively used in the circuit block of determining high-pulse widths and be coupled the DPPM signal that directly comes from the signal input to receive, the circuit block that is exclusively used in definite low pulse duration then is coupled to by the signal of signal inverter to be imported.Just interlock subsequently and at parallel output register it is combined into data word by two circuit block data recovered bit groups.

Can be by short delay chain (chain) thus carry modulated signal and postpone to export to synchronous triggering formula register and determine pulsewidth using subsequently with the non-inhibit signal of sampling.Delay chain provides the specific delays relevant with the signal pulse rising edge, selects this rising edge to fall in the time so that one group of possible M-bit data value is represented in each pulse in the pulses switch of expectation.Can be used for becoming the gate of corresponding M-bit data group or other logical means to explain fixed pulse width conversion by one group and deposit output from trigger.

Description of drawings

Fig. 1 is according to the diagram of one group of DPPM pulse of the present invention (signal value is to the time), and wherein each pulse duration of DPPM pulse is used to represent the dibit data symbol of one group of correspondence.

Fig. 2 a and 2b are the diagrams that is used for the DPPM spike train of one group of example data according to the present invention, and the system clock cycle that is illustrated in the single 100ns of scheduling to last is interior to 9 high and low transmission of carrying out the DPPM train of impulses of pulse.

Fig. 3 is the exemplary circuit figure of typical DPPM encoder circuit, is used to generate the DPPM signal by decoder demodulation of the present invention.

Fig. 4 is the schematic circuit of the present invention typical case DPPM decoder circuit.

Specific embodiment

The present invention returns diphasic pulse modulation (DPPM) conversion of signals to the decoder circuit (its embodiment has been shown among Fig. 4) that its numerical data is represented.DPPM is the method that a kind of mode with binary condition (1 and 0) is present in the expression data in the digital circuit, and the duration separately of height that wherein replaces and low signal pulses string or width are represented the data of every pulse 2 (or more).Exemplary embodiments shown in Figure 1 is used 2 codings.Use one group of distinct pulse widths of each possibility dibit symbol value of expression to come coded-bit right, such as:

The 00=4ns pulse

The 01=6ns pulse

The 10=8ns pulse

The 11=10ns pulse

To 4,6,8 and the selection of 10ns pulsewidth be arbitrarily, as long as can correctly distinguish different pulsewidths, then also can use 4,5,6 and 7ns or other pulsewidth at the decoding circuit of DPPM signal transmission receiving terminal.Decoding circuit (and processing variation, noise and Signal Degrade and the temperature/voltage variation in communication environments) has also limited the figure place of every pulse codified in the practical application, and wherein every pulse 3 bits have 8 kind (=2 ³) the possible pulsewidth that need correctly be resolved, and every pulse 4 bits have 16 kind (=2 ⁴) the possible pulsewidth that need correctly be resolved.Can think that data transfer rate is the figure place (or alternatively, the umber of pulse of per second) of per second coding, it depends on the umber of pulse in every system clock and depends on the clock frequency of this system.

" two-phase " is meant information carried out the pulse and the low fact of carrying out pulsing as height.Most pulse width modulating schemes only change the width that height carries out pulse, therefore are actually the adjustment duty factor.DPPM in the height of each " circulation " and lower part with different groups of bits encoded, thereby the high and low width that carries out pulse of separate modulation.Therefore, concerning the pulse train that has produced, clock cycle and duty factor are not effective notions.The character of DPPM is " no clock ", only means to change relevant pulsewidth with regard to the decodable code data by detecting with each.This just means that clock need not to send together with data, also needn't encode and recovered clock from data.Therefore this is a main advantage when the strict pulse train of different chip chamber transmission time sequences, is because it has exempted needs to processing clock, and can introduces the chance of timing fluctuation and error to the processing of clock.What only will consider about clock is the fact that some pulses " circulation " can take place in each system clock cycle.For example, Fig. 2 a and 2b are illustrated in the example of the DPPM pulse train of the alternately high and low pulse (5 high impulses and 4 low pulses) that transmits 18 bit data (forming as 9 pairs of dibits at this) in the 100ns system clock cycle.These 18 can form for example 16 bit data word of subsidiary two error correcting codes.Each system clock cycle just can transmit a data word like this.

Owing on the positive of pulse train and negative, all send information, so DPPM is a kind of non-return-to-zero (or non-normalizing) modulation scheme naturally.The pulse train in when yet usually expectation is included in a system clock is each such sequence ending place make zero (or one).This situation about preferably selecting of the easiest realization is: as the example among Fig. 2 a and the 2b, multidigit symbolic number in a word that will be represented as pulse is an odd number, and this is because last symbol need make zero (or normalizing) with the back edge transformation as a last pulse in this sequence.If but neglect this pulse to force its recurrence by additional pulse of encoder insertion and decoder, then need not to defer to this rule.

Like this, the DPPM method will be expressed as the signal pulse with specific width such as the M data-bit-group of dibit (M=2).2 ^MIn the individual possible data value each is all corresponding to 2 ^MIn the individual distinct pulse widths one, and represent continuous M data-bit-group by the pulse of height alternating signals.Conversion between the signal pulse of signal encoding and the decoding circuit execution data bit and the information content is expressed.

For data bit is encoded into signal pulse, the data word that is received at first is divided into the ordered sequence of M data-bit-group, convert each group of this sequence to corresponding with it pulse signal then and represent, so just produced a series of high-low signal pulses of expression data.The execution data word is the change-over time of specifying signal pulse to a kind of mode of the conversion of signal pulse, each change-over time is all corresponding to previous fringe time, and previous fringe time is increased by the specified pulse width corresponding to current M data-bit-group, subsequently just in those particular conversion time place's generation signal pulse transitions.Following with reference to Fig. 3 describe carry out in this way conversion typical encoder hardware.

For the DPPM signal decoding is become data, will determine each pulsewidth high and low signal pulses, convert it back to the ordered sequence of M data-bit-group subsequently, and recombine into data word.A kind of method of being carried out this conversion by typical decoder hardware has been illustrated in following description with reference to Fig. 4.

The encoder circuit that the present invention uses

With reference to Fig. 3, typical DPPM encoder circuit is divided into two parts the data word (for example, 18 bits are formed 9 dibits) that receives on the parallel data input bus 11 of 11A and 11B herein.The load signal (not shown) indicates when data can be used.If free of data can be used, then the DPPM encoder keeps idle.Sys_Clock12 is at the outside system clock of creating of DPPM encoder.

Circuit obtains the data that receive on odd and even number data/ address bus 11A and 11B, with it synchronously to system clock and be written into two and be advanced into the shift register 13A and the 13B of serial output.Odd bits (promptly, position 1,3,5,7,9,11,13,15 and 17) is written into another shift register 13A (odd number shift register) from bus 11A, simultaneously even bit (that is position 2,4,6,8,10,12,14,16 and 18) is written into a shift register 13B (even number shift register) from bus 11B.

Then paired 15A of the content in these registers and the serial of 15B ground are shifted out.The end that is synchronized to each DPPM signal pulse that is continuously removed of register 13A and 13B data has been guaranteed in the shift clock pulse of exporting 29 feed-ins from multiplexer.Thus, data word is divided into the ordered sequence of the individual data bit of every group of M (M=2 herein).If these data are divided into three every group or four, then input bus 11 can be divided into three or four parts that are loaded into three or four shift registers usually, and each shift register provides one every group output in its serial output.

Register output 15A and 15B are linked to state machine 19 to input 17, and the N position output 21 of this state machine 19 is its currency and the right function of 2 bits that is encoded.More specifically, state machine 19 is with its state that adds up repeatedly corresponding to the amount of importing the right pulsewidth of 17 received continuous 2 bits at state machine.N position output 21 only has an activity bit and is used as input 23, selects continuous tap with control multiplexer 25 from current controlled delay chain 27.Use output 29 synchronizer triggers 31 of multiplexer, this just encodes the data into a series of high and low pulse of the right value of its width means 2 bits in its output 33.

Marginal detector circuit 14 (can be any known marginal detector) sends a duration at each rising edge place of system clock Sys_Clock be 2 to the initial pulse of 3ns.This initial pulse state machine 19 be reset to the first tap selection mode (tap_select[44:1]=0, and tap_select[0]=1).This initial pulse also is set to trigger 31 ' setting ' state (high output).Appear in the input 12 delay chain 27 with the synchronous 1ns pulse of system clock in order to initial 92-element.First delay element 26 that illustrates is separately considered to be written into shift register 13A and 13B and first pair of data bit is presented to the used time of state machine 19.

Each element in this calibration delay chain 27 is so that it has the 1ns delay.Therefore, pulse needs 92ns by this delay chain.When using the described pulse width sets of Fig. 1, suppose that the time delay (corresponding to tap_select[0]) at 2ns locates to take place the transformation of a DPPM signal, then the size of this delay chain just is shown required maximum total time of a series of DPPM signal pulses corresponding to the word table with whole 18-position.That is it is right, to need duration of 90ns to transmit as nine " 11 " bits of the height of nine 10ns pulsewidths and low signal pulses.If select other word size and pulse width sets, then the quantity of delay element and every element possibility time delay is also with corresponding change.The cycle of system clock must surpass the total duration of a signal pulse sequence when all signals all are the pulsewidth of maximum.If use delay lock ring (DLL) that this delay chain is calibrated to system clock, then can adjust pulsewidth automatically in proportion for different system clocks.

The current bit that least significant bit among two shift register 13A and the 13B indicates to be encoded is right, and is input to capability of tap selector state machine 19 from line 17.This state machine 19 is that 92-element delay chain 27 is selected a tapping point.Right for four kinds of possible bits, pulsewidth can be 4,6,8 or 10ns, effectively postpones point in this case only on the even number delay element, so 46 effective tapping points are arranged in this implementation.(still, be arbitrarily to the selection of pulsewidth, and can select other one group of pulsewidth.In that being provided, enough intervals select pulsewidth so that decoder can be purchased on their basis of accurate differentiation.Decision whether " enough " factor such as error expected/noise margin, the noisiness in the system and adopted comprise the technical characteristic of handling fluctuation, switch speed and setting/maintenance requirement.)

Select 21 based on current tapping point (STATE (i)) and the next one 2 bit data that will encode (the DATA[1:0]) tapping point that adds up.Preferably tap is selected to realize as monostability machine 19 (shift register that can repeatedly be shifted in each circulation basically), wherein single effective status depends on 2 bit data value of input from data wire 17, is added up by 1,2,3,4 and 5 positions on each clock.Though each state requires a register can cause the wasting of resources, this realization can be purchased switching state as quick as thought, therefore can quick control multiplexer 25.Between the delay chain tap from T2 to T92 that the tap selection 21 and the multiplexer 25 of state machine 19 outputs are selected is one to one.Regularly be that this tapping point must be added to next value before the rising edge of propagating on the delay chain arrives next tapping point.

Tapping point selects 21 to be the selector control 23 that is used for multiplexer 25.The output 29 of multiplexer 25 is the 1ns pulses that produce at each selected tapping point place.This multiplexer is exported 29 synchronizer triggers 31, also forms the shift clock pulse, this pulse the data among shift register 13A and the 13B are shifted and with state machine 19 from a state synchronized to NextState.The output 33 of trigger 31 is the DPPM output of Fig. 3 entire decoder circuit.

According to decoder circuit of the present invention

With reference to Fig. 4, the serial D PPM signal that typical DPPM decoder circuit processes of the present invention receives in input 43 is to obtain the parallel data by output register 78 outputs.Sys_Clock is at the outside system clock of creating of DPPM decoder.Antitorque skewback (deskew) 45 and 46 allows the DPPM signal is finely tuned individual delays, be used for synchronous d type flip flop 51A to 51D and 52A to 52D and provide by those identical data that trigger is sampled.For example can control the amount of deskew by the register (not shown) of the venier circuit in tuning each piece 45 and 46.The separately high and low pulse of decoding.Following will the detailed description in detail is coupled to the inverter 48 upset DPPM signal pulses of DPPM signal input 43 by antitorque skewback 45 and 46, so that can use essentially identical electronic circuit decode this height and low pulse.

Generally come the specified data value by detecting the pulsewidth relevant with each rising edge of a pulse.By the modulation signal of short these data of delay chain transmission expression, output then is used for synchronously and the sampling undelayed signal.The result decodes just to need not independence or clock recovered.More specifically, be connected in series to DPPM data decoder in parallel and comprise two delay chains 49 and 50, they all have K-1 the output not at the same level of expression delay chain, and wherein K is the number of the different length of delays of expression coded data.For 2-position coding, K=4 (for 3-position coding-, K=8 etc.).

Get back to Fig. 1, for the realization of using 2-position coding, for example can use 4,6,8 and the pulsewidth of 10ns represent data.By to moment T5, T7 and T9 place sampling pulse between the various possibility trailing edges moment of different coding pwm value, just can determine the length of this pulse, and be decoded into its paired data position composition.In the T5 moment (after being rising edge of a pulse 5ns), the 4ns pulse of coding dibit data value 00 finishes like this, and the pulse of other dibit data value of encoding also is not transformed into opposite signal condition at its trailing edge.Similarly, at T7 constantly, the 6ns pulse of encoded data value 01 finishes, and at T9 constantly after a while, the 8ns pulse of encoded data value 10 just will finish, but the 10ns pulse of encoded data value 11 will still proceed to next nanosecond.

As shown in Figure 4, the rising edge that sends data pulse occurs constantly by first delay chain 49 and at T5, T7 and T9, the data pulse that is used for synchronous one group of trigger 51B-51D and samples thus and present on online 55.Carry out pulse for low, at first upset is introduced the DPPM signal, sends then by the oppisite phase data pulse to sample and to present on online 56 of second delay chain 50 that uses to 52D in conjunction with another group trigger 52B.Therefore with regard to high and the low pulse of independently having decoded.And have two delay chains of the low pulse of before sampling, overturning by use, just might only use the rising edge of propagating by the delay chain DPPM signal of decoding.This just produces the added advantage that can be avoided rising/decline data discrete in the delay chain.

63 to 66 in logic AND gate circuit outputs to line 57B to 51D and 52B to 52D by trigger 51B and converts the data value corresponding with them to 57D and 58B to the sampling pulse value on the 58D.

This shows that the DPPM method allow to be used the rising edge decoding pulsewidth of pulse, just need not clock thus, this just means and need not extra clock line, clock coding or or clock recovery circuitry on the receiver.In fact, because the not delayed data pulses of in fact using the delay form of data pulse to come synchronously (or sampling) to introduce, so this technology just has the added advantage of avoiding introducing the possibility of error when manipulation or recovered clock.

Claims (8)

1. (DPPM) decoder circuit is modulated in a diphasic pulse, comprising:

Be configured to receive the DPPM signal input of the DPPM signal of being formed by the alternately high-low signal pulse of the corresponding specific width of M bit group of a series of and data bit;

Be coupled to the signal inverter of described DPPM signal input;

The height and the low pulsewidth that are coupled to described DPPM signal input are determined circuit block, described low pulsewidth determines that circuit block is coupled to described DPPM signal input by described signal inverter, and each pulsewidth determines that circuit is built as the corresponding M bit data value of pulse duration of output and each high-low signal pulse;

Be coupled to described height and low pulsewidth and determine the parallel output register of circuit block, described parallel output register is configured to receive and the described M bit data value that interweaves, and output is corresponding to the data word of described DPPM signal.

2. DPPM decoder circuit as claimed in claim 1 is characterized in that, each pulsewidth determines that circuit block comprises:

After one group of specific delays relevant with the pilot signal edge of a pulse device of described DPPM signal condition is deposited in each pulse, described specific delays is selected as falling between the expection pulse transition time of possible M bit data value collection; And

Logic device, the output of being coupled to described LD device is used for the described DPPM signal condition collection of having deposited is converted to the corresponding M bit data value of each signal pulse.

3. DPPM decoder circuit as claimed in claim 2, it is characterized in that, the described device that is used to deposit comprises a plurality of D flip-flop registers, make the input of each data be coupled to described DPPM signal input and make each clock input be coupled to delay chain branch that described delay chain makes input be coupled to described DPPM signal input corresponding to described specific delays collection.

4. DPPM decoder circuit as claimed in claim 1 is characterized in that, each pulsewidth determines that circuit block comprises:

Be configured to receive the DPPM signal pulse and it is propagated into the delay chain of a plurality of taps;

Be coupled to the marginal detector of first tap;

Have a plurality of triggers of the clock input of being coupled to described first tap each tap afterwards, described trigger is set in advance by the output of marginal detector, and described trigger has the data input that is coupled with the reception and the described DPPM signal pulse of sampling;

Gate is coupled with the input of described trigger, and is configured to determine that according to it pulse length converts described sampling pulse to the M-bit data value; And

Shift register is configured to receive the data value of the continuous high or low pulse of same level, and is written into described parallel output register with described data value is parallel.

5. operation diphasic pulse modulation (DPPM) decoder circuit comprises a series of signal pulses switch is become the method for data:

The form of a series of alternately high-low signal pulses receives the DPPM signal, and each high or low signal pulse is characterised in that: 2 ^M2 of the M bit group of any of the individual pulsewidth that may disperse and data bit ^MThe unique correspondence of individual possible data value; The described DPPM signal of after each of a plurality of time of delays, sampling, each that think described signal pulse is determined pulsewidth and corresponding M-bit data value; And

Continuous M-bit data value is combined into data word.

6. method as claimed in claim 5 is characterized in that, the described DPPM signal of sampling comprises with the data value of determining each signal pulse in the described DPPM signal:

The described DPPM signal that receives is offered 2 ^MThe data of each of-1 trigger register are imported, and logic high state are offered the data input of last trigger register; In the described DPPM signal that receives, detect the rising pulse edge, and set in advance all trigger registers in response to the detection of this rising edge;

Postpone described a plurality of specific delays times of the DPPM signal that receives, and the DPPM signal after each is postponed offers the clock input of different trigger registers, fall within described 2 selected described time of delay ^MBetween the expection pulses switch time of individual possible discrete pulse width sets and expect that in the end pulses switch is after the time; And

One group of signal condition of described trigger register is logically converted to the corresponding M-bit data value of each signal pulse.

7. method as claimed in claim 6, it is characterized in that, the independent circuits piece that high impulse is converted to data is carried out the transformation of low pulse to data, each circuit block is identical and described DPPM signal is just anti-phase before the circuit block that is exclusively used in the low pulse of conversion receives, and the detection of rising pulse edge is performed as by the detection of each circuit block to the rising pulse edge.

8. method as claimed in claim 5, it is characterized in that, continuous M-bit data value is combined into data word to be comprised: the described data value that will obtain from each signal pulse is written into shift register, and when each finishes system clock period, export the content of described shift register, each system clock period is characterised in that a plurality of signal pulses of the described DPPM signal that receives represent a data word.

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