CN100579125C - Method for the PCI Ethernet media to access the controller transmission data - Google Patents
Method for the PCI Ethernet media to access the controller transmission data Download PDFInfo
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- CN100579125C CN100579125C CN200710123413A CN200710123413A CN100579125C CN 100579125 C CN100579125 C CN 100579125C CN 200710123413 A CN200710123413 A CN 200710123413A CN 200710123413 A CN200710123413 A CN 200710123413A CN 100579125 C CN100579125 C CN 100579125C
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Abstract
The present invention provides a method for visiting controller MAC transfer data through a PCI ethernet media. Said method comprises the following steps: step A: when preparing to transfer data frames to host port, MAC starts to read corresponding buffer descriptor from original address of a descriptor sequence at the current buffer of the host port through PCI bus and tests whether the buffer descriptor contains data frames, wherein if the buffer descriptor doesn't contain data frames, a data writing operation at the host port buffer is initiated and step B is implemented, or else, the next buffer descriptor is tested and step A is returned to; step B: MAC writes data frames to be transferred to the host port together with buffer descriptor address of the next frame at a buffer descriptor corresponding to the host port through the PCI bus, and signs a state that said buffer descriptor contains data frames after the data frames are received. The present invention can reduce operation times of PCI bus and improve utilization rate of PCI.
Description
Technical field
The present invention relates to the computer and the communications field, particularly a kind of PCI Ethernet MAC controller (Media Access Control, MAC) method of transmission data.
Background technology
At present, in computer and communication technical field, peripheral parts interconnected (Peripheral ComponentInterconnect, PCI) the ethernet mac controller is a kind of common communication equipment.Usually in PCI ethernet mac controller, select the communication interface of pci bus interface for use as ethernet mac and main frame.Pci bus is 32 or 64 peripheral parts interconnected local buss of multiaddress multidata of a kind of high speed, and when operating frequency was 33MHz, maximum data transfer rate was 132MB/s (32) and 266MB/s (64).From founding the pci bus standard so far, pci bus has come true and has gone up the STD bus of computer.In many computer systems or communication system, all be to be connected between outside expansion equipment (for example subcard or interface board) and the CPU by pci bus.
In the ethernet mac sublayer, mainly defined encapsulation, the deblocking of Frame, and Frame sends and the media access control method that receives.Pci bus allows ethernet mac controller fast access system memory.The read-write operation of pci bus can be undertaken by burst (Burst) mode.Main frame waited for deposit data that MAC read in the data buffer zone earlier before sending Frame; The Frame that MAC receives also will leave the processing of waiting for main frame in the data buffer zone in.
At present, in main frame, adopt following data buffer zone way to manage mostly: as shown in Figure 1, in the internal memory (for example, synchronous DRAM SDRAM) of main frame, mark off two buffering areas, deposit the data that will send for one, be called transmission buffering area (TX-BUFFER); Another deposits the Frame that receives, and is called to receive buffering area (RX-BUFFER).Each buffering area is divided into n little data buffer zone (Buffer), i.e. Buffer_1～Buffer_n again.Each little data buffer zone only is used to deposit a Frame.The buffering area of each store data frame all have the corresponding buffer region descriptor (BufferDescriptors, BD) corresponding with it.Data buffer zone Buffer and its corresponding buffer descriptor that each is little separate.Receive buffering area like this and just have one by receiving tactic reception buffer description (Rx Buffer Descriptors) formation correspondence with it; Send buffering area just have a transmission buffer descriptor of arranging by sending order (Tx Buffer Descriptors, Tx-BD) formation is corresponding with it, the transmission of data and receiving course are all undertaken by buffer descriptor.
The form of buffer descriptor mostly adopts following sheet form:
Wherein: status field (Status), the state of designation data frame is if Own=1 represents in this data buffer area descriptor Frame is arranged; If Own=0, representing does not have Frame in this data buffer area descriptor; The various states of other designation data frame;
Length (Length) is indicated the length of these frame data;
The initial address of buffering area (Buffer Address) is indicated the initial address of this frame data buffering area.
As shown in Figure 2, be the schematic diagram of existing buffer descriptor BD formation, this buffer descriptor formation is a loop configuration, again will be from first buffer descriptor after last buffer descriptor is used.
The receiving course of Frame:
After the system reset initialization, main frame at first receives first address of buffer descriptor by PCI collocating uplink (reception) initial address; Before MAC receives the complete data of a frame and it is stored in the internal memory of main frame, need earlier with this deposit data the reception first-in first-out module of MAC (First InFirst Out, FIFO) in; MAC begins to read corresponding buffer descriptor Rx-BD from the initial address of reading buffer descriptor Rx-BD formation by PCI, and detect the status field of this Rx-BD, if Own=0, then write the Frame that receives in the buffering area of this Rx-BD these frame data pointed by the PCI burst mode, one frame data receive the back and upgrade this Rx-BD, indicate it to deposit effective data frame, main frame just can be handled this frame data by this flag bit, if Own=1, then scan the Rx-BD of next frame data, and the like, get the Rx-BD of last frame data after, just forward the Rx-BD of first frame data again to.If during the Own=1 of all Rx-BD, illustrate that then buffering area is full, at this moment MAC will be with need in time soar reception area buffering area or carry out flow control of interrupt notification main frame.
The process of transmitting of Frame:
After the system reset initialization, main frame at first sends first address of buffer descriptor by PCI configurating downlink (transmission) initial address; Main frame is sending the data buffer zone with a frame or multiframe deposit data earlier, and is sending startup transmission order by pci bus to MAC when sending data; After MAC detects and sends order, will notify PCI to send control module to main frame application pci bus; After obtaining pci bus, reading in PCI according to the initial address of transmission buffer descriptor (Tx-BD) formation among the MAC sends in the control module, and detect the status field of the Tx-BD of these frame data, as Own=1, the data in this frame data buffering area then that Tx-BD is pointed are passed through the PCI burst mode transfer in the Tx-FIFO of MAC.When the data among the Tx-FIFO were full, MAC sent the data among the Tx-FIFO.After one frame data send and finish, PCI sends control module will upgrade (Own is put 0) with the status field in this frame data buffering area by pci bus, indicate these frame data to send, so that main frame reuses this Tx-BD.Such process of transmitting PCI that finishes sends the Tx-BD that control module is then read in second frame data, detects the status field of this Tx-BD, if Own=1 then begins the transmission of second Frame, the rest may be inferred, shows Own=0 up to the status field of the Tx-BD that is read.
By reception and the process of transmitting of analyzing frame data, can see receiving and sending needing 3 pci bus operations in the frame active data, promptly for reception:
1, reads the Rx-BD of a certain frame data that receive, and detect its status field;
2, MAC this frame data that will receive are written to this Rx-BD buffering area pointed;
3, upgrade the Rx-BD of these frame data.
For transmission:
1, reads the Tx-BD of a certain frame data that will send, and detect its status field;
2, the data of the Tx-BD of MAC this frame data that will send buffering area pointed are read among the FIFO of MAC;
3, upgrade the Tx-BD of these frame data.
For the operation of above PCI, use pci bus must ask bus earlier before at every turn, through the arbitration of moderator, after obtaining the authorization, begin the data transmission.So under the situation for the network data parcel, pci bus becomes the bottleneck of transfer of data, it is particularly valuable that the bandwidth of PCI shows.
Summary of the invention
The objective of the invention is to, a kind of method of PCI Ethernet MAC controller transmission data is provided, can reduce the number of operations of pci bus, improved the utilance of PCI.
The method of PCI Ethernet MAC controller MAC transmission data of the present invention comprises the following steps:
Steps A: MAC is when preparing to the host side transmit data frames, begin to read corresponding buffer descriptor by pci bus from the initial address of the current buffer descriptor formation of host side, and detect whether comprise Frame in the described buffer descriptor, if not, then initiate data writing operation to the buffering area of host side, and execution in step B; Otherwise, detect next buffer descriptor, and return steps A;
Step B: described MAC will prepare the Frame that transmits to host side with the buffer descriptor address of next frame together by pci bus write to host side in the corresponding buffer descriptor, and receive the back described buffer descriptor of sign for comprising the Frame state at these frame data.
Wherein, the buffer descriptor of described host side and the buffer descriptor among the MAC comprise: the initial address of status field, length, next buffer descriptor, and the content of current data frame.
Wherein, before described steps A, comprise the following steps: further after the system reset initialization that main frame at first passes through pci bus collocating uplink initial address with the initial address of first buffer descriptor.
In addition, in described steps A, judge by the status field of detecting described buffer descriptor whether it comprises Frame, if the sign Own in the described status field is 1, then representing has Frame in the described buffer descriptor; If the sign Own in the described status field is 0, then representing does not have Frame in the described buffer descriptor.
Wherein, in described step B, described MAC prepared before the host side transmit data frames, described Frame is stored in it receives in the first-in first-out RX-FIFO module.
The method of PCI Ethernet MAC controller MAC transmission data of the present invention comprises the following steps:
Steps A ': MAC is when preparing from the host side read data frame, begin to read corresponding buffer descriptor by pci bus from the initial address of the current buffer descriptor formation of host side, and the initial address of preserving next buffer descriptor, detect then in the current described buffer descriptor and whether comprise Frame, if, execution in step B ' then; Otherwise, then detect next buffer descriptor, and return steps A ';
Step B ': the Frame in the current buffer descriptor of host side is sent to MAC by pci bus, and receives the back described buffer descriptor of sign for not comprising the Frame state at these frame data.
Wherein, the buffer descriptor of described host side and the buffer descriptor among the MAC comprise: the initial address of status field, length, next buffer descriptor, and the content of current data frame.
Wherein, in described steps A ' before, comprise the following steps: further after the system reset initialization that main frame at first passes through pci bus configurating downlink initial address with the initial address of first buffer descriptor.
In addition, in described steps A ' in, judge by the status field of detecting described buffer descriptor whether it comprises Frame, if the sign Own in the described status field is 1, then representing has Frame in the described buffer descriptor; If the sign Own in the described status field is 0, then representing does not have Frame in the described buffer descriptor.
Wherein, in described step B ', described MAC is stored in it with described Frame and sends in the first-in first-out TX-FIFO module after the host side read data frame.
The invention has the beneficial effects as follows: according to the method for PCI Ethernet MAC controller transmission data of the present invention, by buffer descriptor (BD) and corresponding with it data buffer zone (Buffer) are placed on continuous address, PCI transmits and sends a valid data frame only needs 2 pci buss operations, can reduce the number of operations of pci bus, improve the utilance of PCI.
Description of drawings
The schematic diagram that Fig. 1 communicates by letter with ethernet mac by pci bus interface for main frame;
Fig. 2 is existing buffer descriptor formation schematic diagram;
Fig. 3 is a buffer descriptor formation schematic diagram of the present invention.
Embodiment
Below, 1～3 describe the method that PCI Ethernet MAC controller of the present invention is transmitted data in detail with reference to the accompanying drawings.
In the method for PCI Ethernet MAC controller transmission data of the present invention, the employing BD+B pattern of buffer descriptor, particularly, as shown in the table:
Wherein, status field (Status), the state of indication current data frame is if Own=1 represents in the current data buffer area descriptor Frame is arranged; If Own=0 does not have Frame in the expression current data buffer area descriptor; The various states of other position designation data frame;
Length (Length), the length of indication current frame data;
Next Buffer Descriptor Address is the initial address of next buffer descriptor;
Buffer, the content of indication current data frame.
After the system reset initialization, main frame at first passes through pci bus collocating uplink initial address with the initial address of first Rx-BD+B.When MAC received the complete data of a frame and be stored among the reception FIFO of MAC, MAC need be stored in these frame data in the internal memory of main frame, and for this reason, the method for PCI Ethernet MAC controller MAC transmission data of the present invention need be carried out the following step:
Step 100:MAC reads corresponding Rx-BD by pci bus from the initial address of host side Rx-BD+B, and detects the status field of this Rx-BD+B, if Own=0, then execution in step 200; Otherwise, continue to detect next buffer descriptor, and the like, up to Own=0.
Wherein, in step 100, behind the Rx-BD+B that gets the last frame data, just forward the Rx-BD+B of first frame data again to.
Step 200:MAC preserves the address of the buffer descriptor of next frame, and will prepare to write by the pci bus burst mode together with the buffer descriptor address of next frame among the Rx-BD+B of corresponding these frame data of host side to this Frame that host side transmits.
Wherein, in the buffering area of host side, stored complete buffer descriptor formation, and what store is the buffer descriptor of current data frame in the buffering area of MAC.
Wherein, in MAC, need to detect the mistake in the pci bus, the mistake data that then retransfer occur, can correctly write among the Rx-BD+B to guarantee Frame.
After the system reset initialization, main frame at first passes through PCI configurating downlink initial address with the buffer descriptor and the buffering area Rx-BD+B initial address of first frame data.Main frame is when sending data, earlier a frame or multiframe deposit data are being sent the data buffer zone, and send to start to the command register of ethernet mac by pci bus and send order, for this reason, the method for PCI Ethernet MAC controller MAC transmission data of the present invention need be carried out the following step:
Step 100 ': after MAC detects and sends order, will notify PCI to send control module, PCI sends control module by PCI master control (Master) pattern application pci bus;
Step 200 ': obtain to initiate PCI burst read operation after the pci bus, the descending initial address that obtains according to MAC reads host side transmission buffer descriptor Tx-BD, and the initial address of preserving next buffer descriptor, under the situation that does not stop pci bus, detect the status field of this Tx-BD simultaneously, if this Tx-BD is non-NULL, then execution in step 300 ';
Step 300 ': the Frame among the Buffer of this Tx-BD+B of host side is passed through PCI burst mode transfer in the transmission first-in first-out unit Tx-FIFO of MAC;
Step 400 ': continue to read next Tx-BD, if Tx-BD does not comprise effective data frame, then stop this PCI burst operation, the rest may be inferred, shows that up to the status field of the Tx-BD that is read this transmission buffering area is for empty.
Based on as mentioned above, PCI is address self-propagation modes when the transmission data, as can be seen in the method for PCI Ethernet MAC controller transmission data of the present invention, buffer descriptor BD formation also is a loop configuration, and can receive and send a valid data frame by the present invention and only need the operation of 2 pci buss.
For reception:
1, read Rx-BD among the Rx-BD+B, and the detected state territory;
2, Rx-BD after MAC will upgrade and the Frame that receives write among the Rx-BD+B.
For transmission:
1, read Tx-BD among the Tx-BD+B, and detected state territory simultaneously, if Own=1 then continues to read Buffer, if Own=0 then finishes this pci bus operation.
2, the Tx-BD among the renewal Tx-BD+B.
In sum, method according to PCI Ethernet MAC controller transmission data of the present invention, by buffer descriptor (BD) and corresponding with it data buffer zone (Buffer) are placed on continuous address, PCI transmits and sends a valid data frame only needs 2 pci buss operations, can reduce the number of operations of pci bus, improve the utilance of PCI; Especially under the situation for the network data parcel, good effect is arranged for the efficient that improves transfer of data.
More than be in order to make those of ordinary skills understand the present invention; and to detailed description that the present invention carried out; but can expect; in the scope that does not break away from claim of the present invention and contained, can also make other variation and modification, these variations and revising all in protection scope of the present invention.
Claims (6)
1. a PCI is characterized in that with the method for big net MAC controller MAC transmission data, comprises the following steps:
Steps A: after the system reset initialization, main frame at first passes through pci bus collocating uplink initial address with the initial address of first buffer descriptor, MAC is when preparing to the host side transmit data frames, begin to read corresponding buffer descriptor by pci bus from the initial address of the current buffer descriptor formation of host side, and detect whether comprise Frame in the described buffer descriptor, if not, then initiate data writing operation to the buffering area of host side, and execution in step B; Otherwise, detect next buffer descriptor, and return steps A;
Step B: described MAC will prepare the Frame that transmits to host side with the buffer descriptor address of next frame together by pci bus write to host side in the corresponding buffer descriptor, and receive the back described buffer descriptor of sign for comprising the Frame state at these frame data;
Wherein, the buffer descriptor of described host side and the buffer descriptor among the MAC comprise: the initial address of status field, length, next buffer descriptor, and the content of current data frame.
2. the method for PCI Ethernet MAC controller MAC transmission data as claimed in claim 1, it is characterized in that, in described steps A, judge by the status field of detecting described buffer descriptor whether it comprises Frame, if the sign Own in the described status field is 1, then representing has Frame in the described buffer descriptor; If the sign Own in the described status field is 0, then representing does not have Frame in the described buffer descriptor.
3. the method for PCI Ethernet MAC controller MAC transmission data as claimed in claim 1, it is characterized in that, in described step B, described MAC prepared before the host side transmit data frames, described Frame is stored in it receives in the first-in first-out RX-FIFO module.
4. the method for PCI Ethernet MAC controller MAC transmission data is characterized in that, comprises the following steps:
Steps A ': after the system reset initialization, main frame at first passes through pci bus configurating downlink initial address with the initial address of first buffer descriptor, MAC is when preparing from the host side read data frame, begin to read corresponding buffer descriptor by pci bus from the initial address of the current buffer descriptor formation of host side, and the initial address of preserving next buffer descriptor, detect then in the current described buffer descriptor and whether comprise Frame, if, execution in step B ' then; Otherwise, then detect next buffer descriptor, and return steps A ';
Step B ': the Frame in the current buffer descriptor of host side is sent to MAC by pci bus, and receives the back described buffer descriptor of sign for not comprising the Frame state at these frame data;
Wherein, the buffer descriptor of described host side and the buffer descriptor among the MAC comprise: the initial address of status field, length, next buffer descriptor, and the content of current data frame.
5. the method for PCI Ethernet MAC controller MAC transmission data as claimed in claim 4, it is characterized in that, in described steps A ' in, judge by the status field of detecting described buffer descriptor whether it comprises Frame, if the sign Own in the described status field is 1, then representing has Frame in the described buffer descriptor; If the sign Own in the described status field is 0, then representing does not have Frame in the described buffer descriptor.
6. the method for PCI Ethernet MAC controller MAC transmission data as claimed in claim 4, it is characterized in that, in described step B ', described MAC is stored in it with described Frame and sends in the first-in first-out TX-FIFO module after the host side read data frame.
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| CN102625105A (en) * | 2012-03-27 | 2012-08-01 | 广东威创视讯科技股份有限公司 | Multi-channel video encoding and decoding data transmission method and device based on single chip |
| CN103685578B (en) * | 2014-01-08 | 2017-08-04 | 珠海全志科技股份有限公司 | The data transmission method of master-slave equipment |
| CN104199783B (en) * | 2014-09-15 | 2017-06-20 | 烽火通信科技股份有限公司 | The caching of ethernet data frame and the method and device for forwarding in FPGA |
| CN106230718A (en) * | 2016-08-03 | 2016-12-14 | 天津光电聚能专用通信设备有限公司 | Based on XilinxFPGA many kilomega networks converging system and implementation method |
| CN112115082A (en) * | 2020-09-17 | 2020-12-22 | 盛科网络（苏州）有限公司 | DMA controller and data transmission method thereof |
| CN113037604B (en) * | 2021-03-16 | 2022-09-13 | 西安微电子技术研究所 | Ethernet control system based on two-stage descriptor characterization |
| CN114564420B (en) * | 2022-01-19 | 2023-08-18 | 中国电子科技集团公司第十研究所 | Method for sharing parallel bus by multi-core processor |
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