CN100576507C - The method of adjustment of integrated circuit bipolar transistor performance and manufacture method thereof - Google Patents
The method of adjustment of integrated circuit bipolar transistor performance and manufacture method thereof Download PDFInfo
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- CN100576507C CN100576507C CN200710040981A CN200710040981A CN100576507C CN 100576507 C CN100576507 C CN 100576507C CN 200710040981 A CN200710040981 A CN 200710040981A CN 200710040981 A CN200710040981 A CN 200710040981A CN 100576507 C CN100576507 C CN 100576507C
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Abstract
The invention discloses a kind of method of adjustment and manufacture method thereof of body silicon CMOS integrated circuit bipolar transistor performance, wherein, method of adjustment comprises step: determine the bias of integrated circuit bipolar transistor performance parameter; Determine the technological parameter that the ion of doped region bottommost layer in the described integrated circuit injects according to the bias of described performance parameter; The technological parameter that injects according to described ion carries out ion to the bottommost layer of described doped region and injects and handle.Method of adjustment of the present invention and manufacture method can be under the prerequisites that does not influence the MOS device performance, adjust the performance of bipolar transistor neatly, both can be used for satisfying the different needs of integrated circuit bipolar transistor on using, also can be used for avoiding taking place in the circuit latch-up.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of method of adjustment and manufacture method thereof of body silicon CMOS integrated circuit bipolar transistor performance.
Background technology
Semiconductor fabrication process is a kind of plane manufacture craft, forms a large amount of various types of complex devices on same substrate, and it is connected to each other to have complete electric function.Along with very lagre scale integrated circuit (VLSIC) (ULSI, developing rapidly Ultra Large Scale Integration), the integrated level of chip is more and more higher, and the size of components and parts is more and more littler, is all had higher requirement in the aspects such as design, manufacturing and detection of circuit.For the overall performance that further improves integrated circuit, improve monitoring dynamics to integrated circuit technology, in integrated circuit, form bipolar transistor (can utilize usually parasitic bipolar transistor form) intrinsic in the integrated circuit and finish some circuit function, or by the parasitic bipolar transistor performance detection in the integrated circuit being realized the method for the monitoring of manufacturing process and product quality has also been obtained application more and more widely.
Exemplify the situation of a kind of parasitic bipolar transistor common in the MOS integrated circuit below.Fig. 1 is existing MOS device profile schematic diagram, as shown in Figure 1, N type well region 102 and P type well region 106 on P type substrate 101, have been formed respectively, and make respectively within it by isolation channel 1010 separated PMOS device and nmos devices, wherein, the PMOS device by N type well region 102 and on grid structure 103 and the source/leakage doped region 104,105 of P type form, nmos device by P type well region 106 and on grid 107 and the source/leakage doped region 108,109 of N type form. Bipolar transistor 110 and 120 among the figure be exactly in this cmos device intrinsic parasitic bipolar transistor.Wherein vertical positive-negative-positive bipolar transistor 110 is formed by the P type source region (connecing power supply) 104 in the PMOS device, N type well region 102 and P type substrate 101, and horizontal npn type bipolar transistor 120 is formed by the N type drain region (ground connection) 108 in the nmos device, P type well region 106 and N type well region 102.
Fig. 2 is the equivalent circuit diagram of the parasitic bipolar transistor in the MOS device shown in Figure 1, as shown in Figure 1, 2, the collector electrode of horizontal NPN transistor 120 links to each other by N type well region 102 with the base stage of vertical PNP transistor 110, and the collector electrode of vertical PNP transistor 110 links to each other by P type substrate 101 with the base stage of horizontal NPN transistor 120.Except parasitic bipolar transistor, in the MOS circuit, have dead resistance, parasitic capacitance etc. toward contact, only show the dead resistance 201 of P type substrate and the dead resistance 202 of N type well region among Fig. 2.
In the practical application, often utilize the parasitic bipolar transistor in the above-mentioned MOS integrated circuit to form the bipolar transistor that can realize certain function, it is advantageous that:
1, technology is simple, and normal MOS technology can form parasitic bipolar transistor in its circuit: the doping content of N trap is generally 1 * 10 in the MOS technology
17Cm
-3, suitable with the collector electrode requirement of bipolar transistor, in addition, the shallow junction heavy doping characteristics in source/drain region also help forming the bipolar transistor emitter region of low-resistance in the device;
2, the space of a whole page that takies is long-pending less, power consumption is lower and it is simple and convenient to realize.
Notice when parasitic bipolar transistor in utilizing circuit is realized certain function, tend to its performance is proposed different requirements.
Except being used for realizing certain circuit function, another reason that integrated circuit bipolar transistor receives much concern is the latch-up that it may cause circuit.Latch-up can cause the electric current in the circuit to roll up suddenly, even increases to the degree that is enough to the fuse metal interconnection line, and it is one of problem very important in the ic manufacturing process.The reason that latch-up occurs can be by finding out in the equivalent circuit diagram shown in Figure 2: the parasitic bipolar transistor 110 and 120 in the MOS circuit has formed an inverter, through voltage spike or certain transition the time, this inverter just may form positive feedback, electric current in the circuit is rolled up, thereby cause latch-up.
For avoiding causing because of parasitic bipolar transistor the generation of latch-up, the notification number of Granted publication on the 15th is that the Chinese patent of CN1167132C discloses a kind of method of utilizing electrostatic protection device to suppress the latch-up of parasitic bipolar transistor in September, 2004.This method has effectively prevented the snap back of parasitic bipolar transistor by add resistance and power supply between the source of nmos device (leakage) utmost point and ground signalling, has suppressed the latch-up that causes because of parasitic bipolar transistor in the MOS circuit.But this method more complicated realize comparatively difficulty, and flexibility ratio is also not enough, can not be applicable to various application.Still wish and to avoid the generation of latch-up only by adjusting the performance (as reducing transistorized gain) of integrated circuit endoparasitism bipolar transistor.
The difference that in integrated circuit, acts on along with bipolar transistor, also inequality to its performance demands, at this moment, hope can have a kind of process can realize adjustment to integrated circuit bipolar transistor (comprising parasitic bipolar transistor) performance, with the generation that makes it satisfy needs of using or avoid latch-up effectively.But, in the existing integrated circuits manufacture method, the performance that changes the bipolar transistor in the integrated circuit will inevitably cause the performance change of corresponding M OS device, promptly can not be implemented under the situation of taking into account the performance of MOS device in the integrated circuit, the adjustment of bipolar transistor (comprising parasitic bipolar transistor) performance.
Summary of the invention
The invention provides a kind of method of adjustment and manufacture method thereof of integrated circuit bipolar transistor performance, can under the situation of taking into account the MOS device performance, in ic manufacturing process, realize adjustment to bipolar transistor (comprising parasitic bipolar transistor) performance.
The invention provides a kind of method of adjustment of integrated circuit bipolar transistor performance, comprise step:
Determine the bias of integrated circuit bipolar transistor performance parameter;
Determine the technological parameter that the ion of doped region bottommost layer in the described integrated circuit injects according to the bias of described performance parameter;
The technological parameter that injects according to described ion carries out ion injection processing to described doped region bottommost layer.
Wherein, described performance parameter is the gain of bipolar transistor.
If described doped region refers to well region, determine that the technological parameter of the ion injection of doped region bottommost layer in the integrated circuit comprises step:
When the required bias of described bipolar transistor gain is negative value, increase the ion implantation energy and/or the dosage of described well region bottommost layer;
When the required bias of described bipolar transistor gain be on the occasion of the time, reduce the ion implantation energy and/or the dosage of described well region bottommost layer.
If described doped region refers to source/drain region, determine that the technological parameter of the ion injection of doped region bottommost layer in the integrated circuit comprises step:
When the required bias of described bipolar transistor gain is negative value, reduce the ion implantation energy and/or the dosage of described source/drain region bottommost layer;
When the required bias of described bipolar transistor gain be on the occasion of the time, increase the ion implantation energy and/or the dosage of described source/drain region bottommost layer.
If described doped region refers to well region and source/drain region, determine that the technological parameter of the ion injection of doped region bottommost layer in the integrated circuit comprises step:
When the required bias of described bipolar transistor gain is negative value, increases the ion implantation energy and/or the dosage of described well region bottommost layer, and/or reduce the ion implantation energy and/or the dosage of described source/drain region bottommost layer;
When the required bias of described bipolar transistor gain be on the occasion of the time, reduce the ion implantation energy and/or the dosage of described well region bottommost layer, and/or increase the ion implantation energy and/or the dosage of described source/drain region bottommost layer.
In addition, the bipolar transistor in the described integrated circuit is included in the parasitic bipolar transistor that forms in the integrated circuit.
The present invention has the manufacture method of a kind of integrated circuit of identical or relevant art feature, comprises step:
Determine the required performance parameter that reaches of integrated circuit bipolar transistor;
Determine the technological parameter that the ion of doped region bottommost layer in the described integrated circuit injects according to described performance parameter;
The technological parameter that injects according to described ion carries out ion injection processing, forms the described doped region bottommost layer in the described integrated circuit.
Wherein, described doped region comprises in well region, the source/drain region one at least.
Compared with prior art, the present invention has the following advantages:
The method of adjustment of integrated circuit bipolar transistor performance provided by the invention and manufacture method thereof, according to specific requirement (or bias) to integrated circuit bipolar transistor (comprising parasitic bipolar transistor) performance, ion implantation technology parameter to the doped region bottommost layer is set in the integrated circuit fabrication process, it is little for the influence of the MOS device in the integrated circuit that the ion of this part injects situation, but can effectively change each performance parameter of corresponding bipolar transistor, as gain, cut-in voltage etc.Method of adjustment of the present invention has been taken all factors into consideration the MOS device in the integrated circuit and the performance requirement of bipolar transistor, can be under the prerequisite that does not influence the MOS device performance, adjust the performance of bipolar transistor neatly, both can be used for satisfying the different needs that it is used, also can be used for avoiding the generation of latch-up.
The method of adjustment of integrated circuit bipolar transistor performance provided by the invention and manufacture method thereof, can pass through adjustment realization to the doping situation of well region or source/drain region bottommost layer, and the adjustment trend in two zones is just in time opposite, both can adjust separately arbitrary zone wherein, also the adjustment in two zones can be combined and carry out, so more can guarantee taking into account the performance requirement of MOS device in the integrated circuit and bipolar transistor.
Description of drawings
Fig. 1 is existing MOS device profile schematic diagram;
Fig. 2 is the equivalent circuit diagram of the parasitic bipolar transistor in the MOS device shown in Figure 1;
Fig. 3 is the device profile schematic diagram of well region situation in the explanation PMOS device of the present invention;
Fig. 4 is the schematic diagram of the gain of explanation parasitic bipolar transistor with the ion implantation dosage variation of N type well region;
Fig. 5 is the device profile schematic diagram of source/drain region situation in the explanation PMOS device of the present invention;
Fig. 6 is the schematic diagram of the gain of explanation parasitic bipolar transistor with the ion implantation dosage variation in P type source/drain region;
Fig. 7 is the schematic diagram of the gain of explanation parasitic bipolar transistor with the ion implantation energy variation in P type source/drain region;
Fig. 8 is the flow chart of the method for adjustment of integrated circuit bipolar transistor performance of the present invention;
Fig. 9 is the flow chart of method for manufacturing integrated circuit of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Processing method of the present invention can be applied to various occasions; and can utilize many suitable material; be to be illustrated below by preferred embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.
Secondly, the present invention utilizes schematic diagram to describe in detail, when the embodiment of the invention is described in detail in detail, for convenience of explanation, the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, should be with this as limitation of the invention, in addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
Doped region described in the presents be meant the well region that in integrated circuit, forms and in source/drain region any or a plurality of.
Realize at first will understanding the influence which factor is its performance parameter can be subjected to the adjustment or the change of the performance parameter of the bipolar transistor in the integrated circuit.Gain with bipolar transistor is that example describes below.
After bipolar transistor can be realized the minor variations of input electric current amplified, the electric current big in output output changed, between this output and input current ratio (beta) just be defined as the gain (β) of bipolar transistor.The formula of gain can be expressed as:
Wherein, D
BAnd D
EBe the diffusivity of minority carrier in base and the emitter region, N
BAnd N
EBe respectively doping content in base and the emitter region, L
EBe minority carrier characteristic diffusion length in the emitter region, W is a base length.As can be seen from the above equation, change bipolar transistor eaily method be the doping content that changes its emitter region or base.But, for parasitic bipolar crystal intrinsic in the MOS circuit, its base, emitter region and collector region and MOS device are shared, as seeing by Fig. 1: the base correspondence of parasitic bipolar transistor be the N type well region of PMOS device, the emitter region correspondence of parasitic bipolar transistor be P type source/drain region, the collector region correspondence of parasitic bipolar transistor be P type substrate.Therefore, if direct doping situation to each district changes for the performance that changes the parasitic bipolar transistor in the integrated circuit, will inevitably cause the performance parameter of MOS device that corresponding change takes place, this is worthless.The present invention is by the concrete analysis to each step process in the integrated circuit, determined that a kind of one side can carry out flexible adjustment to the performance parameter of the bipolar transistor in the integrated circuit (as gain), again the performance parameter of MOS device has not been had the technology method of adjustment of big influence on the other hand.
Usually when forming well region, carrying out twice above ion to I haven't seen you for ages injects, and the energy that each ion injects is all inequality, the well region that the result forms is actual can be divided into multilayer, and Fig. 3 is the device profile schematic diagram of well region situation in the explanation PMOS device of the present invention, as shown in Figure 3, in the present embodiment, the ion of well region injects and divides for three times, because of the energy difference of three injections, the degree of depth difference that it forms in substrate.Repeatedly ion injects, and injects the bottommost layer 301 that has once formed well region in substrate of energy maximum, and energy is once placed in the middle, has formed the intermediate layer 302 of well region, and the energy minimum has once formed the upper strata 303 of well region.
Can be drawn by formula listed earlier, the gain of adjusting parasitic bipolar transistor can realize by the doping content of adjusting its emitter region (the P type source/drain region of PMOS device) and base (the N type well region of PMOS device).For the gain to parasitic bipolar transistor under the situation that does not influence the MOS device performance is adjusted, at first each layer of well region doping situation has been carried out experimental analysis to the influence of MOS device and parasitic bipolar transistor, discovery is when changing the doping situation of well region bottommost layer 301, can obviously change the performance of parasitic bipolar transistor, simultaneously, but very little to the influence of MOS device.
Fig. 4 is the schematic diagram of the gain of explanation parasitic bipolar transistor with the ion implantation dosage variation of N type well region, as shown in Figure 4, abscissa is the ion implantation dosage of the N type well region bottommost layer in the PMOS device, and ordinate is the yield value of parasitic bipolar transistor, and 401 is each data point among the figure.Can see that when the ion implantation dosage of well region bottommost layer increased, the gain of parasitic bipolar transistor reduced thereupon.
In addition, similar analysis has also been done in emitter region (the P type source/drain region of PMOS device) for parasitic bipolar transistor, Fig. 5 is the device profile schematic diagram of source/drain region situation in the explanation PMOS device of the present invention, as shown in Figure 5, in the MOS device manufacturing processes, source/the drain region that has can divide several steps to form: the formation of lightly doped drain (LDD, Light-Doped Drain) 503,513, the formation of the formation of source, upper strata/leakage doped layer 502,512 and bottommost layer source/leakage doped layer 501,511.More than each layer when forming, the energy that ion injects also increases successively, the degree of depth of formation is also more and more darker.Carrying out after the experimental analysis to source/drain region each layer doping situation to the influence of MOS device and parasitic bipolar transistor, discovery in the change source/during the doping situation of drain region bottommost layer 501,511, can when obviously changing the parasitic bipolar transistor performance, keep little influence equally to the MOS device performance.
Fig. 6 is the schematic diagram of the gain of explanation parasitic bipolar transistor with the ion implantation dosage variation in P type source/drain region, as shown in Figure 6, abscissa is the ion implantation dosage of P type source/drain region bottommost layer, and ordinate is the yield value of parasitic bipolar transistor, and 601 is each data point among the figure.Can see that when P type source/drain region bottommost layer ion implantation dosage increased, the gain of parasitic bipolar transistor increased thereupon.
Implantation dosage when injecting except the ion that changes above each doped region bottommost layer can cause that the gain of parasitic bipolar transistor changes, the injection energy that changes the ion injection of each doped region bottommost layer equally also can cause the variation of parasitic bipolar transistor gain.
Fig. 7 is the schematic diagram of the gain of explanation parasitic bipolar transistor with the ion implantation energy variation in P type source/drain region, as shown in Figure 7, abscissa is the ion implantation energy in P type source/drain region, and ordinate is the yield value of parasitic bipolar transistor, and 701 is each data point among the figure.Can see that when P type source/drain region bottommost layer ion implantation energy increased, the gain of parasitic bipolar transistor equally also can increase thereupon.
Confirmed that more than ion implanting conditions (doping situation) to the bottommost layer of each doped region in the integrated circuit (comprising well region and source/drain region) is when changing, significant change also can take place in the gain of the parasitic bipolar transistor in it thereupon, but needs also to prove that the change of ion implanting conditions of bottommost layer of each doped region is little to the performance impact of PMOS device.Table 1 is the device parameters tabulation under the different technology conditions, the device of wherein having listed large and small size respectively each performance parameter when the injection energy of employing standard, the implantation dosage that reduces the well region bottommost layer and raising source/drain region bottommost layer and three kinds of process conditions of dosage are made.
Device parameters tabulation under table 1 different technology conditions
Can see, changed the ion implanting conditions of each doped region bottommost layer after, the change in gain amount of integrated circuit endoparasitism bipolar transistor is quite obvious.Simultaneously, though variation has taken place the situation of the doping of each doped region, no matter be for large scale or undersized MOS device, this variation is but also little to the influence of each performance parameter of MOS device.Utilize this characteristics, promptly can be implemented under the prerequisite that does not influence the MOS device performance, to the adjustment flexibly of the bipolar transistor in the circuit (perhaps parasitic bipolar transistor) performance, satisfying integrated circuit bipolar transistor, or avoid the generation of latch-up at the different needs of using.
Fig. 8 is the flow chart of the method for adjustment of integrated circuit bipolar transistor performance of the present invention, how be example with the PMOS device below describes in detail under the prerequisite that does not influence the PMOS device performance in conjunction with Fig. 8, realizes adjustment to the performance of the bipolar transistor in it (comprising parasitic bipolar transistor) by the manufacturing process of adjusting integrated circuit.
At first, determine the bias (S801) of integrated circuit bipolar transistor performance parameter.The performance parameter of the bipolar transistor of difference in functionality requires different in the integrated circuit, (as the requirement of finishing the bipolar transistor of certain function and parasitic bipolar transistor is just inequality, the former may require certain gain, the latter then wishes to gain the smaller the better), therefore, different products may be different to its performance requirement, usually a kind of standard technology flow process and process conditions can be set aborning, the performance parameter of the bipolar transistor in the integrated circuit that produces under this kind technology is determined, if when turning out a produce, the performance of the bipolar transistor in it has been proposed to be different from the requirement of standard technology, just need make amendment to process conditions according to its concrete performance requirement.Before formal the production, determine bias between performance parameter that performance parameter that its needs reach and standard technology reached according to its concrete effect or client's specific requirement earlier, and concrete fabrication process condition is adjusted at this bias.What need in the present embodiment to adjust is the gain of integrated circuit endoparasitism bipolar transistor, for avoid the generation of latch-up as far as possible, wishes that its yield value is the smaller the better.As the gain of the parasitic bipolar transistor in the integrated circuit that requires in the present embodiment to produce between 0.5-0.6.
After the bias of the performance parameter of determining it, determine the technological parameter (S802) that the ion of doped region bottommost layer in the described integrated circuit injects according to this bias.Parasitic bipolar transistor gain under the tentative standard technology is between 1.0-1.1, and in the present embodiment because need further to reduce the probability of latch-up, requirement is this yield value will be limited between the 0.5-0.6, at this moment, need utilize method of the present invention corresponding technological conditions to be changed according to the bias of the performance parameter of concrete bipolar transistor.
In the present embodiment, be to realize the adjustment of the performance parameter of the bipolar transistor in the integrated circuit by the ion implanting conditions that changes the well region bottommost layer, the rule of its adjustment is: when the bias of the gain of the bipolar transistor in the integrated circuit is negative value (showing needs to reduce), increase the ion implantation energy and/or the dosage of described well region bottommost layer; When the bias of bipolar transistor gain on the occasion of the time (showing needs to improve), reduce the ion implantation energy and/or the dosage of described well region bottommost layer.In present embodiment, the yield value of bipolar transistor need reduce about 0.5, so the ion implantation dosage of well region bottommost layer in the standard technology further can be improved, as can be by original 1 * 10
13/ cm
2Be increased to 4 * 10
13/ cm
2, as shown in Figure 4, this moment, the yield value of bipolar transistor can drop between the 0.5-0.6, had satisfied requirement.
In another embodiment of the present invention, can also adjust the performance parameter of bipolar transistor by the ion implanting conditions of change source/drain region bottommost layer, the rule of its adjustment is: when the bias of the gain of the bipolar transistor in the integrated circuit is negative value (showing needs to reduce), reduce the ion implantation energy and/or the dosage of described source/drain region bottommost layer; When the bias of described bipolar transistor gain on the occasion of the time (showing needs to improve), increase the ion implantation energy and/or the dosage of described source/drain region bottommost layer.In this embodiment, the deviation value of the yield value of bipolar transistor is about-0.5, so the ion implantation dosage of source in the standard technology/drain region bottommost layer can be reduced, as can be by original 7 * 10
14/ cm
2Be reduced to 1 * 10
14/ cm
2, can drop to the yield value of bipolar transistor between the 0.5-0.6 this moment.In addition, also the ion implantation energy of source in the standard technology/drain region bottommost layer can be reduced, as being reduced to 5Kev by the injection energy of original 20Kev, can drop to the yield value of bipolar transistor between the 0.5-0.6 this moment equally.
In another embodiment more of the present invention, the ion implanting conditions of bottommost layer that can also be by changing well region and source/drain region is simultaneously adjusted the performance parameter of bipolar transistor, the rule of its adjustment is: when the bias of the gain of the bipolar transistor in the integrated circuit is negative value (showing needs to reduce), increase the ion implantation energy and/or the dosage of described well region bottommost layer, and/or reduce the ion implantation energy and/or the dosage of described source/drain region bottommost layer; When the bias of bipolar transistor gain on the occasion of the time (showing needs to improve), reduce the ion implantation energy and/or the dosage of described well region bottommost layer, and/or increase the ion implantation energy and/or the dosage of described source/drain region bottommost layer.In this embodiment, the yield value of bipolar transistor is a negative value, can select simultaneously the ion implantation dosage (and/or degree of depth) of the well region bottommost layer in the standard technology is improved, and the ion implantation dosage (and/or energy) of source/drain region bottommost layer reduced, as being increased to 2 * 10 by ion implantation dosage with the well region bottommost layer
13/ cm
2, the ion implantation dosage of source/drain region bottommost layer is reduced to 5 * 10
14/ cm
2, the ion implantation energy of source/drain region bottommost layer is reduced to 10Kev, equally also the yield value of bipolar transistor can be dropped between the 0.5-0.6.
At this moment, adjust the performance of bipolar transistor because utilized the change of the ion implanting conditions of well region and source/drain region bottommost layer among this embodiment simultaneously, its adjustment scheme is more flexible and changeable, can guarantee that more the present invention has taken into account the performance requirement of MOS device and the performance requirement of bipolar transistor in the integrated circuit to the adjustment of technological parameter.
After determining technological parameter, the technological parameter that injects according to the ion of having determined carries out ion to the bottommost layer of described doped region and injects and handle (S803) again, bipolar transistor that so just can the formation performance meets the demands in integrated circuit under the prerequisite that does not influence the MOS device performance.
The foregoing description describes the adjustment to bipolar transistor performance in the PMOS device in detail, the adjustment of the performance of the bipolar transistor in connecting for nmos device or circuit, said method is suitable equally, the step of its enforcement is similar to the above embodiments, the extension of this application is easy to understand and realization for those of ordinary skills, does not repeat them here.
The foregoing description is by the doped region in the PMOS device (is comprised well region and source/drain region, or in the two any) energy that injects of the ion of bottommost layer and/or the adjustment of dosage, realization is to the adjustment of the gain performance of the bipolar transistor in the integrated circuit, can also utilize identical method that other performance parameters of bipolar transistor are adjusted in other embodiments of the invention, as cut-in voltage, operating current etc., concrete set-up procedure is similar to the above embodiments, after being subjected to the enlightenment of method of adjustment of the present invention, the ordinary skill of this area does not repeat them here for the member should be easy to derive.
Notice in the ic manufacturing process, performance parameter to the parasitic bipolar transistor in the circuit also detects through regular meeting: first, because the parasitic bipolar transistor changes of performance parameters in the integrated circuit may cause device latch-up etc. to occur, device reliability is descended, should keep the performance parameter of the parasitic bipolar transistor in the integrated circuit stable and meet certain requirements aborning as far as possible; Second, it can find the problem that some exist early in MOS technology is made, go wrong as the doping situation when the doped region bottommost layer, when having departed from normal value, general whole survey method may be difficult for measuring, and then can by the detection to the performance parameter of parasitic bipolar transistor.
Therefore, remove in the foregoing description and utilize the requirement of method of the present invention according to physical circuit, outside the situation that the performance of the bipolar transistor in the integrated circuit is adjusted, in other embodiments of the invention, the performance parameter actual value of the bipolar transistor in the device that can also obtain according to detection and the departure between predicted value, the problem that may occur in the analysing integrated circuits manufacture process.If the performance parameter of MOS device is normal, then can behind the technological parameter that redefines the injection of doped region bottommost layer ion, produce again, the performance of the parasitic bipolar transistor that performance in the circuit is departed from adjusts, the performance parameter that makes it near or equal predicted value.At this moment, method of the present invention can be suitable for equally, and the step of its enforcement is similar to the above embodiments, and the extension of this application is easy to understand and realization for those of ordinary skills equally, does not repeat them here.
Except utilizing method of adjustment of the present invention adjusts the performance of integrated circuit bipolar transistor, utilize manufacture method of the present invention can also be easily and flexibly to make integrated circuit according to requirement to the performance parameter of integrated circuit bipolar transistor.Fig. 9 is the flow chart of method for manufacturing integrated circuit of the present invention, below in conjunction with Fig. 9 method for manufacturing integrated circuit of the present invention is described in detail:
At first, determine the required performance parameter that reaches of integrated circuit bipolar transistor (S901).
Then, determine the technological parameter (S902) that the ion of doped region bottommost layer in the integrated circuit injects according to described performance parameter.Through experiment repeatedly or produce, the doping condition of pairing doped region bottommost layer when the different performance that can determine integrated circuit bipolar transistor requires.Therefore, when carrying out production, can realize directly determining the technological parameter that the ion of doped region (comprising in well region and the source/drain region at least) bottommost layer injects according to the concrete performance requirement of bipolar transistor.When the gain of the bipolar transistor in requiring the PMOS device is between 0.5-0.6, can be directly be set to 4 * 10 according to the ion implantation dosage of Fig. 4 N type well region
13/ cm
2
Follow again, at least a slice substrate is provided, carry out technological operations such as photoetching, etching, film growth, ion injection thereon respectively, to form structures such as isolation channel in the integrated circuit, well region, grid, source/drain region within it, wherein need be during the bottommost layer of the described doped region in forming integrated circuit according to S902 in the technological parameter that injects of determined ion carry out ion and inject and handle (S903).
The method of adjustment of integrated circuit bipolar transistor performance of the present invention and manufacture method thereof not only can be used for satisfying the different needs of integrated circuit bipolar transistor on using, also can be used for avoiding latch-up takes place in the circuit, can also be used to monitoring and normally the carrying out of adjusting process.Notice; so long as by adjusting the doping situation of the bottommost layer of doped region in the integrated circuit; be implemented under the little prerequisite of MOS device performance influence, to the adjustment of the performance of the bipolar transistor in the integrated circuit (comprising parasitic bipolar transistor), all should belong to protection scope of the present invention.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (9)
1, a kind of method of adjustment of integrated circuit bipolar transistor performance is characterized in that, comprises step:
Determine the bias of the gain of the entozoic bipolar transistor of MOS integrated circuit;
Determine the technological parameter that the ion of doped region bottommost layer in the described MOS integrated circuit injects according to the bias of described gain;
The technological parameter that injects according to described ion carries out ion injection processing to described doped region bottommost layer;
Wherein said doped region comprises in well region, source area and the drain region at least.
2, method of adjustment as claimed in claim 1 is characterized in that, determines that the technological parameter of the ion injection of doped region bottommost layer in the integrated circuit comprises step:
When the required bias of described bipolar transistor gain is negative value, increase the ion implantation energy and/or the dosage of described well region bottommost layer;
When the required bias of described bipolar transistor gain be on the occasion of the time, reduce the ion implantation energy and/or the dosage of described well region bottommost layer.
3, method of adjustment as claimed in claim 1 is characterized in that, determines that the technological parameter of the ion injection of doped region bottommost layer in the integrated circuit comprises step:
When the required bias of described bipolar transistor gain is negative value, reduce the ion implantation energy and/or the dosage of described source/drain region bottommost layer;
When the required bias of described bipolar transistor gain be on the occasion of the time, increase the ion implantation energy and/or the dosage of described source/drain region bottommost layer.
4, method of adjustment as claimed in claim 1 is characterized in that, determines that the technological parameter of the ion injection of doped region bottommost layer in the integrated circuit comprises step:
When the required bias of described bipolar transistor gain is negative value, increases the ion implantation energy and/or the dosage of described well region bottommost layer, and/or reduce the ion implantation energy and/or the dosage of described source/drain region bottommost layer;
When the required bias of described bipolar transistor gain be on the occasion of the time, reduce the ion implantation energy and/or the dosage of described well region bottommost layer, and/or increase the ion implantation energy and/or the dosage of described source/drain region bottommost layer.
5, method of adjustment as claimed in claim 1 is characterized in that: described source area comprises the bottommost layer source area doped layer of the upper strata source area doped layer of lightly doped drain, described lightly doped drain lower floor, described upper strata source area doped layer lower floor.
6, method of adjustment as claimed in claim 1 is characterized in that: described drain region comprises lightly doped drain, drain region, the upper strata doped layer of described lightly doped drain lower floor, the bottommost layer drain region doped layer of drain region, described upper strata doped layer lower floor.
7, a kind of manufacture method of integrated circuit is characterized in that, comprises step:
Determine the required gain that reaches of the entozoic bipolar transistor of MOS integrated circuit;
Determine the technological parameter that the ion of doped region bottommost layer in the described MOS integrated circuit injects according to described gain;
The technological parameter that injects according to described ion carries out ion injection processing, forms the described doped region bottommost layer in the described MOS integrated circuit;
Wherein said doped region comprises in well region, source area and the drain region at least.
8, manufacture method as claimed in claim 7 is characterized in that: described source area comprises the bottommost layer source area doped layer of the upper strata source area doped layer of lightly doped drain, described lightly doped drain lower floor, described upper strata source area doped layer lower floor.
9, manufacture method as claimed in claim 7 is characterized in that: described drain region comprises lightly doped drain, drain region, the upper strata doped layer of described lightly doped drain lower floor, the bottommost layer drain region doped layer of drain region, described upper strata doped layer lower floor.
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