CN100576506C - The manufacturing design method of integrated circuit - Google Patents
The manufacturing design method of integrated circuit Download PDFInfo
- Publication number
- CN100576506C CN100576506C CN200610029907A CN200610029907A CN100576506C CN 100576506 C CN100576506 C CN 100576506C CN 200610029907 A CN200610029907 A CN 200610029907A CN 200610029907 A CN200610029907 A CN 200610029907A CN 100576506 C CN100576506 C CN 100576506C
- Authority
- CN
- China
- Prior art keywords
- density
- pattern density
- pattern
- graph area
- subregion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
A kind of manufacturing design method of integrated circuit comprises: the initial designs figure is carried out density calculation, and described density comprises local density and global density; Extract pattern density; Adjust pattern density to targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density; Determine manufacturability pattern density criterion according to described targeted graphical density; Improve initial designs according to described manufacturability pattern density criterion.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacturing design method of integrated circuit.
Background technology
The continuous micro of integrated circuit (IC) process technique, especially after 0.13 micron system, the live width of silicon processing procedure is all less than the wavelength length of exposing, make that the control of stability of processing procedure is day by day difficult, spin-off effects on many processing procedures is not fully considered when previous design, the lack of resolution that is processing procedure accurately is transformed on the wafer with the geometric figure that IC engineer is designed, design work simple before making can't be continued to accept, thus, must repetitiousness synthesize and the work of placement-and-routing, and can postpone the deadline and cause waste on the cost certainly like this.
At these geometric figures behind etch process, occur " design of manufacturability guiding " that the situation of distortion produces (Design For Manufacturability, DFM), at the theme that is beginning to become the IC design over nearly, two year.DFM or yield guiding design (Design for Yield, DFY), be exactly in brief IC is accomplished to the various effects (Effects) that manufacture process institute may take place by design and makes a variation (Variation) and the prior in addition careful analyzing and testing of influence to the IC function by the processing procedure personnel, and the designer contains in design process into these information reference amounts, so that designed IC has better tolerance (tolerance) to reach the easier high yield that has to process variation.
Thus, present design engineer in work except considering the problem of logical designs such as the leading portion logic is synthetic, wiring, also must solve process stage such as photoetching in the actual production, etching and produce measurable or uncertain puzzlement, promptly adding manufacturability after traditional design detects, make and in design, can adopt the most accurate electrical parameter model, to solve actual critical dimension and former layout deviation and processing procedure defect problem.
In actual processing procedure, accurately Control Critical size and minimizing glossing generation of defects are made IC and are very important, studies show that, critical dimension variations and glossing generation of defects depend on the pattern density of each layer pattern significantly, and this pattern density is defined as the area ratio of graph area and non-graph area; Thus, pattern density how to control each layer pattern becomes those skilled in the art's problem demanding prompt solution with the manufacturability that improves design.
The patent No. provides a kind of grid layer fill method that reduces pattern density in the Chinese patent application of " 00806056.8 ", this method obtains targeted graphical density by changing the pattern filling size, but when not being provided, no pattern filling how to obtain targeted graphical density, thus, be badly in need of a kind of the utilization and have the manufacturing design method that pattern density directly obtains the integrated circuit of targeted graphical density now.
Summary of the invention
The invention provides a kind of manufacturing design method of integrated circuit, can pass through the controlling Design pattern density, strengthen the manufacturability of product.
The manufacturing design method of a kind of integrated circuit provided by the invention comprises:
The initial designs figure is carried out density calculation, and described density comprises local density and global density;
Extract pattern density;
Adjust pattern density to targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density;
Determine manufacturability pattern density criterion according to described targeted graphical density;
Improve initial designs according to described manufacturability pattern density criterion.
The specific region size range that need choose during described calculating local density is 0.25 micron
2～2500 microns
2Have the overlapping region between described adjacent specific region, and the border of arbitrary specific region overlaps with the center of adjacent specific region;
Described adjustment pattern density to the method for targeted graphical density comprises:
The initial designs figure is pressed the density value subregion;
A predetermined pattern density;
Adjust the interior pattern density of different subregions to described predetermined pattern density;
The analog equipment characteristic parameter and the actual product of the described pattern density of correspondence are required to compare;
If described analog equipment characteristic parameter satisfies the actual product requirement, then described pattern density can be defined as the localized target pattern density, and then, the chip with described even localized target pattern density is carried out global density calculate, described density value is decided to be the overall goals pattern density;
Otherwise, predetermined next pattern density;
Repeat described contrast, determining step, until drawing targeted graphical density.
Described predetermined pattern density range is 1%～30%; Described analog equipment characteristic parameter comprises optical transmission speed, maximum/minimum local density, maximum/minimum global density, chip performance parameter and chip yield statistics etc.;
Described adjustment pattern density to the method for predetermined pattern density comprises:
Described initial designs figure is pressed the density value subregion, and described subregion comprises graph area and non-graph area;
In described subregion graph area, form hole; The described hole place is full of the medium that differs from the graph area material.
Described adjustment pattern density to the method for predetermined pattern density comprises:
Described initial designs figure is pressed the density value subregion, and described subregion comprises graph area and non-graph area;
In the non-graph area of described subregion, make pattern filling.
Described manufacturability pattern density criterion be described localized target pattern density less than 50%, described overall goals pattern density is less than 30%.
The method of a kind of definite manufacturability pattern density criterion provided by the invention comprises:
The initial designs figure is pressed the density value subregion;
A predetermined pattern density;
Adjust the interior pattern density of different subregions to described predetermined pattern density;
The analog equipment characteristic parameter and the actual product of the described pattern density of correspondence are required to compare;
If described analog equipment characteristic parameter satisfies the actual product requirement, then described pattern density can be defined as the localized target pattern density, and then, the chip with described even localized target pattern density is carried out global density calculate, described density value is decided to be the overall goals pattern density;
Otherwise, predetermined next pattern density;
Repeat described contrast, determining step, draw targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density;
Determine manufacturability pattern density criterion according to described targeted graphical density.
Described predetermined pattern density value scope is 1%～30%; Described analog equipment characteristic parameter comprises optical transmission speed, maximum/minimum local density, maximum/minimum global density, chip performance parameter and chip yield statistics etc.
Pattern density in the different subregions of described adjustment to the method for described predetermined pattern density comprises:
Described initial designs figure is pressed the density value subregion, and described subregion comprises graph area and non-graph area;
In described subregion graph area, form hole; The described hole place is full of the medium that differs from the graph area material.
Pattern density in the different subregions of described adjustment to the method for described predetermined pattern density comprises:
Described initial designs figure is pressed the density value subregion, and described subregion comprises graph area and non-graph area;
In the non-graph area of described subregion, make pattern filling.
A kind of method that changes existing pattern density with acquisition targeted graphical density provided by the invention comprises:
The initial designs figure is carried out density calculation;
Extract pattern density;
Determine targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density;
Described initial designs figure is pressed the density value subregion, and described subregion comprises graph area and non-graph area;
Adjust pattern density acquisition localized target pattern density in each subregion;
Obtain the overall goals pattern density according to the localized target pattern density.
Pattern density obtains the method for localized target pattern density for form hole in described subregion graph area in each subregion of described adjustment; The described hole place is full of the medium that differs from the graph area material; Pattern density obtains the method for localized target pattern density for to make pattern filling in the non-graph area of described subregion in each subregion of described adjustment.
Compared with prior art, the present invention has the following advantages:
1. by the controlling Design pattern density, promptly controlling Design graphics sub density is less than 50%, global density is less than 30%, and it is inhomogeneous and grind the generation of defective etc. to have reduced characteristic size, has strengthened the manufacturability of product, has reduced production cost simultaneously;
2. employing the inventive method by form hole in the high density graph district, is filled dummy electrodes in the low-density graph area, can utilize existing pattern density directly to obtain targeted graphical density;
3. by the controlling Design pattern density, in the manufacturability that strengthens product, can shorten the trial production of new products time, and reduce R﹠D costs.
Description of drawings
Fig. 1 is the initial designs schematic diagram of the explanation embodiment of the invention;
Fig. 2 is the initial designs figure subregion schematic diagram of the explanation embodiment of the invention;
Fig. 3 A～3B is the first pattern density improved procedure schematic diagram of the explanation embodiment of the invention;
Fig. 4 is the second graph density mode schematic diagram of the explanation embodiment of the invention;
Wherein: same section indicates with same label;
10: the initial designs figure; 20: non-graph area;
30: graph area; 40: high pattern density zone;
50: the targeted graphical density area; 60: low pattern density zone;
70: hole; 80: filled media;
90: pattern filling.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The inventive method is applicable to the design of the random layer in the ic manufacturing process, comprising: grid layer, diffusion layer and metal level etc., for avoiding causing unnecessary beyonding one's depth, well-known circuit, system and technological operation are not described.
Adopt the idiographic flow of the inventive method to be: at first, the initial designs figure is carried out density calculation, described density comprises local density and global density; Then, extract pattern density, adjust pattern density then to targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density; And then determine manufacturability pattern density criterion according to described targeted graphical density; At last, improve initial designs according to described manufacturability pattern density criterion.
At first, carry out initial designs, and described initial designs figure is carried out density calculation by former designing requirement.
Fig. 1 is the initial designs schematic diagram of the explanation embodiment of the invention, and as shown in Figure 1, described initial designs figure 10 comprises graph area 30 and non-graph area 20; Described density is the area ratio of graph area 30 and non-graph area 20 in the selection area; Described selection area can be the interior arbitrary region of chip (die).Space or position in term " area " the expression design configuration, and can exchange with term " zone ".
Described density comprises local density and global density; Described local figure density is the area ratio of graph area and non-graph area in the specific region; Described whole pattern density is the area ratio of graph area and non-graph area in the chip range; The selection of described specific region size is relevant with process nodes; As embodiments of the invention, process nodes is elected 90 nanometers as, and described specific region is a square region; Described specific region size range is elected 0.25 micron as
2～2500 microns
2Arbitrary region in the chip can be contained in described specific region.
Really; being chosen as of described specific region size and shape is convenient to the special selection that illustrates that the embodiment of the invention is made; should be as qualification to protection range, any change that those skilled in the art make this all should be included in the present invention's scope required for protection.
Be the local density in any specific zone in the accurate Calculation chip, need choose described each specific region in proper order, make between adjacent specific region to have the overlapping region, and the border of arbitrary specific region overlaps with the center of adjacent specific region; So, can avoid in the chip periphery circuit, producing defective.Described density calculation can repeat according to actual needs.
Then, extract pattern density, and adjust pattern density to determine targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density, and then definite manufacturability pattern density criterion.
According to the density calculation result, extract pattern density, and the initial designs figure is divided into plurality of regions by density value, as: in the first area density range be 0～10%, in the second area density range be 10%～20% ... the rest may be inferred, obtains a plurality of initial designs figure subregions with different densities scope.
Really; the special selection that the partitioned mode of described initial designs figure is made for ease of the explanation embodiment of the invention; should be as qualification to protection range, any change that those skilled in the art make this all should be included in the present invention's scope required for protection.
Be definite targeted graphical density, and then definite manufacturability pattern density criterion, the at first relation of analyzed pattern density and product feature parameter; Described characteristic parameter comprises: optical transmission speed, maximum/minimum local density, maximum/minimum global density, chip performance parameter and chip yield statistics etc.; Described characteristic parameter is an actual process parameter; Described targeted graphical density can be special pattern density or special pattern density range; As embodiments of the invention, described targeted graphical density comprises localized target pattern density and overall goals pattern density.
The concrete grammar of determining targeted graphical density is:
At first, a predetermined pattern density value, as, 10%; Then, adjust the pattern density in the different initial designs figure subregions, make pattern density in the different subregions all less than described predetermined pattern density value; And then, contrast the database interior simulation product feature parameter and the actual product requirement of the design configuration of corresponding described pattern density value, if the analog equipment characteristic parameter that obtains satisfies the actual product requirement, then described pattern density value can be defined as localized target pattern density value, and then, chip with described even localized target pattern density value is carried out global density calculate, described density value is decided to be overall goals pattern density value; Otherwise, predetermined next pattern density value, as, 20%, repeat described contrast, determining step, until drawing the targeted graphical density value.
Fig. 2 is the initial designs figure subregion schematic diagram of the explanation embodiment of the invention, as shown in Figure 2, for the explanation embodiments of the invention, the initial designs figure is divided into high density graph district 40, target density graph area 50 and low-density graph area 60 by density.
Really; the special selection that the concrete selection of described predetermined pattern density value and the concrete form of subregion are made for ease of the explanation embodiment of the invention; should be as qualification to protection range, any change that those skilled in the art make this all should be included in the present invention's scope required for protection.
The targeted graphical density value of comprehensive various product and the corresponding different materials layer pattern of identical product is determined manufacturability pattern density criterion.
As embodiments of the invention, described manufacturability pattern density criterion be described localized target pattern density less than 50%, described overall goals pattern density is less than 30%.If density value exceeds described manufacturability pattern density criterion in the described selection area, then described initial designs does not satisfy the design manufacturability and detects requirement, needs to improve initial designs by subsequent step; If density value meets described manufacturability pattern density criterion in the described selection area, then described initial designs satisfies the design manufacturability and detects requirement, referable production.
Fig. 3 A～3B is for the first pattern density improved procedure schematic diagram of the explanation embodiment of the invention, and to initial designs high density graph subregion 40, the concrete steps of adjusting pattern density in the subregion are:
As shown in Figure 3A, in described initial designs figure subregion, form hole 70, reduce pattern density in the described subregion by reducing graph area area in the described subregion and increasing non-graph area area.
Really, the special selection that described square hole is made for ease of the explanation embodiment of the invention should be as the qualification to protection range, and any change that those skilled in the art make this all should be included in the present invention's scope required for protection.
Obviously, shown in Fig. 3 B, form hole 70 in described graph area, then be full of the filled media 80 that differs from the graph area material at the described hole place, so that described graph area links to each other with other layer pattern district, still be equivalent to reduce the graph area area, increase non-graph area area, and then reach the purpose that reduces pattern density in the selection area.
Fig. 4 is the second graph density mode schematic diagram of the explanation embodiment of the invention, as shown in Figure 4, to initial designs low-density figure subregion 60, the concrete steps of adjusting pattern density in the subregion are: make pattern filling 90 in described subregion, be equivalent to increase the graph area area, reduce non-graph area area, and then increased pattern density in the selection area.The shape of described pattern filling and specification are determined according to designing requirement, process node and technological requirement.As the embodiment of the inventive method, the shape of described pattern filling can be selected square, rectangle, cross and T shape, L shaped etc. for use.
Really, the special selection that described square pattern filling is made for ease of the explanation embodiment of the invention should be as the qualification to protection range, and any change that those skilled in the art make this all should be included in the present invention's scope required for protection.
It should be noted, pattern filling in the embodiment of the invention will not be electrically connected to any active device in the chip, from total pattern density viewpoint, the accurate design of pattern filling is not crucial, but it should have rational interval and distribution, does not wish the effect that produces so that meet design requirement and reduce other as far as possible.
At last, improve initial designs and carry out duplicate detection.
If described local density greater than 50% or described global density greater than 30%, promptly described initial designs does not satisfy the design manufacturability and detects requirement, needs to improve initial designs and carry out duplicate detection by above-mentioned steps.
Adopt the inventive method, by the controlling Design pattern density, promptly controlling Design graphics sub density is less than 50%, global density is less than 30%, it is inhomogeneous and grind the generation of defective etc. to have reduced characteristic size, has strengthened the manufacturability of product, has reduced production cost simultaneously; Adopt the inventive method,, in the low-density graph area, fill dummy electrodes, can utilize existing pattern density directly to obtain targeted graphical density by in the high density graph district, forming hole; By the controlling Design pattern density, in the manufacturability that strengthens product, can shorten the trial production of new products time, and reduce R﹠D costs.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (17)
1. the manufacturing design method of an integrated circuit is characterized in that, comprising:
The initial designs figure is carried out density calculation, described density comprises local density and global density, described local density is the area ratio of graph area and non-graph area in the specific region, and the border that has overlapping region and arbitrary specific region between adjacent described specific region overlaps with the center of adjacent specific region;
Extract pattern density;
Adjust pattern density to targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density, when described pattern density is higher than described targeted graphical density, forms hole in having the graph area of described pattern density; When described pattern density is lower than described targeted graphical density, in having the graph area of described pattern density, fill dummy electrodes;
Determine manufacturability pattern density criterion according to described targeted graphical density;
Improve initial designs according to described manufacturability pattern density criterion.
2. method according to claim 1 is characterized in that: the specific region size range that need choose when calculating local density is 0.25 micron
2～2500 microns
2
3. method according to claim 1 is characterized in that: described adjustment pattern density to the method for targeted graphical density comprises:
The initial designs figure is pressed the density value subregion;
A predetermined pattern density;
Adjust the interior pattern density of different subregions to described predetermined pattern density;
The analog equipment characteristic parameter and the actual product of the described pattern density of correspondence are required to compare;
Judge whether described analog equipment characteristic parameter satisfies the actual product requirement, if then described pattern density can be defined as the localized target pattern density, and then, the chip with described localized target pattern density is carried out global density calculate, described density value is decided to be the overall goals pattern density; Otherwise, predetermined next pattern density;
Repeat described contrast, determining step, until drawing targeted graphical density.
4. method according to claim 3 is characterized in that: described predetermined pattern density range is 1%～30%.
5. method according to claim 3 is characterized in that: described analog equipment characteristic parameter comprises optical transmission speed, maximum/minimum local density, maximum/minimum global density, chip performance parameter and chip yield statistics.
6. method according to claim 3 is characterized in that: the described hole place is full of the medium that differs from the graph area material.
7. method according to claim 1 is characterized in that: described manufacturability pattern density criterion be described localized target pattern density less than 50%, described overall goals pattern density is less than 30%.
8. the method for a definite manufacturability pattern density criterion is characterized in that, comprising:
The initial designs figure is pressed the density value subregion;
A predetermined pattern density;
Adjust the interior pattern density of different subregions to described predetermined pattern density;
The analog equipment characteristic parameter and the actual product of the described pattern density of correspondence are required to compare;
Judge whether described analog equipment characteristic parameter satisfies the actual product requirement, if then described pattern density can be defined as the localized target pattern density, and then, the chip with described localized target pattern density is carried out global density calculate, described density value is decided to be the overall goals pattern density; Otherwise, predetermined next pattern density;
Repeat described contrast, determining step, draw targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density;
Determine manufacturability pattern density criterion according to described targeted graphical density.
9. method according to claim 8 is characterized in that: described predetermined pattern density value scope is 1%～30%.
10. method according to claim 8 is characterized in that: described analog equipment characteristic parameter comprises optical transmission speed, maximum/minimum local density, maximum/minimum global density, chip performance parameter and chip yield statistics.
11. method according to claim 8 is characterized in that: the pattern density in the different subregions of described adjustment to the method for described predetermined pattern density comprises:
Described initial designs figure is pressed the density value subregion, and described subregion comprises graph area and non-graph area;
In described subregion graph area, form hole.
12. method according to claim 11 is characterized in that: the described hole place is full of the medium that differs from the graph area material.
13. method according to claim 8 is characterized in that: the pattern density in the different subregions of described adjustment to the method for described predetermined pattern density comprises:
Described initial designs figure is pressed the density value subregion, and described subregion comprises graph area and non-graph area;
In the non-graph area of described subregion, make pattern filling.
14. one kind changes existing pattern density to obtain the method for targeted graphical density, it is characterized in that, comprising:
The initial designs figure is carried out density calculation;
Extract pattern density;
Determine targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density;
Described initial designs figure is pressed the density value subregion, and described subregion comprises graph area and non-graph area;
Adjust pattern density acquisition localized target pattern density in each subregion;
Obtain the overall goals pattern density according to the localized target pattern density.
15. method according to claim 14 is characterized in that: pattern density obtains the method for localized target pattern density for to form hole in described subregion graph area in each subregion of described adjustment.
16. method according to claim 15 is characterized in that: the described hole place is full of the medium that differs from the graph area material.
17. method according to claim 14 is characterized in that: pattern density obtains the method for localized target pattern density for to make pattern filling in the non-graph area of described subregion in each subregion of described adjustment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610029907A CN100576506C (en) | 2006-08-10 | 2006-08-10 | The manufacturing design method of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610029907A CN100576506C (en) | 2006-08-10 | 2006-08-10 | The manufacturing design method of integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101123218A CN101123218A (en) | 2008-02-13 |
| CN100576506C true CN100576506C (en) | 2009-12-30 |
Family
ID=39085476
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200610029907A Active CN100576506C (en) | 2006-08-10 | 2006-08-10 | The manufacturing design method of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100576506C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254786B (en) * | 2010-05-20 | 2013-02-13 | 上海华虹Nec电子有限公司 | Method for analyzing and checking local pattern density of chip |
| US9171777B2 (en) | 2012-12-19 | 2015-10-27 | Infineon Technologies Ag | Semiconductor device and method for manufacturing a semiconductor device |
| CN110928136B (en) * | 2019-12-25 | 2023-06-30 | 上海华力微电子有限公司 | Method for reducing critical dimension drift |
-
2006
- 2006-08-10 CN CN200610029907A patent/CN100576506C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101123218A (en) | 2008-02-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4744980B2 (en) | Pattern verification method, program thereof, and method of manufacturing semiconductor device | |
| CN102760732B (en) | System and methods for converting planar design to finfet design | |
| CN105378565B (en) | Use the IC manufacturing of direct-write photoetching | |
| CN102760180A (en) | System and methods for converting planar design to finfet design | |
| CN102779201A (en) | System and methods for converting planar design to FinFET design | |
| CN102760179A (en) | System and methods for converting planar design to FinFET design | |
| JP2008176303A (en) | Mask generation method, mask formation method, pattern formation method and semiconductor device | |
| US7392496B1 (en) | Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit | |
| US11334705B2 (en) | Electrical circuit design using cells with metal lines | |
| CN102799060A (en) | Dummy pattern and method for forming same | |
| CN100576506C (en) | The manufacturing design method of integrated circuit | |
| JP4768500B2 (en) | Semiconductor integrated circuit wiring layout apparatus, wiring layout method, and wiring layout program | |
| US20020188925A1 (en) | Pattern-creating method, pattern-processing apparatus and exposure mask | |
| TWI537760B (en) | Integrated circuit design and fabrication method | |
| JPH0876348A (en) | Mask data verifier, mask data former mask data verifying method, mask data forming method and auxiliary pattern forming method | |
| KR20050077167A (en) | Method for correction mask layout by ocp using multi simulation model | |
| US7970485B2 (en) | Systems and methods for determining width/space limits for a mask layout | |
| CN103218466A (en) | Integrated circuit design and manufacturing method | |
| US10083833B1 (en) | Integration fill technique | |
| KR100676606B1 (en) | Method for forming dummy pattern for cmp process | |
| US8316336B1 (en) | Method and mechanism for modeling interconnect structures for integrated circuits | |
| JP2010062475A (en) | Layout pattern generating method, method of manufacturing semiconductor device, program, and layout pattern generating device | |
| US20090199153A1 (en) | Exposure condition setting method and program for setting exposure conditions | |
| CN107479334B (en) | A kind of method of line width measurement and problem assessment | |
| CN107121895A (en) | The method for improving the uniformity of graphics critical dimension in photoetching process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111109 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |