CN100568381C - 用于获得存储器系统的时钟的系统与方法 - Google Patents

用于获得存储器系统的时钟的系统与方法 Download PDF

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CN100568381C
CN100568381C CNB2006101366078A CN200610136607A CN100568381C CN 100568381 C CN100568381 C CN 100568381C CN B2006101366078 A CNB2006101366078 A CN B2006101366078A CN 200610136607 A CN200610136607 A CN 200610136607A CN 100568381 C CN100568381 C CN 100568381C
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memory
controller
frequency
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CN1959839A (zh
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凯文·C·高尔
弗兰克·D·费雷奥洛
马丁·L·施马茨
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns

Abstract

一种用于获得存储器系统的时钟的系统和方法。所述方法包括在集线器设备处接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道进行通信，以及经由存储器接口与存储器设备进行通信。从参考振荡器时钟获得按基时钟频率操作的基时钟。通过把基时钟乘以存储器乘数来获得存储器接口时钟。通过把基时钟乘以控制器乘数来获得控制器接口时钟。存储器接口时钟施加于存储器接口，控制器接口时钟施加于控制器接口。

Description

用于获得存储器系统的时钟的系统与方法
技术领域
本发明涉及由通过菊花链控制器通道连接于存储器控制器的集线器设备构成的存储器系统。该集线器设备附接于或者驻留在包含存储器设备的存储器模块中。更具体地讲，本发明涉及允许在相同控制器通道上的存储器设备在变动的频率上操作。
背景技术
大多数高性能计算主存储器系统都使用了多个存储器模块，这些存储器模块具有通过一个或多个控制器通道连接于控制器的多个存储器设备。连接于相同控制器通道的所有存储器模块按相同的控制器频率操作，并且它们的所有存储器设备按相同的频率操作。控制器通道频率与存储器设备时钟频率的比率通常为固定的整数。当在通道中混合时，这些限制限制了存储器设备操作频率。由于通道频率与存储器设备频率的该固定比率，那些不能够获得最高数据速率的通道将在通道和存储器设备频率两者降低的情况下操作。这些典型的主存储器系统一定操作于不快于通道上最慢的存储器模块。当通道具有慢于其它存储器模块的存储器模块时，整个通道或许整个存储器系统肯定会慢下来，以兼容该慢速存储器模块的能力。
存储器系统操作频率的降低导致计算机系统主存储器性能的相应降低。所需要的是这样的存储器系统：其以最高支持速率操作其控制器通道，同时以它们最高支持速率操作存储器模块上的所有存储器设备。这一能力将最大化主存储器系统的性能。
发明内容
示例性实施例包括一种用于获得存储器系统的时钟的方法。该方法包括在集线器设备上接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道进行通信，并且经由存储器接口与存储器设备进行通信。从参考振荡器时钟获得按基时钟频率操作的基时钟。通过把基时钟乘以存储器乘数(memory multiplier)来获得存储器接口时钟。通过把基时钟乘以控制器乘数(controller multiplier)来获得控制器接口时钟。存储器接口时钟施加于存储器接口，控制器接口时钟施加于控制器接口。其中，经由在按控制器通道时钟频率操作的控制器接口和按存储器模块时钟频率操作的存储器接口之间的时钟域交叉功能来传递控制器接口信息。
另一个示例性实施例包括一种用于获得存储器系统的时钟的计算机程序产品。该计算机程序产品包括处理电路可读的和存储了用于实施方法的处理电路所执行的指令的存储媒体。该方法包括在集线器设备处接收参考振荡器时钟。该集线器设备经由控制器接口与控制器通道进行通信，并且经由存储器接口与存储器设备进行通信。从参考振荡器时钟获得按基时钟频率操作的基时钟。通过把基时钟乘以存储器乘数来获得存储器接口时钟。通过把基时钟乘以控制器乘数来获得控制器接口时钟。存储器接口时钟施加于存储器接口，控制器接口时钟施加于控制器接口。其中，经由在按控制器通道时钟频率操作的控制器接口和按存储器模块时钟频率操作的存储器接口之间的时钟域交叉功能来传递控制器接口信息。
另一个示例性实施例包括一种用于获得存储器系统的时钟的设备。该设备包括：在集线器设备处接收参考振荡器时钟的装置。集线器设备经由控制器接口与控制器通道进行通信，以及集线器设备经由存储器接口与存储器设备进行通信。该设备还包括：从参考振荡器时钟获得基时钟的装置，基时钟按基时钟频率操作；通过把基时钟乘以存储器乘数，获得存储器接口时钟的装置；通过把基时钟乘以控制器乘数，获得控制器接口时钟的装置；把存储器接口时钟施加于存储器接口的装置；以及把控制器接口时钟施加于控制器接口的装置。其中，经由在按控制器通道时钟频率操作的控制器接口和按存储器模块时钟频率操作的存储器接口之间的时钟域交叉功能来传递控制器接口信息。
另一个示例性实施例包括在存储器系统中的集线器设备。该集线器设备包括存储器接口、控制器以及时钟获得机构。所述存储器接口用于传输和从位于存储器模块上的存储器设备中接收数据。响应于按存储器模块时钟频率操作的存储器接口时钟来进行传输和接收。响应于按控制器通道时钟频率操作的控制器接口时钟，所述控制器接口被用于传输和从控制通道中接收数据。时钟获得机构实施：接收参考振荡器时钟；从参考振荡器时钟中获得按基时钟频率操作的基时钟；通过把基时钟乘以存储器乘数来获得存储器接口时钟；通过把基时钟乘以控制器乘数来获得控制器接口时钟；将存储器接口时钟施加于存储器接口；以及将控制器接口时钟施加于控制器接口。
又一个示例性实施例包括存储器系统。该存储器系统包括控制器、与控制器进行通信的控制器通道、一个或多个存储器模块以及一个或多个集线器设备。每一个存储器模块包括一个或多个存储器设备。集线器设备缓存地址、命令以及数据。每一个集线器设备与一个或多个存储器模块进行通信，并且经由控制器通道与控制器进行通信。使用从参考振荡器时钟获得的基时钟的倍数，按控制器通道操作频率和存储器设备操作频率来独立地配置每一个集线器设备。控制器通道操作频率用于与控制器通道的通信。存储器设备操作频率用于与存储器设备的通信。
附图说明
现在，参照附图，图中，以相同的参考数字标记相同的元件，在这些图中：
图1描述了示例性存储器系统，该存储器系统具有多层以点到点连接的菊花链存储器模块；
图2描述了示例性存储器系统，该存储器系统具有通过菊花链通道连接于存储器模块和连接于控制器通道的集线器设备；
图3描述了示例性集线器设备，该集线器设备使用了具有转发控制器接口总线时钟参考的m∶n计时(clocking)；
图4描述了示例性集线器设备，该集线器设备使用了具有独立分布时钟参考的m∶n计时；
图5描述了示例性存储器系统控制器通道，该存储器系统控制器通道具有使用了m∶n计时的控制器接口转发参考时钟和独立存储器设备频率；
图6描述了示例性存储器系统控制器通道，该存储器系统控制器通道具有使用了m∶n计时的独立分布参考时钟和独立存储器设备频率；以及
图7是可由各个示例性实施例实现的、使用m∶n比率的样本控制器和存储器接口数据速率的表。
具体实施方式
示例性实施例涉及计算机存储器系统，其由通过源于控制器的控制器通道互连的存储器模块构成。所述存储器模块附接于集线器逻辑设备，该集线器逻辑设备进一步附接于存储器模块上的存储器设备。存储器控制器通道在公共时钟频率上操作。每一个存储器模块通过控制器通道上的转发控制器接口总线时钟或者通过独立参考振荡器输入信号来接收公共参考振荡器频率。集线器设备唯一地配置为按各个操作频率操作它们的附接存储器设备，所述各个操作频率可以是参考振荡器频率的非整数倍。这使得变动存储器设备速度等级的存储器模块将按各个独立频率操作，同时驻留在按公共时钟频率操作的存储器控制器通道中。
如图1中所示，示例性实施例包括存储器系统，其由通过菊花链控制器通道114连接于存储器控制器102的一个或多个存储器模块110构成。存储器模块110包括缓存来往于控制器通道114的命令、地址和数据信号的集线器设备112、以及连接于集线器设备112的一个或多个存储器设备108。控制器通道114的下游部分向集线器设备112传输写数据和存储器操作命令。控制器通道114的上游部分将被请求的读数据返回到控制器102。在示例性实施例中，可以用控制器通道操作频率和存储器设备操作频率独立地配置每一个集线器设备112，以允许控制器通道114按一个频率操作和存储器设备108按不同的频率操作。另外，该存储器系统中的每一个存储器模块110及其相关的存储器设备108也可以按不同操作速度或者频率操作。
图2描述了包括存储器系统的供替换的示例性实施例，所述存储器系统由被连接到集线器设备112的一个或多个存储器模块110构成，所述集线器设备112通过菊花链控制器通道114被进一步连接于存储器控制器102。在本实施例中，集线器设备112不位于存储器模块110上，而改为集线器设备112与存储器模块110进行通信。可以使用与集线器设备112的多点连接或者通过使用点到点连接来构造控制器通道114。如图2中所示，存储器模块110可以经由多点连接和/或点到点连接而与集线器设备112进行通信。其它硬件配置也是可能的，例如，示例性实施例可以仅利用菊花链集线器设备112和/或存储器模块110的单一层。
图3描述了示例性集线器设备112，该集线器设备112将具有转发控制器接口总线时钟参考322的m∶n计时用作参考振荡器时钟。集线器设备112包括时钟域交叉功能304、存储器接口302、控制器接口306以及锁相环路(PLL)308(在这里，其也被称为时钟获得机构，因为其可以以包括软件和/或硬件的其它方式来实现)。存储器接口302经由mem_data总线310将数据发送到存储器模块110上的存储器设备108和从存储器模块110上的存储器设备108中接收数据，mem_data总线310按‘2*Y’Mbps操作，并且由具有‘Y’MHz频率的memory_clock 312计时。控制器接口306经由downstream_drv 314(向下游驱动数据和命令)和downstream_rcv 316(接收数据)与下游存储器模块110进行通信。另外，控制器接口306还经由upstream_rcv 318(接收数据和命令)和upstream_drv 320(向上游驱动数据和命令)与上游存储器模块110或者控制器102(如果没有上游存储器模块110)进行通信。
本发明的示例性实施例在集线器设备112中使用了两个可配置的整数比率，即‘m’和‘n’，以允许控制器通道114中的每个存储器模块110按公共通道频率(在这里，其也被称为控制器通道时钟频率)操作，但具有唯一的存储器设备频率(在这里，其也被称为存储器模块时钟频率)。控制器乘数‘m’被定义为公共通道频率‘X’与小的固定的基时钟频率例如但不限于是133MHz、100MHz、66MHz等的比率。把控制器通道114上转发的时钟用作它们的内部参考时钟的集线器设备112将把转发控制器接口总线时钟参考322的频率除以‘m’，以产生例如133MHz的基时钟。如果想要的控制器接口频率不能由基时钟频率匀分，则通过下舍入到基时钟频率(‘b’)的下一个整数倍而获得控制器接口频率。该基时钟将被用作为参考振荡器时钟和输入到PLL 308，在这里，将其乘以‘m’，以产生控制器接口时钟的清除和分布版本(a cleaned up and distributed version)。存储器乘数‘n’被定义为存储器设备时钟频率与基频率(例如，133MHz)的比率。集线器设备112在它们的PLL 308中把133MHz的基时钟乘以‘n’，以产生按‘Y’MHz运行的清除存储器接口时钟。所得到的控制器通道频率与存储器设备操作频率的比率为‘m∶n’。
由于集线器设备112知道控制器接口与存储器接口操作频率的比率，所以在集线器设备112中使用简化的时钟域交叉功能304来传递往返于存储器接口302的控制器接口信息。如果控制器接口306和/或存储器接口302使用双数据速率(DDR)计时来进行操作，则数据速率(以Mbps为单位)将两倍于各自接口时钟频率(即2X和/或2Y)。如果把DDR用在这两个接口上，则数据速率的比率将还是‘m∶n’。
图4描述了示例性集线器设备，该集线器设备使用具有作为参考振荡器时钟的输入到PLL 308的独立分布参考时钟402的‘m∶n’计时。使用独立分布参考时钟402的主存储器系统也可以使用‘m∶n’计时。在这种情况下，输入参考时钟402的频率必须是基时钟的频率(例如133MHz)的整数倍。把按‘W’MHz的频率操作的参考时钟402除以整数‘L’，以产生133MHz基时钟，其被用作为PLL 308中的乘法器的输入时钟。如果独立分布参考时钟402具有等于133MHz的频率，则‘L’简单地为1。PLL 308把基时钟乘以‘m’，以产生其频率为‘X’的清除控制器接口时钟。PLL 308还把基时钟乘以‘n’，以产生其频率为‘Y’的存储器接口时钟。把简化的时钟域交叉功能304用于在控制器接口306和存储器接口302中的逻辑电路(logic)之间传送信息。
图5描述了示例性存储器系统控制器通道114，其具有使用m∶n计时的控制器接口转发参考时钟322和独立存储器设备频率。使用‘m∶n’计时的存储器系统能够按唯一配置的存储器接口频率操作它们的存储器模块110，所述唯一配置的存储器接口频率等于由它们的存储器设备108支持的最高频率。图5表示存储器系统的单通道，在该存储器系统中，把标为DIMM 0 502的存储器模块配置为按‘Y0’频率操作其存储器设备108，而把标为DIMM 1504的存储器模块配置为按‘Y1’频率操作其存储器设备108。DIMM 0 502和DIMM 1 504均按公共的‘X’控制器接口频率操作。图6描述了示例性存储器系统通道，其具有独立分布参考时钟402和独立存储器设备频率，并且使用了m∶n计时，以最大化频率和性能。
如果在特定系统中，存储器通道频率即‘X’受到其电气和/或时序要求所限，则通过使用m∶n计时也能够最大化存储器设备频率。操作频率的这个最大化导致存储器通道的优化，以及因此导致计算机系统、性能的优化。
当配置使用m∶n计时的最佳性能的存储器系统时，用户应首先估计所支持的最高控制器通道频率。这被下舍入到基时钟频率(例如，133MHz)的下一个整数倍，从而得到‘X’。把‘X’除以基时钟频率，以针对控制器通道114中的所有集线器设备112来确定‘m’。对于控制器通道114中的每个存储器模块110，用户应估计所支持的最高存储器设备操作频率。这将是集线器设备112和存储器设备108规格的功能以及存储器模块110本身上的存储器接口302的电气分析的结果。应该把该最大操作频率下舍入到基时钟频率的下一个整数倍，由此对于所述存储器模块110，得到‘Y’。把‘Y’除以基时钟频率，以确定针对所述具体存储器模块100和/或集线器设备112的‘n’。
图7是可由示例性实施例实现的、使用m∶n比率的样本控制器和存储器接口数据速率的表。使用m∶n计时的存储器系统是相当灵活的，并且可以极大地优化。下表表示各个m和n的值，以及针对133MHz的基时钟频率的数据速率和m∶n比率。某些有趣的整数m∶n比率以‘*’加以强调，以说明那些设置，这些设置可用于按各种控制器通道和存储器设备操作频率重新创建更典型的固定的数据速率比率。
通过按其最高支持速率操作控制器通道、同时按它们的最高支持频率操作存储器模块上的所有存储器设备，示例性实施例可以被用于最大化存储器系统的性能。对于每个存储器模块，连接于控制器通道的每个存储器模块上的存储器设备的频率可以是不同的，从而允许在相同的控制器通道上优化变动速度的存储器设备。
如上所述，可以按计算机实现的过程和用于实践这些过程的装置的形式来体现本发明的实施例。也可以按包含体现在可触摸媒体中的指令的计算机程序代码的形式体现本发明的各实施例，所述可触摸媒体例如为软盘、CD-ROM、硬盘、或任何其它计算机可读存储媒体，其中，当把计算机程序代码加载于计算机并且由计算机执行时，计算机成为用于实践本发明的装置。还可以以计算机程序代码的形式体现本发明，该计算机程序代码无论例如存储在存储媒体中、加载于计算机和/或由计算机执行，还是在诸如电线或电缆乃至光纤的某种传输媒体上、或者经由电磁辐射将其加以传输都是可以的，其中，当把计算机程序代码加载于计算机和由计算机执行时，计算机成为用于实践本发明的装置。当在通用微处理器上实现时，计算机程序代码段配置微处理器以创建特定的逻辑电路。
尽管参考各个示例性实施例描述了本发明，但本领域技术人员知道，在不背离本发明范围的情况下，可以对本发明进行各种改变，并且可以对其要素进行等效替换。另外，在不背离本发明实质范围的情况下，也可以对本发明进行众多的修改，以适应某一具体情况或本发明所讲述的内容。因此，不旨在把本发明限制于所公开的作为实现本发明所考虑的最佳模式的具体实施例，而本发明将包括落入所附权利要求范围内的所有实施例。而且，术语第一、第二等的使用不表示任何次序或重要性，而是把术语第一、第二等用于区分一个要素和另一个要素。

Claims (49)

1.一种用于获得存储器系统的时钟的方法，该方法包括：
在集线器设备处接收参考振荡器时钟，集线器设备经由控制器接口与控制器通道进行通信，以及集线器设备经由存储器接口与存储器设备进行通信；
从参考振荡器时钟获得基时钟，基时钟按基时钟频率操作；
通过把基时钟乘以存储器乘数，获得存储器接口时钟；
通过把基时钟乘以控制器乘数，获得控制器接口时钟；
把存储器接口时钟施加于存储器接口；以及
把控制器接口时钟施加于控制器接口，
其中，经由在按控制器通道时钟频率操作的控制器接口和按存储器模块时钟频率操作的存储器接口之间的时钟域交叉功能来传递控制器接口信息。
2.根据权利要求1所述的方法，其中，从在所述控制器通道时钟频率上的转发控制器接口总线时钟中获得参考振荡器时钟，所述控制器通道时钟频率是基时钟频率的整数倍。
3.根据权利要求2所述的方法，其中，通过把最大控制器通道时钟频率下取整到基时钟频率的下一个整数倍来确定控制器通道时钟频率。
4.根据权利要求1所述的方法，其中，从独立分布参考时钟获得参考振荡器时钟，该独立分布参考时钟具有为基时钟频率的整数倍的频率。
5.根据权利要求4所述的方法，其中，通过把参考振荡器时钟的频率除以整数倍来获得基时钟。
6.根据权利要求1所述的方法还包括：
在第二集线器设备处接收参考振荡器时钟，第二集线器设备经由第二控制器接口与控制器通道进行通信，以及第二集线器设备经由第二存储器接口与第二存储器设备进行通信；
通过把基时钟乘以第二存储器乘数，获得第二存储器接口时钟；以及
把第二存储器接口时钟施加于第二存储器接口。
7.根据权利要求6所述的方法，其中，第二存储器乘数不同于该存储器乘数。
8.根据权利要求1所述的方法还包括：
通过把基时钟乘以第二控制器乘数，获得第二控制器接口时钟；以及
把第二控制器接口时钟施加于第二控制器接口。
9.根据权利要求1所述的方法，其中，控制器通道时钟频率是存储器模块时钟频率的非整数倍。
10.根据权利要求1所述的方法，其中，通过把最大存储器模块时钟频率除以基时钟频率并且下取整到最近的整数，计算存储器乘数。
11.根据权利要求10所述的方法，其中，存储器模块时钟频率为由存储器接口所存取的存储器模块的最大操作频率。
12.根据权利要求1所述的方法，其中，通过把最大控制器通道时钟频率除以基时钟频率并且下取整到最近的整数，计算控制器乘数。
13.根据权利要求12所述的方法，其中，控制器通道时钟频率为所存取的控制器通道的最大操作频率。
14.根据权利要求1所述的方法，其中，基时钟频率为133MHz。
15.根据权利要求1所述的方法，其中，存储器乘数不同于控制器乘数。
16.根据权利要求1所述的方法，其中，所述控制器通道时钟频率不小于所述存储器模块时钟频率。
17.一种用于获得存储器系统的时钟的设备，该设备包括：
在集线器设备处接收参考振荡器时钟的装置，集线器设备经由控制器接口与控制器通道进行通信，以及集线器设备经由存储器接口与存储器设备进行通信；
从参考振荡器时钟获得基时钟的装置，基时钟按基时钟频率操作；
通过把基时钟乘以存储器乘数，获得存储器接口时钟的装置；
通过把基时钟乘以控制器乘数，获得控制器接口时钟的装置；
把存储器接口时钟施加于存储器接口的装置；以及
把控制器接口时钟施加于控制器接口的装置，
其中，经由在按控制器通道时钟频率操作的控制器接口和按存储器模块时钟频率操作的存储器接口之间的时钟域交叉功能来传递控制器接口信息。
18.根据权利要求17所述的设备，还包括从在所述控制器通道时钟频率上的转发控制器接口总线时钟中获得参考振荡器时钟的装置，所述控制器通道时钟频率是基时钟频率的整数倍。
19.根据权利要求18所述的设备，还包括通过把最大控制器通道时钟频率下取整到基时钟频率的下一个整数倍来确定控制器通道时钟频率的装置。
20.根据权利要求17所述的设备，还包括从独立分布参考时钟获得参考振荡器时钟的装置，该独立分布参考时钟具有为基时钟频率的整数倍的频率。
21.根据权利要求20所述的设备，还包括通过把参考振荡器时钟的频率除以整数倍来获得基时钟的装置。
22.根据权利要求17所述的设备还包括：
在第二集线器设备处接收参考振荡器时钟的装置，第二集线器设备经由第二控制器接口与控制器通道进行通信，以及第二集线器设备经由第二存储器接口与第二存储器设备进行通信；
通过把基时钟乘以第二存储器乘数，获得第二存储器接口时钟的装置；以及
把第二存储器接口时钟施加于第二存储器接口的装置。
23.根据权利要求22所述的设备，其中，第二存储器乘数不同于该存储器乘数。
24.根据权利要求17所述的设备还包括：
通过把基时钟乘以第二控制器乘数，获得第二控制器接口时钟的装置；以及
把第二控制器接口时钟施加于第二控制器接口的装置。
25.根据权利要求17所述的设备，其中，控制器通道时钟频率是存储器模块时钟频率的非整数倍。
26.根据权利要求17所述的设备，还包括通过把最大存储器模块时钟频率除以基时钟频率并且下取整到最近的整数，计算存储器乘数的装置。
27.根据权利要求26所述的设备，其中，存储器模块时钟频率为由存储器接口所存取的存储器模块的最大操作频率。
28.根据权利要求17所述的设备，还包括通过把最大控制器通道时钟频率除以基时钟频率并且下取整到最近的整数，计算控制器乘数的装置。
29.根据权利要求28所述的设备，其中，控制器通道时钟频率为所存取的控制器通道的最大操作频率。
30.根据权利要求17所述的设备，其中，基时钟频率为133MHz。
31.根据权利要求17所述的设备，其中，存储器乘数不同于控制器乘数
32.根据权利要求17所述的设备，其中，所述控制器通道时钟频率不小于所述存储器模块时钟频率。
33.一个存储器系统中的集线器设备，该集线器设备包括：
存储器接口，用于从位于存储器模块上的存储器设备中传输和接收数据，响应于按存储器模块时钟频率操作的存储器接口时钟来产生所述传输和接收；
控制器接口，用于响应于按控制器通道时钟频率操作的控制器接口时钟来从控制器通道中传输和接收数据；以及
时钟获得机构，用于实施：
接收参考振荡器时钟；
从参考振荡器时钟中获得基时钟，基时钟按基时钟频率操作；
通过把基时钟乘以存储器乘数，获得存储器接口时钟；
通过把基时钟乘以控制器乘数，获得控制器接口时钟；
把存储器接口时钟施加于存储器接口；以及
把控制器接口时钟施加于控制器接口。
34.根据权利要求33所述的集线器设备，其中，从在控制器通道时钟频率上的转发控制器接口总线时钟中获得参考振荡器时钟，所述控制器通道时钟频率为基时钟频率的整数倍。
35.根据权利要求33所述的集线器设备，其中，通过把参考振荡器时钟除以控制器乘数来获得基时钟。
36.根据权利要求33所述的集线器设备，其中，从独立分布参考时钟获得参考振荡器时钟，所述独立分布参考时钟具有为基时钟频率的整数倍的频率。
37.根据权利要求36所述的集线器设备，其中，通过把参考振荡器时钟除以整数倍来获得基时钟。
38.根据权利要求33所述的集线器设备，其中，控制器通道时钟频率为存储器模块时钟频率的非整数倍。
39.根据权利要求33所述的集线器设备，其中，存储器乘数可以不同于控制器乘数。
40.根据权利要求33所述的集线器设备，其中，控制器通道为点到点的存储器通道。
41.根据权利要求33所述的集线器设备，其中，控制器通道为多点存储器通道。
42.根据权利要求33所述的集线器设备，其中，控制器通道为菊花链存储器通道。
43.一种存储器系统，包括：
控制器；
与控制器进行通信的控制器通道；
一个或多个存储器模块，每个存储器模块包括一个或多个存储器设备；以及
一个或多个集线器设备，用于缓存地址、命令以及数据，每个集线器设备与一个或多个存储器模块进行通信，并且经由控制器通道与控制器进行通信，其中，使用从参考振荡器时钟获得的基时钟的倍数，按控制器通道操作频率和存储器设备操作频率来独立地配置每个集线器设备，控制器通道操作频率用于与控制器通道的通信，存储器设备操作频率用于与存储器设备的通信。
44.根据权利要求43所述的存储器系统，其中，从转发控制器接口总线时钟获得参考振荡器时钟。
45.根据权利要求43所述的存储器系统，其中，从独立分布参考时钟获得参考振荡器时钟。
46.根据权利要求43所述的存储器系统，其中，存储器通道为点到点通道。
47.根据权利要求43所述的存储器系统，其中，存储器通道为多点通道。
48.根据权利要求43所述的存储器系统，其中，存储器通道为菊花链通道。
49.根据权利要求43所述的存储器系统，其中，集线器设备位于存储器模块上。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080114924A1 (en) * 2006-11-13 2008-05-15 Jack Edward Frayer High bandwidth distributed computing solid state memory storage system
US7917799B2 (en) * 2007-04-12 2011-03-29 International Business Machines Corporation Method and system for digital frequency clocking in processor cores
US8161314B2 (en) * 2007-04-12 2012-04-17 International Business Machines Corporation Method and system for analog frequency clocking in processor cores
TW200915176A (en) * 2007-09-19 2009-04-01 Asustek Comp Inc Method for setting actual operation frequency of memory and setting module thereof
US8621132B2 (en) * 2008-01-08 2013-12-31 Cisco Technology, Inc. System and methods for memory expansion
US8825965B2 (en) * 2008-01-08 2014-09-02 Cisco Technology, Inc. System and methods for memory expansion
US8321719B2 (en) * 2009-09-25 2012-11-27 Intel Corporation Efficient clocking scheme for a bidirectional data link
WO2011106055A1 (en) 2010-02-23 2011-09-01 Rambus Inc. Coordinating memory operations using memory-device generated reference signals
TWI486780B (zh) * 2013-08-13 2015-06-01 Phison Electronics Corp 連接介面單元與記憶體儲存裝置
KR20180002939A (ko) * 2016-06-29 2018-01-09 삼성전자주식회사 메모리 장치, 그것을 포함하는 메모리 패키지, 및 그것을 포함하는 메모리 모듈
US10404244B2 (en) 2017-03-31 2019-09-03 Hewlett Packard Enterprise Development Lp Adjustments of output clocks
CN113223566B (zh) * 2021-05-21 2022-12-02 长江先进存储产业创新中心有限责任公司 存储器的控制系统及其控制方法

Family Cites Families (345)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL220449A (zh) 1956-09-04
US3333253A (en) 1965-02-01 1967-07-25 Ibm Serial-to-parallel and parallel-toserial buffer-converter using a core matrix
US3395400A (en) 1966-04-26 1968-07-30 Bell Telephone Labor Inc Serial to parallel data converter
US4028675A (en) 1973-05-14 1977-06-07 Hewlett-Packard Company Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system
US3825904A (en) 1973-06-08 1974-07-23 Ibm Virtual memory system
US4135240A (en) 1973-07-09 1979-01-16 Bell Telephone Laboratories, Incorporated Protection of data file contents
US4150428A (en) * 1974-11-18 1979-04-17 Northern Electric Company Limited Method for providing a substitute memory in a data processing system
US4472780A (en) 1981-09-28 1984-09-18 The Boeing Company Fly-by-wire lateral control system
US4453215A (en) 1981-10-01 1984-06-05 Stratus Computer, Inc. Central processing apparatus for fault-tolerant computing
US4475194A (en) 1982-03-30 1984-10-02 International Business Machines Corporation Dynamic replacement of defective memory words
US4641263A (en) 1982-05-17 1987-02-03 Digital Associates Corporation Controller system or emulating local parallel minicomputer/printer interface and transferring serial data to remote line printer
US4479214A (en) 1982-06-16 1984-10-23 International Business Machines Corporation System for updating error map of fault tolerant memory
US4486739A (en) 1982-06-30 1984-12-04 International Business Machines Corporation Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code
US4833605A (en) 1984-08-16 1989-05-23 Mitsubishi Denki Kabushiki Kaisha Cascaded information processing module having operation unit, parallel port, and serial port for concurrent data transfer and data processing
US4683555A (en) 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
US4740916A (en) 1985-12-19 1988-04-26 International Business Machines Corporation Reconfigurable contiguous address space memory system including serially connected variable capacity memory modules and a split address bus
US4723120A (en) 1986-01-14 1988-02-02 International Business Machines Corporation Method and apparatus for constructing and operating multipoint communication networks utilizing point-to point hardware and interfaces
EP0269812B1 (de) 1986-10-16 1991-02-06 Siemens Aktiengesellschaft Verfahren und Anordnung zur Versorgung einer Taktleitung mit einem von zwei Taktsignalen in Abhängigkeit vom Pegel eines der beiden Taktsignale
JPS63231550A (ja) 1987-03-19 1988-09-27 Hitachi Ltd 多重仮想空間制御方式
US4803485A (en) 1987-03-23 1989-02-07 Amp Incorporated Lan communication system and medium adapter for use therewith
US4782487A (en) 1987-05-15 1988-11-01 Digital Equipment Corporation Memory test method and apparatus
US4943984A (en) 1988-06-24 1990-07-24 International Business Machines Corporation Data processing system parallel data bus having a single oscillator clocking apparatus
US4964129A (en) 1988-12-21 1990-10-16 Bull Hn Information Systems Inc. Memory controller with error logging
US4964130A (en) 1988-12-21 1990-10-16 Bull Hn Information Systems Inc. System for determining status of errors in a memory subsystem
JP3038781B2 (ja) 1989-04-21 2000-05-08 日本電気株式会社 メモリアクセス制御回路
US5053947A (en) 1989-09-29 1991-10-01 Allegro Microsystems, Inc. Extended multistation bus system and method
US5206946A (en) 1989-10-27 1993-04-27 Sand Technology Systems Development, Inc. Apparatus using converters, multiplexer and two latches to convert SCSI data into serial data and vice versa
JP2724893B2 (ja) 1989-12-28 1998-03-09 三菱電機株式会社 半導体集積回路装置
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5517626A (en) 1990-05-07 1996-05-14 S3, Incorporated Open high speed bus for microcomputer system
GB2246494B (en) 1990-05-25 1994-08-31 Silicon Systems Inc Method and apparatus for serial communications
CA2045790A1 (en) 1990-06-29 1991-12-30 Richard Lee Sites Branch prediction in high-performance processor
CA2045789A1 (en) 1990-06-29 1991-12-30 Richard Lee Sites Granularity hint for translation buffer in high performance processor
US5530941A (en) 1990-08-06 1996-06-25 Ncr Corporation System and method for prefetching data from a main computer memory into a cache memory
US5357621A (en) 1990-09-04 1994-10-18 Hewlett-Packard Company Serial architecture for memory module control
US5522064A (en) * 1990-10-01 1996-05-28 International Business Machines Corporation Data processing apparatus for dynamically setting timings in a dynamic memory system
US5287531A (en) 1990-10-31 1994-02-15 Compaq Computer Corp. Daisy-chained serial shift register for determining configuration of removable circuit boards in a computer system
US5214747A (en) 1990-12-24 1993-05-25 Eastman Kodak Company Segmented neural network with daisy chain control
JP2999845B2 (ja) 1991-04-25 2000-01-17 沖電気工業株式会社 シリアルアクセスメモリの倍速コントロール方式
FR2683924B1 (fr) 1991-11-18 1997-01-03 Bull Sa Memoire integree, son procede de gestion et systeme informatique en resultant.
US5347270A (en) 1991-12-27 1994-09-13 Mitsubishi Denki Kabushiki Kaisha Method of testing switches and switching circuit
US5387911A (en) 1992-02-21 1995-02-07 Gleichert; Marc C. Method and apparatus for transmitting and receiving both 8B/10B code and 10B/12B code in a switchable 8B/10B transmitter and receiver
US5715407A (en) 1992-03-06 1998-02-03 Rambus, Inc. Process and apparatus for collision detection on a parallel bus by monitoring a first line of the bus during even bus cycles for indications of overlapping packets
US5375127A (en) 1992-03-25 1994-12-20 Ncr Corporation Method and apparatus for generating Reed-Soloman error correcting code across multiple word boundaries
US5265212A (en) 1992-04-01 1993-11-23 Digital Equipment Corporation Sharing of bus access among multiple state machines with minimal wait time and prioritization of like cycle types
EP0567707A1 (en) 1992-04-30 1993-11-03 International Business Machines Corporation Implementation of column redundancy in a cache memory architecture
US5270964A (en) 1992-05-19 1993-12-14 Sun Microsystems, Inc. Single in-line memory module
US5410545A (en) 1992-07-28 1995-04-25 Digital Equipment Corporation Long-term storage of controller performance
DE69331061T2 (de) 1992-08-10 2002-06-06 Monolithic System Tech Inc Fehlertolerantes hierarchisiertes Bussystem
US5594925A (en) 1993-01-05 1997-01-14 Texas Instruments Incorporated Method and apparatus determining order and identity of subunits by inputting bit signals during first clock period and reading configuration signals during second clock period
US5544309A (en) 1993-04-22 1996-08-06 International Business Machines Corporation Data processing system with modified planar for boundary scan diagnostics
US5531135A (en) * 1993-06-11 1996-07-02 Volkswagon Ag Pedal arrangement for a motor vehicle
JP3489147B2 (ja) 1993-09-20 2004-01-19 株式会社日立製作所 データ転送方式
DE69422678T2 (de) 1993-10-12 2001-02-22 Matsushita Electric Ind Co Ltd Verschlüsselungssystem, Verschlüsselungsgerät und Entschlüsselungsgerät
SE502576C2 (sv) 1993-11-26 1995-11-13 Ellemtel Utvecklings Ab Feltolerant kösystem
US5845310A (en) 1993-12-15 1998-12-01 Hewlett-Packard Co. System and methods for performing cache latency diagnostics in scalable parallel processing architectures including calculating CPU idle time and counting number of cache misses
US5822749A (en) 1994-07-12 1998-10-13 Sybase, Inc. Database system with methods for improving query performance with cache optimization strategies
JPH0887451A (ja) 1994-09-09 1996-04-02 Internatl Business Mach Corp <Ibm> アドレス変換を管理する方法およびアドレス変換マネージャ
US5611055A (en) 1994-09-27 1997-03-11 Novalink Technologies Method and apparatus for implementing a PCMCIA auxiliary port connector for selectively communicating with peripheral devices
US5475690A (en) 1994-11-10 1995-12-12 Digital Equipment Corporation Delay compensated signal propagation
US6002411A (en) 1994-11-16 1999-12-14 Interactive Silicon, Inc. Integrated video and memory controller with data processing and graphical processing capabilities
US6170047B1 (en) 1994-11-16 2001-01-02 Interactive Silicon, Inc. System and method for managing system memory and/or non-volatile memory using a memory controller with integrated compression and decompression capabilities
US5513135A (en) 1994-12-02 1996-04-30 International Business Machines Corporation Synchronous memory packaged in single/dual in-line memory module and method of fabrication
JP3467880B2 (ja) * 1994-12-26 2003-11-17 ソニー株式会社 クロック信号発生装置
US5881154A (en) 1995-01-17 1999-03-09 Kokusai Denshin Denwa Co., Ltd. Data scramble transmission system
US5629685A (en) 1995-02-23 1997-05-13 International Business Machines Corporation Segmentable addressable modular communication network hubs
US6446224B1 (en) 1995-03-03 2002-09-03 Fujitsu Limited Method and apparatus for prioritizing and handling errors in a computer system
IN188196B (zh) 1995-05-15 2002-08-31 Silicon Graphics Inc
US5546023A (en) 1995-06-26 1996-08-13 Intel Corporation Daisy chained clock distribution scheme
US5852617A (en) 1995-12-08 1998-12-22 Samsung Electronics Co., Ltd. Jtag testing of buses using plug-in cards with Jtag logic mounted thereon
US5754804A (en) 1996-01-30 1998-05-19 International Business Machines Corporation Method and system for managing system bus communications in a data processing system
JPH09231130A (ja) 1996-02-26 1997-09-05 Mitsubishi Electric Corp マイクロコンピュータ
US5764155A (en) 1996-04-03 1998-06-09 General Electric Company Dynamic data exchange server
JP3710198B2 (ja) 1996-04-18 2005-10-26 沖電気工業株式会社 Ｓｔｍ−ｎ信号の誤り訂正符号化・復号化方法、ｓｔｍ−ｎ信号の誤り訂正符号化回路及びｓｔｍ−ｎ信号の誤り訂正復号化回路
US5661677A (en) 1996-05-15 1997-08-26 Micron Electronics, Inc. Circuit and method for on-board programming of PRD Serial EEPROMS
US5917760A (en) 1996-09-20 1999-06-29 Sldram, Inc. De-skewing data signals in a memory system
JPH10173122A (ja) 1996-12-06 1998-06-26 Mitsubishi Electric Corp メモリモジュール
US20020103988A1 (en) 1996-12-18 2002-08-01 Pascal Dornier Microprocessor with integrated interfaces to system memory and multiplexed input/output bus
US5926838A (en) 1997-03-19 1999-07-20 Micron Electronics Interface for high speed memory
US5870320A (en) 1997-06-23 1999-02-09 Sun Microsystems, Inc. Method for reducing a computational result to the range boundaries of a signed 16-bit integer in case of overflow
US6138213A (en) 1997-06-27 2000-10-24 Advanced Micro Devices, Inc. Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line
US6292903B1 (en) 1997-07-09 2001-09-18 International Business Machines Corporation Smart memory interface
US6011732A (en) 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
US6128746A (en) 1997-08-26 2000-10-03 International Business Machines Corporation Continuously powered mainstore for large memory subsystems
US6230236B1 (en) 1997-08-28 2001-05-08 Nortel Networks Corporation Content addressable memory system with cascaded memories and self timed signals
JP3445476B2 (ja) 1997-10-02 2003-09-08 株式会社東芝 半導体メモリシステム
US6378018B1 (en) 1997-10-10 2002-04-23 Intel Corporation Memory device and system including a low power interface
US6085276A (en) 1997-10-24 2000-07-04 Compaq Computers Corporation Multi-processor computer system having a data switch with simultaneous insertion buffers for eliminating arbitration interdependencies
WO1999024906A1 (fr) 1997-11-06 1999-05-20 Hitachi, Ltd. Processeur de donnees et systeme de traitement de donnees
US5973591A (en) * 1997-11-19 1999-10-26 Schwartz; David Electronic signaling system
US5917780A (en) 1997-12-03 1999-06-29 Daniel Robbins Watch having a multiplicity of band attachment positions and wristband for use therewith
DE69836437T2 (de) 1997-12-05 2007-09-27 Intel Corporation, Santa Clara Speichersystem mit speichermodul mit einem speichermodul-steuerbaustein
US6145028A (en) 1997-12-11 2000-11-07 Ncr Corporation Enhanced multi-pathing to an array of storage devices
US7373440B2 (en) * 1997-12-17 2008-05-13 Src Computers, Inc. Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format
US7024518B2 (en) 1998-02-13 2006-04-04 Intel Corporation Dual-port buffer-to-memory interface
US6198304B1 (en) * 1998-02-23 2001-03-06 Xilinx, Inc. Programmable logic device
US6096091A (en) 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
US6185718B1 (en) 1998-02-27 2001-02-06 International Business Machines Corporation Memory card design with parity and ECC for non-parity and non-ECC systems
US5959914A (en) 1998-03-27 1999-09-28 Lsi Logic Corporation Memory controller with error correction memory test application
US6643745B1 (en) 1998-03-31 2003-11-04 Intel Corporation Method and apparatus for prefetching data into cache
US5870325A (en) 1998-04-14 1999-02-09 Silicon Graphics, Inc. Memory system with multiple addressing and control busses
US6173382B1 (en) 1998-04-28 2001-01-09 International Business Machines Corporation Dynamic configuration of memory module using modified presence detect data
US6003121A (en) 1998-05-18 1999-12-14 Intel Corporation Single and multiple channel memory detection and sizing
US6216247B1 (en) 1998-05-29 2001-04-10 Intel Corporation 32-bit mode for a 64-bit ECC capable memory subsystem
DE69817333T2 (de) 1998-06-05 2004-06-09 International Business Machines Corp. Verfahren und Vorrichtung zum Laden von Befehlskodes in einen Speicher und zum Verbinden dieser Befehlskodes
US6499070B1 (en) 1998-06-08 2002-12-24 Texas Instruments Incorporated Circuitry and method of transferring parallel and serial data
JPH11353228A (ja) 1998-06-10 1999-12-24 Mitsubishi Electric Corp メモリモジュールシステム
US6170059B1 (en) 1998-07-10 2001-01-02 International Business Machines Corporation Tracking memory modules within a computer system
US6260127B1 (en) 1998-07-13 2001-07-10 Compaq Computer Corporation Method and apparatus for supporting heterogeneous memory in computer systems
US6505305B1 (en) 1998-07-16 2003-01-07 Compaq Information Technologies Group, L.P. Fail-over of multiple memory blocks in multiple memory modules in computer system
US6496540B1 (en) 1998-07-22 2002-12-17 International Business Machines Corporation Transformation of parallel interface into coded format with preservation of baud-rate
US6158040A (en) 1998-07-29 2000-12-05 Neomagic Corp. Rotated data-aligmnent in wade embedded DRAM for page-mode column ECC in a DVD controller
US6272609B1 (en) 1998-07-31 2001-08-07 Micron Electronics, Inc. Pipelined memory controller
JP4083302B2 (ja) 1998-08-12 2008-04-30 株式会社東芝 動画像スクランブル／デスクランブル装置
US6587912B2 (en) 1998-09-30 2003-07-01 Intel Corporation Method and apparatus for implementing multiple memory buses on a memory module
US5995405A (en) 1998-10-27 1999-11-30 Micron Technology, Inc. Memory module with flexible serial presence detect configuration
US6226729B1 (en) 1998-11-03 2001-05-01 Intel Corporation Method and apparatus for configuring and initializing a memory device and a memory channel
US6442698B2 (en) 1998-11-04 2002-08-27 Intel Corporation Method and apparatus for power management in a memory subsystem
US6349390B1 (en) * 1999-01-04 2002-02-19 International Business Machines Corporation On-board scrubbing of soft errors memory module
US6233639B1 (en) 1999-01-04 2001-05-15 International Business Machines Corporation Memory card utilizing two wire bus
US6357018B1 (en) 1999-01-26 2002-03-12 Dell Usa, L.P. Method and apparatus for determining continuity and integrity of a RAMBUS channel in a computer system
JP3275867B2 (ja) * 1999-01-26 2002-04-22 日本電気株式会社 スキャンテスト回路及びスキャンテスト回路を含む半導体集積回路及びスキャンテスト回路を搭載した半導体集積回路試験用基板
JP3484093B2 (ja) 1999-02-01 2004-01-06 インターナショナル・ビジネス・マシーンズ・コーポレーション 連想メモリ
US6115278A (en) 1999-02-09 2000-09-05 Silicon Graphics, Inc. Memory system with switching for data isolation
US6341315B1 (en) 1999-02-26 2002-01-22 Crossroads Systems, Inc. Streaming method and system for fiber channel network devices
US6564329B1 (en) 1999-03-16 2003-05-13 Linkup Systems Corporation System and method for dynamic clock generation
US6460107B1 (en) * 1999-04-29 2002-10-01 Intel Corporation Integrated real-time performance monitoring facility
JP3512678B2 (ja) 1999-05-27 2004-03-31 富士通株式会社 キャッシュメモリ制御装置および計算機システム
US6393528B1 (en) 1999-06-30 2002-05-21 International Business Machines Corporation Optimized cache allocation algorithm for multiple speculative requests
US6425044B1 (en) 1999-07-13 2002-07-23 Micron Technology, Inc. Apparatus for providing fast memory decode using a bank conflict table
US6839393B1 (en) * 1999-07-14 2005-01-04 Rambus Inc. Apparatus and method for controlling a master/slave system via master device synchronization
US7017020B2 (en) * 1999-07-16 2006-03-21 Broadcom Corporation Apparatus and method for optimizing access to memory
US6792495B1 (en) 1999-07-27 2004-09-14 Intel Corporation Transaction scheduling for a bus system
US7155016B1 (en) 1999-08-20 2006-12-26 Paradyne Corporation Communication device and method for using non-self-synchronizing scrambling in a communication system
US6549971B1 (en) * 1999-08-26 2003-04-15 International Business Machines Corporation Cascaded differential receiver circuit
US6594713B1 (en) 1999-09-10 2003-07-15 Texas Instruments Incorporated Hub interface unit and application unit interfaces for expanded direct memory access processor
US6484271B1 (en) 1999-09-16 2002-11-19 Koninklijke Philips Electronics N.V. Memory redundancy techniques
US6393512B1 (en) 1999-09-27 2002-05-21 Ati International Srl Circuit and method for detecting bank conflicts in accessing adjacent banks
US6467013B1 (en) 1999-09-30 2002-10-15 Intel Corporation Memory transceiver to couple an additional memory channel to an existing memory channel
US6262493B1 (en) 1999-10-08 2001-07-17 Sun Microsystems, Inc. Providing standby power to field replaceable units for electronic systems
US6889284B1 (en) 1999-10-19 2005-05-03 Intel Corporation Method and apparatus for supporting SDRAM memory
US6526469B1 (en) * 1999-11-12 2003-02-25 International Business Machines Corporation Bus architecture employing varying width uni-directional command bus
US6557069B1 (en) * 1999-11-12 2003-04-29 International Business Machines Corporation Processor-memory bus architecture for supporting multiple processors
US6513091B1 (en) * 1999-11-12 2003-01-28 International Business Machines Corporation Data routing using status-response signals
US6584576B1 (en) 1999-11-12 2003-06-24 Kingston Technology Corporation Memory system using complementary delay elements to reduce rambus module timing skew
JP2001167077A (ja) 1999-12-09 2001-06-22 Nec Kofu Ltd ネットワークシステムにおけるデータアクセス方法、ネットワークシステムおよび記録媒体
US6601149B1 (en) 1999-12-14 2003-07-29 International Business Machines Corporation Memory transaction monitoring system and user interface
US6487627B1 (en) 1999-12-22 2002-11-26 Intel Corporation Method and apparatus to manage digital bus traffic
US6307789B1 (en) 1999-12-28 2001-10-23 Intel Corporation Scratchpad memory
US6408398B1 (en) 1999-12-29 2002-06-18 Intel Corporation Method and apparatus for detecting time domains on a communication channel
US6609171B1 (en) * 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
KR100575864B1 (ko) 1999-12-30 2006-05-03 주식회사 하이닉스반도체 램버스 디램
US6910146B2 (en) 1999-12-31 2005-06-21 Intel Corporation Method and apparatus for improving timing margin in an integrated circuit as determined from recorded pass/fail indications for relative phase settings
US7266634B2 (en) 2000-01-05 2007-09-04 Rambus Inc. Configurable width buffered module having flyby elements
US6502161B1 (en) 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
US6845472B2 (en) 2000-01-25 2005-01-18 Hewlett-Packard Development Company, L.P. Memory sub-system error cleansing
US6219288B1 (en) 2000-03-03 2001-04-17 International Business Machines Corporation Memory having user programmable AC timings
US6631439B2 (en) 2000-03-08 2003-10-07 Sun Microsystems, Inc. VLIW computer processing architecture with on-chip dynamic RAM
JP4569913B2 (ja) * 2000-03-10 2010-10-27 エルピーダメモリ株式会社 メモリモジュール
JP2001290697A (ja) * 2000-04-06 2001-10-19 Hitachi Ltd 情報処理システム
US6704842B1 (en) * 2000-04-12 2004-03-09 Hewlett-Packard Development Company, L.P. Multi-processor system with proactive speculative data transfer
US7269765B1 (en) 2000-04-13 2007-09-11 Micron Technology, Inc. Method and apparatus for storing failing part locations in a module
US6546359B1 (en) * 2000-04-24 2003-04-08 Sun Microsystems, Inc. Method and apparatus for multiplexing hardware performance indicators
US6721944B2 (en) * 2000-05-31 2004-04-13 Sun Microsystems, Inc. Marking memory elements based upon usage of accessed information during speculative execution
US7039755B1 (en) 2000-05-31 2006-05-02 Advanced Micro Devices, Inc. Method and apparatus for powering down the CPU/memory controller complex while preserving the self refresh state of memory in the system
US6748518B1 (en) 2000-06-06 2004-06-08 International Business Machines Corporation Multi-level multiprocessor speculation mechanism
US6622217B2 (en) * 2000-06-10 2003-09-16 Hewlett-Packard Development Company, L.P. Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system
US6697919B2 (en) * 2000-06-10 2004-02-24 Hewlett-Packard Development Company, L.P. System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system
US6415376B1 (en) * 2000-06-16 2002-07-02 Conexant Sytems, Inc. Apparatus and method for issue grouping of instructions in a VLIW processor
US6791555B1 (en) 2000-06-23 2004-09-14 Micron Technology, Inc. Apparatus and method for distributed memory control in a graphics processing system
US6611905B1 (en) * 2000-06-29 2003-08-26 International Business Machines Corporation Memory interface with programable clock to output time based on wide range of receiver loads
US6587112B1 (en) * 2000-07-10 2003-07-01 Hewlett-Packard Development Company, L.P. Window copy-swap using multi-buffer hardware support
US6446174B1 (en) 2000-07-11 2002-09-03 Intel Corporation Computer system with dram bus
US6738836B1 (en) 2000-08-31 2004-05-18 Hewlett-Packard Development Company, L.P. Scalable efficient I/O port protocol
US6977979B1 (en) 2000-08-31 2005-12-20 Hewlett-Packard Development Company, L.P. Enhanced clock forwarding data recovery
US6487102B1 (en) 2000-09-18 2002-11-26 Intel Corporation Memory module having buffer for isolating stacked memory devices
US6317352B1 (en) 2000-09-18 2001-11-13 Intel Corporation Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules
US6553450B1 (en) * 2000-09-18 2003-04-22 Intel Corporation Buffer to multiply memory interface
US6625687B1 (en) * 2000-09-18 2003-09-23 Intel Corporation Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing
US6625685B1 (en) * 2000-09-20 2003-09-23 Broadcom Corporation Memory controller with programmable configuration
US6532525B1 (en) * 2000-09-29 2003-03-11 Ati Technologies, Inc. Method and apparatus for accessing memory
ATE437476T1 (de) * 2000-10-06 2009-08-15 Pact Xpp Technologies Ag Zellenanordnung mit segmentierter zwischenzellstruktur
US6636875B1 (en) 2000-10-25 2003-10-21 International Business Machines Corporation System and method for synchronizing related data elements in disparate storage systems
US6611902B2 (en) 2000-11-13 2003-08-26 Matsushita Electric Industrial Co., Ltd. Information processor and information processing method
US6285172B1 (en) 2000-11-13 2001-09-04 Texas Instruments Incorporated Digital phase-locked loop circuit with reduced phase jitter frequency
US6898726B1 (en) 2000-11-15 2005-05-24 Micron Technology, Inc. Memory system that sets a predetermined phase relationship between read and write clock signals at a bus midpoint for a plurality of spaced device locations
US6590827B2 (en) * 2000-11-21 2003-07-08 Via Technologies, Inc. Clock device for supporting multiplicity of memory module types
US6510100B2 (en) * 2000-12-04 2003-01-21 International Business Machines Corporation Synchronous memory modules and memory systems with selectable clock termination
US6993612B2 (en) * 2000-12-07 2006-01-31 Micron Technology, Inc. Arbitration method for a source strobed bus
US6834355B2 (en) 2000-12-15 2004-12-21 Intel Corporation Circuit in which the time delay of an input clock signal is dependent only on its logic phase width and a ratio of capacitances
US6934785B2 (en) * 2000-12-22 2005-08-23 Micron Technology, Inc. High speed interface with looped bus
US6622227B2 (en) 2000-12-27 2003-09-16 Intel Corporation Method and apparatus for utilizing write buffers in memory control/interface
US6493250B2 (en) 2000-12-28 2002-12-10 Intel Corporation Multi-tier point-to-point buffered memory interface
TW527537B (en) * 2001-01-03 2003-04-11 Leadtek Research Inc Conversion device of SDR and DDR, and interface card, motherboard and memory module interface using the same
US6832329B2 (en) 2001-02-08 2004-12-14 International Business Machines Corporation Cache thresholding method, apparatus, and program for predictive reporting of array bit line or driver failures
JP3888070B2 (ja) * 2001-02-23 2007-02-28 株式会社ルネサステクノロジ 消費電力制御インタフェースを有する論理回路モジュール及び該モジュールを記憶した記憶媒体
US6445624B1 (en) 2001-02-23 2002-09-03 Micron Technology, Inc. Method of synchronizing read timing in a high speed memory system
US20020124201A1 (en) 2001-03-01 2002-09-05 International Business Machines Corporation Method and system for log repair action handling on a logically partitioned multiprocessing system
US6874102B2 (en) * 2001-03-05 2005-03-29 Stratus Technologies Bermuda Ltd. Coordinated recalibration of high bandwidth memories in a multiprocessor computer
US6754762B1 (en) 2001-03-05 2004-06-22 Honeywell International Inc. Redundant bus switching
US6882082B2 (en) * 2001-03-13 2005-04-19 Micron Technology, Inc. Memory repeater
US6678811B2 (en) * 2001-04-07 2004-01-13 Hewlett-Packard Development Company, L.P. Memory controller with 1X/MX write capability
US6625702B2 (en) 2001-04-07 2003-09-23 Hewlett-Packard Development Company, L.P. Memory controller with support for memory modules comprised of non-homogeneous data width RAM devices
US6721185B2 (en) * 2001-05-01 2004-04-13 Sun Microsystems, Inc. Memory module having balanced data I/O contacts pads
US6779075B2 (en) 2001-05-15 2004-08-17 Leadtek Research Inc. DDR and QDR converter and interface card, motherboard and memory module interface using the same
US6766389B2 (en) 2001-05-18 2004-07-20 Broadcom Corporation System on a chip for networking
CA2447555A1 (en) * 2001-06-04 2002-12-12 Nct Group, Inc. System and method for increasing the effective bandwidth of a communications network
US20030090879A1 (en) * 2001-06-14 2003-05-15 Doblar Drew G. Dual inline memory module
US6760817B2 (en) 2001-06-21 2004-07-06 International Business Machines Corporation Method and system for prefetching utilizing memory initiated prefetch write operations
US20030033463A1 (en) * 2001-08-10 2003-02-13 Garnett Paul J. Computer system storage
US6681292B2 (en) * 2001-08-27 2004-01-20 Intel Corporation Distributed read and write caching implementation for optimized input/output applications
US20040098549A1 (en) 2001-10-04 2004-05-20 Dorst Jeffrey R. Apparatus and methods for programmable interfaces in memory controllers
US6965952B2 (en) 2001-10-15 2005-11-15 Intel Corporation Bus framer
US6901491B2 (en) * 2001-10-22 2005-05-31 Sun Microsystems, Inc. Method and apparatus for integration of communication links with a remote direct memory access protocol
US6594748B1 (en) 2001-11-09 2003-07-15 Lsi Logic Corporation Methods and structure for pipelined read return control in a shared RAM controller
DE10155449A1 (de) 2001-11-12 2003-05-28 Infineon Technologies Ag Verfahren zur Rekonfiguration eines Speichers
US6675280B2 (en) * 2001-11-30 2004-01-06 Intel Corporation Method and apparatus for identifying candidate virtual addresses in a content-aware prefetcher
US7385993B2 (en) 2001-12-21 2008-06-10 International Business Machines Corporation Queue scheduling mechanism in a data packet transmission system
US6792516B2 (en) 2001-12-28 2004-09-14 Intel Corporation Memory arbiter with intelligent page gathering logic
US6925534B2 (en) 2001-12-31 2005-08-02 Intel Corporation Distributed memory module cache prefetch
US6865646B2 (en) * 2001-12-31 2005-03-08 Intel Corporation Segmented distributed memory module cache
US6799241B2 (en) 2002-01-03 2004-09-28 Intel Corporation Method for dynamically adjusting a memory page closing policy
US6775747B2 (en) 2002-01-03 2004-08-10 Intel Corporation System and method for performing page table walks on speculative software prefetch operations
KR100454126B1 (ko) 2002-01-15 2004-10-26 삼성전자주식회사 분리된 클록 라인을 구비한 정보 처리 시스템
US7227949B2 (en) 2002-01-31 2007-06-05 Texas Instruments Incorporated Separate self-synchronizing packet-based scrambler having replay variation
GB2386441B (en) 2002-03-12 2006-09-27 Advanced Risc Mach Ltd Bus interface selection by page table attributes
DE10215362A1 (de) 2002-04-08 2003-10-30 Infineon Technologies Ag Integrierter Speicher mit einem Speicherzellenfeld mit mehreren Speicherbänken und Schaltungsanordnung mit einem integrierten Speicher
US6918068B2 (en) 2002-04-08 2005-07-12 Harris Corporation Fault-tolerant communications system and associated methods
US6948091B2 (en) 2002-05-02 2005-09-20 Honeywell International Inc. High integrity recovery from multi-bit data failures
US7376146B2 (en) 2002-05-16 2008-05-20 Intel Corporation Bus conversion device, system and method
US6807650B2 (en) 2002-06-03 2004-10-19 International Business Machines Corporation DDR-II driver impedance adjustment control algorithm and interface circuits
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7203318B2 (en) 2002-06-17 2007-04-10 M/A-Com Private Radio Systems, Inc. Secure transmission system for a digital trunked radio system
US7212548B2 (en) 2002-06-21 2007-05-01 Adtran, Inc. Multiple T1 channel inverse multiplexing method and apparatus
TW559694B (en) 2002-06-21 2003-11-01 Via Tech Inc Method and system of calibrating the control delay time
AU2003211701B2 (en) 2002-06-21 2007-09-06 Hymo Corporation Water-soluble polymer dispersion, process for producing the same and method of use therefor
US6832286B2 (en) 2002-06-25 2004-12-14 Hewlett-Packard Development Company, L.P. Memory auto-precharge
US7047384B2 (en) 2002-06-27 2006-05-16 Intel Corporation Method and apparatus for dynamic timing of memory interface signals
US6996766B2 (en) 2002-06-28 2006-02-07 Sun Microsystems, Inc. Error detection/correction code which detects and corrects a first failing component and optionally a second failing component
US6741096B2 (en) 2002-07-02 2004-05-25 Lsi Logic Corporation Structure and methods for measurement of arbitration performance
US6854043B2 (en) * 2002-07-05 2005-02-08 Hewlett-Packard Development Company, L.P. System and method for multi-modal memory controller system operation
JP4159415B2 (ja) 2002-08-23 2008-10-01 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
JP2004093462A (ja) * 2002-09-02 2004-03-25 Oki Electric Ind Co Ltd 半導体集積回路とその試験方法
KR20040021485A (ko) 2002-09-04 2004-03-10 삼성전자주식회사 메모리 접근시간을 줄이기 위하여 페이지 모드를 선택할수 있는 메모리 제어장치 및 메모리 접근 제어방법
US20040054864A1 (en) 2002-09-13 2004-03-18 Jameson Neil Andrew Memory controller
US20040078615A1 (en) * 2002-10-17 2004-04-22 Intel Corporation (A Delaware Corporation) Multi-module system, distribution circuit and their methods of operation
DE10248672B4 (de) 2002-10-18 2016-02-11 Robert Bosch Gmbh Verfahren zur Übertragung von Daten auf einem Bus
US7313583B2 (en) 2002-10-22 2007-12-25 Broadcom Corporation Galois field arithmetic unit for use within a processor
US6996639B2 (en) * 2002-12-10 2006-02-07 Intel Corporation Configurably prefetching head-of-queue from ring buffers
US20040117588A1 (en) 2002-12-12 2004-06-17 International Business Machines Corporation Access request for a data processing system having no system memory
US7093076B2 (en) 2002-12-12 2006-08-15 Samsung Electronics, Co., Ltd. Memory system having two-way ring topology and memory device and memory module for ring-topology memory system
US6978416B2 (en) 2002-12-19 2005-12-20 International Business Machines Corporation Error correction with low latency for bus structures
US6944084B2 (en) 2002-12-31 2005-09-13 Intel Corporation Memory system that measures power consumption
US7308524B2 (en) 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
US7047370B1 (en) 2003-01-14 2006-05-16 Cisco Technology, Inc. Full access to memory interfaces via remote request
US7096407B2 (en) 2003-02-18 2006-08-22 Hewlett-Packard Development Company, L.P. Technique for implementing chipkill in a memory system
US7216276B1 (en) 2003-02-27 2007-05-08 Marvell International Ltd. Apparatus and method for testing and debugging an integrated circuit
US6922658B2 (en) 2003-03-31 2005-07-26 International Business Machines Corporation Method and system for testing the validity of shared data in a multiprocessing system
US7234099B2 (en) * 2003-04-14 2007-06-19 International Business Machines Corporation High reliability memory module with a fault tolerant address and command bus
US7016213B2 (en) 2003-05-13 2006-03-21 Advanced Micro Devices, Inc. Method for initializing a system including a host and plurality of memory modules connected via a serial memory interconnect
US7320100B2 (en) 2003-05-20 2008-01-15 Cray Inc. Apparatus and method for memory with bit swapping on the fly and testing
TW200427224A (en) 2003-05-21 2004-12-01 Myson Century Inc Clock multiplier
US7127629B2 (en) 2003-06-03 2006-10-24 Intel Corporation Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signal
US7165153B2 (en) * 2003-06-04 2007-01-16 Intel Corporation Memory channel with unidirectional links
US7428644B2 (en) 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
US7260685B2 (en) 2003-06-20 2007-08-21 Micron Technology, Inc. Memory hub and access method having internal prefetch buffers
DE10330812B4 (de) * 2003-07-08 2006-07-06 Infineon Technologies Ag Halbleiterspeichermodul
KR100500454B1 (ko) * 2003-07-28 2005-07-12 삼성전자주식회사 메모리 모듈 테스트 시스템 및 메모리 모듈 평가 시스템
US7844801B2 (en) * 2003-07-31 2010-11-30 Intel Corporation Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors
DE10335978B4 (de) 2003-08-06 2006-02-16 Infineon Technologies Ag Hub-Baustein zum Anschließen von einem oder mehreren Speicherbausteinen
US7210059B2 (en) * 2003-08-19 2007-04-24 Micron Technology, Inc. System and method for on-board diagnostics of memory modules
US7136958B2 (en) 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
US20050050237A1 (en) * 2003-08-28 2005-03-03 Jeddeloh Joseph M. Memory module and method having on-board data search capabilities and processor-based system using such memory modules
US7194593B2 (en) * 2003-09-18 2007-03-20 Micron Technology, Inc. Memory hub with integrated non-volatile memory
US20050080581A1 (en) * 2003-09-22 2005-04-14 David Zimmerman Built-in self test for memory interconnect testing
US7197594B2 (en) * 2003-09-23 2007-03-27 Infineon Technologies Flash Gmbh & Co. Kg Circuit, system and method for encoding data to be stored on a non-volatile memory array
US7124329B2 (en) 2003-09-26 2006-10-17 International Business Machines Corporation Implementing memory failure analysis in a data processing system
US7386765B2 (en) 2003-09-29 2008-06-10 Intel Corporation Memory device having error checking and correction
US7334159B1 (en) 2003-09-29 2008-02-19 Rockwell Automation Technologies, Inc. Self-testing RAM system and method
US20050071707A1 (en) * 2003-09-30 2005-03-31 Hampel Craig E. Integrated circuit with bi-modal data strobe
US7139965B2 (en) * 2003-10-08 2006-11-21 Hewlett-Packard Development Company, L.P. Bus device that concurrently synchronizes source synchronous data while performing error detection and correction
US7433258B2 (en) * 2003-10-10 2008-10-07 Datasecure Llc. Posted precharge and multiple open-page RAM architecture
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US20050086424A1 (en) * 2003-10-21 2005-04-21 Infineon Technologies North America Corp. Well-matched echo clock in memory system
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
US7113418B2 (en) * 2003-11-04 2006-09-26 Hewlett-Packard Development Company, L.P. Memory systems and methods
US7177211B2 (en) * 2003-11-13 2007-02-13 Intel Corporation Memory channel test fixture and method
US7206962B2 (en) 2003-11-25 2007-04-17 International Business Machines Corporation High reliability memory subsystem using data error correcting code symbol sliced command repowering
US7073010B2 (en) * 2003-12-02 2006-07-04 Super Talent Electronics, Inc. USB smart switch with packet re-ordering for interleaving among multiple flash-memory endpoints aggregated as a single virtual USB endpoint
US7155623B2 (en) 2003-12-03 2006-12-26 International Business Machines Corporation Method and system for power management including local bounding of device group power consumption
US7752470B2 (en) 2003-12-03 2010-07-06 International Business Machines Corporation Method and system for power management including device controller-based device use evaluation and power-state control
TWI237767B (en) 2003-12-23 2005-08-11 High Tech Comp Corp Serial/parallel data transformer module and related computer systems
US20050138267A1 (en) 2003-12-23 2005-06-23 Bains Kuljit S. Integral memory buffer and serial presence detect capability for fully-buffered memory modules
JP4085389B2 (ja) 2003-12-24 2008-05-14 日本電気株式会社 マルチプロセッサシステム、マルチプロセッサシステムにおける一貫性制御装置及び一貫性制御方法
US7216196B2 (en) 2003-12-29 2007-05-08 Micron Technology, Inc. Memory hub and method for memory system performance monitoring
US7197670B2 (en) 2003-12-31 2007-03-27 Intel Corporation Methods and apparatuses for reducing infant mortality in semiconductor devices utilizing static random access memory (SRAM)
US7321979B2 (en) * 2004-01-22 2008-01-22 International Business Machines Corporation Method and apparatus to change the operating frequency of system core logic to maximize system memory bandwidth
US7181584B2 (en) * 2004-02-05 2007-02-20 Micron Technology, Inc. Dynamic command and/or address mirroring system and method for memory modules
US7412574B2 (en) 2004-02-05 2008-08-12 Micron Technology, Inc. System and method for arbitration of memory responses in a hub-based memory system
US7363436B1 (en) 2004-02-26 2008-04-22 Integrated Device Technology, Inc. Collision detection in a multi-port memory system
US7114109B2 (en) * 2004-03-11 2006-09-26 International Business Machines Corporation Method and apparatus for customizing and monitoring multiple interfaces and implementing enhanced fault tolerance and isolation features
US7120723B2 (en) 2004-03-25 2006-10-10 Micron Technology, Inc. System and method for memory hub-based expansion bus
US7200832B2 (en) 2004-03-26 2007-04-03 Lsi Logic Corp Macro cell for integrated circuit physical layer interface
US7213082B2 (en) 2004-03-29 2007-05-01 Micron Technology, Inc. Memory hub and method for providing memory sequencing hints
US9047094B2 (en) 2004-03-31 2015-06-02 Icera Inc. Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor
US7724750B2 (en) 2004-04-01 2010-05-25 Nokia Corporation Expedited data transmission in packet based network
US7027336B2 (en) 2004-05-10 2006-04-11 Hynix Semiconductor Inc. Semiconductor memory device for controlling output timing of data depending on frequency variation
US7162567B2 (en) * 2004-05-14 2007-01-09 Micron Technology, Inc. Memory hub and method for memory sequencing
US7222213B2 (en) 2004-05-17 2007-05-22 Micron Technology, Inc. System and method for communicating the synchronization status of memory modules during initialization of the memory modules
US7304905B2 (en) * 2004-05-24 2007-12-04 Intel Corporation Throttling memory in response to an internal temperature of a memory device
US7363419B2 (en) 2004-05-28 2008-04-22 Micron Technology, Inc. Method and system for terminating write commands in a hub-based memory system
US20060010339A1 (en) 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US7500123B2 (en) 2004-06-28 2009-03-03 Ati Technologies Ulc Apparatus and method for reducing power consumption in a graphics processing device
US7318130B2 (en) 2004-06-29 2008-01-08 Intel Corporation System and method for thermal throttling of memory modules
US20060004953A1 (en) 2004-06-30 2006-01-05 Vogt Pete D Method and apparatus for increased memory bandwidth
US7539800B2 (en) * 2004-07-30 2009-05-26 International Business Machines Corporation System, method and storage medium for providing segment level sparing
US7296129B2 (en) 2004-07-30 2007-11-13 International Business Machines Corporation System, method and storage medium for providing a serialized memory interface with a bus repeater
US20060036826A1 (en) * 2004-07-30 2006-02-16 International Business Machines Corporation System, method and storage medium for providing a bus speed multiplier
US7091890B1 (en) 2004-08-17 2006-08-15 Xilinx, Inc. Multi-purpose source synchronous interface circuitry
US7404118B1 (en) 2004-09-02 2008-07-22 Sun Microsystems, Inc. Memory error analysis for determining potentially faulty memory components
US8621304B2 (en) 2004-10-07 2013-12-31 Hewlett-Packard Development Company, L.P. Built-in self-test system and method for an integrated circuit
US7360027B2 (en) 2004-10-15 2008-04-15 Intel Corporation Method and apparatus for initiating CPU data prefetches by an external agent
US20060095679A1 (en) 2004-10-28 2006-05-04 Edirisooriya Samantha J Method and apparatus for pushing data into a processor cache
US7331010B2 (en) * 2004-10-29 2008-02-12 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
US7334070B2 (en) * 2004-10-29 2008-02-19 International Business Machines Corporation Multi-channel memory architecture for daisy chained arrangements of nodes with bridging between memory channels
US20060112238A1 (en) 2004-11-23 2006-05-25 Sujat Jamil Techniques for pushing data to a processor cache
US20060161733A1 (en) 2005-01-19 2006-07-20 Emulex Design & Manufacturing Corporation Host buffer queues
US20060168407A1 (en) 2005-01-26 2006-07-27 Micron Technology, Inc. Memory hub system and method having large virtual page size
US20060195631A1 (en) 2005-01-31 2006-08-31 Ramasubramanian Rajamani Memory buffers for merging local data from memory modules
JP4516458B2 (ja) 2005-03-18 2010-08-04 株式会社日立製作所 フェイルオーバークラスタシステム及びフェイルオーバー方法
US7861055B2 (en) 2005-06-07 2010-12-28 Broadcom Corporation Method and system for on-chip configurable data ram for fast memory and pseudo associative caches
US20070005922A1 (en) * 2005-06-30 2007-01-04 Swaminathan Muthukumar P Fully buffered DIMM variable read latency
US20070025304A1 (en) * 2005-07-26 2007-02-01 Rangsan Leelahakriengkrai System and method for prioritizing transmission legs for precaching data
US7328381B2 (en) * 2005-08-01 2008-02-05 Micron Technology, Inc. Testing system and method for memory modules having a memory hub architecture
US7319340B2 (en) 2005-08-01 2008-01-15 Micron Technology, Inc. Integrated circuit load board and method having on-board test circuit
US7865570B2 (en) * 2005-08-30 2011-01-04 Illinois Institute Of Technology Memory server
US7430145B2 (en) 2005-09-16 2008-09-30 Hewlett-Packard Development Company, L.P. System and method for avoiding attempts to access a defective portion of memory
US20070165457A1 (en) 2005-09-30 2007-07-19 Jin-Ki Kim Nonvolatile memory system
US7496777B2 (en) 2005-10-12 2009-02-24 Sun Microsystems, Inc. Power throttling in a memory system
US7685392B2 (en) 2005-11-28 2010-03-23 International Business Machines Corporation Providing indeterminate read data latency in a memory system
US7386771B2 (en) 2006-01-06 2008-06-10 International Business Machines Corporation Repair of memory hard failures during normal operation, using ECC and a hard fail identifier circuit
US7353316B2 (en) 2006-03-24 2008-04-01 Micron Technology, Inc. System and method for re-routing signals between memory system components
US20080162807A1 (en) 2006-12-29 2008-07-03 Rothman Michael A Method and apparatus for redundant memory arrays
US7877666B2 (en) 2006-12-30 2011-01-25 Intel Corporation Tracking health of integrated circuit structures
US8041989B2 (en) 2007-06-28 2011-10-18 International Business Machines Corporation System and method for providing a high fault tolerant memory system

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